diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-12 09:05:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-12 09:05:25 -0500 |
| commit | 4583a5114aa34efb3b83e9a2e40dd74f7c49facb (patch) | |
| tree | 2b1fef9b86d8c589f2dbc2e17c03c85a9e1900d3 /tests/quick | |
| parent | 9d6d8e02aab300c524ca9cf216a11e71d10826aa (diff) | |
| download | gem5-4583a5114aa34efb3b83e9a2e40dd74f7c49facb.tar.xz | |
stats: Bump regressions to match latest changes
Updates after timezone hick-up and sorting of dictionary items in the
SimObject.
Diffstat (limited to 'tests/quick')
6 files changed, 7190 insertions, 7192 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 560fdc0dc..1efe64b0a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.802883 # Number of seconds simulated -sim_ticks 2802882713500 # Number of ticks simulated -final_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2802882634000 # Number of ticks simulated +final_tick 2802882634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1349319 # Simulator instruction rate (inst/s) -host_op_rate 1644123 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25757810314 # Simulator tick rate (ticks/s) -host_mem_usage 564420 # Number of bytes of host memory used -host_seconds 108.82 # Real time elapsed on the host -sim_insts 146828498 # Number of instructions simulated -sim_ops 178908222 # Number of ops (including micro ops) simulated +host_inst_rate 1078207 # Simulator instruction rate (inst/s) +host_op_rate 1313778 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20582448891 # Simulator tick rate (ticks/s) +host_mem_usage 574132 # Number of bytes of host memory used +host_seconds 136.18 # Real time elapsed on the host +sim_insts 146828350 # Number of instructions simulated +sim_ops 178908035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1117092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9456444 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory -system.physmem.bytes_read::total 11808788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 151956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081888 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 11809044 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1117092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151956 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1269048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6071744 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8408464 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 8407824 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148282 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193669 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16928 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 193673 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 94871 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135541 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135531 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3373828 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4213178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2166250 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2999706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2166250 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3380144 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7212884 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -89,356 +89,13 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 75957 # Transaction distribution -system.membus.trans_dist::ReadResp 75957 # Transaction distribution -system.membus.trans_dist::WriteReq 30905 # Transaction distribution -system.membus.trans_dist::WriteResp 30905 # Transaction distribution -system.membus.trans_dist::Writeback 94881 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60384 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15620 # Transaction distribution -system.membus.trans_dist::ReadExReq 196326 # Transaction distribution -system.membus.trans_dist::ReadExResp 152193 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 460689 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460689 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 107632 # number of replacements -system.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use -system.l2c.tags.total_refs 207938 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.742920 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.057357 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60384 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1906 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 12994 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45387 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.921387 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4903910 # Number of tag accesses -system.l2c.tags.data_accesses 4903910 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 59 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 28044 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 76113 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 38 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 35 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11456 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11379 # number of ReadReq hits -system.l2c.ReadReq_hits::total 127193 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 225882 # number of Writeback hits -system.l2c.Writeback_hits::total 225882 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 506 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 571 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13825 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3137 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16962 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 59 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89938 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11456 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14516 # number of demand (read+write) hits -system.l2c.demand_hits::total 144155 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 59 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28044 # number of overall hits -system.l2c.overall_hits::cpu0.data 89938 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11456 # number of overall hits -system.l2c.overall_hits::cpu1.data 14516 # number of overall hits -system.l2c.overall_hits::total 144155 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16888 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 11308 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2363 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31692 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9982 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3290 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13272 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 756 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1185 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1941 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136781 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152600 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16888 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 148089 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16941 # number of demand (read+write) misses -system.l2c.demand_misses::total 184292 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16888 # number of overall misses -system.l2c.overall_misses::cpu0.data 148089 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2363 # number of overall misses -system.l2c.overall_misses::cpu1.data 16941 # number of overall misses -system.l2c.overall_misses::total 184292 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 76 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 61 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 44932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 87421 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 40 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12501 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 225882 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150606 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18956 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169562 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 76 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238027 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 40 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31457 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328447 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 76 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 61 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 40 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.032787 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.375857 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.622152 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.032787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94881 # number of writebacks -system.l2c.writebacks::total 94881 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram -system.iobus.trans_dist::ReadReq 31002 # Transaction distribution -system.iobus.trans_dist::ReadResp 31002 # Transaction distribution -system.iobus.trans_dist::WriteReq 59433 # Transaction distribution -system.iobus.trans_dist::WriteResp 23209 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -462,9 +119,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339791 # DTB read hits +system.cpu0.dtb.read_hits 20339775 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16391007 # DTB write hits +system.cpu0.dtb.write_hits 16390998 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -475,12 +132,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346662 # DTB read accesses -system.cpu0.dtb.write_accesses 16392100 # DTB write accesses +system.cpu0.dtb.read_accesses 20346646 # DTB read accesses +system.cpu0.dtb.write_accesses 16392091 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730798 # DTB hits +system.cpu0.dtb.hits 36730773 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36738762 # DTB accesses +system.cpu0.dtb.accesses 36738737 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -502,7 +159,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 97439560 # ITB inst hits +system.cpu0.itb.inst_hits 97439484 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -519,38 +176,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97442918 # ITB inst accesses -system.cpu0.itb.hits 97439560 # DTB hits +system.cpu0.itb.inst_accesses 97442842 # ITB inst accesses +system.cpu0.itb.hits 97439484 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97442918 # DTB accesses -system.cpu0.numCycles 5605767393 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442842 # DTB accesses +system.cpu0.numCycles 5605767234 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95427097 # Number of instructions committed -system.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses +system.cpu0.committedInsts 95427026 # Number of instructions committed +system.cpu0.committedOps 115560441 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762684 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000275 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100762762 # number of integer instructions +system.cpu0.num_func_calls 8000257 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204260 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762684 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457418 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135520 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written -system.cpu0.num_mem_refs 37873781 # number of memory refs -system.cpu0.num_load_insts 20597370 # Number of load instructions -system.cpu0.num_store_insts 17276411 # Number of store instructions -system.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles -system.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles +system.cpu0.num_cc_register_reads 349971578 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907537 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873766 # number of memory refs +system.cpu0.num_load_insts 20597356 # Number of load instructions +system.cpu0.num_store_insts 17276410 # Number of store instructions +system.cpu0.num_idle_cycles 5488182675.223932 # Number of idle cycles +system.cpu0.num_busy_cycles 117584558.776067 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941666 # Number of branches fetched +system.cpu0.Branches 21941641 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction -system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887374 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -578,18 +235,101 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597356 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276410 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116882229 # Class of executed instruction +system.cpu0.op_class::total 116882135 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 693468 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853471 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932329 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.777182 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853471 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 74113668 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113668 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108613 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108613 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690292 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690292 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363025 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363025 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798905 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798905 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35144985 # number of overall hits +system.cpu0.dcache.overall_hits::total 35144985 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295766 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295766 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18448 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18448 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668860 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668860 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769182 # number of overall misses +system.cpu0.dcache.overall_misses::total 769182 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986058 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986058 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467765 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467765 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914167 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914167 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048360 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048360 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 511566 # number of writebacks +system.cpu0.dcache.writebacks::total 511566 # number of writebacks +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109631 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96331750 # Total number of references to valid blocks. +system.cpu0.icache.tags.total_refs 96331674 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.774181 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.774113 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy @@ -599,26 +339,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195993956 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195993956 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96331750 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96331750 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96331750 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96331750 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96331750 # number of overall hits -system.cpu0.icache.overall_hits::total 96331750 # number of overall hits +system.cpu0.icache.tags.tag_accesses 195993804 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993804 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331674 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331674 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331674 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331674 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331674 # number of overall hits +system.cpu0.icache.overall_hits::total 96331674 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses system.cpu0.icache.overall_misses::total 1110152 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441902 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97441902 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97441902 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97441902 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97441902 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97441902 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441826 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441826 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441826 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441826 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441826 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441826 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses @@ -643,123 +383,123 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 252387 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16137.494570 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1809761 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268581 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.738232 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 252467 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16137.499100 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1809671 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268655 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.736041 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.802195 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.197687 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081095 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.849314 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.564278 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.791544 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.201142 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081297 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.858530 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.566587 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201328 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201329 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16188 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5625 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7524 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988037 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39447588 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39447588 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7603 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3246 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065220 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 351970 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428039 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511617 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511617 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94214 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94214 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7603 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3246 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065220 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446184 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522253 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7603 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3246 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065220 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446184 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522253 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 205 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 119 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44932 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128186 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173442 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26232 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26232 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175300 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175300 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 205 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 119 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44932 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303486 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348742 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 205 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 119 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44932 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303486 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348742 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7808 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3365 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5647 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7609 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2581 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39448657 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39448657 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7673 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3273 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065177 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 351940 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1428063 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511566 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511566 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94243 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94243 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7673 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3273 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065177 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446183 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1522306 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7673 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3273 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065177 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446183 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1522306 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 211 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44975 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128216 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173525 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26236 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26236 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18448 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18448 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175271 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175271 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 211 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44975 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303487 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 348796 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 211 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44975 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303487 # number of overall misses +system.cpu0.l2cache.overall_misses::total 348796 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7884 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3396 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601481 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511617 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511617 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26249 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26249 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1601588 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511566 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511566 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26252 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26252 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18448 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18448 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7808 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3365 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7884 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3396 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1870995 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7808 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3365 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1871102 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7884 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3396 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1870995 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035364 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040474 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266967 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 1871102 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.036219 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040512 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267030 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108346 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999391 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999391 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650322 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650322 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.036219 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040512 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404827 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186412 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.036219 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040512 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404827 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186412 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,128 +508,45 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks -system.cpu0.l2cache.writebacks::total 192916 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192870 # number of writebacks +system.cpu0.l2cache.writebacks::total 192870 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 693468 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145013 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses -system.cpu0.dcache.overall_misses::total 769179 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks -system.cpu0.dcache.writebacks::total 511617 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26252 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44700 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220284 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500256 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80909882 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 322119 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152078946 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322137 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656435 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.082643 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275341 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2436900 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 219535 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656435 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -913,9 +570,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173926 # DTB read hits +system.cpu1.dtb.read_hits 12173905 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7587211 # DTB write hits +system.cpu1.dtb.write_hits 7587201 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -926,12 +583,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176779 # DTB read accesses -system.cpu1.dtb.write_accesses 7587717 # DTB write accesses +system.cpu1.dtb.read_accesses 12176758 # DTB read accesses +system.cpu1.dtb.write_accesses 7587707 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761137 # DTB hits +system.cpu1.dtb.hits 19761106 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19764496 # DTB accesses +system.cpu1.dtb.accesses 19764465 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -953,7 +610,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 53671662 # ITB inst hits +system.cpu1.itb.inst_hits 53671578 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -970,38 +627,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673396 # ITB inst accesses -system.cpu1.itb.hits 53671662 # DTB hits +system.cpu1.itb.inst_accesses 53673312 # ITB inst accesses +system.cpu1.itb.hits 53671578 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673396 # DTB accesses -system.cpu1.numCycles 5605296302 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673312 # DTB accesses +system.cpu1.numCycles 5605296143 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51401401 # Number of instructions committed -system.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses +system.cpu1.committedInsts 51401324 # Number of instructions committed +system.cpu1.committedOps 63347594 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984226 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170855 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984315 # number of integer instructions +system.cpu1.num_func_calls 9170833 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967095 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984226 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674651 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298354 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026390 # number of memory refs -system.cpu1.num_load_insts 12289548 # Number of load instructions -system.cpu1.num_store_insts 7736842 # Number of store instructions -system.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles -system.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles +system.cpu1.num_cc_register_reads 196268580 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894392 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026364 # number of memory refs +system.cpu1.num_load_insts 12289528 # Number of load instructions +system.cpu1.num_store_insts 7736836 # Number of store instructions +system.cpu1.num_idle_cycles 5539682653.586912 # Number of idle cycles +system.cpu1.num_busy_cycles 65613489.413088 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217497 # Number of branches fetched +system.cpu1.Branches 15217468 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401373 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28395 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401296 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -1029,18 +686,100 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736842 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289528 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736836 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459543 # Class of executed instruction +system.cpu1.op_class::total 65459439 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 191947 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.736020 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503484 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.421646 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736020 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 39751950 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39751950 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858675 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858675 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397476 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397476 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72420 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72420 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256151 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256151 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306251 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306251 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92478 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92478 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22559 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22559 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229117 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229117 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259835 # number of overall misses +system.cpu1.dcache.overall_misses::total 259835 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995314 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995314 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489954 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489954 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 19485268 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485268 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566086 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566086 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237516 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237516 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 120692 # number of writebacks +system.cpu1.dcache.writebacks::total 120692 # number of writebacks +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523402 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148838 # Total number of references to valid blocks. +system.cpu1.icache.tags.total_refs 53148754 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.445730 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.445569 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy @@ -1049,26 +788,26 @@ system.cpu1.icache.tags.occ_task_id_blocks::1024 512 system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107869418 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107869418 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148838 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148838 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148838 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148838 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148838 # number of overall hits -system.cpu1.icache.overall_hits::total 53148838 # number of overall hits +system.cpu1.icache.tags.tag_accesses 107869250 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869250 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148754 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148754 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148754 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148754 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148754 # number of overall hits +system.cpu1.icache.overall_hits::total 53148754 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses system.cpu1.icache.overall_misses::total 523914 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672752 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672752 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672752 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672752 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672752 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672752 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672668 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672668 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672668 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672668 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672668 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672668 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -1093,121 +832,121 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 48605 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15302.416394 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716648 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.297716 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48632 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15302.414906 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716436 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63462 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.289212 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.635884 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.959660 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.032491 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.997092 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.791267 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.505959 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.533576 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.964027 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.029845 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.932073 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.955385 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.505953 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200378 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227221 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200374 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227231 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14804 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9351 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4901 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15213580 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15213580 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3243 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1759 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510095 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99336 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614433 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120654 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120654 # number of Writeback hits +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9309 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4941 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001587 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903564 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15214590 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15214590 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3250 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1767 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510040 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99338 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614395 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120692 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120692 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19759 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19759 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3243 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1759 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510095 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119095 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634192 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3243 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1759 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510095 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119095 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634192 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 343 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13819 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73339 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87768 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28855 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28855 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22557 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22557 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43856 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43856 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 343 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13819 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117195 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131624 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 343 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13819 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117195 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131624 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3586 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2026 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19796 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19796 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3250 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1767 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510040 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119134 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634191 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3250 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1767 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510040 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119134 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634191 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 345 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 269 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13874 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73337 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87825 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28856 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28856 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22559 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22559 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43819 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43819 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 345 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 269 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13874 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117156 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131644 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 345 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 269 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13874 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117156 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131644 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3595 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2036 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 702201 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120654 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120654 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28862 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28862 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22557 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22557 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 702220 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120692 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120692 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28863 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28863 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22559 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22559 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3586 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2026 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3595 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2036 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765816 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3586 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2026 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 765835 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3595 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2036 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765816 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.131787 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026376 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424723 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.124990 # miss rate for ReadReq accesses +system.cpu1.l2cache.overall_accesses::total 765835 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.132122 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026481 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424711 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.125068 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689397 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689397 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.131787 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026376 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495980 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171874 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.131787 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026376 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495980 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171874 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688816 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688816 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.132122 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026481 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495814 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171896 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.132122 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026481 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495814 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171896 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1216,134 +955,107 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks -system.cpu1.l2cache.writebacks::total 32966 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32939 # number of writebacks +system.cpu1.l2cache.writebacks::total 32939 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 191947 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503515 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39752012 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39752012 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858696 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858696 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397487 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397487 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72422 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72422 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256183 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256183 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306283 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306283 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92477 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92477 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22557 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22557 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229116 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229116 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259834 # number of overall misses -system.cpu1.dcache.overall_misses::total 259834 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995335 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995335 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489964 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489964 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485299 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485299 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566117 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566117 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237495 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120654 # number of writebacks -system.cpu1.dcache.writebacks::total 120654 # number of writebacks -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120692 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28863 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22559 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51422 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707576 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774454 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866030 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499552 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56434626 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499621 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371622 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.313465 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463902 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 941666 68.65% 68.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 429956 31.35% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371622 # Request fanout histogram +system.iobus.trans_dist::ReadReq 31002 # Transaction distribution +system.iobus.trans_dist::ReadResp 31002 # Transaction distribution +system.iobus.trans_dist::WriteReq 59433 # Transaction distribution +system.iobus.trans_dist::WriteResp 23209 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1382,5 +1094,293 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 107659 # number of replacements +system.l2c.tags.tagsinuse 62143.932416 # Cycle average of tags in use +system.l2c.tags.total_refs 208094 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168104 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.237888 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48688.063077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7324.743178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3758.906335 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1656.372339 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 711.015210 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742921 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60436 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1910 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13081 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45354 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4903872 # Number of tag accesses +system.l2c.tags.data_accesses 4903872 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 74 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 28084 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 76119 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 40 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 38 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11510 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11381 # number of ReadReq hits +system.l2c.ReadReq_hits::total 127309 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 225809 # number of Writeback hits +system.l2c.Writeback_hits::total 225809 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 496 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 63 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 559 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 61 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13793 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3108 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16901 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28084 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89912 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 40 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11510 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14489 # number of demand (read+write) hits +system.l2c.demand_hits::total 144210 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28084 # number of overall hits +system.l2c.overall_hits::cpu0.data 89912 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 40 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11510 # number of overall hits +system.l2c.overall_hits::cpu1.data 14489 # number of overall hits +system.l2c.overall_hits::total 144210 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16891 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 11305 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2364 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1123 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31694 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 10009 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13304 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1183 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1942 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136769 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15820 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152589 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16891 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 148074 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16943 # number of demand (read+write) misses +system.l2c.demand_misses::total 184283 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 16891 # number of overall misses +system.l2c.overall_misses::cpu0.data 148074 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2364 # number of overall misses +system.l2c.overall_misses::cpu1.data 16943 # number of overall misses +system.l2c.overall_misses::total 184283 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 81 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 44975 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 87424 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 42 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 38 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13874 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12504 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 159003 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 225809 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225809 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10505 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3358 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 820 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150562 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169490 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 81 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44975 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 237986 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13874 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31432 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328493 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 81 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44975 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 237986 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13874 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31432 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328493 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.375564 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129312 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.170391 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089811 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199330 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952784 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.981239 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.959677 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.925610 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992450 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.965209 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.908390 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.835799 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.900283 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.375564 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622196 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.170391 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.539037 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.560995 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.375564 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622196 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.170391 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.539037 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.560995 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 94871 # number of writebacks +system.l2c.writebacks::total 94871 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 75959 # Transaction distribution +system.membus.trans_dist::ReadResp 75959 # Transaction distribution +system.membus.trans_dist::WriteReq 30905 # Transaction distribution +system.membus.trans_dist::WriteResp 30905 # Transaction distribution +system.membus.trans_dist::Writeback 94871 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60398 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40937 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15640 # Transaction distribution +system.membus.trans_dist::ReadExReq 196324 # Transaction distribution +system.membus.trans_dist::ReadExResp 152195 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652163 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773589 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846541 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18087396 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20421860 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 460700 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 460700 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 460700 # Request fanout histogram +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 305363 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305363 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225809 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41007 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101570 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213619 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213619 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117852 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410871 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34663730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432818 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45096548 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 36713 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 838824 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203946 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802348 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838824 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 5bbc68c06..755cdf962 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783854 # Number of seconds simulated -sim_ticks 2783854177000 # Number of ticks simulated -final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783854461500 # Number of ticks simulated +final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1378246 # Simulator instruction rate (inst/s) -host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26874016957 # Simulator tick rate (ticks/s) -host_mem_usage 553624 # Number of bytes of host memory used -host_seconds 103.59 # Real time elapsed on the host -sim_insts 142771179 # Number of instructions simulated -sim_ops 173800939 # Number of ops (including micro ops) simulated +host_inst_rate 1414038 # Simulator instruction rate (inst/s) +host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27571822204 # Simulator tick rate (ticks/s) +host_mem_usage 560116 # Number of bytes of host memory used +host_seconds 100.97 # Real time elapsed on the host +sim_insts 142771592 # Number of instructions simulated +sim_ops 173801445 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -66,138 +66,12 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74235 # Transaction distribution -system.membus.trans_dist::ReadResp 74235 # Transaction distribution -system.membus.trans_dist::WriteReq 27560 # Transaction distribution -system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101899 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 146085 # Transaction distribution -system.membus.trans_dist::ReadExResp 146085 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322858 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322858 # Request fanout histogram -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 30171 # Transaction distribution -system.iobus.trans_dist::ReadResp 30171 # Transaction distribution -system.iobus.trans_dist::WriteReq 59016 # Transaction distribution -system.iobus.trans_dist::WriteResp 22792 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -222,9 +96,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525864 # DTB read hits +system.cpu.dtb.read_hits 31525959 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124034 # DTB write hits +system.cpu.dtb.write_hits 23124081 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -235,12 +109,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534444 # DTB read accesses -system.cpu.dtb.write_accesses 23125482 # DTB write accesses +system.cpu.dtb.read_accesses 31534539 # DTB read accesses +system.cpu.dtb.write_accesses 23125529 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54649898 # DTB hits +system.cpu.dtb.hits 54650040 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54659926 # DTB accesses +system.cpu.dtb.accesses 54660068 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -262,7 +136,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 147037671 # ITB inst hits +system.cpu.itb.inst_hits 147038107 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -279,38 +153,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147042433 # ITB inst accesses -system.cpu.itb.hits 147037671 # DTB hits +system.cpu.itb.inst_accesses 147042869 # ITB inst accesses +system.cpu.itb.hits 147038107 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147042433 # DTB accesses -system.cpu.numCycles 5567711435 # number of cpu cycles simulated +system.cpu.itb.accesses 147042869 # DTB accesses +system.cpu.numCycles 5567712004 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142771179 # Number of instructions committed -system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses +system.cpu.committedInsts 142771592 # Number of instructions committed +system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873782 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls -system.cpu.num_int_insts 153160639 # number of integer instructions +system.cpu.num_func_calls 16873874 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls +system.cpu.num_int_insts 153161099 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read -system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written +system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written -system.cpu.num_mem_refs 55938446 # number of memory refs -system.cpu.num_load_insts 31855497 # Number of load instructions -system.cpu.num_store_insts 24082949 # Number of store instructions -system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles -system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles +system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written +system.cpu.num_mem_refs 55938603 # number of memory refs +system.cpu.num_load_insts 31855595 # Number of load instructions +system.cpu.num_store_insts 24083008 # Number of store instructions +system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles +system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396779 # Number of branches fetched +system.cpu.Branches 36396923 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -338,18 +212,101 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177217756 # Class of executed instruction +system.cpu.op_class::total 177218284 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 819396 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits +system.cpu.dcache.overall_hits::total 52863618 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses +system.cpu.dcache.overall_misses::total 814069 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks +system.cpu.dcache.writebacks::total 682037 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1699006 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy @@ -360,26 +317,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits -system.cpu.icache.overall_hits::total 145341254 # number of overall hits +system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits +system.cpu.icache.overall_hits::total 145341690 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses system.cpu.icache.overall_misses::total 1699524 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -396,16 +353,16 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -422,29 +379,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses @@ -469,26 +426,26 @@ system.cpu.l2cache.overall_misses::total 181765 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses @@ -498,17 +455,17 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -521,111 +478,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks system.cpu.l2cache.writebacks::total 101899 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 819392 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits -system.cpu.dcache.overall_hits::total 52863480 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses -system.cpu.dcache.overall_misses::total 814065 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks -system.cpu.dcache.writebacks::total 682036 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36632 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -634,19 +508,74 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3231951 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram +system.iobus.trans_dist::ReadReq 30171 # Transaction distribution +system.iobus.trans_dist::ReadResp 30171 # Transaction distribution +system.iobus.trans_dist::WriteReq 59016 # Transaction distribution +system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -685,5 +614,76 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 74235 # Transaction distribution +system.membus.trans_dist::ReadResp 74235 # Transaction distribution +system.membus.trans_dist::WriteReq 27560 # Transaction distribution +system.membus.trans_dist::WriteResp 27560 # Transaction distribution +system.membus.trans_dist::Writeback 101899 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution +system.membus.trans_dist::ReadExReq 146085 # Transaction distribution +system.membus.trans_dist::ReadExResp 146085 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 322858 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 322858 # Request fanout histogram +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 00e66bf9d..23357c831 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.866923 # Number of seconds simulated -sim_ticks 2866923142000 # Number of ticks simulated -final_tick 2866923142000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.866913 # Number of seconds simulated +sim_ticks 2866913114000 # Number of ticks simulated +final_tick 2866913114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 699616 # Simulator instruction rate (inst/s) -host_op_rate 846245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15203294122 # Simulator tick rate (ticks/s) -host_mem_usage 599680 # Number of bytes of host memory used -host_seconds 188.57 # Real time elapsed on the host -sim_insts 131928295 # Number of instructions simulated -sim_ops 159578500 # Number of ops (including micro ops) simulated +host_inst_rate 786450 # Simulator instruction rate (inst/s) +host_op_rate 951292 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17090693254 # Simulator tick rate (ticks/s) +host_mem_usage 609256 # Number of bytes of host memory used +host_seconds 167.75 # Real time elapsed on the host +sim_insts 131924636 # Number of instructions simulated +sim_ops 159576421 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 235364 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 833280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9630848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 236004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 838784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9619456 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 438560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365696 # Number of bytes read from this memory -system.physmem.bytes_read::total 12555416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 235364 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 285240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6390016 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 50964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 440736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1362944 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 12550680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 236004 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 50964 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6395008 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8726096 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 8731088 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 150482 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12141 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 13632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 150304 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6876 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 21339 # Number of read requests responded to by this memory -system.physmem.num_reads::total 205336 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 99844 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 21296 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 205262 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 99922 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140504 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 140582 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 290653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3359298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 292574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3355336 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 152972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 476363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4379404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82096 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2228876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 808650 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 17777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 153732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 475405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4377768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82320 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 17777 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2230625 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3043715 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2228876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 808984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 808652 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3045467 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2230625 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 296828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3359298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 298749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3355336 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 152986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 476363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7423119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 205337 # Number of read requests accepted -system.physmem.writeReqs 140504 # Number of write requests accepted -system.physmem.readBursts 205337 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140504 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13124800 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16768 # Total number of bytes read from write queue -system.physmem.bytesWritten 8739776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12555480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8726096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 262 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.inst 17777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 153746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 475405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 808987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7423234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 205263 # Number of read requests accepted +system.physmem.writeReqs 140582 # Number of write requests accepted +system.physmem.readBursts 205263 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140582 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13120768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue +system.physmem.bytesWritten 8744768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12550744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8731088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15133 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12897 # Per bank write bursts -system.physmem.perBankRdBursts::1 12279 # Per bank write bursts -system.physmem.perBankRdBursts::2 13044 # Per bank write bursts -system.physmem.perBankRdBursts::3 12666 # Per bank write bursts -system.physmem.perBankRdBursts::4 21207 # Per bank write bursts -system.physmem.perBankRdBursts::5 12512 # Per bank write bursts -system.physmem.perBankRdBursts::6 12819 # Per bank write bursts -system.physmem.perBankRdBursts::7 13070 # Per bank write bursts -system.physmem.perBankRdBursts::8 12092 # Per bank write bursts -system.physmem.perBankRdBursts::9 12100 # Per bank write bursts -system.physmem.perBankRdBursts::10 12291 # Per bank write bursts -system.physmem.perBankRdBursts::11 10982 # Per bank write bursts -system.physmem.perBankRdBursts::12 11837 # Per bank write bursts -system.physmem.perBankRdBursts::13 12135 # Per bank write bursts -system.physmem.perBankRdBursts::14 11741 # Per bank write bursts -system.physmem.perBankRdBursts::15 11403 # Per bank write bursts -system.physmem.perBankWrBursts::0 8736 # Per bank write bursts -system.physmem.perBankWrBursts::1 8619 # Per bank write bursts -system.physmem.perBankWrBursts::2 9216 # Per bank write bursts -system.physmem.perBankWrBursts::3 8724 # Per bank write bursts -system.physmem.perBankWrBursts::4 8630 # Per bank write bursts -system.physmem.perBankWrBursts::5 8715 # Per bank write bursts -system.physmem.perBankWrBursts::6 8820 # Per bank write bursts -system.physmem.perBankWrBursts::7 8946 # Per bank write bursts -system.physmem.perBankWrBursts::8 8394 # Per bank write bursts -system.physmem.perBankWrBursts::9 8545 # Per bank write bursts -system.physmem.perBankWrBursts::10 8627 # Per bank write bursts -system.physmem.perBankWrBursts::11 8114 # Per bank write bursts -system.physmem.perBankWrBursts::12 8397 # Per bank write bursts -system.physmem.perBankWrBursts::13 8288 # Per bank write bursts -system.physmem.perBankWrBursts::14 8182 # Per bank write bursts -system.physmem.perBankWrBursts::15 7606 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 15112 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12846 # Per bank write bursts +system.physmem.perBankRdBursts::1 12299 # Per bank write bursts +system.physmem.perBankRdBursts::2 13037 # Per bank write bursts +system.physmem.perBankRdBursts::3 12736 # Per bank write bursts +system.physmem.perBankRdBursts::4 21227 # Per bank write bursts +system.physmem.perBankRdBursts::5 12513 # Per bank write bursts +system.physmem.perBankRdBursts::6 12853 # Per bank write bursts +system.physmem.perBankRdBursts::7 12957 # Per bank write bursts +system.physmem.perBankRdBursts::8 12050 # Per bank write bursts +system.physmem.perBankRdBursts::9 12106 # Per bank write bursts +system.physmem.perBankRdBursts::10 12270 # Per bank write bursts +system.physmem.perBankRdBursts::11 11010 # Per bank write bursts +system.physmem.perBankRdBursts::12 11804 # Per bank write bursts +system.physmem.perBankRdBursts::13 12158 # Per bank write bursts +system.physmem.perBankRdBursts::14 11709 # Per bank write bursts +system.physmem.perBankRdBursts::15 11437 # Per bank write bursts +system.physmem.perBankWrBursts::0 8735 # Per bank write bursts +system.physmem.perBankWrBursts::1 8638 # Per bank write bursts +system.physmem.perBankWrBursts::2 9213 # Per bank write bursts +system.physmem.perBankWrBursts::3 8824 # Per bank write bursts +system.physmem.perBankWrBursts::4 8594 # Per bank write bursts +system.physmem.perBankWrBursts::5 8713 # Per bank write bursts +system.physmem.perBankWrBursts::6 8840 # Per bank write bursts +system.physmem.perBankWrBursts::7 8875 # Per bank write bursts +system.physmem.perBankWrBursts::8 8399 # Per bank write bursts +system.physmem.perBankWrBursts::9 8546 # Per bank write bursts +system.physmem.perBankWrBursts::10 8611 # Per bank write bursts +system.physmem.perBankWrBursts::11 8118 # Per bank write bursts +system.physmem.perBankWrBursts::12 8409 # Per bank write bursts +system.physmem.perBankWrBursts::13 8327 # Per bank write bursts +system.physmem.perBankWrBursts::14 8185 # Per bank write bursts +system.physmem.perBankWrBursts::15 7610 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 2866922767000 # Total gap between requests +system.physmem.totGap 2866912757000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 195567 # Read request sizes (log2) +system.physmem.readPktSize::6 195493 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136068 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 121119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21791 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 7029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136146 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 121382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 7045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 5373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -191,158 +191,154 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 81121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.529616 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.748883 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.565122 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39339 48.49% 48.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16179 19.94% 68.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6333 7.81% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3376 4.16% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3166 3.90% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1954 2.41% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1081 1.33% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1008 1.24% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8685 10.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 81121 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6712 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.551698 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.132444 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6710 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 80938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.150881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.124225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.049708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39103 48.31% 48.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16130 19.93% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6485 8.01% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3355 4.15% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3128 3.86% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1920 2.37% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1075 1.33% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1014 1.25% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8728 10.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 80938 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6722 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.497025 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 543.729847 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6720 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6712 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6712 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.345501 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.833911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.781170 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5518 82.21% 82.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 369 5.50% 87.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 92 1.37% 89.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 214 3.19% 92.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 187 2.79% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 23 0.34% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 12 0.18% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.25% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 32 0.48% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.09% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 162 2.41% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.13% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.19% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6722 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6722 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.326837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.830242 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.742760 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5511 81.98% 81.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 381 5.67% 87.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 92 1.37% 89.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 211 3.14% 92.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 209 3.11% 95.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.31% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.19% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.21% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 24 0.36% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.12% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.42% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.12% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 17 0.25% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.04% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6712 # Writes before turning the bus around for reads -system.physmem.totQLat 6009454502 # Total ticks spent queuing -system.physmem.totMemAccLat 9854610752 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1025375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29303.69 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 7 0.10% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6722 # Writes before turning the bus around for reads +system.physmem.totQLat 5976562250 # Total ticks spent queuing +system.physmem.totMemAccLat 9820537250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1025060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29152.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48053.69 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47902.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.49 # Average write queue length when enqueuing +system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.80 # Average write queue length when enqueuing system.physmem.readRowHits 175010 # Number of row buffer hits during reads -system.physmem.writeRowHits 85502 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes -system.physmem.avgGap 8289713.39 # Average gap between requests -system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731290601750 # Time in different power states -system.physmem.memoryStateTime::REF 95732780000 # Time in different power states +system.physmem.writeRowHits 85700 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.71 # Row buffer hit rate for writes +system.physmem.avgGap 8289588.56 # Average gap between requests +system.physmem.pageHitRate 76.30 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2731202883250 # Time in different power states +system.physmem.memoryStateTime::REF 95732520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 39899739250 # Time in different power states +system.physmem.memoryStateTime::ACT 39977707750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 323265600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 290009160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 176385000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 158239125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 861853200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 737724000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 456230880 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 428671440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187253317680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187253317680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82699072155 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81115825050 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647609467250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648998280500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919379591765 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1918982066955 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.491656 # Core power per rank (mW) -system.physmem.averagePower::1 669.352997 # Core power per rank (mW) +system.physmem.actEnergy::0 322237440 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 289653840 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 175824000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 158045250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 861650400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 737435400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 456399360 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 429008400 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 187252809120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 187252809120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82565899920 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81397166220 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1647721613250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1648746818250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1919356433490 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1919010936480 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.485397 # Core power per rank (mW) +system.physmem.averagePower::1 669.364885 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -361,751 +357,13 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 228669 # Transaction distribution -system.membus.trans_dist::ReadResp 228668 # Transaction distribution -system.membus.trans_dist::WriteReq 31179 # Transaction distribution -system.membus.trans_dist::WriteResp 31179 # Transaction distribution -system.membus.trans_dist::Writeback 99844 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85785 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41193 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15133 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 28316 # Transaction distribution -system.membus.trans_dist::ReadExResp 11444 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14564 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 800908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 873624 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19154259 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21473555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 128959 # Total snoops (count) -system.membus.snoop_fanout::samples 475734 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 475734 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 475734 # Request fanout histogram -system.membus.reqLayer0.occupancy 88166499 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12097497 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1514306999 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1971607923 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38585418 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 132855 # number of replacements -system.l2c.tags.tagsinuse 64219.366353 # Cycle average of tags in use -system.l2c.tags.total_refs 486769 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197473 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.464990 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12668.220978 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.836009 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1159.806509 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1415.804508 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38683.036536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.697637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 527.060368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 909.811701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8848.084656 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193302 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017697 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021603 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590256 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000026 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.135011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979910 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 45009 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19601 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5222 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39585 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1500 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 17888 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.686783 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.299088 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6123027 # Number of tag accesses -system.l2c.tags.data_accesses 6123027 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 138 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 10210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 28863 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 166586 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 49 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4197 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 10271 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47730 # number of ReadReq hits -system.l2c.ReadReq_hits::total 268223 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 239796 # number of Writeback hits -system.l2c.Writeback_hits::total 239796 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 9662 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 934 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10596 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 248 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 151 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 399 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4158 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2526 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6684 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 138 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 10210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 33021 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 166586 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4197 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12797 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 47730 # number of demand (read+write) hits -system.l2c.demand_hits::total 274907 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 138 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits -system.l2c.overall_hits::cpu0.inst 10210 # number of overall hits -system.l2c.overall_hits::cpu0.data 33021 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 166586 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4197 # number of overall hits -system.l2c.overall_hits::cpu1.data 12797 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 47730 # number of overall hits -system.l2c.overall_hits::total 274907 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3114 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6976 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 769 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1415 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq misses -system.l2c.ReadReq_misses::total 184109 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8503 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4264 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 881 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1309 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2190 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 6116 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5504 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 11620 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 3114 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 13092 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 769 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6919 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) misses -system.l2c.demand_misses::total 195729 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3114 # number of overall misses -system.l2c.overall_misses::cpu0.data 13092 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 150483 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 769 # number of overall misses -system.l2c.overall_misses::cpu1.data 6919 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 21339 # number of overall misses -system.l2c.overall_misses::total 195729 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 706500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 269607250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 570989749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 266750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 69445999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 122855750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18430164853 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8530144 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 9612086 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 18142230 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1132453 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2244405 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3376858 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 492352141 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 397195181 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 889547322 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 706500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 269607250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1063341890 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 266750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 69445999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 520050931 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19319712175 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 706500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 269607250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1063341890 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 266750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 69445999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 520050931 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19319712175 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 146 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 134 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 13324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 35839 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 317069 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 52 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 4966 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11686 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69069 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 452332 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 239796 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 239796 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 18165 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5198 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 23363 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1129 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1460 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2589 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 10274 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 8030 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 18304 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 146 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 134 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 13324 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 46113 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 317069 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 52 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 4966 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19716 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69069 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 470636 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 146 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 134 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 13324 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 46113 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 317069 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 52 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 4966 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19716 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69069 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 470636 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007463 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.233714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.194648 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021277 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.154853 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.121085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.407022 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.468098 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.820316 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.546462 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.780337 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.896575 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.845886 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.595289 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.685430 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.634834 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.007463 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.233714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.283911 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.021277 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.154853 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.350933 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.415882 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.007463 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.233714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.283911 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.021277 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.154853 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.350933 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.415882 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86579.078356 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 81850.594753 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90306.890767 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 86823.851590 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 100104.638301 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.192285 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2254.241557 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1421.025300 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1285.417707 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1714.595111 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1541.944292 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80502.312132 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72164.822129 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76553.125818 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 86579.078356 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 81220.737091 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 90306.890767 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75162.730308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 98706.436834 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 86579.078356 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 81220.737091 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 90306.890767 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75162.730308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 98706.436834 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 2 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 99844 # number of writebacks -system.l2c.writebacks::total 99844 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 3114 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6976 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 769 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1414 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 184108 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8503 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4264 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12767 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 881 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1309 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2190 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 6116 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5504 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 11620 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 3114 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 13092 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 769 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6918 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 195728 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 3114 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 13092 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 769 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6918 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 195728 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 607500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230914750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 484247749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 228750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59892499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105166750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 16146124355 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 85791947 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42794256 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 128586203 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8846879 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13136807 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 21983686 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 415913357 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 327528317 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 743441674 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 607500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 230914750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 900161106 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 228750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 59892499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 432695067 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16889566029 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 607500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 230914750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 900161106 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 228750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 59892499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 432695067 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16889566029 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796970001 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814272500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6097046501 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540071000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712688499 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4252759499 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337041001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526960999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10349806000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.194648 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120999 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.407020 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.468098 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.820316 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.546462 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.780337 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.896575 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845886 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595289 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.685430 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.634834 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.415880 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.415880 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69416.248423 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74375.353607 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87699.200225 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.609197 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.176360 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10071.763374 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10041.860386 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.757830 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10038.212785 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68004.146010 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59507.325036 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63979.490017 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 631517 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 631501 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31179 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 239796 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 96205 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41592 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137797 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39833 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39833 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1252484 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399771 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1652255 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37452048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8279747 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45731795 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 304794 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1040942 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.035049 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.183904 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1004458 96.50% 96.50% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1040942 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1516413702 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2125399996 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 850129169 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31019 # Transaction distribution -system.iobus.trans_dist::ReadResp 31019 # Transaction distribution -system.iobus.trans_dist::WriteReq 59414 # Transaction distribution -system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 26 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326665578 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36844582 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1129,25 +387,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24351510 # DTB read hits -system.cpu0.dtb.read_misses 6410 # DTB read misses -system.cpu0.dtb.write_hits 18124813 # DTB write hits -system.cpu0.dtb.write_misses 1105 # DTB write misses +system.cpu0.dtb.read_hits 24351477 # DTB read hits +system.cpu0.dtb.read_misses 6408 # DTB read misses +system.cpu0.dtb.write_hits 18124986 # DTB write hits +system.cpu0.dtb.write_misses 1114 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3406 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1454 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1440 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24357920 # DTB read accesses -system.cpu0.dtb.write_accesses 18125918 # DTB write accesses +system.cpu0.dtb.read_accesses 24357885 # DTB read accesses +system.cpu0.dtb.write_accesses 18126100 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 42476323 # DTB hits -system.cpu0.dtb.misses 7515 # DTB misses -system.cpu0.dtb.accesses 42483838 # DTB accesses +system.cpu0.dtb.hits 42476463 # DTB hits +system.cpu0.dtb.misses 7522 # DTB misses +system.cpu0.dtb.accesses 42483985 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1169,8 +427,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 115065468 # ITB inst hits -system.cpu0.itb.inst_misses 3349 # ITB inst misses +system.cpu0.itb.inst_hits 115065570 # ITB inst hits +system.cpu0.itb.inst_misses 3350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1179,45 +437,45 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 115068817 # ITB inst accesses -system.cpu0.itb.hits 115065468 # DTB hits -system.cpu0.itb.misses 3349 # DTB misses -system.cpu0.itb.accesses 115068817 # DTB accesses -system.cpu0.numCycles 5733846284 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 115068920 # ITB inst accesses +system.cpu0.itb.hits 115065570 # DTB hits +system.cpu0.itb.misses 3350 # DTB misses +system.cpu0.itb.accesses 115068920 # DTB accesses +system.cpu0.numCycles 5733826228 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 111421342 # Number of instructions committed -system.cpu0.committedOps 134707084 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 119417138 # Number of integer alu accesses +system.cpu0.committedInsts 111421445 # Number of instructions committed +system.cpu0.committedOps 134708041 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 119418221 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 12527292 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14979198 # number of instructions that are conditional controls -system.cpu0.num_int_insts 119417138 # number of integer instructions +system.cpu0.num_func_calls 12527454 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14979151 # number of instructions that are conditional controls +system.cpu0.num_int_insts 119418221 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 220360477 # number of times the integer registers were read -system.cpu0.num_int_register_writes 83042635 # number of times the integer registers were written +system.cpu0.num_int_register_reads 220362058 # number of times the integer registers were read +system.cpu0.num_int_register_writes 83043778 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 488370374 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 49987740 # number of times the CC registers were written -system.cpu0.num_mem_refs 43585643 # number of memory refs -system.cpu0.num_load_insts 24597805 # Number of load instructions -system.cpu0.num_store_insts 18987838 # Number of store instructions -system.cpu0.num_idle_cycles 5477706580.128089 # Number of idle cycles -system.cpu0.num_busy_cycles 256139703.871911 # Number of busy cycles -system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles -system.cpu0.Branches 28215087 # Number of branches fetched +system.cpu0.num_cc_register_reads 488373650 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 49988627 # number of times the CC registers were written +system.cpu0.num_mem_refs 43585923 # number of memory refs +system.cpu0.num_load_insts 24597873 # Number of load instructions +system.cpu0.num_store_insts 18988050 # Number of store instructions +system.cpu0.num_idle_cycles 5477680330.504089 # Number of idle cycles +system.cpu0.num_busy_cycles 256145897.495911 # Number of busy cycles +system.cpu0.not_idle_fraction 0.044673 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.955327 # Percentage of idle cycles +system.cpu0.Branches 28215151 # Number of branches fetched system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 94726294 68.43% 68.43% # Class of executed instruction -system.cpu0.op_class::IntMult 104119 0.08% 68.51% # Class of executed instruction +system.cpu0.op_class::IntAlu 94727035 68.43% 68.43% # Class of executed instruction +system.cpu0.op_class::IntMult 104174 0.08% 68.51% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction @@ -1241,69 +499,260 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7379 0.01% 68.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::MemRead 24597805 17.77% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 18987838 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 24597873 17.77% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 18988050 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 138425707 # Class of executed instruction +system.cpu0.op_class::total 138426785 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2071 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1060721 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483228 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 114004226 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1061233 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 107.426198 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 2075 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 658574 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.573597 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41679745 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 659086 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 63.238705 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.573597 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946433 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.946433 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 85564578 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 85564578 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23153254 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23153254 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17430094 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17430094 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323112 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 323112 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358254 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 358254 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353760 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 353760 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 40583348 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 40583348 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 40906460 # number of overall hits +system.cpu0.dcache.overall_hits::total 40906460 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 360294 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 360294 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 297575 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 297575 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106237 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 106237 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21398 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21398 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 657869 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 657869 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 764106 # number of overall misses +system.cpu0.dcache.overall_misses::total 764106 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4477052020 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4477052020 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4450265428 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4450265428 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335153501 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 335153501 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473430117 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 473430117 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1336000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1336000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8927317448 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8927317448 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8927317448 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8927317448 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513548 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23513548 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727669 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17727669 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429349 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 429349 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379652 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 379652 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375130 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 375130 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 41241217 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 41241217 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 41670566 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 41670566 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015323 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.015323 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016786 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.016786 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247437 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247437 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056362 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056362 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056967 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056967 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015952 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.015952 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018337 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018337 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 483361 # number of writebacks +system.cpu0.dcache.writebacks::total 483361 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7378 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7378 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15071 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15071 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 7378 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 7378 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 7378 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 7378 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 352916 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 352916 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297575 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 297575 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96924 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 96924 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6327 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6327 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21370 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21370 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 650491 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 650491 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 747415 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 747415 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3678269480 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3678269480 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3844865572 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3844865572 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1196073992 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1196073992 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89532500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89532500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429878883 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429878883 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1262000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1262000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523135052 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7523135052 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8719209044 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8719209044 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564453750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564453750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183862994 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183862994 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748316744 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748316744 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015009 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015009 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225746 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225746 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016665 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016665 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056967 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056967 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015773 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015773 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017936 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.017936 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 1061124 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.483230 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 114003925 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1061636 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 107.385135 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483228 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483230 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 231192178 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 231192178 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 114004226 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 114004226 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 114004226 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 114004226 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 114004226 # number of overall hits -system.cpu0.icache.overall_hits::total 114004226 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1061242 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1061242 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1061242 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1061242 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1061242 # number of overall misses -system.cpu0.icache.overall_misses::total 1061242 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8993016265 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8993016265 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8993016265 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8993016265 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8993016265 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8993016265 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065468 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115065468 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 115065468 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115065468 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 115065468 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115065468 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009223 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009223 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009223 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009223 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009223 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009223 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8474.048582 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8474.048582 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8474.048582 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8474.048582 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 231192785 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 231192785 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 114003925 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 114003925 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 114003925 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 114003925 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 114003925 # number of overall hits +system.cpu0.icache.overall_hits::total 114003925 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1061645 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1061645 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1061645 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1061645 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1061645 # number of overall misses +system.cpu0.icache.overall_misses::total 1061645 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000982497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9000982497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9000982497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9000982497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9000982497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9000982497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065570 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115065570 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 115065570 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115065570 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 115065570 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115065570 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.335505 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.335505 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8478.335505 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8478.335505 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1312,360 +761,359 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061242 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1061242 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061242 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1061242 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061242 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1061242 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7400481735 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7400481735 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7400481735 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7400481735 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7400481735 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7400481735 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061645 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1061645 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061645 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1061645 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061645 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1061645 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407816003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407816003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407816003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7407816003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407816003 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7407816003 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009223 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009223 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009223 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6973.415804 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.677098 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9920146 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228501 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9247232 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 457 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923384 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228338 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9249316 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 376 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 42 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 443914 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 777982 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 35 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 445319 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778112 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 355628 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16102.172005 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1937789 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 371860 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.211071 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2843494453500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6709.486955 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.515536 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.136878 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 805.451650 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1129.365506 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7457.215481 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.409515 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.replacements 357554 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16100.801595 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1935390 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 373791 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.177733 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6719.608952 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.125628 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135893 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 793.879272 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1140.668616 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7443.383233 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.410132 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.049161 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.068931 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455152 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982799 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8004 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8222 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 41 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1974 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4878 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1002 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4665 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 528 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.488525 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.501831 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 38047907 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 38047907 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7536 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3405 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045714 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 373715 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1430370 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 484430 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 484430 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10145 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 10145 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2013 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2013 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213040 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 213040 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7536 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3405 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1045714 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 586755 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1643410 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7536 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3405 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1045714 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 586755 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1643410 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 196 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15528 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 83217 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 99215 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29791 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 29791 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19296 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19296 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048455 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.069621 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.454308 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982715 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7987 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8246 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1881 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4986 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 978 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2886 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4666 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 532 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.487488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.503296 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 38013369 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 38013369 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7065 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3186 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1046032 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 372434 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1428717 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 483361 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 483361 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10097 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 10097 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2054 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2054 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212764 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 212764 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7065 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3186 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1046032 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 585198 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1641481 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7065 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3186 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1046032 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 585198 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1641481 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 284 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 213 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15613 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 83733 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 99843 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29803 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 29803 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19308 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19308 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44826 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44826 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 196 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 15528 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 128043 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 144041 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 196 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 15528 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 128043 # number of overall misses -system.cpu0.l2cache.overall_misses::total 144041 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6536750 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 592785719 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2259626174 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 2863295143 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522985276 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 522985276 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377523884 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377523884 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1293996 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1293996 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513538321 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1513538321 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6536750 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 592785719 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 3773164495 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 4376833464 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6536750 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 592785719 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 3773164495 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 4376833464 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7810 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3601 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061242 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456932 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1529585 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 484430 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 484430 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39936 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 39936 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21309 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21309 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44911 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44911 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 284 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 213 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 15613 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 128644 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 144754 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 284 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 213 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 15613 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 128644 # number of overall misses +system.cpu0.l2cache.overall_misses::total 144754 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6608000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4758500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598124482 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2271341908 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 2880832890 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522877259 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 522877259 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377985887 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377985887 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1224995 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1224995 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513514605 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1513514605 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6608000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4758500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598124482 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 3784856513 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 4394347495 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6608000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4758500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598124482 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 3784856513 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 4394347495 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7349 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3399 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061645 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456167 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1528560 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 483361 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 483361 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39900 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 39900 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21362 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21362 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257866 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 257866 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7810 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3601 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1061242 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 714798 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1787451 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7810 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3601 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1061242 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 714798 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1787451 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054429 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014632 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182121 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.064864 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745969 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745969 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905533 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905533 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257675 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 257675 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7349 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3399 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1061645 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 713842 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1786235 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7349 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3399 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1061645 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 713842 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1786235 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.062665 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014706 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183558 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.065318 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.746942 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.746942 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.903848 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.903848 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173834 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173834 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054429 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014632 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179132 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.080585 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054429 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014632 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179132 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.080585 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22176.020408 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38175.278143 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27153.420263 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28859.498493 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17555.143365 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17555.143365 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19564.877902 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19564.877902 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 161749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 161749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33764.741913 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33764.741913 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 30386.025257 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 30386.025257 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174293 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174293 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.062665 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014706 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.180214 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.081039 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.062665 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014706 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.180214 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.081039 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22340.375587 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38309.388458 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27126.006568 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28853.629098 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17544.450525 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17544.450525 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19576.646312 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19576.646312 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 153124.375000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 153124.375000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33700.309612 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33700.309612 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 30357.347604 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 30357.347604 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 6544 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 74 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 99 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 74.675676 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 66.101010 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 204753 # number of writebacks -system.cpu0.l2cache.writebacks::total 204753 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2208 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2732 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 4940 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1247 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1247 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2208 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3979 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6187 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2208 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3979 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6187 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 274 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 196 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13320 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80485 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 94275 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 443910 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29791 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29791 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19296 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19296 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 205226 # number of writebacks +system.cpu0.l2cache.writebacks::total 205226 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2290 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2728 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 5018 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2290 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3938 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6228 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2290 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3938 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6228 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 284 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 213 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13323 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 81005 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 94825 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 445317 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29803 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29803 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19308 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19308 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43579 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43579 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 274 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 196 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13320 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124064 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 137854 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 274 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 196 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13320 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124064 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 581764 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2974500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 455365525 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1657319721 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2120277496 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17833673651 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489027550 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489027550 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261183602 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261183602 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1027996 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1027996 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080146893 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080146893 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2974500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 455365525 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2737466614 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 3200424389 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2974500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 455365525 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2737466614 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 21034098040 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43701 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43701 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 284 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 213 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13323 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124706 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 138526 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 284 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 213 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13323 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124706 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 583843 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3267500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457593766 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1665461966 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2130941732 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17831693567 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489548028 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489548028 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261537598 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261537598 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 965995 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 965995 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080387358 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080387358 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3267500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457593766 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2745849324 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 3211329090 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3267500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457593766 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2745849324 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21043022657 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328493002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975701502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987031009 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987031009 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328411497 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975619997 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3986952006 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3986952006 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315524011 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962732511 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176142 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.061634 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315363503 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962572003 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177578 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062036 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745969 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745969 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905533 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905533 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.746942 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.746942 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.903848 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.903848 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.168999 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.168999 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077123 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169597 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169597 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077552 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.325471 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20591.659576 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22490.347346 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40174.075040 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16415.278104 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16415.278104 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13535.634432 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13535.634432 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 128499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 128499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24785.949494 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24785.949494 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23216.042980 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36155.723008 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.326857 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1675,248 +1123,57 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 659666 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.509746 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41678625 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 660178 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 63.132405 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.509746 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946308 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.946308 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 85565275 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 85565275 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23152761 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23152761 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17429713 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17429713 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 322896 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 322896 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358209 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 358209 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353793 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 353793 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40582474 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40582474 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40905370 # number of overall hits -system.cpu0.dcache.overall_hits::total 40905370 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 360920 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 360920 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297802 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297802 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106369 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 106369 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21424 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21424 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21331 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21331 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 658722 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 658722 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 765091 # number of overall misses -system.cpu0.dcache.overall_misses::total 765091 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4478152013 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4478152013 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4451575229 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4451575229 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336099252 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 336099252 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472564125 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 472564125 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1408000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1408000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8929727242 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8929727242 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8929727242 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8929727242 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513681 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23513681 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727515 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17727515 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429265 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 429265 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379633 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 379633 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 375124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41241196 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41241196 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 41670461 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 41670461 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015349 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.015349 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016799 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016799 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247793 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247793 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056433 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056433 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056864 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056864 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015972 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.015972 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018361 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018361 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12407.602829 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12407.602829 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14948.103871 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14948.103871 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15687.978529 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15687.978529 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.866439 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.866439 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13556.139376 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13556.139376 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11671.457698 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11671.457698 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 484431 # number of writebacks -system.cpu0.dcache.writebacks::total 484431 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7369 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15106 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15106 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 7369 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 7369 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 7369 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 7369 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353551 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 353551 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297802 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297802 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97063 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 97063 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6318 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6318 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 651353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 651353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 748416 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 748416 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3677967737 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3677967737 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3845809771 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3845809771 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1192380739 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1192380739 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89588750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89588750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429129875 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429129875 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1332000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1332000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523777508 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7523777508 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8716158247 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8716158247 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564560247 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564560247 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183952491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183952491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748512738 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748512738 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015036 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015036 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016799 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226114 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226114 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016642 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016642 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056827 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056827 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015794 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015794 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.017960 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10402.934052 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10402.934052 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12913.982347 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12913.982347 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12284.606276 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12284.606276 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14179.922444 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14179.922444 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20130.875592 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20130.875592 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11550.998472 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11550.998472 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11646.140979 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11646.140979 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1734773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1628939 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26255 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26255 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 484430 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 593528 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1734345 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1628634 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26254 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26254 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 483361 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 595652 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43635 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 101479 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 80946 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43669 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 279524 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269229 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2140528 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2251817 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10000 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21524 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4423869 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67955576 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 81003288 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14404 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31240 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 149004508 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 985271 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3214597 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.271498 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.444733 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadExReq 279437 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269063 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141334 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2249028 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9800 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21070 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4421232 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981368 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80878536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13596 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29396 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 148902896 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 988296 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3215199 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.272128 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.445055 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2341839 72.85% 72.85% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 872758 27.15% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2340254 72.79% 72.79% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 874945 27.21% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3214597 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1701148418 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3215199 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1699304627 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115449999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115610498 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1603332265 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1603950497 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1151834640 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1150471329 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13714500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13721750 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1941,25 +1198,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4826536 # DTB read hits -system.cpu1.dtb.read_misses 2746 # DTB read misses -system.cpu1.dtb.write_hits 4130096 # DTB write hits -system.cpu1.dtb.write_misses 525 # DTB write misses +system.cpu1.dtb.read_hits 4826061 # DTB read hits +system.cpu1.dtb.read_misses 2744 # DTB read misses +system.cpu1.dtb.write_hits 4130169 # DTB write hits +system.cpu1.dtb.write_misses 524 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 441 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4829282 # DTB read accesses -system.cpu1.dtb.write_accesses 4130621 # DTB write accesses +system.cpu1.dtb.read_accesses 4828805 # DTB read accesses +system.cpu1.dtb.write_accesses 4130693 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 8956632 # DTB hits -system.cpu1.dtb.misses 3271 # DTB misses -system.cpu1.dtb.accesses 8959903 # DTB accesses +system.cpu1.dtb.hits 8956230 # DTB hits +system.cpu1.dtb.misses 3268 # DTB misses +system.cpu1.dtb.accesses 8959498 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1981,7 +1238,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20887785 # ITB inst hits +system.cpu1.itb.inst_hits 20883965 # ITB inst hits system.cpu1.itb.inst_misses 1747 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1998,38 +1255,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20889532 # ITB inst accesses -system.cpu1.itb.hits 20887785 # DTB hits +system.cpu1.itb.inst_accesses 20885712 # ITB inst accesses +system.cpu1.itb.hits 20883965 # DTB hits system.cpu1.itb.misses 1747 # DTB misses -system.cpu1.itb.accesses 20889532 # DTB accesses -system.cpu1.numCycles 5732937622 # number of cpu cycles simulated +system.cpu1.itb.accesses 20885712 # DTB accesses +system.cpu1.numCycles 5732918807 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20506953 # Number of instructions committed -system.cpu1.committedOps 24871416 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22187475 # Number of integer alu accesses +system.cpu1.committedInsts 20503191 # Number of instructions committed +system.cpu1.committedOps 24868380 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22184707 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 1209546 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2572136 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22187475 # number of integer instructions +system.cpu1.num_func_calls 1209330 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2571856 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22184707 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 39849843 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15447126 # number of times the integer registers were written +system.cpu1.num_int_register_reads 39845208 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15444901 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 90450390 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 8861668 # number of times the CC registers were written -system.cpu1.num_mem_refs 9246104 # number of memory refs -system.cpu1.num_load_insts 4945808 # Number of load instructions -system.cpu1.num_store_insts 4300296 # Number of store instructions -system.cpu1.num_idle_cycles 5671542273.082585 # Number of idle cycles -system.cpu1.num_busy_cycles 61395348.917415 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010709 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989291 # Percentage of idle cycles -system.cpu1.Branches 3892449 # Number of branches fetched +system.cpu1.num_cc_register_reads 90439564 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 8859928 # number of times the CC registers were written +system.cpu1.num_mem_refs 9245671 # number of memory refs +system.cpu1.num_load_insts 4945342 # Number of load instructions +system.cpu1.num_store_insts 4300329 # Number of store instructions +system.cpu1.num_idle_cycles 5671530100.732908 # Number of idle cycles +system.cpu1.num_busy_cycles 61388706.267092 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010708 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989292 # Percentage of idle cycles +system.cpu1.Branches 3891928 # Number of branches fetched system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 16016240 63.31% 63.31% # Class of executed instruction -system.cpu1.op_class::IntMult 33559 0.13% 63.44% # Class of executed instruction +system.cpu1.op_class::IntAlu 16013514 63.30% 63.30% # Class of executed instruction +system.cpu1.op_class::IntMult 33536 0.13% 63.44% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction @@ -2053,69 +1310,261 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4035 0.02% 63.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4037 0.02% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::MemRead 4945808 19.55% 83.00% # Class of executed instruction -system.cpu1.op_class::MemWrite 4300296 17.00% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4945342 19.55% 83.00% # Class of executed instruction +system.cpu1.op_class::MemWrite 4300329 17.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 25300005 # Class of executed instruction +system.cpu1.op_class::total 25296825 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 565422 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.690526 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20321845 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 565934 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 35.908507 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 115084597500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690526 # Average occupied blocks per requestor +system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 218952 # number of replacements +system.cpu1.dcache.tags.tagsinuse 479.963069 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8650768 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 219309 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.445568 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.963069 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937428 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.937428 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18157371 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18157371 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4461777 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4461777 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3918409 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3918409 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64134 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 64134 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87180 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87180 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79638 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79638 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8380186 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8380186 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8444320 # number of overall hits +system.cpu1.dcache.overall_hits::total 8444320 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 155208 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 155208 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 103786 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 103786 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34227 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 34227 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17933 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17933 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23205 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23205 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 258994 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 258994 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 293221 # number of overall misses +system.cpu1.dcache.overall_misses::total 293221 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219053526 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2219053526 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2269605832 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2269605832 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325236501 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 325236501 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538183221 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 538183221 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1673500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1673500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4488659358 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4488659358 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4488659358 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4488659358 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4616985 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4616985 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022195 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4022195 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98361 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 98361 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105113 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105113 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102843 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 102843 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8639180 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8639180 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8737541 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8737541 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033617 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.033617 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025803 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.025803 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347973 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347973 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170607 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170607 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225635 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225635 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029979 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029979 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033559 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033559 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17331.132605 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17331.132605 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15308.110122 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15308.110122 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 135060 # number of writebacks +system.cpu1.dcache.writebacks::total 135060 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 314 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12325 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12325 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154894 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 154894 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103785 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103785 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33053 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 33053 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5608 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5608 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23205 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23205 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 258679 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 258679 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 291732 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 291732 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1899677974 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1899677974 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2055753168 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2055753168 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496489496 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496489496 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84032750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84032750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490566779 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490566779 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1599500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1599500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3955431142 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3955431142 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4451920638 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4451920638 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961065499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961065499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382997 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382997 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794448496 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794448496 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033549 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033549 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025803 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025803 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.336038 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.336038 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053352 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053352 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225635 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225635 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033388 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033388 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12264.374178 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19807.806215 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19807.806215 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15021.011587 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15021.011587 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 565004 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.690467 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20318443 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 565516 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 35.929033 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690467 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 112 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 110 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 5 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 42341495 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 42341495 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20321845 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20321845 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20321845 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20321845 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20321845 # number of overall hits -system.cpu1.icache.overall_hits::total 20321845 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 565935 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 565935 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 565935 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 565935 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 565935 # number of overall misses -system.cpu1.icache.overall_misses::total 565935 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4686937020 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4686937020 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4686937020 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4686937020 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4686937020 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4686937020 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20887780 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20887780 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20887780 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20887780 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20887780 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20887780 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027094 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.027094 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027094 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.027094 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027094 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.027094 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8281.758541 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8281.758541 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8281.758541 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8281.758541 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 42333437 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 42333437 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20318443 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20318443 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20318443 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20318443 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20318443 # number of overall hits +system.cpu1.icache.overall_hits::total 20318443 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 565517 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 565517 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 565517 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 565517 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 565517 # number of overall misses +system.cpu1.icache.overall_misses::total 565517 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4683990281 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4683990281 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4683990281 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4683990281 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4683990281 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4683990281 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20883960 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20883960 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20883960 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20883960 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20883960 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20883960 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027079 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.027079 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027079 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.027079 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027079 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.027079 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8282.669276 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8282.669276 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8282.669276 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8282.669276 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2124,356 +1573,356 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565935 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 565935 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 565935 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 565935 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 565935 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 565935 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3837864980 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3837864980 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3837864980 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3837864980 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3837864980 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3837864980 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565517 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 565517 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 565517 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 565517 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 565517 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 565517 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835548219 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835548219 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835548219 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3835548219 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835548219 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3835548219 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027094 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027094 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027094 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6781.458966 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027079 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027079 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027079 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6782.374746 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4614389 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23334 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471466 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 174 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4611088 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 22954 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4468812 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 204 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 12 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119403 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 521875 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 20 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119098 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522488 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85170 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15608.903517 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 832047 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100420 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.285670 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4763.037570 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.132590 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.368696 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 855.518210 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1503.059843 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8483.786608 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.290713 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000023 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052217 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091739 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517809 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952692 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9266 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5973 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1188 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8006 # Occupied blocks per task id +system.cpu1.l2cache.tags.replacements 85089 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15598.515375 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 830428 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 100250 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.283571 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2855976531500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4729.771122 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.150877 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.487977 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 867.406317 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1520.802657 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8476.896425 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.288682 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000030 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052942 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.092822 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517389 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.952058 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9282 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5865 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1139 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8074 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4453 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.565552 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 16694338 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 16694338 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3134 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1760 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560288 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 123283 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 688465 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 134894 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 134894 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1542 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1542 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 898 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 898 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39293 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 39293 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3134 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1760 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 560288 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 162576 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 727758 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3134 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1760 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 560288 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 162576 # number of overall hits -system.cpu1.l2cache.overall_hits::total 727758 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 333 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 282 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5647 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 70211 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 76473 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29395 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29395 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22356 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22356 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33464 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33464 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 333 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 282 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 5647 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 103675 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 109937 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 333 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 282 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 5647 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 103675 # number of overall misses -system.cpu1.l2cache.overall_misses::total 109937 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6884250 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5668750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192294729 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1548076900 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1752924629 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536345651 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 536345651 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436560063 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436560063 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1532500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1532500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1065249640 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1065249640 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6884250 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5668750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192294729 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2613326540 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2818174269 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6884250 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5668750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192294729 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2613326540 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2818174269 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3467 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2042 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565935 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193494 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 764938 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 134894 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 134894 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30937 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30937 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23254 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23254 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72757 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 72757 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3467 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2042 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 565935 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 266251 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 837695 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3467 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2042 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 565935 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 266251 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 837695 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138100 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009978 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.362859 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.099973 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950157 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950157 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961383 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961383 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1132 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4460 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.566528 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.357971 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 16688806 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 16688806 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2996 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1704 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 559876 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 123244 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 687820 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 135060 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 135060 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1609 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1609 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 861 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 861 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39179 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 39179 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2996 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1704 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 559876 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 162423 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 726999 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2996 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1704 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 559876 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 162423 # number of overall hits +system.cpu1.l2cache.overall_hits::total 726999 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5641 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 70311 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 76567 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29399 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29399 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22337 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22337 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33598 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 33598 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 277 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 5641 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 103909 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 110165 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 277 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 5641 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 103909 # number of overall misses +system.cpu1.l2cache.overall_misses::total 110165 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6952000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5546000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192723218 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1546712890 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1751934108 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537154147 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 537154147 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436854563 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436854563 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1562500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1562500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1072389357 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1072389357 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6952000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5546000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192723218 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2619102247 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2824323465 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6952000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5546000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192723218 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2619102247 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2824323465 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3334 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565517 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193555 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 764387 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 135060 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 135060 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31008 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 31008 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23198 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23198 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72777 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 72777 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3334 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 565517 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 266332 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 837164 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3334 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 565517 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 266332 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 837164 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.139828 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009975 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363261 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.100168 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.948110 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.948110 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962885 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962885 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.459942 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.459942 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138100 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009978 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389388 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.131238 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138100 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009978 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389388 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.131238 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20101.950355 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34052.546308 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22048.922534 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22922.137604 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18246.152441 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18246.152441 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19527.646404 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19527.646404 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 255416.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 255416.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31832.704996 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31832.704996 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 25634.447629 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 25634.447629 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.461657 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.461657 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.139828 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009975 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.390148 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.131593 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.139828 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009975 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.390148 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.131593 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20021.660650 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34164.725758 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21998.163730 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22881.059830 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18271.170686 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18271.170686 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19557.441151 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19557.441151 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 223214.285714 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223214.285714 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31918.249807 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31918.249807 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 25637.212046 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 25637.212046 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 1642 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 41 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.463415 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 46.914286 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 35043 # number of writebacks -system.cpu1.l2cache.writebacks::total 35043 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 682 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 211 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 211 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 682 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 997 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 682 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 997 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 333 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 282 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4965 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70107 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 75687 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 119401 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29395 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29395 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22356 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22356 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33253 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 33253 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 333 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 282 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4965 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103360 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 108940 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 333 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 282 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4965 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103360 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 228341 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3694250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143766018 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1054723430 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206735448 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3265998125 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430847649 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430847649 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306945673 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306945673 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1280500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1280500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 812696840 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 812696840 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3694250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143766018 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1867420270 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2019432288 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3694250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143766018 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1867420270 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 5285430413 # number of overall MSHR miss cycles +system.cpu1.l2cache.writebacks::writebacks 35198 # number of writebacks +system.cpu1.l2cache.writebacks::total 35198 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 739 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 100 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 839 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 193 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 193 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 739 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 293 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 1032 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 739 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 293 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 1032 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 338 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4902 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70211 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 75728 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 119097 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29399 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29399 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22337 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22337 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33405 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 33405 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 338 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4902 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103616 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 109133 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 338 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4902 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103616 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 228230 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3607000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143902025 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1053014200 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1205109225 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3247389638 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430450689 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430450689 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306453691 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306453691 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1303500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1303500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820460623 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820460623 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3607000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143902025 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1873474823 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2025569848 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3607000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143902025 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1873474823 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 5272959486 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 915969500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928445000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796605001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796605001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916023500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928499000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796472502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796472502 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712574501 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725050001 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362321 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.098945 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712496002 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1724971502 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362744 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099070 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950157 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950157 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961383 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961383 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.948110 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.948110 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962885 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962885 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457042 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457042 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130047 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.459005 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.459005 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130360 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272583 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15044.481008 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15943.761121 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27353.189044 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14657.174656 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14657.174656 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13729.901279 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13729.901279 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213416.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213416.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24439.805130 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24439.805130 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18537.105636 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23147.093220 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272623 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2483,300 +1932,213 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 218971 # number of replacements -system.cpu1.dcache.tags.tagsinuse 479.931321 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8650668 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 219324 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.442414 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104113508000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.931321 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937366 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.937366 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18158178 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18158178 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4462217 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4462217 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3918401 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3918401 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64226 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 64226 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87223 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87223 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79606 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79606 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8380618 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8380618 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8444844 # number of overall hits -system.cpu1.dcache.overall_hits::total 8444844 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 155213 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 155213 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 103694 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 103694 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34142 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 34142 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17915 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17915 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23305 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23305 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 258907 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 258907 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 293049 # number of overall misses -system.cpu1.dcache.overall_misses::total 293049 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2221366762 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2221366762 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2262833509 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2262833509 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325848251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325848251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539203701 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 539203701 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1640500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1640500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4484200271 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4484200271 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4484200271 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4484200271 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4617430 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4617430 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022095 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4022095 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98368 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 98368 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105138 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105138 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102911 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102911 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8639525 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8639525 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8737893 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8737893 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033615 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.033615 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025781 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025781 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347084 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347084 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170395 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170395 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226458 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226458 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029968 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033538 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033538 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14311.731376 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14311.731376 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21822.222202 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21822.222202 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18188.571086 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18188.571086 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23136.824759 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23136.824759 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17319.733615 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17319.733615 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15301.878768 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15301.878768 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 134894 # number of writebacks -system.cpu1.dcache.writebacks::total 134894 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 307 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12314 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12314 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 307 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 307 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 307 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154906 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 154906 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103694 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103694 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32987 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 32987 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5601 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5601 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23260 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23260 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 258600 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 258600 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 291587 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 291587 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902428238 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902428238 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2049146491 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2049146491 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494497248 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494497248 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84788249 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84788249 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491455299 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491455299 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1568500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1568500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3951574729 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3951574729 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4446071977 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4446071977 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 960995749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 960995749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833535999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833535999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794531748 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794531748 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033548 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033548 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025781 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025781 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335343 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335343 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053273 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053273 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226021 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226021 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033370 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033370 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12281.178508 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12281.178508 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19761.475987 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19761.475987 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14990.670507 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14990.670507 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15138.055526 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15138.055526 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21128.774678 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21128.774678 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15280.644737 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15280.644737 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15247.840188 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15247.840188 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1203948 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 816897 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 134894 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 171563 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 1205511 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 816520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 135060 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 171236 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 86145 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89650 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 86319 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42477 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89729 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 90932 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 78151 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1132224 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880229 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5367 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9390 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2027210 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36220548 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28766783 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13868 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 65009367 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 817024 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1760474 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.414632 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.492658 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadExReq 90979 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 78176 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131388 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880635 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9255 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2026584 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36193796 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28781627 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13336 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 64996683 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 818999 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1762052 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.415245 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.492764 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1030526 58.54% 58.54% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 729948 41.46% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1030369 58.48% 58.48% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 731683 41.52% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1760474 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 658123967 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1762052 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 658210715 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89509999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 89516500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 849202770 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 848574281 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 438590477 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 438678337 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3325000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5923750 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5921000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36427 # number of replacements -system.iocache.tags.tagsinuse 14.452095 # Cycle average of tags in use -system.iocache.tags.total_refs 16 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36443 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277168075000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.452095 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.903256 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.903256 # Average percentage of cache occupancy +system.iobus.trans_dist::ReadReq 31019 # Transaction distribution +system.iobus.trans_dist::ReadResp 31019 # Transaction distribution +system.iobus.trans_dist::WriteReq 59407 # Transaction distribution +system.iobus.trans_dist::WriteResp 59440 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326671825 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36845580 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 36443 # number of replacements +system.iocache.tags.tagsinuse 14.446794 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 277163106000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.446794 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.902925 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.902925 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328485 # Number of tag accesses -system.iocache.tags.data_accesses 328485 # Number of data accesses +system.iocache.tags.tag_accesses 328557 # Number of tag accesses +system.iocache.tags.data_accesses 328557 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses system.iocache.ReadReq_misses::total 253 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 26 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 26 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses system.iocache.demand_misses::total 253 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 253 # number of overall misses system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31613377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31613377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31613377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31613377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31613377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31613377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36250 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36250 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000717 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000717 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124954.059289 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124954.059289 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124954.059289 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124954.059289 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2791,28 +2153,663 @@ system.iocache.demand_mshr_misses::realview.ide 253 system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18456377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18456377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2245537783 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2245537783 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18456377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18456377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18456377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18456377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2250014028 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2250014028 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72950.106719 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72950.106719 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 132935 # number of replacements +system.l2c.tags.tagsinuse 64217.518730 # Cycle average of tags in use +system.l2c.tags.total_refs 488817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 197475 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.475336 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 12771.193603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.858844 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037003 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1138.507599 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1415.888274 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.641656 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 536.042723 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 904.271560 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8794.277876 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.194873 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.017372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.021605 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.589749 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013798 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134190 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979882 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 44757 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 19776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5076 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39488 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1542 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 18030 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.682938 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.301758 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6143442 # Number of tag accesses +system.l2c.tags.data_accesses 6143442 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 146 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 155 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 10201 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 29439 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168037 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 53 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 44 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 4112 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 10373 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47653 # number of ReadReq hits +system.l2c.ReadReq_hits::total 270213 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 240423 # number of Writeback hits +system.l2c.Writeback_hits::total 240423 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 9633 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10633 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4104 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2566 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6670 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 155 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 10201 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 33543 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 168037 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 53 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 4112 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12939 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 47653 # number of demand (read+write) hits +system.l2c.demand_hits::total 276883 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 155 # number of overall hits +system.l2c.overall_hits::cpu0.inst 10201 # number of overall hits +system.l2c.overall_hits::cpu0.data 33543 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 168037 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 53 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits +system.l2c.overall_hits::cpu1.inst 4112 # number of overall hits +system.l2c.overall_hits::cpu1.data 12939 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 47653 # number of overall hits +system.l2c.overall_hits::total 276883 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3124 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6991 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150306 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 786 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1400 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq misses +system.l2c.ReadReq_misses::total 183916 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8554 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4191 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12745 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 893 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1293 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2186 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 6191 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5553 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 11744 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 3124 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 13182 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 150306 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 786 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6953 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) misses +system.l2c.demand_misses::total 195660 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 3124 # number of overall misses +system.l2c.overall_misses::cpu0.data 13182 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 150306 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 786 # number of overall misses +system.l2c.overall_misses::cpu1.data 6953 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 21296 # number of overall misses +system.l2c.overall_misses::total 195660 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 598250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 271876998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 570375499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 223500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 71055248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 119227499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18387871837 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 9302615 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 9559091 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 18861706 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1287445 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2175907 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3463352 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 491575637 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 403495431 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 895071068 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 598250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 271876998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1061951136 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 223500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 71055248 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 522722930 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 19282942905 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 598250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 271876998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1061951136 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 223500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 71055248 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 522722930 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of overall miss cycles +system.l2c.overall_miss_latency::total 19282942905 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 154 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 156 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 13325 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 36430 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318343 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 56 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 4898 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 11773 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68949 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 454129 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 240423 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 240423 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 18187 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5191 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 23378 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1140 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1430 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2570 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 10295 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8119 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 18414 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 154 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 156 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 13325 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 46725 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318343 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 4898 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 19892 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68949 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 472543 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 154 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 156 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 13325 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 46725 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318343 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 4898 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 19892 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68949 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 472543 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006410 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.234447 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.191902 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.022222 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.160474 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.118916 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.404986 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.470336 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.807359 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.545171 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.904196 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.850584 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.601360 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.683951 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.637776 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.006410 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.234447 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.282119 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.022222 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.160474 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.349538 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.414058 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.006410 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.234447 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.282119 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.022222 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.160474 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.349538 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.414058 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87028.488476 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 81587.111858 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90401.078880 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 85162.499286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 99979.728990 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1087.516367 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2280.861608 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1479.929855 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1441.707727 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1682.836040 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1584.333028 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79401.653529 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72662.602377 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76215.179496 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 98553.321604 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 98553.321604 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 370 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 46.250000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 99922 # number of writebacks +system.l2c.writebacks::total 99922 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 3124 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6991 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 786 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1400 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 183915 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8554 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4191 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12745 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 893 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1293 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2186 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 6191 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5553 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 11744 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 3124 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 13182 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 786 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6953 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 195659 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 3124 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 13182 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 786 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6953 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 195659 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 498750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 233055498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 483422499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 187500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 61295748 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101745999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 16105922337 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86281499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42154679 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 128436178 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8967891 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12981791 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 21949682 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 414199861 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 333199069 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 747398930 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 498750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 233055498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 897622360 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 187500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 61295748 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 434945068 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16853321267 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 498750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 233055498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 897622360 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 187500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 61295748 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 434945068 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16853321267 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796922003 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814310000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6097036003 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540062000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712612000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4252674000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8336984003 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526922000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10349710003 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191902 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.118916 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.404984 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.470336 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.807359 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.545171 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.904196 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850584 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.601360 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.683951 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.637776 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.414055 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.414055 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 228475 # Transaction distribution +system.membus.trans_dist::ReadResp 228474 # Transaction distribution +system.membus.trans_dist::WriteReq 31175 # Transaction distribution +system.membus.trans_dist::WriteResp 31175 # Transaction distribution +system.membus.trans_dist::Writeback 99922 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 85905 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41202 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15112 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 28459 # Transaction distribution +system.membus.trans_dist::ReadExResp 11563 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678409 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 800961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 873677 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29108 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19154495 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21473791 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 129134 # Total snoops (count) +system.membus.snoop_fanout::samples 475892 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 475892 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 475892 # Request fanout histogram +system.membus.reqLayer0.occupancy 88166996 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 12082997 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1515063497 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1971064197 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38584420 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 633379 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 633359 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 240423 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 96357 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41586 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 137943 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 39964 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 39964 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256968 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399943 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1656911 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37604672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8289023 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45893695 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 305031 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1043713 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.034956 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.183668 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1007229 96.50% 96.50% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1043713 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1520313197 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2134327544 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 850356790 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index c670f647a..4e27b0ea0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,55 +4,55 @@ sim_seconds 2.902619 # Nu sim_ticks 2902619131000 # Number of ticks simulated final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 756630 # Simulator instruction rate (inst/s) -host_op_rate 912268 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19520630002 # Simulator tick rate (ticks/s) -host_mem_usage 553652 # Number of bytes of host memory used -host_seconds 148.70 # Real time elapsed on the host -sim_insts 112506995 # Number of instructions simulated -sim_ops 135649572 # Number of ops (including micro ops) simulated +host_inst_rate 783857 # Simulator instruction rate (inst/s) +host_op_rate 945096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20223090080 # Simulator tick rate (ticks/s) +host_mem_usage 560080 # Number of bytes of host memory used +host_seconds 143.53 # Real time elapsed on the host +sim_insts 112507011 # Number of instructions simulated +sim_ops 135649580 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 168277 # Number of read requests accepted system.physmem.writeReqs 122785 # Number of write requests accepted @@ -211,20 +211,20 @@ system.physmem.wrQLenPdf::60 13 # Wh system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.640199 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.584074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21469 36.67% 36.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14640 25.00% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5516 9.42% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3473 5.93% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2278 3.89% 80.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 999 1.71% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7539 12.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes @@ -268,12 +268,12 @@ system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads -system.physmem.totQLat 1492072500 # Total ticks spent queuing -system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1491102500 # Total ticks spent queuing +system.physmem.totMemAccLat 4642883750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8870.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27620.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -284,35 +284,35 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing -system.physmem.readRowHits 138435 # Number of row buffer hits during reads -system.physmem.writeRowHits 90000 # Number of row buffer hits during writes +system.physmem.readRowHits 138436 # Number of row buffer hits during reads +system.physmem.writeRowHits 90002 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes system.physmem.avgGap 9972510.17 # Average gap between requests system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states +system.physmem.memoryStateTime::IDLE 2755210874500 # Time in different power states system.physmem.memoryStateTime::REF 96924620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states +system.physmem.memoryStateTime::ACT 50483546000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ) +system.physmem.actEnergy::0 226731960 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 215936280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 123712875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 117822375 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.480439 # Core power per rank (mW) -system.physmem.averagePower::1 669.392466 # Core power per rank (mW) +system.physmem.actBackEnergy::0 86730297120 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 85558991580 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1665488607000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1666516068000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1943242491315 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1942986381555 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.480387 # Core power per rank (mW) +system.physmem.averagePower::1 669.392153 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -325,197 +325,12 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 70649 # Transaction distribution -system.membus.trans_dist::ReadResp 70649 # Transaction distribution -system.membus.trans_dist::WriteReq 27618 # Transaction distribution -system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 82180 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 128451 # Transaction distribution -system.membus.trans_dist::ReadExResp 128451 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 281834 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 281834 # Request fanout histogram -system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -540,9 +355,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24532668 # DTB read hits +system.cpu.dtb.read_hits 24532671 # DTB read hits system.cpu.dtb.read_misses 8148 # DTB read misses -system.cpu.dtb.write_hits 19614514 # DTB write hits +system.cpu.dtb.write_hits 19614515 # DTB write hits system.cpu.dtb.write_misses 1410 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -553,12 +368,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24540816 # DTB read accesses -system.cpu.dtb.write_accesses 19615924 # DTB write accesses +system.cpu.dtb.read_accesses 24540819 # DTB read accesses +system.cpu.dtb.write_accesses 19615925 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44147182 # DTB hits +system.cpu.dtb.hits 44147186 # DTB hits system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 44156740 # DTB accesses +system.cpu.dtb.accesses 44156744 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -580,7 +395,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 115605897 # ITB inst hits +system.cpu.itb.inst_hits 115605918 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -597,38 +412,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115610659 # ITB inst accesses -system.cpu.itb.hits 115605897 # DTB hits +system.cpu.itb.inst_accesses 115610680 # ITB inst accesses +system.cpu.itb.hits 115605918 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115610659 # DTB accesses +system.cpu.itb.accesses 115610680 # DTB accesses system.cpu.numCycles 5805238262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112506995 # Number of instructions committed -system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses +system.cpu.committedInsts 112507011 # Number of instructions committed +system.cpu.committedOps 135649580 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119948946 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses system.cpu.num_func_calls 9898964 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls -system.cpu.num_int_insts 119948923 # number of integer instructions +system.cpu.num_conditional_control_insts 15236406 # number of instructions that are conditional controls +system.cpu.num_int_insts 119948946 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read -system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written +system.cpu.num_int_register_reads 218165471 # number of times the integer registers were read +system.cpu.num_int_register_writes 82686622 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written -system.cpu.num_mem_refs 45428231 # number of memory refs -system.cpu.num_load_insts 24855392 # Number of load instructions -system.cpu.num_store_insts 20572839 # Number of store instructions -system.cpu.num_idle_cycles 5386456122.024144 # Number of idle cycles -system.cpu.num_busy_cycles 418782139.975856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072139 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927861 # Percentage of idle cycles -system.cpu.Branches 25929456 # Number of branches fetched +system.cpu.num_cc_register_reads 489970666 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51914345 # number of times the CC registers were written +system.cpu.num_mem_refs 45428250 # number of memory refs +system.cpu.num_load_insts 24855398 # Number of load instructions +system.cpu.num_store_insts 20572852 # Number of store instructions +system.cpu.num_idle_cycles 5386458042.024144 # Number of idle cycles +system.cpu.num_busy_cycles 418780219.975856 # Number of busy cycles +system.cpu.not_idle_fraction 0.072138 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927862 # Percentage of idle cycles +system.cpu.Branches 25929462 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93218062 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114523 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -656,18 +471,202 @@ system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Class of executed instruction -system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24855398 17.91% 85.18% # Class of executed instruction +system.cpu.op_class::MemWrite 20572852 14.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138771625 # Class of executed instruction +system.cpu.op_class::total 138771647 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 822746 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43252602 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 823258 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.538332 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 177194888 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177194888 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23122389 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23122389 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831358 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831358 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41953747 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41953747 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42345868 # number of overall hits +system.cpu.dcache.overall_hits::total 42345868 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 402166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 402166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 701192 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 701192 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 820347 # number of overall misses +system.cpu.dcache.overall_misses::total 820347 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900442000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5900442000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658351003 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11658351003 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17558793003 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17558793003 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17558793003 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17558793003 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23524555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23524555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19130384 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19130384 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42654939 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42654939 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43166215 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43166215 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14671.657972 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14671.657972 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.750239 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.750239 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.348166 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25041.348166 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.104608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21404.104608 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 686230 # number of writebacks +system.cpu.dcache.writebacks::total 686230 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401539 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 401539 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 700565 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 700565 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 817569 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 817569 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083326500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083326500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002800997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002800997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086127497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16086127497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497317497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17497317497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12659.608407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12659.608407 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.465936 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.465936 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22961.648808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22961.648808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21401.640103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21401.640103 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1699818 # number of replacements system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113905561 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 113905582 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.990267 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.990280 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy @@ -678,44 +677,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117306233 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117306233 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113905561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113905561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113905561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113905561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113905561 # number of overall hits -system.cpu.icache.overall_hits::total 113905561 # number of overall hits +system.cpu.icache.tags.tag_accesses 117306254 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117306254 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113905582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113905582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113905582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113905582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113905582 # number of overall hits +system.cpu.icache.overall_hits::total 113905582 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1700336 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1700336 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1700336 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1700336 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1700336 # number of overall misses system.cpu.icache.overall_misses::total 1700336 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23243215000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23243215000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23243215000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23243215000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23243215000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23243215000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115605897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115605897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115605897 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115605897 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115605897 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115605897 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23242723500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23242723500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23242723500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23242723500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23242723500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23242723500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115605918 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115605918 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115605918 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115605918 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115605918 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115605918 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014708 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.014708 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014708 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.014708 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014708 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.014708 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.777620 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13669.777620 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13669.777620 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13669.777620 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.488560 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13669.488560 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13669.488560 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13669.488560 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -730,12 +729,12 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1700336 system.cpu.icache.demand_mshr_misses::total 1700336 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1700336 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1700336 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835992000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19835992000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835501500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19835501500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835501500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19835501500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835501500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19835501500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles @@ -746,28 +745,28 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.636380 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.636380 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.636380 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.636380 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.636380 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.636380 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 88869 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64932.369340 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2760846 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 64932.369335 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2760844 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 154135 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 17.911869 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 17.911856 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822165 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822123 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809354 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012212 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001590 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724050 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001596 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.773221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -784,15 +783,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6951 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995804 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26241966 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26241966 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 26241950 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26241950 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7097 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 1682273 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 514822 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2207892 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 686231 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 686231 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 514821 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2207891 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 686230 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 686230 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 166049 # number of ReadExReq hits @@ -800,13 +799,13 @@ system.cpu.l2cache.ReadExReq_hits::total 166049 # nu system.cpu.l2cache.demand_hits::cpu.dtb.walker 7097 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3700 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 1682273 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 680871 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2373941 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 680870 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2373940 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7097 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3700 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 1682273 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 680871 # number of overall hits -system.cpu.l2cache.overall_hits::total 2373941 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 680870 # number of overall hits +system.cpu.l2cache.overall_hits::total 2373940 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 18039 # number of ReadReq misses @@ -830,32 +829,32 @@ system.cpu.l2cache.overall_misses::cpu.data 142426 # system.cpu.l2cache.overall_misses::total 160474 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 567750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312883000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918689000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2232289250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312392500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918323250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2231433000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982643216 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8982643216 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1312392500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9900966466 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11214076216 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1312392500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9900966466 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11214076216 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 527013 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2238131 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 686231 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 686231 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 527012 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2238130 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 686230 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 686230 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2742 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2742 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -865,13 +864,13 @@ system.cpu.l2cache.ReadExReq_accesses::total 296284 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7104 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3702 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 1700312 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 823297 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2534415 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 823296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2534414 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7104 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3702 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1700312 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 823297 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2534415 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 823296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2534414 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000985 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000540 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010609 # miss rate for ReadReq accesses @@ -895,25 +894,25 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.172995 system.cpu.l2cache.overall_miss_rate::total 0.063318 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81107.142857 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72780.253894 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75357.968994 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73821.530143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72753.062808 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75327.967353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73793.214061 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.574316 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.574316 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72753.062808 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69516.566259 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69880.954024 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72753.062808 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69516.566259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69880.954024 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,25 +946,25 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 142426 system.cpu.l2cache.overall_mshr_misses::total 160474 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 480750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1087047500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766535000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1854188250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1086559000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766168250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1853333000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352907784 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352907784 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1086559000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119076034 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9206240784 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1086559000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119076034 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9206240784 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles @@ -997,25 +996,25 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172995 system.cpu.l2cache.overall_mshr_miss_rate::total 0.063318 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60260.962359 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.122467 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61317.776712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60233.882144 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62847.038799 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61289.493700 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56458.769025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56458.769025 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1025,195 +1024,11 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 822747 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43252597 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823259 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.538262 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177194873 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177194873 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23122385 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23122385 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831357 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41953742 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41953742 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42345863 # number of overall hits -system.cpu.dcache.overall_hits::total 42345863 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 402167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 402167 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 701193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 701193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 820348 # number of overall misses -system.cpu.dcache.overall_misses::total 820348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19130383 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42654935 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42654935 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43166211 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43166211 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 686231 # number of writebacks -system.cpu.dcache.writebacks::total 686231 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401540 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 401540 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2294825 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2294810 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 686230 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution @@ -1221,17 +1036,17 @@ system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456073 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5912638 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96806921 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205706201 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 52963 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3276132 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1240,24 +1055,126 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3239673 98.89% 98.89% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3276132 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2353772500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2564911000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1311851755 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 30195 # Transaction distribution +system.iobus.trans_dist::ReadResp 30195 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1343,5 +1260,88 @@ system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 70649 # Transaction distribution +system.membus.trans_dist::ReadResp 70649 # Transaction distribution +system.membus.trans_dist::WriteReq 27618 # Transaction distribution +system.membus.trans_dist::WriteResp 27618 # Transaction distribution +system.membus.trans_dist::Writeback 82180 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution +system.membus.trans_dist::ReadExReq 128451 # Transaction distribution +system.membus.trans_dist::ReadExResp 128451 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 219 # Total snoops (count) +system.membus.snoop_fanout::samples 281834 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 281834 # Request fanout histogram +system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1264017500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1594856995 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index b1c7d16c5..cdf4d3024 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,439 +1,95 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783854 # Number of seconds simulated -sim_ticks 2783854177000 # Number of ticks simulated -final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783854461500 # Number of ticks simulated +final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1241693 # Simulator instruction rate (inst/s) -host_op_rate 1511561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24211403286 # Simulator tick rate (ticks/s) -host_mem_usage 555676 # Number of bytes of host memory used -host_seconds 114.98 # Real time elapsed on the host -sim_insts 142771179 # Number of instructions simulated -sim_ops 173800939 # Number of ops (including micro ops) simulated +host_inst_rate 1108552 # Simulator instruction rate (inst/s) +host_op_rate 1349484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21615280295 # Simulator tick rate (ticks/s) +host_mem_usage 562164 # Number of bytes of host memory used +host_seconds 128.79 # Real time elapsed on the host +sim_insts 142771592 # Number of instructions simulated +sim_ops 173801445 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 726948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4668448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4668256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 484032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5677124 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5677316 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 11558024 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 726948 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 484032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 6521152 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::total 8857012 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 19812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73460 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 7563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88709 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189567 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 101893 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::total 142498 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 261130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1676973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1676904 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 173871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2039304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2039372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4151806 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 261130 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 173871 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342491 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2342490 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3181564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2342490 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 261130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1683265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1683196 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 173871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2039307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333371 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74229 # Transaction distribution -system.membus.trans_dist::ReadResp 74229 # Transaction distribution -system.membus.trans_dist::WriteReq 27560 # Transaction distribution -system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101893 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 146085 # Transaction distribution -system.membus.trans_dist::ReadExResp 146085 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498777 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679107 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258755 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20592451 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322846 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322846 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322846 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 110021 # number of replacements -system.l2c.tags.tagsinuse 65155.315046 # Cycle average of tags in use -system.l2c.tags.total_refs 2731069 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.579223 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.450806 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.246169 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.238625 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4020.301933 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.174390 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076969 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.072162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061345 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26229699 # Number of tag accesses -system.l2c.tags.data_accesses 26229699 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4718 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246713 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4981 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847891 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 258771 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201046 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682259 # number of Writeback hits -system.l2c.Writeback_hits::total 682259 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72299 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78743 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151042 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4718 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2285 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319012 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4981 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847891 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337514 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352088 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4718 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2285 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833258 # number of overall hits -system.l2c.overall_hits::cpu0.data 319012 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4981 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847891 # number of overall hits -system.l2c.overall_hits::cpu1.data 337514 # number of overall hits -system.l2c.overall_hits::total 2352088 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10795 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9750 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7563 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5779 # number of ReadReq misses -system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63973 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83891 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10795 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73723 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7563 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89670 # number of demand (read+write) misses -system.l2c.demand_misses::total 181759 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10795 # number of overall misses -system.l2c.overall_misses::cpu0.data 73723 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7563 # number of overall misses -system.l2c.overall_misses::cpu1.data 89670 # number of overall misses -system.l2c.overall_misses::total 181759 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4723 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2286 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844053 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4983 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855454 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264550 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2234941 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682259 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682259 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1261 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136272 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162634 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4723 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2286 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844053 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392735 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4983 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855454 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427184 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533847 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4723 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2286 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844053 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392735 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4983 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855454 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427184 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533847 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.012789 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038017 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008841 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990484 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989298 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469451 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515827 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012789 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187717 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008841 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209910 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012789 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187717 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008841 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209910 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101893 # number of writebacks -system.l2c.writebacks::total 101893 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.physmem.bw_total::cpu1.data 2039375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333370 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2291797 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291797 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682259 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417092 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20768 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41564 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924301 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96322187 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205252475 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36632 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272090 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3235626 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272090 # Request fanout histogram -system.iobus.trans_dist::ReadReq 30171 # Transaction distribution -system.iobus.trans_dist::ReadResp 30171 # Transaction distribution -system.iobus.trans_dist::WriteReq 59016 # Transaction distribution -system.iobus.trans_dist::WriteResp 22792 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -457,25 +113,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997157 # DTB read hits -system.cpu0.dtb.read_misses 4809 # DTB read misses -system.cpu0.dtb.write_hits 11281332 # DTB write hits -system.cpu0.dtb.write_misses 894 # DTB write misses +system.cpu0.dtb.read_hits 15997075 # DTB read hits +system.cpu0.dtb.read_misses 4808 # DTB read misses +system.cpu0.dtb.write_hits 11281657 # DTB write hits +system.cpu0.dtb.write_misses 898 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16001966 # DTB read accesses -system.cpu0.dtb.write_accesses 11282226 # DTB write accesses +system.cpu0.dtb.read_accesses 16001883 # DTB read accesses +system.cpu0.dtb.write_accesses 11282555 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278489 # DTB hits -system.cpu0.dtb.misses 5703 # DTB misses -system.cpu0.dtb.accesses 27284192 # DTB accesses +system.cpu0.dtb.hits 27278732 # DTB hits +system.cpu0.dtb.misses 5706 # DTB misses +system.cpu0.dtb.accesses 27284438 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -497,8 +153,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 74798311 # ITB inst hits -system.cpu0.itb.inst_misses 2590 # ITB inst misses +system.cpu0.itb.inst_hits 74797961 # ITB inst hits +system.cpu0.itb.inst_misses 2591 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -507,45 +163,45 @@ system.cpu0.itb.flush_tlb 2813 # Nu system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1908 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74800901 # ITB inst accesses -system.cpu0.itb.hits 74798311 # DTB hits -system.cpu0.itb.misses 2590 # DTB misses -system.cpu0.itb.accesses 74800901 # DTB accesses -system.cpu0.numCycles 5536444793 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 74800552 # ITB inst accesses +system.cpu0.itb.hits 74797961 # DTB hits +system.cpu0.itb.misses 2591 # DTB misses +system.cpu0.itb.accesses 74800552 # DTB accesses +system.cpu0.numCycles 5536444794 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72639683 # Number of instructions committed -system.cpu0.committedOps 87981695 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77491900 # Number of integer alu accesses +system.cpu0.committedInsts 72639396 # Number of instructions committed +system.cpu0.committedOps 87981758 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77492054 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses -system.cpu0.num_func_calls 8694354 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9459791 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77491900 # number of integer instructions +system.cpu0.num_func_calls 8694368 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9459714 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77492054 # number of integer instructions system.cpu0.num_fp_insts 5289 # number of float instructions -system.cpu0.num_int_register_reads 144070444 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447556 # number of times the integer registers were written +system.cpu0.num_int_register_reads 144071276 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54447497 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268879109 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31834194 # number of times the CC registers were written -system.cpu0.num_mem_refs 27909453 # number of memory refs -system.cpu0.num_load_insts 16164742 # Number of load instructions -system.cpu0.num_store_insts 11744711 # Number of store instructions -system.cpu0.num_idle_cycles 5353616970.490369 # Number of idle cycles -system.cpu0.num_busy_cycles 182827822.509631 # Number of busy cycles +system.cpu0.num_cc_register_reads 268879516 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31833951 # number of times the CC registers were written +system.cpu0.num_mem_refs 27909687 # number of memory refs +system.cpu0.num_load_insts 16164649 # Number of load instructions +system.cpu0.num_store_insts 11745038 # Number of store instructions +system.cpu0.num_idle_cycles 5353616424.336780 # Number of idle cycles +system.cpu0.num_busy_cycles 182828369.663220 # Number of busy cycles system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles -system.cpu0.Branches 18600859 # Number of branches fetched +system.cpu0.Branches 18600789 # Number of branches fetched system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61776837 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction +system.cpu0.op_class::IntAlu 61776684 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59679 0.07% 68.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction @@ -573,85 +229,21 @@ system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16164742 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11744711 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16164649 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11745038 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89752572 # Class of executed instruction +system.cpu0.op_class::total 89752652 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1699006 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145341254 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121642 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542037 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148740302 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148740302 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73956125 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71385129 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145341254 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73956125 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71385129 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145341254 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73956125 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71385129 # number of overall hits -system.cpu0.icache.overall_hits::total 145341254 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844062 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855462 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699524 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844062 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855462 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699524 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844062 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855462 # number of overall misses -system.cpu0.icache.overall_misses::total 1699524 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74800187 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72240591 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74800187 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72240591 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74800187 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72240591 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 819391 # number of replacements +system.cpu0.dcache.tags.replacements 819395 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783615 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819903 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597534 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53783754 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819907 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597384 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830642 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830585 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166589 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -660,35 +252,35 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219234055 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219234055 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305331 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14823339 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128670 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894284 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445424 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185757 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209284 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395041 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234994 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222322 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219234631 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219234631 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305258 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14823504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128762 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10894595 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445159 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185755 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209287 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395042 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234989 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222327 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236693 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223429 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236688 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223434 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26199615 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26268763 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468378 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385372 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26478047 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863419 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197455 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198864 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396319 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137533 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164129 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301662 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26199853 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26268663 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468516 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385608 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26477950 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863558 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197451 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198871 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396322 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137556 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164107 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61720 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 116065 # number of SoftPFReq misses @@ -697,41 +289,41 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334988 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362993 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697981 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389333 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424713 # number of overall misses -system.cpu0.dcache.overall_misses::total 814046 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502786 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022203 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031817 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609553 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240102 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511106 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239657 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226288 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 335007 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 362978 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697985 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389352 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424698 # number of overall misses +system.cpu0.dcache.overall_misses::total 814050 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022375 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032151 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609266 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240100 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271007 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511107 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239652 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226293 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236693 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223431 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236688 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223436 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26534603 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631756 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26774705 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26902760 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677465 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26534860 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631641 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26774960 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26902648 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677608 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012737 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012467 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014137 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226341 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227746 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012469 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014136 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226343 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227743 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227086 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses @@ -741,8 +333,8 @@ system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013630 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014541 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015787 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -752,9 +344,73 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682259 # number of writebacks -system.cpu0.dcache.writebacks::total 682259 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682260 # number of writebacks +system.cpu0.dcache.writebacks::total 682260 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 1699006 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 145341690 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121641 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542038 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 148740738 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148740738 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73955769 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71385921 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145341690 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73955769 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71385921 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145341690 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73955769 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71385921 # number of overall hits +system.cpu0.icache.overall_hits::total 145341690 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844069 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855455 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699524 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844069 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855455 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699524 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844069 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855455 # number of overall misses +system.cpu0.icache.overall_misses::total 1699524 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799838 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72241376 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74799838 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72241376 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74799838 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72241376 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -778,25 +434,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15527003 # DTB read hits -system.cpu1.dtb.read_misses 5395 # DTB read misses -system.cpu1.dtb.write_hits 11842462 # DTB write hits +system.cpu1.dtb.read_hits 15527184 # DTB read hits +system.cpu1.dtb.read_misses 5393 # DTB read misses +system.cpu1.dtb.write_hits 11842180 # DTB write hits system.cpu1.dtb.write_misses 794 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3187 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 923 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15532398 # DTB read accesses -system.cpu1.dtb.write_accesses 11843256 # DTB write accesses +system.cpu1.dtb.read_accesses 15532577 # DTB read accesses +system.cpu1.dtb.write_accesses 11842974 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27369465 # DTB hits -system.cpu1.dtb.misses 6189 # DTB misses -system.cpu1.dtb.accesses 27375654 # DTB accesses +system.cpu1.dtb.hits 27369364 # DTB hits +system.cpu1.dtb.misses 6187 # DTB misses +system.cpu1.dtb.accesses 27375551 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -818,8 +474,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 72238481 # ITB inst hits -system.cpu1.itb.inst_misses 3051 # ITB inst misses +system.cpu1.itb.inst_hits 72239267 # ITB inst hits +system.cpu1.itb.inst_misses 3050 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -828,45 +484,45 @@ system.cpu1.itb.flush_tlb 2817 # Nu system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2020 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72241532 # ITB inst accesses -system.cpu1.itb.hits 72238481 # DTB hits -system.cpu1.itb.misses 3051 # DTB misses -system.cpu1.itb.accesses 72241532 # DTB accesses -system.cpu1.numCycles 88014935 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72242317 # ITB inst accesses +system.cpu1.itb.hits 72239267 # DTB hits +system.cpu1.itb.misses 3050 # DTB misses +system.cpu1.itb.accesses 72242317 # DTB accesses +system.cpu1.numCycles 88015463 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 70131496 # Number of instructions committed -system.cpu1.committedOps 85819244 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75668739 # Number of integer alu accesses +system.cpu1.committedInsts 70132196 # Number of instructions committed +system.cpu1.committedOps 85819687 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75669045 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses -system.cpu1.num_func_calls 8179428 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9270456 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75668739 # number of integer instructions +system.cpu1.num_func_calls 8179506 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9270587 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75669045 # number of integer instructions system.cpu1.num_fp_insts 6195 # number of float instructions -system.cpu1.num_int_register_reads 140985899 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52730443 # number of times the integer registers were written +system.cpu1.num_int_register_reads 140985974 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52730811 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261968424 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30529611 # number of times the CC registers were written -system.cpu1.num_mem_refs 28028993 # number of memory refs -system.cpu1.num_load_insts 15690755 # Number of load instructions -system.cpu1.num_store_insts 12338238 # Number of store instructions -system.cpu1.num_idle_cycles 85360290.427990 # Number of idle cycles -system.cpu1.num_busy_cycles 2654644.572010 # Number of busy cycles +system.cpu1.num_cc_register_reads 261969583 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30530010 # number of times the CC registers were written +system.cpu1.num_mem_refs 28028916 # number of memory refs +system.cpu1.num_load_insts 15690946 # Number of load instructions +system.cpu1.num_store_insts 12337970 # Number of store instructions +system.cpu1.num_idle_cycles 85360794.411583 # Number of idle cycles +system.cpu1.num_busy_cycles 2654668.588417 # Number of busy cycles system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles -system.cpu1.Branches 17795920 # Number of branches fetched +system.cpu1.Branches 17796134 # Number of branches fetched system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59374689 67.88% 67.88% # Class of executed instruction -system.cpu1.op_class::IntMult 57198 0.07% 67.95% # Class of executed instruction +system.cpu1.op_class::IntAlu 59375218 67.88% 67.88% # Class of executed instruction +system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction @@ -894,20 +550,75 @@ system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::MemRead 15690755 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12338238 14.11% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15690946 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12337970 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87465184 # Class of executed instruction +system.cpu1.op_class::total 87465632 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iobus.trans_dist::ReadReq 30171 # Transaction distribution +system.iobus.trans_dist::ReadResp 30171 # Transaction distribution +system.iobus.trans_dist::WriteReq 59016 # Transaction distribution +system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -946,5 +657,294 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 110021 # number of replacements +system.l2c.tags.tagsinuse 65155.314991 # Cycle average of tags in use +system.l2c.tags.total_refs 2731075 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 15.579258 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48893.450285 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5044.246320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.238679 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4020.302070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2464.174515 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.076969 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.072162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061345 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037600 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26229756 # Number of tag accesses +system.l2c.tags.data_accesses 26229756 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2286 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 833265 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 246709 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4981 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 847884 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 258778 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2201051 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682260 # number of Writeback hits +system.l2c.Writeback_hits::total 682260 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 72325 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78718 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151043 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2286 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833265 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 319034 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4981 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 847884 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337496 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352094 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4719 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2286 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833265 # number of overall hits +system.l2c.overall_hits::cpu0.data 319034 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4981 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847884 # number of overall hits +system.l2c.overall_hits::cpu1.data 337496 # number of overall hits +system.l2c.overall_hits::total 2352094 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10795 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9750 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 7563 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5779 # number of ReadReq misses +system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63970 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83894 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10795 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73720 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89673 # number of demand (read+write) misses +system.l2c.demand_misses::total 181759 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10795 # number of overall misses +system.l2c.overall_misses::cpu0.data 73720 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7563 # number of overall misses +system.l2c.overall_misses::cpu1.data 89673 # number of overall misses +system.l2c.overall_misses::total 181759 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4724 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2287 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844060 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 256459 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4983 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 855447 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 264557 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2234946 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682260 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682260 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1261 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 136295 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162612 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4724 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2287 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844060 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392754 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4983 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855447 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427169 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533853 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4724 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2287 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844060 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392754 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4983 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855447 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427169 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533853 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.012789 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038018 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008841 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021844 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989298 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469350 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515915 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012789 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187700 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008841 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209924 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012789 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187700 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008841 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209924 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 101893 # number of writebacks +system.l2c.writebacks::total 101893 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 74229 # Transaction distribution +system.membus.trans_dist::ReadResp 74229 # Transaction distribution +system.membus.trans_dist::WriteReq 27560 # Transaction distribution +system.membus.trans_dist::WriteResp 27560 # Transaction distribution +system.membus.trans_dist::Writeback 101893 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution +system.membus.trans_dist::ReadExReq 146085 # Transaction distribution +system.membus.trans_dist::ReadExResp 146085 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498777 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 606179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679107 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18258755 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20592451 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 322846 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 322846 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 322846 # Request fanout histogram +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 2291800 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291800 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682260 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417092 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444886 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20766 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41566 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5924310 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96322507 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41532 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83132 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205252795 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 36632 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3272095 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3235631 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3272095 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 092eed50c..36c2b5576 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.438275 # Number of seconds simulated -sim_ticks 47438274662000 # Number of ticks simulated -final_tick 47438274662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.566016 # Number of seconds simulated +sim_ticks 47566015848000 # Number of ticks simulated +final_tick 47566015848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 649244 # Simulator instruction rate (inst/s) -host_op_rate 763603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34889420828 # Simulator tick rate (ticks/s) -host_mem_usage 811016 # Number of bytes of host memory used -host_seconds 1359.68 # Real time elapsed on the host -sim_insts 882760938 # Number of instructions simulated -sim_ops 1038251286 # Number of ops (including micro ops) simulated +host_inst_rate 675626 # Simulator instruction rate (inst/s) +host_op_rate 794684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35963293075 # Simulator tick rate (ticks/s) +host_mem_usage 873656 # Number of bytes of host memory used +host_seconds 1322.63 # Real time elapsed on the host +sim_insts 893600449 # Number of instructions simulated +sim_ops 1051070162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 477376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 221952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 405952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 701748 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13046680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 27196672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 278976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 430208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 568824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13928160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 27822464 # Number of bytes read from this memory -system.physmem.bytes_read::total 85079012 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 701748 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 568824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1270572 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 44376640 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 54965772 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 45117316 # Number of bytes written to this memory -system.physmem.bytes_written::total 151290320 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 7459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 3468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 51372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 203876 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 424948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4359 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 6722 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8976 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 217642 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 434726 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1369891 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 693385 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 861117 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 704959 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2366189 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 10063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 4679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 8557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 14793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 275024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 573307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 5881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 9069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 293606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 586498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1793468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 14793 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 26784 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 935461 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 143989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1158680 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 951074 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3189204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 935461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 154052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 8557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 14793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1433704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 573307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 5881 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 9069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1244680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 586498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4982671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1369891 # Number of read requests accepted -system.physmem.writeReqs 2366189 # Number of write requests accepted -system.physmem.readBursts 1369891 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2366189 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 87382976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 290048 # Total number of bytes read from write queue -system.physmem.bytesWritten 145690880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 85079012 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 151290320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4532 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 89741 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 95337 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 80179 # Per bank write bursts -system.physmem.perBankRdBursts::1 81898 # Per bank write bursts -system.physmem.perBankRdBursts::2 76695 # Per bank write bursts -system.physmem.perBankRdBursts::3 88857 # Per bank write bursts -system.physmem.perBankRdBursts::4 82614 # Per bank write bursts -system.physmem.perBankRdBursts::5 89869 # Per bank write bursts -system.physmem.perBankRdBursts::6 79228 # Per bank write bursts -system.physmem.perBankRdBursts::7 87605 # Per bank write bursts -system.physmem.perBankRdBursts::8 77754 # Per bank write bursts -system.physmem.perBankRdBursts::9 127975 # Per bank write bursts -system.physmem.perBankRdBursts::10 81231 # Per bank write bursts -system.physmem.perBankRdBursts::11 85621 # Per bank write bursts -system.physmem.perBankRdBursts::12 74411 # Per bank write bursts -system.physmem.perBankRdBursts::13 85967 # Per bank write bursts -system.physmem.perBankRdBursts::14 83368 # Per bank write bursts -system.physmem.perBankRdBursts::15 82087 # Per bank write bursts -system.physmem.perBankWrBursts::0 134695 # Per bank write bursts -system.physmem.perBankWrBursts::1 125793 # Per bank write bursts -system.physmem.perBankWrBursts::2 142260 # Per bank write bursts -system.physmem.perBankWrBursts::3 126417 # Per bank write bursts -system.physmem.perBankWrBursts::4 155026 # Per bank write bursts -system.physmem.perBankWrBursts::5 152020 # Per bank write bursts -system.physmem.perBankWrBursts::6 183109 # Per bank write bursts -system.physmem.perBankWrBursts::7 140837 # Per bank write bursts -system.physmem.perBankWrBursts::8 128222 # Per bank write bursts -system.physmem.perBankWrBursts::9 141420 # Per bank write bursts -system.physmem.perBankWrBursts::10 135722 # Per bank write bursts -system.physmem.perBankWrBursts::11 146309 # Per bank write bursts -system.physmem.perBankWrBursts::12 139215 # Per bank write bursts -system.physmem.perBankWrBursts::13 127398 # Per bank write bursts -system.physmem.perBankWrBursts::14 153454 # Per bank write bursts -system.physmem.perBankWrBursts::15 144523 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 233408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 408704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 743028 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13616152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 28206528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 271488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 437568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 534776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13513568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 26761152 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 461312 # Number of bytes read from this memory +system.physmem.bytes_read::total 85187684 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 743028 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 534776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1277804 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 43935424 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 56825292 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 43859652 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6846976 # Number of bytes written to this memory +system.physmem.bytes_written::total 151467344 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3647 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 6386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 52017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 212774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 440727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 6837 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 8444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 211164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 418143 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7208 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1371589 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 686491 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 890172 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 685308 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106984 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2368955 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 8592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 15621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 286258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 592997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 5708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 9199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 284101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 562611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1790936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 15621 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11243 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 26864 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 923673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 1194662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 922080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 143947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3184361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 923673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 8592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 15621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1480920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 592997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 5708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 9199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11243 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1206181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 562611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 153645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4975296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1371589 # Number of read requests accepted +system.physmem.writeReqs 2368955 # Number of write requests accepted +system.physmem.readBursts 1371589 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2368955 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 87480576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 301120 # Total number of bytes read from write queue +system.physmem.bytesWritten 145871552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 85187684 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 151467344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4705 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 89687 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 96177 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 85059 # Per bank write bursts +system.physmem.perBankRdBursts::1 83413 # Per bank write bursts +system.physmem.perBankRdBursts::2 77756 # Per bank write bursts +system.physmem.perBankRdBursts::3 83623 # Per bank write bursts +system.physmem.perBankRdBursts::4 79267 # Per bank write bursts +system.physmem.perBankRdBursts::5 92440 # Per bank write bursts +system.physmem.perBankRdBursts::6 79265 # Per bank write bursts +system.physmem.perBankRdBursts::7 88179 # Per bank write bursts +system.physmem.perBankRdBursts::8 75468 # Per bank write bursts +system.physmem.perBankRdBursts::9 124700 # Per bank write bursts +system.physmem.perBankRdBursts::10 77875 # Per bank write bursts +system.physmem.perBankRdBursts::11 89966 # Per bank write bursts +system.physmem.perBankRdBursts::12 78954 # Per bank write bursts +system.physmem.perBankRdBursts::13 87199 # Per bank write bursts +system.physmem.perBankRdBursts::14 85039 # Per bank write bursts +system.physmem.perBankRdBursts::15 78681 # Per bank write bursts +system.physmem.perBankWrBursts::0 146127 # Per bank write bursts +system.physmem.perBankWrBursts::1 131230 # Per bank write bursts +system.physmem.perBankWrBursts::2 144620 # Per bank write bursts +system.physmem.perBankWrBursts::3 127213 # Per bank write bursts +system.physmem.perBankWrBursts::4 148937 # Per bank write bursts +system.physmem.perBankWrBursts::5 150009 # Per bank write bursts +system.physmem.perBankWrBursts::6 182023 # Per bank write bursts +system.physmem.perBankWrBursts::7 144700 # Per bank write bursts +system.physmem.perBankWrBursts::8 124458 # Per bank write bursts +system.physmem.perBankWrBursts::9 140305 # Per bank write bursts +system.physmem.perBankWrBursts::10 119798 # Per bank write bursts +system.physmem.perBankWrBursts::11 155853 # Per bank write bursts +system.physmem.perBankWrBursts::12 153554 # Per bank write bursts +system.physmem.perBankWrBursts::13 129042 # Per bank write bursts +system.physmem.perBankWrBursts::14 144270 # Per bank write bursts +system.physmem.perBankWrBursts::15 137104 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 47438271681000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 47566012867000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1326654 # Read request sizes (log2) +system.physmem.readPktSize::6 1328352 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2363586 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 850336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 158236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 84690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 51684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 44428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2366352 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 854051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 158360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 84564 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 51448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 44074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 25068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1973 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -191,156 +191,157 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 89049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 97576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 118285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 123036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 124126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 148935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 128713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 131381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 133864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 133437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 132728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 131540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 133641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 128245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 124149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 123411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 120132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 89303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 97776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 118763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 123056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 124315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 149365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 133979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 128880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 131405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 133820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 133411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 132599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 131583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 133798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 128352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 124285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 123534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 120195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 831449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.321107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.348246 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.173071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 412387 49.60% 49.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 160013 19.25% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 57469 6.91% 75.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 29190 3.51% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24961 3.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16130 1.94% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12424 1.49% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 12438 1.50% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 106437 12.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 831449 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 117879 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.582360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 193.016425 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 117876 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 832768 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.211728 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.211424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.275385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 413524 49.66% 49.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 160093 19.22% 68.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 57236 6.87% 75.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 29306 3.52% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24972 3.00% 82.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16042 1.93% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12534 1.51% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 12228 1.47% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 106833 12.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 832768 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 117976 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 11.586017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 192.972695 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 117973 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 117879 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 117879 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.311497 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.988433 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.874271 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 75351 63.92% 63.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 36700 31.13% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3007 2.55% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 902 0.77% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 786 0.67% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 199 0.17% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 149 0.13% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 77 0.07% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 81 0.07% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 117976 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 117976 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.319548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.993188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.933657 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 75459 63.96% 63.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 36712 31.12% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3025 2.56% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 865 0.73% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 773 0.66% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 198 0.17% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 143 0.12% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 73 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 88 0.07% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.02% 99.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 14 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 396 0.34% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 29 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 39 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.01% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 383 0.32% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.04% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 22 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 47 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 46 0.04% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 10 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 9 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 6 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 117879 # Writes before turning the bus around for reads -system.physmem.totQLat 39355914512 # Total ticks spent queuing -system.physmem.totMemAccLat 64956395762 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6826795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28824.59 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 117976 # Writes before turning the bus around for reads +system.physmem.totQLat 39242427762 # Total ticks spent queuing +system.physmem.totMemAccLat 64871502762 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6834420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28709.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47574.59 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47459.41 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.79 # Average write queue length when enqueuing -system.physmem.readRowHits 1064531 # Number of row buffer hits during reads -system.physmem.writeRowHits 1745793 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.69 # Row buffer hit rate for writes -system.physmem.avgGap 12697338.30 # Average gap between requests -system.physmem.pageHitRate 77.17 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45390521349500 # Time in different power states -system.physmem.memoryStateTime::REF 1584068200000 # Time in different power states +system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing +system.physmem.readRowHits 1063781 # Number of row buffer hits during reads +system.physmem.writeRowHits 1749574 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes +system.physmem.avgGap 12716335.61 # Average gap between requests +system.physmem.pageHitRate 77.16 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45509072189751 # Time in different power states +system.physmem.memoryStateTime::REF 1588333760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 463683887500 # Time in different power states +system.physmem.memoryStateTime::ACT 468608703999 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3148966800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3136780080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1718186250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1711536750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5202085200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5447566800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 7517817360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 7233384240 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3098437399200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3098437399200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1260445205745 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1262996298315 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27357310364250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27355072563750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31733780024805 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31734035529135 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.948883 # Core power per rank (mW) -system.physmem.averagePower::1 668.954269 # Core power per rank (mW) +system.physmem.actEnergy::0 3171472920 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3124253160 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1730466375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1704701625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 5218192200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 5443409400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 7613086320 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 7156408320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3106780834560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3106780834560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1266482203425 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1265693181210 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27428659482750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27429351607500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31819655738550 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31819254395775 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.957784 # Core power per rank (mW) +system.physmem.averagePower::1 668.949346 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -367,772 +368,13 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1262651 # Transaction distribution -system.membus.trans_dist::ReadResp 1262651 # Transaction distribution -system.membus.trans_dist::WriteReq 38160 # Transaction distribution -system.membus.trans_dist::WriteResp 38160 # Transaction distribution -system.membus.trans_dist::Writeback 693385 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1670201 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1670201 # Transaction distribution -system.membus.trans_dist::UpgradeReq 307572 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 298715 # Transaction distribution -system.membus.trans_dist::UpgradeResp 95343 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 162530 # Transaction distribution -system.membus.trans_dist::ReadExResp 146943 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7267614 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 7415090 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7644986 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229061364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 229266359 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7307968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7307968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 236574327 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 528061 # Total snoops (count) -system.membus.snoop_fanout::samples 4313648 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4313648 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4313648 # Request fanout histogram -system.membus.reqLayer0.occupancy 100869991 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21144997 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 23127462719 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 14206266380 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187834022 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 1088949 # number of replacements -system.l2c.tags.tagsinuse 64239.358232 # Cycle average of tags in use -system.l2c.tags.total_refs 6591556 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1149786 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.732855 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9309.879147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 38.225449 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 41.200627 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 627.976202 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3676.898634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16318.952466 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 311.035795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 436.956601 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 693.970644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9626.822610 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 23157.440058 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.142057 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000583 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000629 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.009582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.056105 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.249007 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004746 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006667 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010589 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.146894 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.353354 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.980215 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32295 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 314 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 28228 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 137 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 836 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1678 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29623 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1122 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4068 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 22816 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.492783 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004791 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.430725 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79894517 # Number of tag accesses -system.l2c.tags.data_accesses 79894517 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5969 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3906 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 130836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 569496 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1489116 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4630 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 144360 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 647503 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1630669 # number of ReadReq hits -system.l2c.ReadReq_hits::total 4632835 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1982686 # number of Writeback hits -system.l2c.Writeback_hits::total 1982686 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 22177 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 28734 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 50911 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6966 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8106 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15072 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48437 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 51237 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 99674 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5969 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3906 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 130836 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 617933 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1489116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4630 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 144360 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 698740 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1630669 # number of demand (read+write) hits -system.l2c.demand_hits::total 4732509 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5969 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3906 # number of overall hits -system.l2c.overall_hits::cpu0.inst 130836 # number of overall hits -system.l2c.overall_hits::cpu0.data 617933 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1489116 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6350 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4630 # number of overall hits -system.l2c.overall_hits::cpu1.inst 144360 # number of overall hits -system.l2c.overall_hits::cpu1.data 698740 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1630669 # number of overall hits -system.l2c.overall_hits::total 4732509 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3468 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6343 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8294 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 128231 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 425212 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4359 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 6722 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 8893 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 146336 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 434855 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1172713 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 33912 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 36287 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 70199 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10020 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11790 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21810 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77130 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73144 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 150274 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3468 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 6343 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8294 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 205361 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 425212 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4359 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 6722 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8893 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 219480 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 434855 # number of demand (read+write) misses -system.l2c.demand_misses::total 1322987 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3468 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 6343 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8294 # number of overall misses -system.l2c.overall_misses::cpu0.data 205361 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 425212 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4359 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 6722 # number of overall misses -system.l2c.overall_misses::cpu1.inst 8893 # number of overall misses -system.l2c.overall_misses::cpu1.data 219480 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 434855 # number of overall misses -system.l2c.overall_misses::total 1322987 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 277093747 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 508086991 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 728511746 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 10412911614 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 44677211677 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 344069994 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 530104242 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 794513741 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 11896672640 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 46121255625 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 116290432017 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 136371763 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 151914842 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 288286605 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46986513 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56444140 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 103430653 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5663882239 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5345531625 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11009413864 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 277093747 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 508086991 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 728511746 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 16076793853 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 44677211677 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 344069994 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 530104242 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 794513741 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 17242204265 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 46121255625 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 127299845881 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 277093747 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 508086991 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 728511746 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 16076793853 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 44677211677 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 344069994 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 530104242 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 794513741 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 17242204265 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 46121255625 # number of overall miss cycles -system.l2c.overall_miss_latency::total 127299845881 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9437 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10249 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 139130 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 697727 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 1914328 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10709 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 11352 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 153253 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 793839 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2065524 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 5805548 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1982686 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1982686 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 56089 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 65021 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 121110 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 16986 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 19896 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 36882 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 125567 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 124381 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249948 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9437 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10249 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 139130 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 823294 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 1914328 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10709 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 11352 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 153253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 918220 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2065524 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 6055496 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9437 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10249 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 139130 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 823294 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 1914328 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10709 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 11352 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 153253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 918220 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2065524 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 6055496 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.367490 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.618890 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.059613 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.183784 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.222121 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.407041 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.592142 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.058028 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.184340 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.210530 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.201999 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.604611 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.558081 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.579630 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.589898 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.592581 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.591345 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.614254 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.588064 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.601221 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.367490 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.618890 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.059613 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.249438 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.222121 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.407041 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.592142 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.058028 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.239028 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.210530 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.218477 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.367490 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.618890 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.059613 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.249438 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.222121 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.407041 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.592142 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.058028 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.239028 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.210530 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.218477 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79900.157728 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 80102.000788 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87835.995418 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 81204.323557 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78933.240193 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78861.089259 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 89341.475430 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 81296.964793 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 99163.590765 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4021.342386 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4186.481164 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4106.705295 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4689.272754 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4787.458863 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4742.349977 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73432.934513 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73082.298275 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73262.266686 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79900.157728 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80102.000788 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 87835.995418 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 78285.525747 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78933.240193 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 78861.089259 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 89341.475430 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 78559.341466 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 96221.539502 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79900.157728 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80102.000788 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 87835.995418 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 78285.525747 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78933.240193 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 78861.089259 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 89341.475430 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 78559.341466 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 96221.539502 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 1844 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 53 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 34.792453 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 693385 # number of writebacks -system.l2c.writebacks::total 693385 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 14 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 264 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 129 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 458 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 264 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 129 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 458 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 264 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 129 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 458 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3468 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6343 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 8271 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 128217 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 424948 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4359 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6722 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 8882 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 146319 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 434726 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 1172255 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 33912 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 36287 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 70199 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10020 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11790 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 21810 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 77130 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73144 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 150274 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3468 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 6343 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8271 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 205347 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 424948 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4359 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 6722 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 8882 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 219463 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 434726 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1322529 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3468 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 6343 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8271 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 205347 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 424948 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4359 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 6722 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 8882 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 219463 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 434726 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1322529 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 234005247 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 429405991 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 623644746 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8803657420 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39426586681 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 289785494 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 446560742 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 682991749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 10059247700 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40752439135 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 101748324905 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17202577789 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 14155732856 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 31358310645 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 344397419 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 367876069 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 712273488 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 102095388 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 120655634 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 222751022 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4691101701 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4422988801 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9114090502 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 234005247 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 429405991 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 623644746 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 13494759121 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39426586681 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 289785494 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 446560742 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 682991749 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 14482236501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 40752439135 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 110862415407 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 234005247 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 429405991 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 623644746 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 13494759121 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39426586681 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 289785494 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 446560742 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 682991749 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 14482236501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40752439135 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 110862415407 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1998253750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5835000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3361097750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7611383750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2007075001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3246096000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5253171001 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4005328751 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5835000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6607193750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12864554751 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.183764 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.184318 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.201920 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.604611 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.558081 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.579630 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.589898 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592581 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591345 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.614254 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.588064 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.601221 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.249421 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.239009 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.218401 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.249421 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.239009 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.218401 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68662.169759 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68748.745549 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 86797.091849 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10155.620990 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10137.957643 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10146.490520 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10189.160479 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10233.726378 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10213.251811 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60820.714391 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60469.605176 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60649.816349 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65716.855474 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65989.421912 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 83826.075199 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65716.855474 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65989.421912 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 83826.075199 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 6645186 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 6637629 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38160 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38160 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1982686 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1563473 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 355152 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 313787 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 668939 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297718 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297718 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9432330 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9652916 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 19085246 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302653655 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 312342176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 614995831 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1425200 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 11183456 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010347 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.101194 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11067738 98.97% 98.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115718 1.03% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 11183456 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 19814172733 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 6396000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15605521398 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 16621378743 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40465 # Transaction distribution -system.iobus.trans_dist::ReadResp 40465 # Transaction distribution -system.iobus.trans_dist::WriteReq 136732 # Transaction distribution -system.iobus.trans_dist::WriteResp 136786 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231338 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231338 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354502 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497645 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36603000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 981958721 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93029000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179341978 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1156,25 +398,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 81279666 # DTB read hits -system.cpu0.dtb.read_misses 78948 # DTB read misses -system.cpu0.dtb.write_hits 73742535 # DTB write hits -system.cpu0.dtb.write_misses 27290 # DTB write misses +system.cpu0.dtb.read_hits 86716512 # DTB read hits +system.cpu0.dtb.read_misses 82712 # DTB read misses +system.cpu0.dtb.write_hits 78633728 # DTB write hits +system.cpu0.dtb.write_misses 28389 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 31886 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34135 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3595 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4682 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8523 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 81358614 # DTB read accesses -system.cpu0.dtb.write_accesses 73769825 # DTB write accesses +system.cpu0.dtb.perms_faults 9159 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86799224 # DTB read accesses +system.cpu0.dtb.write_accesses 78662117 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 155022201 # DTB hits -system.cpu0.dtb.misses 106238 # DTB misses -system.cpu0.dtb.accesses 155128439 # DTB accesses +system.cpu0.dtb.hits 165350240 # DTB hits +system.cpu0.dtb.misses 111101 # DTB misses +system.cpu0.dtb.accesses 165461341 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1196,141 +438,342 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 432012599 # ITB inst hits -system.cpu0.itb.inst_misses 54786 # ITB inst misses +system.cpu0.itb.inst_hits 459685693 # ITB inst hits +system.cpu0.itb.inst_misses 60045 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 22623 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24187 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 432067385 # ITB inst accesses -system.cpu0.itb.hits 432012599 # DTB hits -system.cpu0.itb.misses 54786 # DTB misses -system.cpu0.itb.accesses 432067385 # DTB accesses -system.cpu0.numCycles 94876549324 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 459745738 # ITB inst accesses +system.cpu0.itb.hits 459685693 # DTB hits +system.cpu0.itb.misses 60045 # DTB misses +system.cpu0.itb.accesses 459745738 # DTB accesses +system.cpu0.numCycles 95132031682 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 431769250 # Number of instructions committed -system.cpu0.committedOps 507110651 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 465722099 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 423380 # Number of float alu accesses -system.cpu0.num_func_calls 25579239 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 65525116 # number of instructions that are conditional controls -system.cpu0.num_int_insts 465722099 # number of integer instructions -system.cpu0.num_fp_insts 423380 # number of float instructions -system.cpu0.num_int_register_reads 674979358 # number of times the integer registers were read -system.cpu0.num_int_register_writes 369311745 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 705560 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 308536 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 112703400 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 112387692 # number of times the CC registers were written -system.cpu0.num_mem_refs 155012297 # number of memory refs -system.cpu0.num_load_insts 81273219 # Number of load instructions -system.cpu0.num_store_insts 73739078 # Number of store instructions -system.cpu0.num_idle_cycles 93821929037.552032 # Number of idle cycles -system.cpu0.num_busy_cycles 1054620286.447978 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011116 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988884 # Percentage of idle cycles -system.cpu0.Branches 96363585 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 351187949 69.21% 69.21% # Class of executed instruction -system.cpu0.op_class::IntMult 1094457 0.22% 69.43% # Class of executed instruction -system.cpu0.op_class::IntDiv 58568 0.01% 69.44% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 43852 0.01% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::MemRead 81273219 16.02% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 73739078 14.53% 100.00% # Class of executed instruction +system.cpu0.committedInsts 459439593 # Number of instructions committed +system.cpu0.committedOps 539347874 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 495403687 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 451172 # Number of float alu accesses +system.cpu0.num_func_calls 27064307 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 69711991 # number of instructions that are conditional controls +system.cpu0.num_int_insts 495403687 # number of integer instructions +system.cpu0.num_fp_insts 451172 # number of float instructions +system.cpu0.num_int_register_reads 715734727 # number of times the integer registers were read +system.cpu0.num_int_register_writes 392523746 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 749199 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 337216 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 119686995 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 119275623 # number of times the CC registers were written +system.cpu0.num_mem_refs 165340768 # number of memory refs +system.cpu0.num_load_insts 86711184 # Number of load instructions +system.cpu0.num_store_insts 78629584 # Number of store instructions +system.cpu0.num_idle_cycles 94014587829.536469 # Number of idle cycles +system.cpu0.num_busy_cycles 1117443852.463529 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011746 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988254 # Percentage of idle cycles +system.cpu0.Branches 102470244 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 373021399 69.12% 69.12% # Class of executed instruction +system.cpu0.op_class::IntMult 1165287 0.22% 69.34% # Class of executed instruction +system.cpu0.op_class::IntDiv 62749 0.01% 69.35% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 46895 0.01% 69.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction +system.cpu0.op_class::MemRead 86711184 16.07% 85.43% # Class of executed instruction +system.cpu0.op_class::MemWrite 78629584 14.57% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 507397124 # Class of executed instruction +system.cpu0.op_class::total 539637098 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5117 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 4835795 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.921057 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 427176292 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4836307 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.326959 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 5368 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5553236 # number of replacements +system.cpu0.dcache.tags.tagsinuse 507.463915 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 159572063 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5553747 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.732325 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.463915 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991140 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.991140 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 336276505 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 336276505 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80841388 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80841388 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 74354122 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 74354122 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186421 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 186421 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 887570 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 887570 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1858688 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1858688 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1820106 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1820106 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 155195510 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155195510 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155381931 # number of overall hits +system.cpu0.dcache.overall_hits::total 155381931 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3020518 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3020518 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1355895 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1355895 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 638649 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 638649 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156836 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 156836 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194186 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 194186 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4376413 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4376413 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5015062 # number of overall misses +system.cpu0.dcache.overall_misses::total 5015062 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44235181893 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 44235181893 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23644478419 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 23644478419 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2243299062 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2243299062 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4135736633 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4135736633 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1563000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1563000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 67879660312 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 67879660312 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 67879660312 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 67879660312 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83861906 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83861906 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 75710017 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 75710017 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 825070 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 825070 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 887570 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 887570 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015524 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2015524 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014292 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2014292 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 159571923 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 159571923 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 160396993 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 160396993 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036018 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036018 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774054 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774054 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077814 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077814 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096404 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096404 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027426 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027426 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031267 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031267 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14644.899283 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14644.899283 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17438.281297 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17438.281297 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14303.470262 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14303.470262 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21297.810517 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21297.810517 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15510.341531 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15510.341531 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13535.158750 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13535.158750 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 887570 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3048439 # number of writebacks +system.cpu0.dcache.writebacks::total 3048439 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28957 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 28957 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21342 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21342 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43075 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43075 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 50299 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 50299 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 50299 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 50299 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2991561 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2991561 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1334553 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1334553 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 637409 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 637409 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113761 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113761 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194186 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 194186 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4326114 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4326114 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4963523 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4963523 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36853741584 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 36853741584 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 20599874090 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 20599874090 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14249969925 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14249969925 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 39555111210 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39555111210 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1322683967 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1322683967 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3736995367 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3736995367 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1491000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1491000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 57453615674 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 57453615674 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 71703585599 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 71703585599 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2269904707 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2269904707 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2228690449 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2228690449 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4498595156 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4498595156 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035672 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035672 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017627 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017627 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.772551 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.772551 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056442 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056442 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096404 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096404 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027111 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027111 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030945 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030945 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.234535 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.234535 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15435.785683 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15435.785683 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22356.085222 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22356.085222 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11626.866562 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11626.866562 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19244.411889 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19244.411889 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13280.652261 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13280.652261 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14446.107251 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14446.107251 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 5136279 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.921269 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 454548902 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5136791 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.488884 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 24248022750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.921057 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.921269 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999846 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 868861505 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 868861505 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 427176292 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 427176292 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 427176292 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 427176292 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 427176292 # number of overall hits -system.cpu0.icache.overall_hits::total 427176292 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4836307 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4836307 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4836307 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4836307 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4836307 # number of overall misses -system.cpu0.icache.overall_misses::total 4836307 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 42021880066 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 42021880066 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 42021880066 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 42021880066 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 42021880066 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 42021880066 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 432012599 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 432012599 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 432012599 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 432012599 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 432012599 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 432012599 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011195 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011195 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011195 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011195 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011195 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011195 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8688.836351 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8688.836351 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8688.836351 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8688.836351 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 924508177 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 924508177 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 454548902 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 454548902 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 454548902 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 454548902 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 454548902 # number of overall hits +system.cpu0.icache.overall_hits::total 454548902 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5136791 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5136791 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5136791 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5136791 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5136791 # number of overall misses +system.cpu0.icache.overall_misses::total 5136791 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 44728233484 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 44728233484 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 44728233484 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 44728233484 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 44728233484 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 44728233484 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 459685693 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 459685693 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 459685693 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 459685693 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 459685693 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 459685693 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011175 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011175 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011175 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011175 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011175 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011175 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8707.427163 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8707.427163 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8707.427163 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8707.427163 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8707.427163 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8707.427163 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1339,366 +782,365 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4836307 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4836307 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4836307 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4836307 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4836307 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4836307 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34764760966 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 34764760966 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34764760966 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 34764760966 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34764760966 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 34764760966 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5136791 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5136791 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5136791 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5136791 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5136791 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5136791 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 37020068050 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 37020068050 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 37020068050 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 37020068050 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 37020068050 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 37020068050 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011195 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011195 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7188.286634 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7188.286634 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7188.286634 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011175 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011175 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011175 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7206.847242 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7206.847242 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7206.847242 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 44883381 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 769766 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 41733922 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 7731 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 47709911 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 798067 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 44351595 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8146 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 460 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2371502 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3699891 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 467 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2551636 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3941553 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 2933552 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16178.968525 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 10401290 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2949711 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.526206 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 3159231 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16263.767973 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 10999510 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3175316 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.464068 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 20647851500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 3715.452521 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.338628 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 40.195819 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 822.456727 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3056.932991 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8502.591837 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.226773 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002523 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002453 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.050199 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.186580 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.518957 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.987486 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8877 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7233 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 49 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 502 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2719 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3687 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1920 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2913 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2975 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 925 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.541809 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.441467 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 228304892 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 228304892 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 221810 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122090 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4672690 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2607787 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 7624377 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 2894821 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 2894821 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 81724 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 81724 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31053 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 31053 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 866415 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 866415 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 221810 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122090 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4672690 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3474202 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8490792 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 221810 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122090 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4672690 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3474202 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8490792 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12355 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10686 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 163617 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 944935 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1131593 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 105877 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 105877 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154791 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 154791 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 220288 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 220288 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12355 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10686 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 163617 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1165223 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1351881 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12355 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10686 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 163617 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1165223 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1351881 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 518388959 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 691109452 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 4288633088 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 30316279776 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 35814411275 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2067273148 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2067273148 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3132681305 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3132681305 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1841998 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1841998 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10252738120 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 10252738120 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 518388959 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 691109452 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4288633088 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 40569017896 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 46067149395 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 518388959 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 691109452 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4288633088 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 40569017896 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 46067149395 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 234165 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 132776 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4836307 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3552722 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 8755970 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 2894821 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 2894821 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 187601 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 187601 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 185844 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 185844 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1086703 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1086703 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 234165 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 132776 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 4836307 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4639425 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 9842673 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 234165 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 132776 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 4836307 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4639425 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 9842673 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.052762 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.080481 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.033831 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.265975 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.129237 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.564373 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.564373 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.832908 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.832908 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 3883.106993 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 48.905367 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.754013 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 900.341601 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2586.177603 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8789.482396 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.237006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002985 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003403 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.054952 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.157848 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.536467 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.992662 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8304 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 112 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7669 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 44 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 543 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2171 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5264 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 282 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 59 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3430 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3305 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 150 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.506836 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006836 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.468079 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 240919913 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 240919913 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 231031 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 134927 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4959117 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2742170 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 8067245 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3048439 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3048439 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 86825 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 86825 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33826 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 33826 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 910939 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 910939 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 231031 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 134927 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4959117 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3653109 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8978184 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 231031 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 134927 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4959117 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3653109 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8978184 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12665 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11145 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 177674 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 1000560 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1202044 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 109590 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 109590 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160357 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 160357 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 232216 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 232216 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12665 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 11145 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 177674 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1232776 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1434260 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12665 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 11145 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 177674 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1232776 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1434260 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 536996706 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 703824955 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 4673573829 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32218538016 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 38132933506 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2159798630 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2159798630 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3254740509 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3254740509 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1454999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1454999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10558981803 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 10558981803 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 536996706 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 703824955 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4673573829 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 42777519819 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 48691915309 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 536996706 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 703824955 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4673573829 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 42777519819 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 48691915309 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 243696 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 146072 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5136791 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3742730 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 9269289 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3048439 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3048439 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 196415 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 196415 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194183 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 194183 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1143155 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1143155 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 243696 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146072 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5136791 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4885885 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 10412444 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 243696 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 146072 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5136791 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4885885 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 10412444 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.051970 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.076298 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.034589 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267334 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.129680 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.557951 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.557951 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.825803 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.825803 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.202712 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.202712 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.052762 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.080481 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.033831 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.251157 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.137349 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.052762 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.080481 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.033831 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.251157 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.137349 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 41957.827519 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 64674.288976 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26211.415000 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32082.926102 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31649.551804 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19525.233507 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19525.233507 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20238.135970 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20238.135970 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 306999.666667 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 306999.666667 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46542.426823 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46542.426823 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 41957.827519 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 64674.288976 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26211.415000 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34816.526876 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 34076.334674 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 41957.827519 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 64674.288976 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26211.415000 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34816.526876 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 34076.334674 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 9451 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.203136 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.203136 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.051970 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.076298 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034589 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252314 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.137745 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.051970 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.076298 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034589 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.252314 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.137745 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42400.055744 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 63151.633468 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26304.207869 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32200.505733 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31723.409048 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19707.990054 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19707.990054 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20296.840855 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20296.840855 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 484999.666667 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 484999.666667 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45470.517979 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45470.517979 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42400.055744 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 63151.633468 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26304.207869 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34700.156248 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 33949.155180 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42400.055744 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 63151.633468 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26304.207869 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34700.156248 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 33949.155180 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 12605 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 232 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 256 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 40.737069 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 49.238281 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 969387 # number of writebacks -system.cpu0.l2cache.writebacks::total 969387 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 24596 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 5208 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 29804 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5052 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 5052 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 24596 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10260 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 34856 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 24596 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10260 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 34856 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12355 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10686 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 139021 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 939727 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1101789 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 2371413 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 2371413 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 105877 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 105877 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 154791 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 154791 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 215236 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 215236 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12355 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10686 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 139021 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1154963 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1317025 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12355 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10686 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 139021 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1154963 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 2371413 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 3688438 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 431221053 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 615215054 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2925869007 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 23536761675 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 27509066789 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 70751604946 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 70751604946 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31819773244 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 31819773244 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1812194258 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1812194258 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2134733797 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2134733797 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1512998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1512998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8195268769 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8195268769 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 431221053 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 615215054 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2925869007 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 31732030444 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 35704335558 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 431221053 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 615215054 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2925869007 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 31732030444 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 70751604946 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 106455940504 # number of overall MSHR miss cycles +system.cpu0.l2cache.writebacks::writebacks 1033934 # number of writebacks +system.cpu0.l2cache.writebacks::total 1033934 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 26777 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 5375 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 32152 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4949 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 4949 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 26777 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10324 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 37101 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 26777 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10324 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 37101 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12665 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11145 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 150897 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 995185 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1169892 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 2551548 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 2551548 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 109590 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 109590 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 160357 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 160357 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 227267 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 227267 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12665 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11145 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 150897 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1222452 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1397159 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12665 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11145 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 150897 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1222452 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 2551548 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 3948707 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 447628804 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 624653553 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 3182608268 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25035600452 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 29290491077 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 74439584886 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 74439584886 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 32897037766 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 32897037766 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1861391719 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1861391719 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2218823079 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2218823079 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1202999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1202999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8430579619 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8430579619 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 447628804 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 624653553 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3182608268 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 33466180071 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 37721070696 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 447628804 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 624653553 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3182608268 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 33466180071 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 74439584886 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 112160655582 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2263304784 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5325169534 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2282603541 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2282603541 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2157592792 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5219457542 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2114914551 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2114914551 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4545908325 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7607773075 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.052762 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.080481 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.028745 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.264509 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.125833 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4272507343 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7334372093 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.265898 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.126212 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.564373 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.564373 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832908 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832908 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.557951 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.557951 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.825803 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825803 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.198063 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.198063 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.052762 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.080481 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.028745 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248945 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.133808 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.052762 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.080481 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.028745 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248945 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.198807 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.198807 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.250201 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134182 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.250201 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.374739 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25046.382274 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24967.636080 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29835.210040 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29835.210040 # average HardPFReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.379230 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25156.730107 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25036.918858 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29174.283567 # average HardPFReq mshr miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17116.033303 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17116.033303 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13791.071813 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13791.071813 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 252166.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 252166.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38075.734399 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38075.734399 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27474.499568 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27109.838885 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27474.499568 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29835.210040 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28862.065867 # average overall mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16985.050817 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16985.050817 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13836.770949 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13836.770949 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400999.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37095.485130 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37095.485130 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26998.409412 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28404.400626 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1708,259 +1150,58 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 5282593 # number of replacements -system.cpu0.dcache.tags.tagsinuse 478.557100 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149517101 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5283105 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.300990 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.557100 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934682 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.934682 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 411 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 315346998 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 315346998 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75666916 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75666916 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69634196 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69634196 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181888 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 181888 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 858515 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 858515 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1792597 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1792597 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1751129 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1751129 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 145301112 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 145301112 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 145483000 # number of overall hits -system.cpu0.dcache.overall_hits::total 145483000 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2868190 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2868190 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1290634 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1290634 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 609921 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 609921 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145533 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 145533 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 185941 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 185941 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4158824 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4158824 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4768745 # number of overall misses -system.cpu0.dcache.overall_misses::total 4768745 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41686378389 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41686378389 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22767469365 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 22767469365 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2114986821 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2114986821 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3970270831 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3970270831 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1983000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1983000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 64453847754 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 64453847754 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 64453847754 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 64453847754 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78535106 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78535106 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 70924830 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 70924830 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 791809 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 791809 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 858515 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 858515 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1938130 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1938130 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1937070 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1937070 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149459936 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149459936 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150251745 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150251745 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036521 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036521 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018197 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018197 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770288 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770288 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075089 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.075089 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027826 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031738 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031738 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14534.036584 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14534.036584 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17640.531216 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17640.531216 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14532.695822 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14532.695822 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21352.315148 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21352.315148 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15498.094595 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15498.094595 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13515.893124 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13515.893124 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 858515 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 2894821 # number of writebacks -system.cpu0.dcache.writebacks::total 2894821 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28163 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 28163 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21327 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21327 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41518 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41518 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 49490 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 49490 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 49490 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 49490 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2840027 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2840027 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1269307 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1269307 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 608681 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 608681 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104015 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104015 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185850 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 185850 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4109334 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4109334 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4718015 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4718015 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34673571058 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34673571058 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 19854321886 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19854321886 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13611528726 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13611528726 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 38259906745 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 38259906745 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1241876461 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1241876461 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3588911169 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3588911169 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1889000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1889000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 54527892944 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 54527892944 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68139421670 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 68139421670 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2380477468 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2380477468 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2403593708 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2403593708 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4784071176 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4784071176 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036163 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036163 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017897 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017897 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768722 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768722 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095944 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095944 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027495 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027495 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031401 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031401 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12208.887823 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12208.887823 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15641.859602 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15641.859602 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22362.335486 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22362.335486 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11939.397789 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11939.397789 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19310.794560 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19310.794560 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13269.277441 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13269.277441 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14442.391911 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14442.391911 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 12330313 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9009509 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 16126 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16126 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 2894821 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 3465295 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 858515 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 371533 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344881 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 439023 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1234519 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1094177 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9758864 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14862906 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296442 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542592 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 25460804 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 309696148 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 543504195 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1062208 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1873320 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 856135871 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8448176 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 22253887 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.367543 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.482136 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 12709886 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9530898 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15163 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15163 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3048439 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 3732092 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 887570 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 380241 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 457079 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1289201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1150842 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10359832 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15601688 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 325277 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 566209 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 26853006 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 328927124 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 571100341 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1168576 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1949568 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 903145609 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 8562261 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 23134597 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.358060 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.479430 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 14074632 63.25% 63.25% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8179255 36.75% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 14851033 64.19% 64.19% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 8283564 35.81% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22253887 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 10836211781 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 23134597 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 11405856452 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 180026995 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 183601993 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7309068550 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7759954717 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7654516797 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8048372726 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 164187799 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 179758799 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 308745047 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 322845049 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1985,25 +1226,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 85169560 # DTB read hits -system.cpu1.dtb.read_misses 81568 # DTB read misses -system.cpu1.dtb.write_hits 77252621 # DTB write hits -system.cpu1.dtb.write_misses 28177 # DTB write misses +system.cpu1.dtb.read_hits 81769828 # DTB read hits +system.cpu1.dtb.read_misses 79673 # DTB read misses +system.cpu1.dtb.write_hits 74311746 # DTB write hits +system.cpu1.dtb.write_misses 27355 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 42405 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 41105 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4822 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4547 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11145 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 85251128 # DTB read accesses -system.cpu1.dtb.write_accesses 77280798 # DTB write accesses +system.cpu1.dtb.perms_faults 10770 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 81849501 # DTB read accesses +system.cpu1.dtb.write_accesses 74339101 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162422181 # DTB hits -system.cpu1.dtb.misses 109745 # DTB misses -system.cpu1.dtb.accesses 162531926 # DTB accesses +system.cpu1.dtb.hits 156081574 # DTB hits +system.cpu1.dtb.misses 107028 # DTB misses +system.cpu1.dtb.accesses 156188602 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2025,142 +1266,343 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 451299133 # ITB inst hits -system.cpu1.itb.inst_misses 60868 # ITB inst misses +system.cpu1.itb.inst_hits 434473512 # ITB inst hits +system.cpu1.itb.inst_misses 57336 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29689 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 28749 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 451360001 # ITB inst accesses -system.cpu1.itb.hits 451299133 # DTB hits -system.cpu1.itb.misses 60868 # DTB misses -system.cpu1.itb.accesses 451360001 # DTB accesses -system.cpu1.numCycles 94876549324 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 434530848 # ITB inst accesses +system.cpu1.itb.hits 434473512 # DTB hits +system.cpu1.itb.misses 57336 # DTB misses +system.cpu1.itb.accesses 434530848 # DTB accesses +system.cpu1.numCycles 95132031696 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 450991688 # Number of instructions committed -system.cpu1.committedOps 531140635 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 488008709 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 470535 # Number of float alu accesses -system.cpu1.num_func_calls 27052635 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 68722135 # number of instructions that are conditional controls -system.cpu1.num_int_insts 488008709 # number of integer instructions -system.cpu1.num_fp_insts 470535 # number of float instructions -system.cpu1.num_int_register_reads 711965253 # number of times the integer registers were read -system.cpu1.num_int_register_writes 387496587 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 748074 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 424948 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 118082190 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 117761356 # number of times the CC registers were written -system.cpu1.num_mem_refs 162414438 # number of memory refs -system.cpu1.num_load_insts 85168501 # Number of load instructions -system.cpu1.num_store_insts 77245937 # Number of store instructions -system.cpu1.num_idle_cycles 93789094629.720032 # Number of idle cycles -system.cpu1.num_busy_cycles 1087454694.279977 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011462 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988538 # Percentage of idle cycles -system.cpu1.Branches 100614893 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 367777606 69.20% 69.20% # Class of executed instruction -system.cpu1.op_class::IntMult 1128259 0.21% 69.42% # Class of executed instruction -system.cpu1.op_class::IntDiv 59926 0.01% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 67918 0.01% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::MemRead 85168501 16.03% 85.47% # Class of executed instruction -system.cpu1.op_class::MemWrite 77245937 14.53% 100.00% # Class of executed instruction +system.cpu1.committedInsts 434160856 # Number of instructions committed +system.cpu1.committedOps 511722288 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 470175639 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 456535 # Number of float alu accesses +system.cpu1.num_func_calls 26230713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66122636 # number of instructions that are conditional controls +system.cpu1.num_int_insts 470175639 # number of integer instructions +system.cpu1.num_fp_insts 456535 # number of float instructions +system.cpu1.num_int_register_reads 688104482 # number of times the integer registers were read +system.cpu1.num_int_register_writes 373632663 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 726332 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 408756 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113709240 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113476936 # number of times the CC registers were written +system.cpu1.num_mem_refs 156073929 # number of memory refs +system.cpu1.num_load_insts 81768358 # Number of load instructions +system.cpu1.num_store_insts 74305571 # Number of store instructions +system.cpu1.num_idle_cycles 94082707842.004028 # Number of idle cycles +system.cpu1.num_busy_cycles 1049323853.995978 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011030 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988970 # Percentage of idle cycles +system.cpu1.Branches 96877428 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 354755827 69.28% 69.28% # Class of executed instruction +system.cpu1.op_class::IntMult 1081291 0.21% 69.49% # Class of executed instruction +system.cpu1.op_class::IntDiv 57437 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 66526 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::MemRead 81768358 15.97% 85.49% # Class of executed instruction +system.cpu1.op_class::MemWrite 74305571 14.51% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 531448189 # Class of executed instruction +system.cpu1.op_class::total 512035053 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13727 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 5018265 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.292950 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 446280351 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5018777 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 88.922132 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 13728 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5229569 # number of replacements +system.cpu1.dcache.tags.tagsinuse 446.555743 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 150635340 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5230081 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.801722 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 446.555743 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.872179 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.872179 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 317363377 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 317363377 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76086699 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76086699 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 70396756 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 70396756 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188905 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 188905 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 685307 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 685307 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1701097 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1701097 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1676869 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1676869 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 146483455 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 146483455 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 146672360 # number of overall hits +system.cpu1.dcache.overall_hits::total 146672360 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2949268 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2949268 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1324938 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1324938 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648778 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 648778 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170596 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 170596 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193531 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 193531 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4274206 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4274206 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4922984 # number of overall misses +system.cpu1.dcache.overall_misses::total 4922984 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43925732439 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 43925732439 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22816644952 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 22816644952 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2487645065 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2487645065 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4103865813 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4103865813 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1896000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1896000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 66742377391 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 66742377391 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 66742377391 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 66742377391 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79035967 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79035967 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71721694 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71721694 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 837683 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 837683 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685307 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 685307 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1871693 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1871693 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1870400 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1870400 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 150757661 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 150757661 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 151595344 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 151595344 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037316 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037316 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018473 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018473 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.774491 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.774491 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091145 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091145 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103470 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103470 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028352 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.028352 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032475 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.032475 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14893.774468 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14893.774468 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17220.915207 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17220.915207 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14582.083197 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14582.083197 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21205.211635 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21205.211635 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15615.152239 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15615.152239 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13557.301302 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13557.301302 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 685307 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 2978181 # number of writebacks +system.cpu1.dcache.writebacks::total 2978181 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23865 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 23865 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 515 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 515 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45192 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45192 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 24380 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 24380 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 24380 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 24380 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2925403 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2925403 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1324423 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1324423 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648778 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 648778 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125404 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125404 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193531 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193531 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4249826 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4249826 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4898604 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4898604 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36900792539 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36900792539 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20082419307 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20082419307 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13833136236 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13833136236 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 30583171682 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30583171682 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1453819204 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1453819204 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3706136187 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3706136187 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1808000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1808000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 56983211846 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 56983211846 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 70816348082 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 70816348082 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4114514480 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4114514480 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3994198470 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3994198470 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8108712950 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8108712950 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037014 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037014 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018466 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.774491 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.774491 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067000 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067000 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103470 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103470 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028190 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028190 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032314 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032314 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12613.917651 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12613.917651 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15163.145994 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15163.145994 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21321.833102 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21321.833102 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11593.084782 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.084782 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19150.090616 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19150.090616 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13408.363506 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13408.363506 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14456.434544 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14456.434544 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 4838786 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.335132 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 429634209 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4839298 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 88.780275 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8374030789000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.292950 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969322 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969322 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.335132 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969405 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969405 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 907617048 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 907617048 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 446280351 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 446280351 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 446280351 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 446280351 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 446280351 # number of overall hits -system.cpu1.icache.overall_hits::total 446280351 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5018782 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5018782 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5018782 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5018782 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5018782 # number of overall misses -system.cpu1.icache.overall_misses::total 5018782 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 43828213410 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 43828213410 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 43828213410 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 43828213410 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 43828213410 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 43828213410 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 451299133 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 451299133 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 451299133 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 451299133 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 451299133 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 451299133 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011121 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011121 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011121 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011121 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011121 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011121 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8732.838647 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8732.838647 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8732.838647 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8732.838647 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8732.838647 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8732.838647 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 873786327 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 873786327 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 429634209 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 429634209 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 429634209 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 429634209 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 429634209 # number of overall hits +system.cpu1.icache.overall_hits::total 429634209 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4839303 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4839303 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4839303 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4839303 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4839303 # number of overall misses +system.cpu1.icache.overall_misses::total 4839303 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 42201450669 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 42201450669 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 42201450669 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 42201450669 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 42201450669 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 42201450669 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 434473512 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 434473512 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 434473512 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 434473512 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 434473512 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 434473512 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011138 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011138 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011138 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011138 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011138 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011138 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8720.563823 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8720.563823 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8720.563823 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8720.563823 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8720.563823 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8720.563823 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2169,367 +1611,367 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5018782 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5018782 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5018782 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5018782 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5018782 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5018782 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 36297023628 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 36297023628 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 36297023628 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 36297023628 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 36297023628 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 36297023628 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4839303 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4839303 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4839303 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 4839303 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4839303 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4839303 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 34939638885 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 34939638885 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 34939638885 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 34939638885 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 34939638885 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 34939638885 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8745500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8745500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8745500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 8745500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011121 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011121 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011121 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011121 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7232.237548 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7232.237548 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7232.237548 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7232.237548 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011138 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011138 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011138 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011138 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011138 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011138 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7219.973390 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7219.973390 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7219.973390 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7219.973390 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7219.973390 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7219.973390 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 46849798 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 849083 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 43478767 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8509 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 45129085 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 818764 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 41906843 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8141 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 498 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2512941 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4003522 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 514 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2394823 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3842139 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3186327 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13749.059276 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10995274 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3202540 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.433298 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10289671385000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 3719.678025 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.787845 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 70.255948 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 738.115958 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2404.101650 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6756.119849 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.227031 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003710 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004288 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.045051 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.146735 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.412361 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.839176 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9826 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 113 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6274 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 142 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 1008 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2026 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4347 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 2303 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 31 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 496 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1278 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3095 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1333 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.599731 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006897 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.382935 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 238490090 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 238490090 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 228775 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138969 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4837723 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2811594 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8017061 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3078590 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3078590 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 84508 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 84508 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 36910 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 36910 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 942789 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 942789 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 228775 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138969 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4837723 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3754383 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8959850 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 228775 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138969 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4837723 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3754383 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8959850 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12809 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11666 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 181059 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1016624 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1222158 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 110012 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 110012 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159084 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 159084 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 227840 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 227840 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12809 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11666 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 181059 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1244464 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1449998 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12809 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11666 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 181059 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1244464 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1449998 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 589793966 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 732581953 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 4736583796 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 33373068876 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 39432028591 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2203650350 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2203650350 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3257454308 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3257454308 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2221500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2221500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10235414817 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10235414817 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 589793966 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 732581953 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4736583796 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 43608483693 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 49667443408 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 589793966 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 732581953 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4736583796 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 43608483693 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 49667443408 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 241584 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150635 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5018782 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3828218 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9239219 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3078590 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3078590 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 194520 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 194520 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195994 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 195994 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1170629 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1170629 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 241584 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150635 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5018782 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4998847 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10409848 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 241584 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150635 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5018782 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4998847 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10409848 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.053021 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077445 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.036076 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.265561 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.132279 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.565556 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.565556 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.811678 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.811678 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 3029134 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13674.379805 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10606046 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 3045261 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.482804 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10454752865000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4179.016177 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 54.517433 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 70.326677 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 591.513668 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3188.927208 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5590.078642 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.255067 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003327 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004292 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036103 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.341191 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.834618 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8556 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7510 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 438 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3359 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4072 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 611 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 28 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2836 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3841 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 307 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.522217 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.458374 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 230495604 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 230495604 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 221576 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 129888 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4667071 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2714218 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 7732753 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 2978176 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 2978176 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 79936 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 79936 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35720 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 35720 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 908771 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 908771 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 221576 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 129888 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4667071 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3622989 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8641524 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 221576 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 129888 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4667071 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3622989 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8641524 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12665 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11221 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 172232 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 985367 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1181485 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 109801 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 109801 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157805 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 157805 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 226147 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 226147 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12665 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11221 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 172232 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1211514 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1407632 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12665 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11221 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 172232 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1211514 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1407632 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 578928201 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 733432437 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 4494366580 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 32191641510 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 37998368728 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2189702140 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2189702140 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3225705678 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3225705678 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1763999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1763999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10153420884 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 10153420884 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 578928201 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 733432437 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4494366580 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 42345062394 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 48151789612 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 578928201 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 733432437 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4494366580 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 42345062394 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 48151789612 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 234241 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 141109 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4839303 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3699585 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 8914238 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 2978176 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 2978176 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 189737 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 189737 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193525 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 193525 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1134918 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1134918 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 234241 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 141109 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4839303 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4834503 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10049156 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 234241 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 141109 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4839303 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4834503 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10049156 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.054068 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079520 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.035590 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.266345 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.132539 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.578701 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.578701 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.815424 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.815424 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.194630 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.194630 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.053021 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.077445 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.036076 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.248950 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.139291 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.053021 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.077445 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.036076 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.248950 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.139291 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 46045.278008 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62796.327190 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26160.443811 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32827.347058 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32264.264188 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20030.999800 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20030.999800 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20476.316336 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20476.316336 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 277687.500000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 277687.500000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44923.695650 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44923.695650 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 46045.278008 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62796.327190 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26160.443811 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35041.980879 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 34253.456493 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 46045.278008 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62796.327190 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26160.443811 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35041.980879 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 34253.456493 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 7768 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.199263 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.199263 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.054068 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.079520 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.035590 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.250597 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.140075 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.054068 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.079520 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.035590 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.250597 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.140075 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 45710.872562 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 65362.484360 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26094.840564 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32669.697189 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32161.532925 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19942.460815 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19942.460815 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20441.086645 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20441.086645 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 293999.833333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 293999.833333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44897.437879 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44897.437879 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 45710.872562 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 65362.484360 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26094.840564 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34952.185773 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 34207.654850 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 45710.872562 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 65362.484360 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26094.840564 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34952.185773 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 34207.654850 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 6147 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 221 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 166 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 35.149321 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 37.030120 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1013300 # number of writebacks -system.cpu1.l2cache.writebacks::total 1013300 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 27917 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 1038 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 28955 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6115 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 6115 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 27917 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7153 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 35070 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 27917 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7153 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 35070 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12809 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 11666 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 153142 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1015586 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1193203 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2512812 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 2512812 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 110012 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 110012 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 159084 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 159084 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 221725 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 221725 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12809 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 11666 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 153142 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1237311 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1414928 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12809 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 11666 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 153142 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1237311 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 2512812 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 3927740 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 499166550 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 649598551 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 3217080793 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26145933834 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 30511779728 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 74093026830 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 74093026830 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 26166697651 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 26166697651 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 1898740270 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 1898740270 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2221301592 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2221301592 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1836500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1836500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8021601600 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8021601600 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 499166550 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 649598551 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 3217080793 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34167535434 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 38533381328 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 499166550 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 649598551 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 3217080793 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34167535434 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 74093026830 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 112626408158 # number of overall MSHR miss cycles +system.cpu1.l2cache.writebacks::writebacks 960563 # number of writebacks +system.cpu1.l2cache.writebacks::total 960563 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 26607 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 912 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 27519 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6089 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 6089 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 26607 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7001 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 33608 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 26607 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7001 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 33608 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12665 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 11221 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 145625 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 984455 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1153966 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2394712 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 2394712 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 109801 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 109801 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 157805 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 157805 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 220058 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 220058 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12665 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 11221 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 145625 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1204513 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1374024 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12665 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 11221 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 145625 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1204513 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 2394712 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 3768736 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 489322313 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 653538067 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 3045903499 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 25194010676 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 29382774555 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 71059948043 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 71059948043 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 25441892262 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25441892262 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 1899234087 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 1899234087 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2195015270 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2195015270 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1455999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1455999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7950904534 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7950904534 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 489322313 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 653538067 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 3045903499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33144915210 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 37333679089 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 489322313 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 653538067 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 3045903499 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33144915210 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 71059948043 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 108393627132 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7884500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3785923263 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3793807763 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3621697529 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3621697529 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3918463269 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3926347769 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3819021030 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3819021030 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7884500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7407620792 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7415505292 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.265289 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.129145 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7737484299 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7745368799 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.266099 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.129452 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.565556 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.565556 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.811678 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.811678 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.578701 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.578701 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.815424 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.815424 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.189407 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.189407 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.247519 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135922 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.247519 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193898 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193898 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249149 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136730 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249149 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.377310 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25744.677294 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25571.323344 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29486.100365 # average HardPFReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.375030 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25591.835763 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25462.426584 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29673.692721 # average HardPFReq mshr miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17259.392339 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17259.392339 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13963.073546 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13963.073546 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 229562.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 229562.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36178.155824 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36178.155824 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27233.457341 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28674.608848 # average overall mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17297.056375 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17297.056375 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13909.668705 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13909.668705 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242666.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242666.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36130.949722 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36130.949722 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27171.053118 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28761.268269 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2539,322 +1981,206 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 5412769 # number of replacements -system.cpu1.dcache.tags.tagsinuse 455.628997 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 156797756 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5413278 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.965399 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.628997 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.889900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 330228848 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 330228848 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79329783 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79329783 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 73242746 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 73242746 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190572 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 190572 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 704958 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 704958 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1728485 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1728485 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1710118 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1710118 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 152572529 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 152572529 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 152763101 # number of overall hits -system.cpu1.dcache.overall_hits::total 152763101 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3054941 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3054941 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1365411 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1365411 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 663261 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 663261 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178994 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 178994 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196091 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 196091 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4420352 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4420352 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5083613 # number of overall misses -system.cpu1.dcache.overall_misses::total 5083613 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45633904603 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 45633904603 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23251947701 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 23251947701 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2574333319 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2574333319 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4154245626 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4154245626 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2386500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2386500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 68885852304 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 68885852304 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 68885852304 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 68885852304 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82384724 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82384724 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 74608157 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 74608157 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 853833 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 853833 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 704958 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 704958 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1907479 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1907479 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906209 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1906209 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 156992881 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 156992881 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 157846714 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 157846714 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037081 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037081 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018301 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018301 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.776804 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.776804 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093838 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093838 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102870 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102870 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028156 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.028156 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032206 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.032206 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14937.736802 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14937.736802 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17029.266427 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17029.266427 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14382.232471 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14382.232471 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21185.294715 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21185.294715 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15583.793396 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15583.793396 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13550.569704 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13550.569704 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 704958 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3078594 # number of writebacks -system.cpu1.dcache.writebacks::total 3078594 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23839 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 23839 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 436 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 436 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45139 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45139 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 24275 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 24275 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 24275 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 24275 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3031102 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3031102 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1364975 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1364975 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 663261 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 663261 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 133855 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 133855 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196002 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 196002 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4396077 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4396077 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5059338 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5059338 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38375786357 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38375786357 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20437608309 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20437608309 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14184435008 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14184435008 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 31455228300 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 31455228300 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1522508206 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1522508206 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3750879374 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3750879374 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2276500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2276500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58813394666 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 58813394666 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 72997829674 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 72997829674 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3974280487 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3974280487 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3786981721 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3786981721 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7761262208 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7761262208 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036792 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036792 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018295 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018295 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.776804 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.776804 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.070174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.070174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.102823 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.102823 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028002 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028002 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032052 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032052 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12660.671385 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12660.671385 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14972.881048 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14972.881048 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21385.902394 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21385.902394 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11374.309559 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11374.309559 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19136.944388 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19136.944388 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13378.608852 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13378.608852 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14428.336212 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14428.336212 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 12531191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9460246 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22034 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22034 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3078590 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3649719 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 704958 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 365743 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350744 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 452026 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1320531 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1177447 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 10037784 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15516501 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332477 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 559655 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 26446417 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 321202488 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 568398888 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205080 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1932672 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 892739128 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 8517318 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22943145 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.359651 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.479898 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 12427806 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9137324 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 23353 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 23353 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 2978176 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 3478890 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 685307 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 370922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353849 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 446809 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1290596 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1141918 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9678826 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15042396 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 312565 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544877 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25578664 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 309715832 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 550341480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1128872 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1873928 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 863060112 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 8621982 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22555543 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.370325 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.482892 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 14691626 64.03% 64.03% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8251519 35.97% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 14202655 62.97% 62.97% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 8352888 37.03% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22943145 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11163844442 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 22555543 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10801104660 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175587993 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 179932994 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7529809391 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7260511142 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8141370258 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7881710673 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 182479297 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 172097315 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 318532791 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 311084554 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115665 # number of replacements -system.iocache.tags.tagsinuse 11.304646 # Cycle average of tags in use +system.iobus.trans_dist::ReadReq 40536 # Transaction distribution +system.iobus.trans_dist::ReadResp 40536 # Transaction distribution +system.iobus.trans_dist::WriteReq 137093 # Transaction distribution +system.iobus.trans_dist::WriteResp 137147 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123470 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231816 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231816 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 355366 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48348 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156485 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7514187 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36745000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 22142000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 984235192 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93310000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179557795 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115889 # number of replacements +system.iocache.tags.tagsinuse 11.315870 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115681 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115905 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9130394779000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.406620 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.898026 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462914 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.243627 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706540 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.824342 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.491528 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239021 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.468221 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.707242 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041810 # Number of tag accesses -system.iocache.tags.data_accesses 1041810 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1043961 # Number of tag accesses +system.iocache.tags.data_accesses 1043961 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106984 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106984 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8941 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8978 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8924 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8961 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 54 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 54 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8941 # number of demand (read+write) misses -system.iocache.demand_misses::total 8981 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8924 # number of demand (read+write) misses +system.iocache.demand_misses::total 8964 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8941 # number of overall misses -system.iocache.overall_misses::total 8981 # number of overall misses +system.iocache.overall_misses::realview.ide 8924 # number of overall misses +system.iocache.overall_misses::total 8964 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1994628595 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 2000335595 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1957100855 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1962807855 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1994628595 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 2000692595 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1957100855 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1963164855 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1994628595 # number of overall miss cycles -system.iocache.overall_miss_latency::total 2000692595 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1957100855 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1963164855 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8941 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8978 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8924 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8961 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106782 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106782 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 107038 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 107038 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8941 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8981 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8924 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8964 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8941 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8981 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8924 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8964 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000506 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000506 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000504 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000504 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -2862,48 +2188,48 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 223087.864333 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 222804.142905 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 219307.581242 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 219038.930365 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 223087.864333 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 222769.468322 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 219307.581242 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 219005.450134 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 223087.864333 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 222769.468322 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55195 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 219307.581242 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 219005.450134 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 53861 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.053734 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.810747 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.fast_writes 106984 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8941 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8978 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8924 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8961 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8941 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8981 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8924 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8964 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8941 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8981 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8924 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8964 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529539613 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1533322613 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492924359 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1496707359 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6584739086 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6584739086 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6628374628 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6628374628 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1529539613 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1533523613 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1492924359 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1496908359 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1529539613 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1533523613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1492924359 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1496908359 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2916,18 +2242,693 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171070.306789 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 170786.657719 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167293.182317 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 167024.590894 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 171070.306789 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 170751.988977 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 167293.182317 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 166991.115462 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 171070.306789 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 170751.988977 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 167293.182317 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 166991.115462 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1086855 # number of replacements +system.l2c.tags.tagsinuse 64099.647179 # Cycle average of tags in use +system.l2c.tags.total_refs 6672114 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1148598 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.808920 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 9469.927163 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 51.211523 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 68.031290 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 696.373428 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3179.738420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17944.005062 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 291.904824 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 401.470147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 563.131009 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10017.603756 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 21416.250557 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.144500 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000781 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001038 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.010626 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048519 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.273804 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004454 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006126 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008593 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.152857 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.326786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.978083 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31587 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 309 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 29847 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 114 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1585 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25743 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 33 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 47 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 219 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1360 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9152 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 19154 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.481979 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004715 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.455429 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 80637866 # Number of tag accesses +system.l2c.tags.data_accesses 80637866 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6250 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4321 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 142068 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 620262 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1618371 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6096 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4059 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 137369 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 611754 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1545913 # number of ReadReq hits +system.l2c.ReadReq_hits::total 4696463 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1994497 # number of Writeback hits +system.l2c.Writeback_hits::total 1994497 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 23769 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 27954 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 51723 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 7971 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7653 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 15624 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 52432 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 49853 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 102285 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6250 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4321 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 142068 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 672694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 1618371 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6096 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4059 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 137369 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 661607 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 1545913 # number of demand (read+write) hits +system.l2c.demand_hits::total 4798748 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6250 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4321 # number of overall hits +system.l2c.overall_hits::cpu0.inst 142068 # number of overall hits +system.l2c.overall_hits::cpu0.data 672694 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 1618371 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6096 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4059 # number of overall hits +system.l2c.overall_hits::cpu1.inst 137369 # number of overall hits +system.l2c.overall_hits::cpu1.data 661607 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 1545913 # number of overall hits +system.l2c.overall_hits::total 4798748 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3647 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 6386 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 8946 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 136148 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 441016 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 4242 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 6837 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 8364 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 140626 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 418325 # number of ReadReq misses +system.l2c.ReadReq_misses::total 1174537 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 34627 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 36381 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 71008 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 10699 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 11055 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 21754 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 78297 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72282 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 150579 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3647 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 6386 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8946 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 214445 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 441016 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 4242 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 6837 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 8364 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 212908 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 418325 # number of demand (read+write) misses +system.l2c.demand_misses::total 1325116 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3647 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 6386 # number of overall misses +system.l2c.overall_misses::cpu0.inst 8946 # number of overall misses +system.l2c.overall_misses::cpu0.data 214445 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 441016 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 4242 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 6837 # number of overall misses +system.l2c.overall_misses::cpu1.inst 8364 # number of overall misses +system.l2c.overall_misses::cpu1.data 212908 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 418325 # number of overall misses +system.l2c.overall_misses::total 1325116 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 290095498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 510585994 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 795450996 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11077065870 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 335992750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 542306996 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 742040494 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 11432821383 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 116290930305 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 147041544 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 142085765 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 289127309 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 51916806 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56203152 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 108119958 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5726616061 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5297244481 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11023860542 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 290095498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 510585994 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 795450996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 16803681931 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 335992750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 542306996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 742040494 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 16730065864 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 127314790847 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 290095498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 510585994 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 795450996 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 16803681931 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 335992750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 542306996 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 742040494 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 16730065864 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of overall miss cycles +system.l2c.overall_miss_latency::total 127314790847 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9897 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 10707 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 151014 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 756410 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2059387 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10338 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 10896 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 145733 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 752380 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 1964238 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 5871000 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1994497 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1994497 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 58396 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 64335 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 122731 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 18670 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 18708 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 37378 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 130729 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 122135 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 252864 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9897 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 10707 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 151014 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 887139 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2059387 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10338 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 10896 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 145733 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 874515 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 1964238 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 6123864 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9897 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 10707 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 151014 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 887139 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2059387 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10338 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 10896 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 145733 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 874515 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 1964238 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 6123864 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.368496 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.596432 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.059240 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.179992 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.214149 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.410331 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.627478 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.057393 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.186908 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.212971 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.200057 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.592969 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.565493 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.578566 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.573058 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590924 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.582000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.598926 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.591821 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.595494 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.368496 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.596432 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.059240 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.241726 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.214149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.410331 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.627478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.057393 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.243458 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.212971 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.216386 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.368496 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.596432 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.059240 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.241726 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.214149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.410331 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.627478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.057393 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.243458 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.212971 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.216386 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79543.596929 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79953.960852 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 88916.945674 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 81360.474410 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79206.211693 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 79319.437765 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88718.375658 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81299.485038 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 99010.018675 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4246.441909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3905.493664 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4071.756830 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4852.491448 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5083.957666 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4970.118507 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73139.661302 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73285.803948 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73209.813732 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79543.596929 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79953.960852 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 88916.945674 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 78358.935536 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79206.211693 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 79319.437765 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 88718.375658 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 78578.850320 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 96078.223225 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79543.596929 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79953.960852 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 88916.945674 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 78358.935536 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79206.211693 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 79319.437765 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 88718.375658 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 78578.850320 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 96078.223225 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 2524 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 54 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 46.740741 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 686491 # number of writebacks +system.l2c.writebacks::total 686491 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 30 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 289 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 14 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 182 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 551 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 24 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 289 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 182 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 24 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 289 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 182 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 551 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3647 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6386 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 8916 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 136124 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 440727 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4242 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6837 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 8350 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 140614 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 418143 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 1173986 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 34627 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 36381 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 71008 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10699 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11055 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 21754 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 78297 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72282 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 150579 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3647 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 6386 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8916 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 214421 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 440727 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 4242 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 6837 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 8350 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 212896 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 418143 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1324565 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3647 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 6386 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 8916 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 214421 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 440727 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 4242 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 6837 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 8350 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 212896 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 418143 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1324565 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 244781998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 431307994 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 682060496 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 9367961184 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 40693405448 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 283137750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 457339496 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 636822998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9667271945 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39253909640 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 101717998949 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17785049779 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 13763550872 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 31548600651 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 351208941 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 368943627 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 720152568 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 109133556 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 113272386 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 222405942 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4739079365 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4385575961 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9124655326 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 244781998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 431307994 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 682060496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 14107040549 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 40693405448 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 283137750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 457339496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 636822998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 14052847906 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 39253909640 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 110842654275 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 244781998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 431307994 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 682060496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 14107040549 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 40693405448 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 283137750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 457339496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 636822998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 14052847906 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39253909640 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 110842654275 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1903247752 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5835000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3476254750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7631534752 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1855610501 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3420953000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5276563501 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3758858253 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5835000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6897207750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12908098253 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.368496 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.596432 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.059041 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179961 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.214009 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.410331 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.627478 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.057297 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.186892 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.212878 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.199964 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.592969 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.565493 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.578566 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.573058 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590924 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.582000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.598926 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.591821 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.595494 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.368496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.596432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.059041 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.241699 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.214009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.410331 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.627478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.057297 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.243445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.212878 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.216296 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.368496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.596432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.059041 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.241699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.214009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.410331 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.627478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.057297 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.243445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.212878 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.216296 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68819.320502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68750.422753 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 86643.281052 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10142.632657 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10141.107364 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10141.851172 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10200.351061 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.258345 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10223.680335 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60526.959717 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60673.140768 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60597.130583 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65791.319642 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66008.041044 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 83682.306474 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65791.319642 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66008.041044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 83682.306474 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 1264717 # Transaction distribution +system.membus.trans_dist::ReadResp 1264717 # Transaction distribution +system.membus.trans_dist::WriteReq 38516 # Transaction distribution +system.membus.trans_dist::WriteResp 38516 # Transaction distribution +system.membus.trans_dist::Writeback 686491 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1679861 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1679861 # Transaction distribution +system.membus.trans_dist::UpgradeReq 316703 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 302467 # Transaction distribution +system.membus.trans_dist::UpgradeResp 96183 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 163141 # Transaction distribution +system.membus.trans_dist::ReadExResp 147161 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7297543 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 7446435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 230140 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 230140 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7676575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50660 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229346740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 229554089 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7308288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7308288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 236862377 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 540732 # Total snoops (count) +system.membus.snoop_fanout::samples 4331622 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 4331622 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 4331622 # Request fanout histogram +system.membus.reqLayer0.occupancy 101146499 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 22031996 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 23154905719 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 14237686781 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 187996205 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 6727338 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 6719778 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38516 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38516 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1994497 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1572877 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 365008 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 318091 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 683099 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301724 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301724 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10020344 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9267363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 19287707 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 322818441 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 297911776 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 620730217 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1454894 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 11304872 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.010257 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.100757 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11188916 98.97% 98.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115956 1.03% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 11304872 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 19960086799 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 6306000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 16653624789 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 15972471023 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |