regressions: stats update due to decoder changes

5 files changed, 145 insertions, 163 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 0b4c661be..28f275f3a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000013                       # Nu
 sim_ticks                                    13371000                       # Number of ticks simulated
 final_tick                                   13371000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  32660                       # Simulator instruction rate (inst/s)
-host_op_rate                                    40743                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               94998008                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228356                       # Number of bytes of host memory used
+host_inst_rate                                  32987                       # Simulator instruction rate (inst/s)
+host_op_rate                                    41149                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               95942804                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272856                       # Number of bytes of host memory used
 host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        4596                       # Number of instructions simulated
 sim_ops                                          5734                       # Number of ops (including micro ops) simulated
@@ -537,7 +537,7 @@ system.cpu.ipc_total                         0.171858                       # IP
 system.cpu.int_regfile_reads                    39369                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    8027                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                   15007                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    2981                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     26                       # number of misc regfile writes
 system.cpu.icache.replacements                      4                       # number of replacements
 system.cpu.icache.tagsinuse                147.796211                       # Cycle average of tags in use
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index c182ad17a..675d12028 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -78,7 +78,6 @@ iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
 interrupts=system.cpu.interrupts
-isa=system.cpu.isa
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -458,23 +457,6 @@ mem_side=system.cpu.toL2Bus.slave[0]
 [system.cpu.interrupts]
 type=ArmInterrupts
 
-[system.cpu.isa]
-type=ArmISA
-fpsid=1090793632
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=3
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=4027589137
-id_pfr0=49
-id_pfr1=1
-midr=890224640
-
 [system.cpu.itb]
 type=ArmTLB
 children=walker
@@ -536,7 +518,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 76131bc35..11fc8e27b 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000013                       # Nu
 sim_ticks                                    13371000                       # Number of ticks simulated
 final_tick                                   13371000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37264                       # Simulator instruction rate (inst/s)
-host_op_rate                                    46486                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              108387516                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228452                       # Number of bytes of host memory used
+host_inst_rate                                  36978                       # Simulator instruction rate (inst/s)
+host_op_rate                                    46127                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              107546339                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272728                       # Number of bytes of host memory used
 host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        4596                       # Number of instructions simulated
 sim_ops                                          5734                       # Number of ops (including micro ops) simulated
@@ -492,7 +492,7 @@ system.cpu.ipc_total                         0.171858                       # IP
 system.cpu.int_regfile_reads                    39369                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    8027                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                   15007                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    2981                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     26                       # number of misc regfile writes
 system.cpu.icache.replacements                      4                       # number of replacements
 system.cpu.icache.tagsinuse                147.796211                       # Cycle average of tags in use
@@ -578,6 +578,130 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                      0                       # number of replacements
+system.cpu.dcache.tagsinuse                 86.861870                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2396                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    146                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  16.410959                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data      86.861870                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021207                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021207                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1765                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1765                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          606                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            606                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           13                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           13                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           12                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           12                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data          2371                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2371                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2371                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2371                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          191                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           191                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          307                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          307                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data          498                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            498                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          498                       # number of overall misses
+system.cpu.dcache.overall_misses::total           498                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8138000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8138000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     14907500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     14907500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        87500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        87500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     23045500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     23045500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     23045500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     23045500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1956                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1956                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           15                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           15                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           12                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           12                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2869                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2869                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2869                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2869                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.097648                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.097648                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.336254                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.336254                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.133333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.133333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.173580                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.173580                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.173580                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.173580                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        43750                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        43750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46276.104418                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46276.104418                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           63                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           21                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           85                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           85                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          266                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          266                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          351                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          351                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          351                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          351                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          106                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          106                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           41                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           41                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4925000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4925000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2313500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2313500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7238500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7238500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7238500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7238500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054192                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054192                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044907                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051237                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.051237                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051237                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.051237                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               186.102289                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                      40                       # Total number of references to valid blocks.
@@ -712,129 +836,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 86.861870                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2396                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    146                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  16.410959                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      86.861870                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021207                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021207                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1765                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1765                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          606                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            606                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           13                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           13                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data           12                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           12                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2371                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2371                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2371                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2371                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          191                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           191                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          307                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          307                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          498                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            498                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          498                       # number of overall misses
-system.cpu.dcache.overall_misses::total           498                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8138000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8138000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     14907500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     14907500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        87500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        87500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     23045500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     23045500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     23045500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     23045500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1956                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1956                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           15                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           15                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data           12                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           12                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2869                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2869                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2869                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2869                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.097648                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.097648                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.336254                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.336254                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.133333                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.133333                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.173580                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.173580                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.173580                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.173580                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        43750                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        43750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46276.104418                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46276.104418                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           63                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           21                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           85                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           85                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          266                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          266                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          351                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          351                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          351                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          351                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          106                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          106                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           41                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           41                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4925000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4925000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2313500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2313500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7238500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7238500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7238500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7238500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054192                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054192                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044907                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051237                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.051237                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051237                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.051237                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 1c2308afb..92d6d9a2f 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -463,7 +463,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 13ed71f23..bb0098d76 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000105                       # Nu
 sim_ticks                                   104830500                       # Number of ticks simulated
 final_tick                                  104830500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 100032                       # Simulator instruction rate (inst/s)
-host_op_rate                                   100032                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               10132772                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236868                       # Number of bytes of host memory used
-host_seconds                                    10.35                       # Real time elapsed on the host
+host_inst_rate                                 112424                       # Simulator instruction rate (inst/s)
+host_op_rate                                   112424                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               11388036                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275264                       # Number of bytes of host memory used
+host_seconds                                     9.21                       # Real time elapsed on the host
 sim_insts                                     1034897                       # Number of instructions simulated
 sim_ops                                       1034897                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
@@ -952,7 +952,7 @@ system.cpu1.int_regfile_reads                  422509                       # nu
 system.cpu1.int_regfile_writes                 197149                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu1.misc_regfile_reads                 122869                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
+system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu1.icache.replacements                   317                       # number of replacements
 system.cpu1.icache.tagsinuse                85.783317                       # Cycle average of tags in use
 system.cpu1.icache.total_refs                   18178                       # Total number of references to valid blocks.
@@ -1426,7 +1426,7 @@ system.cpu2.int_regfile_reads                  319017                       # nu
 system.cpu2.int_regfile_writes                 150022                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu2.misc_regfile_reads                  88362                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
+system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu2.icache.replacements                   319                       # number of replacements
 system.cpu2.icache.tagsinuse                80.119670                       # Cycle average of tags in use
 system.cpu2.icache.total_refs                   24566                       # Total number of references to valid blocks.
@@ -1900,7 +1900,7 @@ system.cpu3.int_regfile_reads                  427031                       # nu
 system.cpu3.int_regfile_writes                 198982                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu3.misc_regfile_reads                 124365                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
+system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu3.icache.replacements                   318                       # number of replacements
 system.cpu3.icache.tagsinuse                83.493816                       # Cycle average of tags in use
 system.cpu3.icache.total_refs                   18731                       # Total number of references to valid blocks.