diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/quick | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/quick')
38 files changed, 23714 insertions, 23551 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 44f9ef01c..87d1939f2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,70 +1,73 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870336 # Number of seconds simulated -sim_ticks 1870335522500 # Number of ticks simulated -final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.870335 # Number of seconds simulated +sim_ticks 1870335131500 # Number of ticks simulated +final_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2258331 # Simulator instruction rate (inst/s) -host_op_rate 2258329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66881420828 # Simulator tick rate (ticks/s) -host_mem_usage 346748 # Number of bytes of host memory used -host_seconds 27.97 # Real time elapsed on the host -sim_insts 63154034 # Number of instructions simulated -sim_ops 63154034 # Number of ops (including micro ops) simulated +host_inst_rate 1824221 # Simulator instruction rate (inst/s) +host_op_rate 1824220 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54024573563 # Simulator tick rate (ticks/s) +host_mem_usage 318368 # Number of bytes of host memory used +host_seconds 34.62 # Real time elapsed on the host +sim_insts 63154606 # Number of instructions simulated +sim_ops 63154606 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory -system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory +system.physmem.bytes_read::total 68252608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7863424 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122866 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 42160248 # Throughput (bytes/s) -system.membus.data_through_bus 78853810 # Total data (bytes) +system.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 40739369 # Throughput (bytes/s) +system.membus.data_through_bus 76196274 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 1000626 # number of replacements -system.l2c.tags.tagsinuse 65381.922680 # Cycle average of tags in use -system.l2c.tags.total_refs 2464737 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.312639 # Average number of references to valid blocks. +system.l2c.tags.replacements 1000624 # number of replacements +system.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use +system.l2c.tags.total_refs 2464778 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy @@ -75,42 +78,42 @@ system.l2c.tags.occ_task_id_blocks::1024 65142 # Oc system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 47965 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 32109442 # Number of tag accesses -system.l2c.tags.data_accesses 32109442 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits -system.l2c.Writeback_hits::total 816653 # number of Writeback hits +system.l2c.tags.tag_accesses 32109770 # Number of tag accesses +system.l2c.tags.data_accesses 32109770 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits +system.l2c.Writeback_hits::total 816663 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits -system.l2c.overall_hits::cpu0.data 929311 # number of overall hits -system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits -system.l2c.overall_hits::cpu1.data 51019 # number of overall hits -system.l2c.overall_hits::total 1955312 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 166232 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14288 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180520 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 873092 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929323 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 101902 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 51028 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955345 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 873092 # number of overall hits +system.l2c.overall_hits::cpu0.data 929323 # number of overall hits +system.l2c.overall_hits::cpu1.inst 101902 # number of overall hits +system.l2c.overall_hits::cpu1.data 51028 # number of overall hits +system.l2c.overall_hits::total 1955345 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11892 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941295 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses @@ -120,66 +123,66 @@ system.l2c.SCUpgradeReq_misses::total 165 # nu system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 11892 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses +system.l2c.demand_misses::total 1066663 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11892 # number of overall misses system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses system.l2c.overall_misses::cpu1.data 10570 # number of overall misses -system.l2c.overall_misses::total 1066665 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::total 1066663 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 884984 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689852 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 103636 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37648 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716120 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816663 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816663 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 281938 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23950 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305888 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 884984 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971790 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 103636 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61598 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3022008 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 884984 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971790 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 103636 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61598 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3022008 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013438 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548427 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016732 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024118 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346559 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410395 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403424 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409849 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013438 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528691 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016732 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171596 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352965 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013438 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528691 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016732 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171596 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352965 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,16 +191,16 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81316 # number of writebacks -system.l2c.writebacks::total 81316 # number of writebacks +system.l2c.writebacks::writebacks 81314 # number of writebacks +system.l2c.writebacks::total 81314 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.435437 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.435433 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 0.435433 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -205,26 +208,24 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375543 # Number of tag accesses system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -235,10 +236,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -256,22 +255,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9154530 # DTB read hits +system.cpu0.dtb.read_hits 9154569 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5936899 # DTB write hits +system.cpu0.dtb.write_hits 5936918 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15091429 # DTB hits +system.cpu0.dtb.data_hits 15091487 # DTB hits system.cpu0.dtb.data_misses 7805 # DTB misses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3855556 # ITB hits +system.cpu0.itb.fetch_hits 3855534 # ITB hits system.cpu0.itb.fetch_misses 3485 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3859041 # ITB accesses +system.cpu0.itb.fetch_accesses 3859019 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -284,34 +283,34 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740671046 # number of cpu cycles simulated +system.cpu0.numCycles 3740670264 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57222076 # Number of instructions committed -system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses +system.cpu0.committedInsts 57222643 # Number of instructions committed +system.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses -system.cpu0.num_func_calls 1399585 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53249924 # number of integer instructions +system.cpu0.num_func_calls 1399593 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls +system.cpu0.num_int_insts 53250480 # number of integer instructions system.cpu0.num_fp_insts 299810 # number of float instructions -system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written +system.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written -system.cpu0.num_mem_refs 15135515 # number of memory refs -system.cpu0.num_load_insts 9184477 # Number of load instructions -system.cpu0.num_store_insts 5951038 # Number of store instructions -system.cpu0.num_idle_cycles 3683437200.584730 # Number of idle cycles -system.cpu0.num_busy_cycles 57233845.415270 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles -system.cpu0.Branches 8650704 # Number of branches fetched -system.cpu0.op_class::No_OpClass 3102513 5.42% 5.42% # Class of executed instruction -system.cpu0.op_class::IntAlu 37823162 66.09% 71.51% # Class of executed instruction -system.cpu0.op_class::IntMult 59490 0.10% 71.61% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 18488 0.03% 71.65% # Class of executed instruction +system.cpu0.num_mem_refs 15135573 # number of memory refs +system.cpu0.num_load_insts 9184516 # Number of load instructions +system.cpu0.num_store_insts 5951057 # Number of store instructions +system.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles +system.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984699 # Percentage of idle cycles +system.cpu0.Branches 8650822 # Number of branches fetched +system.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction +system.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction +system.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction +system.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction @@ -337,38 +336,38 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::MemRead 9401052 16.43% 88.08% # Class of executed instruction -system.cpu0.op_class::MemWrite 5956984 10.41% 98.49% # Class of executed instruction -system.cpu0.op_class::IprAccess 866222 1.51% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction +system.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction +system.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 57230132 # Class of executed instruction +system.cpu0.op_class::total 57230699 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 101703 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174866 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -408,7 +407,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # nu system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal::swpipl 168033 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed @@ -417,19 +416,19 @@ system.cpu0.kern.callpal::whami 2 0.00% 97.18% # nu system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183291 # number of callpals executed +system.cpu0.kern.callpal::total 183289 # number of callpals executed system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1157 -system.cpu0.kern.mode_good::user 1158 +system.cpu0.kern.mode_good::kernel 1155 +system.cpu0.kern.mode_good::user 1156 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3763 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -463,18 +462,18 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 131930255 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 246743474 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) +system.toL2Bus.throughput 133353257 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 246745714 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes) system.iobus.throughput 1460501 # Throughput (bytes/s) system.iobus.data_through_bus 2731626 # Total data (bytes) -system.cpu0.icache.tags.replacements 884404 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 56345132 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 884916 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 63.672859 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 884408 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -482,26 +481,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 58115132 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 58115132 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits -system.cpu0.icache.overall_hits::total 56345132 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses -system.cpu0.icache.overall_misses::total 885000 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits +system.cpu0.icache.overall_hits::total 56345695 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses +system.cpu0.icache.overall_misses::total 885004 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses @@ -517,13 +516,13 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1978686 # number of replacements -system.cpu0.dcache.tags.tagsinuse 507.129778 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13123753 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1979198 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.630844 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1978697 # number of replacements +system.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -531,44 +530,44 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62404072 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62404072 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits +system.cpu0.dcache.overall_hits::total 12760647 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses +system.cpu0.dcache.overall_misses::total 1969341 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses @@ -589,8 +588,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks -system.cpu0.dcache.writebacks::total 775641 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks +system.cpu0.dcache.writebacks::total 775643 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -624,34 +623,34 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.numCycles 3740248099 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5931958 # Number of instructions committed -system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses +system.cpu1.committedInsts 5931963 # Number of instructions committed +system.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses system.cpu1.num_func_calls 182742 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5550578 # number of integer instructions +system.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls +system.cpu1.num_int_insts 5550581 # number of integer instructions system.cpu1.num_fp_insts 28590 # number of float instructions -system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written +system.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written system.cpu1.num_mem_refs 1926244 # number of memory refs system.cpu1.num_load_insts 1170888 # Number of load instructions system.cpu1.num_store_insts 755356 # Number of store instructions -system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles -system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles +system.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles +system.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles -system.cpu1.Branches 836747 # Number of branches fetched +system.cpu1.Branches 836749 # Number of branches fetched system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 3533366 59.53% 63.57% # Class of executed instruction +system.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction -system.cpu1.op_class::FloatAdd 7265 0.12% 63.85% # Class of executed instruction +system.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction @@ -681,9 +680,9 @@ system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Cl system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 5935766 # Class of executed instruction +system.cpu1.op_class::total 5935771 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl @@ -695,11 +694,11 @@ system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # nu system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -751,48 +750,48 @@ system.cpu1.kern.mode_switch_good::kernel 0.592449 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 103091 # number of replacements -system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 5832136 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 103603 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 56.293119 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 103097 # number of replacements +system.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 6039396 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 6039396 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits -system.cpu1.icache.overall_hits::total 5832136 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses -system.cpu1.icache.overall_misses::total 103630 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5832135 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5832135 # number of overall hits +system.cpu1.icache.overall_hits::total 5832135 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 103636 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 103636 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 103636 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 103636 # number of overall misses +system.cpu1.icache.overall_misses::total 103636 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5935771 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5935771 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017460 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017460 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017460 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017460 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,45 +801,45 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 62044 # number of replacements -system.cpu1.dcache.tags.tagsinuse 421.562730 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1836054 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 62382 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.432432 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 62047 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 62385 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.430953 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.558473 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823356 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823356 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 7735310 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 7735310 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 7735314 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109520 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109520 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707454 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 707454 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses +system.cpu1.dcache.demand_hits::cpu1.data 1816974 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1816974 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1816974 # number of overall hits +system.cpu1.dcache.overall_hits::total 1816974 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41445 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41445 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25851 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 25851 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses -system.cpu1.dcache.overall_misses::total 67292 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 67296 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67296 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67296 # number of overall misses +system.cpu1.dcache.overall_misses::total 67296 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) @@ -853,18 +852,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1884270 system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036009 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036009 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035253 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035253 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035715 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035715 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035715 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035715 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -873,8 +872,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks -system.cpu1.dcache.writebacks::total 41012 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks +system.cpu1.dcache.writebacks::total 41020 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index d987ad3fa..8a7bfd4c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,55 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332258000 # Number of ticks simulated -final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829332049000 # Number of ticks simulated +final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2367650 # Simulator instruction rate (inst/s) -host_op_rate 2367648 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72140813877 # Simulator tick rate (ticks/s) -host_mem_usage 343680 # Number of bytes of host memory used -host_seconds 25.36 # Real time elapsed on the host -sim_insts 60038305 # Number of instructions simulated -sim_ops 60038305 # Number of ops (including micro ops) simulated +host_inst_rate 2314619 # Simulator instruction rate (inst/s) +host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70524837278 # Simulator tick rate (ticks/s) +host_mem_usage 315304 # Number of bytes of host memory used +host_seconds 25.94 # Real time elapsed on the host +sim_insts 60038433 # Number of instructions simulated +sim_ops 60038433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 42552540 # Throughput (bytes/s) -system.membus.data_through_bus 77842734 # Total data (bytes) +system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 41099809 # Throughput (bytes/s) +system.membus.data_through_bus 75185198 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -57,26 +60,24 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375534 # Number of tag accesses system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses +system.iocache.demand_misses::total 174 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 174 # number of overall misses +system.iocache.overall_misses::total 174 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -87,10 +88,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -109,7 +108,7 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710427 # DTB read hits +system.cpu.dtb.read_hits 9710428 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses @@ -117,14 +116,14 @@ system.cpu.dtb.write_hits 6352498 # DT system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062925 # DTB hits +system.cpu.dtb.data_hits 16062926 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974648 # ITB hits +system.cpu.itb.fetch_hits 4974637 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979654 # ITB accesses +system.cpu.itb.fetch_accesses 4979643 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -137,34 +136,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664517 # number of cpu cycles simulated +system.cpu.numCycles 3658664099 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038305 # Number of instructions committed -system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses +system.cpu.committedInsts 60038433 # Number of instructions committed +system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913521 # number of integer instructions +system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913650 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115709 # number of memory refs -system.cpu.num_load_insts 9747513 # Number of load instructions +system.cpu.num_mem_refs 16115710 # number of memory refs +system.cpu.num_load_insts 9747514 # Number of load instructions system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles -system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles +system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles +system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983585 # Percentage of idle cycles -system.cpu.Branches 9064385 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199104 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39460699 65.71% 71.04% # Class of executed instruction -system.cpu.op_class::IntMult 60680 0.10% 71.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 71.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 25609 0.04% 71.18% # Class of executed instruction +system.cpu.Branches 9064413 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction +system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction @@ -190,34 +189,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975081 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050143 # Class of executed instruction +system.cpu.op_class::total 60050271 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -256,7 +255,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -265,20 +264,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192180 # number of callpals executed +system.cpu.kern.callpal::total 192179 # number of callpals executed system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -313,13 +312,13 @@ system.tsunami.ethernet.postedInterrupts 0 # nu system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.iobus.throughput 1480181 # Throughput (bytes/s) system.iobus.data_through_bus 2707742 # Total data (bytes) -system.cpu.icache.tags.replacements 919594 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215243 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59129922 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920106 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.264250 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 919591 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -327,26 +326,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970364 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970364 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits -system.cpu.icache.overall_hits::total 59129922 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses -system.cpu.icache.overall_misses::total 920221 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits +system.cpu.icache.overall_hits::total 59130053 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses +system.cpu.icache.overall_misses::total 920218 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -362,15 +361,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992301 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433239 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301014 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992295 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy @@ -379,67 +378,67 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737437 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737437 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,14 +447,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks -system.cpu.l2cache.writebacks::total 74291 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks +system.cpu.l2cache.writebacks::total 74285 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2042702 # number of replacements +system.cpu.dcache.tags.replacements 2042683 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043214 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870759 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -465,52 +464,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369799 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369799 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits -system.cpu.dcache.overall_hits::total 13655992 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses -system.cpu.dcache.overall_misses::total 2026069 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits +system.cpu.dcache.overall_hits::total 13656011 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses +system.cpu.dcache.overall_misses::total 2026051 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -519,11 +518,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks -system.cpu.dcache.writebacks::total 833491 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks +system.cpu.dcache.writebacks::total 833475 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 132867917 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 243049454 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a1c48ce35..034bdfed2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,137 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962822 # Number of seconds simulated -sim_ticks 1962822184500 # Number of ticks simulated -final_tick 1962822184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962815 # Number of seconds simulated +sim_ticks 1962815218500 # Number of ticks simulated +final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 916137 # Simulator instruction rate (inst/s) -host_op_rate 916137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30287148246 # Simulator tick rate (ticks/s) -host_mem_usage 346744 # Number of bytes of host memory used -host_seconds 64.81 # Real time elapsed on the host -sim_insts 59372170 # Number of instructions simulated -sim_ops 59372170 # Number of ops (including micro ops) simulated +host_inst_rate 1506000 # Simulator instruction rate (inst/s) +host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49787604582 # Simulator tick rate (ticks/s) +host_mem_usage 317424 # Number of bytes of host memory used +host_seconds 39.42 # Real time elapsed on the host +sim_insts 59372159 # Number of instructions simulated +sim_ops 59372159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 724800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24150336 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 138496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1080640 # Number of bytes read from this memory -system.physmem.bytes_read::total 28743616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 724800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 138496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7747520 # Number of bytes written to this memory -system.physmem.bytes_written::total 7747520 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377349 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16885 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449119 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121055 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 369264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12303884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1349763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 550554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14644024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369264 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3947133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3947133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3947133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12303884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1349763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 550554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449119 # Number of read requests accepted -system.physmem.writeReqs 121055 # Number of write requests accepted -system.physmem.readBursts 449119 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121055 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28736320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7746176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28743616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7747520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory +system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory +system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408000 # Number of read requests accepted +system.physmem.writeReqs 121085 # Number of write requests accepted +system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue +system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28065 # Per bank write bursts -system.physmem.perBankRdBursts::1 28141 # Per bank write bursts -system.physmem.perBankRdBursts::2 27986 # Per bank write bursts -system.physmem.perBankRdBursts::3 28553 # Per bank write bursts -system.physmem.perBankRdBursts::4 28160 # Per bank write bursts -system.physmem.perBankRdBursts::5 27775 # Per bank write bursts -system.physmem.perBankRdBursts::6 27616 # Per bank write bursts -system.physmem.perBankRdBursts::7 27528 # Per bank write bursts -system.physmem.perBankRdBursts::8 27559 # Per bank write bursts -system.physmem.perBankRdBursts::9 27974 # Per bank write bursts -system.physmem.perBankRdBursts::10 27981 # Per bank write bursts -system.physmem.perBankRdBursts::11 28021 # Per bank write bursts -system.physmem.perBankRdBursts::12 28612 # Per bank write bursts -system.physmem.perBankRdBursts::13 28738 # Per bank write bursts -system.physmem.perBankRdBursts::14 28459 # Per bank write bursts -system.physmem.perBankRdBursts::15 27837 # Per bank write bursts +system.physmem.perBankRdBursts::0 25223 # Per bank write bursts +system.physmem.perBankRdBursts::1 25569 # Per bank write bursts +system.physmem.perBankRdBursts::2 25254 # Per bank write bursts +system.physmem.perBankRdBursts::3 25702 # Per bank write bursts +system.physmem.perBankRdBursts::4 25695 # Per bank write bursts +system.physmem.perBankRdBursts::5 25237 # Per bank write bursts +system.physmem.perBankRdBursts::6 25154 # Per bank write bursts +system.physmem.perBankRdBursts::7 25289 # Per bank write bursts +system.physmem.perBankRdBursts::8 25197 # Per bank write bursts +system.physmem.perBankRdBursts::9 25673 # Per bank write bursts +system.physmem.perBankRdBursts::10 25761 # Per bank write bursts +system.physmem.perBankRdBursts::11 25821 # Per bank write bursts +system.physmem.perBankRdBursts::12 25887 # Per bank write bursts +system.physmem.perBankRdBursts::13 25811 # Per bank write bursts +system.physmem.perBankRdBursts::14 25568 # Per bank write bursts +system.physmem.perBankRdBursts::15 24971 # Per bank write bursts system.physmem.perBankWrBursts::0 7862 # Per bank write bursts -system.physmem.perBankWrBursts::1 7636 # Per bank write bursts +system.physmem.perBankWrBursts::1 7635 # Per bank write bursts system.physmem.perBankWrBursts::2 7481 # Per bank write bursts -system.physmem.perBankWrBursts::3 8065 # Per bank write bursts -system.physmem.perBankWrBursts::4 7619 # Per bank write bursts +system.physmem.perBankWrBursts::3 8078 # Per bank write bursts +system.physmem.perBankWrBursts::4 7635 # Per bank write bursts system.physmem.perBankWrBursts::5 7244 # Per bank write bursts -system.physmem.perBankWrBursts::6 7159 # Per bank write bursts -system.physmem.perBankWrBursts::7 6941 # Per bank write bursts +system.physmem.perBankWrBursts::6 7160 # Per bank write bursts +system.physmem.perBankWrBursts::7 6937 # Per bank write bursts system.physmem.perBankWrBursts::8 6882 # Per bank write bursts system.physmem.perBankWrBursts::9 7297 # Per bank write bursts -system.physmem.perBankWrBursts::10 7427 # Per bank write bursts -system.physmem.perBankWrBursts::11 7400 # Per bank write bursts +system.physmem.perBankWrBursts::10 7429 # Per bank write bursts +system.physmem.perBankWrBursts::11 7398 # Per bank write bursts system.physmem.perBankWrBursts::12 8124 # Per bank write bursts system.physmem.perBankWrBursts::13 8265 # Per bank write bursts -system.physmem.perBankWrBursts::14 8168 # Per bank write bursts +system.physmem.perBankWrBursts::14 8169 # Per bank write bursts system.physmem.perBankWrBursts::15 7464 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1962815073500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 1962808109000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449119 # Read request sizes (log2) +system.physmem.readPktSize::6 408000 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2087 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121085 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -158,356 +161,357 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 68642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.489409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 323.678439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.279001 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15609 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11929 17.38% 40.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5150 7.50% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3087 4.50% 52.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3390 4.94% 57.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1779 2.59% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1473 2.15% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1315 1.92% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24910 36.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 68642 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7087 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 63.355581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1920.089024 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 7082 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.01% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::122880-126975 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7087 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.078312 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.846071 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.814192 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5314 74.98% 74.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 115 1.62% 76.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1264 17.84% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 37 0.52% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.17% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 12 0.17% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 26 0.37% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 96 1.35% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.25% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 39 0.55% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.23% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 10 0.14% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 12 0.17% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 8 0.11% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.06% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 15 0.21% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.04% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 4 0.06% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.03% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 10 0.14% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 6 0.08% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.08% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 4 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 10 0.14% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 9 0.13% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 14 0.20% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7087 # Writes before turning the bus around for reads -system.physmem.totQLat 7297703000 # Total ticks spent queuing -system.physmem.totMemAccLat 15716546750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2245025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16253.06 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.09% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.15% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads +system.physmem.totQLat 2167934250 # Total ticks spent queuing +system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35003.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing -system.physmem.readRowHits 403892 # Number of row buffer hits during reads -system.physmem.writeRowHits 97505 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.55 # Row buffer hit rate for writes -system.physmem.avgGap 3442484.35 # Average gap between requests -system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840580762750 # Time in different power states -system.physmem.memoryStateTime::REF 65542880000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing +system.physmem.readRowHits 365758 # Number of row buffer hits during reads +system.physmem.writeRowHits 97091 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes +system.physmem.avgGap 3709816.21 # Average gap between requests +system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states +system.physmem.memoryStateTime::REF 65542620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56696821000 # Time in different power states +system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18645480 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292657 # Transaction distribution -system.membus.trans_dist::ReadResp 292657 # Transaction distribution +system.membus.throughput 17291736 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292660 # Transaction distribution +system.membus.trans_dist::ReadResp 292660 # Transaction distribution system.membus.trans_dist::WriteReq 12414 # Transaction distribution system.membus.trans_dist::WriteResp 12414 # Transaction distribution -system.membus.trans_dist::Writeback 121055 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1018 # Transaction distribution +system.membus.trans_dist::Writeback 79533 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution -system.membus.trans_dist::ReadExReq 164356 # Transaction distribution -system.membus.trans_dist::ReadExResp 164254 # Transaction distribution +system.membus.trans_dist::ReadExReq 122803 # Transaction distribution +system.membus.trans_dist::ReadExResp 122701 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 943501 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1068148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31184320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31253058 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36559874 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36559874 # Total data (bytes) -system.membus.snoop_data_through_bus 37888 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39221000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31201152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31269890 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33930178 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33930178 # Total data (bytes) +system.membus.snoop_data_through_bus 10304 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 39224500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1574833000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1533573250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3826410374 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3826483141 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376647250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43139750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342221 # number of replacements -system.l2c.tags.tagsinuse 65256.412579 # Cycle average of tags in use -system.l2c.tags.total_refs 2544259 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407367 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.245619 # Average number of references to valid blocks. +system.l2c.tags.replacements 342222 # number of replacements +system.l2c.tags.tagsinuse 65256.426750 # Cycle average of tags in use +system.l2c.tags.total_refs 2542307 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407368 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.240812 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55518.574788 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3744.543964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4299.514442 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1171.756098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 522.023286 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.847146 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.057137 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065605 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017880 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55518.260732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3744.767678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4299.632317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1171.746225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 522.019798 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.847141 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.057141 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.065607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.017879 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.007965 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.995734 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65146 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 748 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 5288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7256 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51736 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7253 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51739 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994049 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26948745 # Number of tag accesses -system.l2c.tags.data_accesses 26948745 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 527962 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 377923 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 461443 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 449896 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1817224 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 850135 # number of Writeback hits -system.l2c.Writeback_hits::total 850135 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 136 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 26946350 # Number of tag accesses +system.l2c.tags.data_accesses 26946350 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 527823 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 377901 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 461413 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 449863 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1817000 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 850078 # 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ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.993252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52912.555559 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001.767960 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.650716 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56065.515243 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60544.909206 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56643.410992 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56070.797953 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60481.716729 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56639.797032 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -643,101 +647,93 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.570023 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.569942 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756486423000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.570023 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035626 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035626 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756486320000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569942 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035621 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375552 # Number of tag accesses system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21474883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21474883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12370994210 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12370994210 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12392469093 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12392469093 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12392469093 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12392469093 # number of overall miss cycles +system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses +system.iocache.demand_misses::total 176 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 176 # number of overall misses +system.iocache.overall_misses::total 176 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122016.380682 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122016.380682 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 297723.195273 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 297723.195273 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 296982.100580 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 296982.100580 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 362942 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28216 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.862986 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41523 # number of writebacks -system.iocache.writebacks::total 41523 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10208100710 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10208100710 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10220422593 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10220422593 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10220422593 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10220422593 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2504351556 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2504351556 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70010.698864 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70010.698864 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 245670.502262 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 245670.502262 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -755,22 +751,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 6067358 # DTB read hits +system.cpu0.dtb.read_hits 6067147 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 4265662 # DTB write hits +system.cpu0.dtb.write_hits 4265547 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 10333020 # DTB hits +system.cpu0.dtb.data_hits 10332694 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3354842 # ITB hits +system.cpu0.itb.fetch_hits 3354719 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3358826 # ITB accesses +system.cpu0.itb.fetch_accesses 3358703 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -783,34 +779,34 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925644369 # number of cpu cycles simulated +system.cpu0.numCycles 3925630437 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 38276564 # Number of instructions committed -system.cpu0.committedOps 38276564 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 35596868 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 153627 # Number of float alu accesses -system.cpu0.num_func_calls 936507 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4464991 # number of instructions that are conditional controls -system.cpu0.num_int_insts 35596868 # number of integer instructions -system.cpu0.num_fp_insts 153627 # number of float instructions -system.cpu0.num_int_register_reads 48919002 # number of times the integer registers were read -system.cpu0.num_int_register_writes 26532177 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 75066 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 75978 # number of times the floating registers were written -system.cpu0.num_mem_refs 10366198 # number of memory refs -system.cpu0.num_load_insts 6090760 # Number of load instructions -system.cpu0.num_store_insts 4275438 # Number of store instructions -system.cpu0.num_idle_cycles 3742234246.498094 # Number of idle cycles -system.cpu0.num_busy_cycles 183410122.501907 # Number of busy cycles -system.cpu0.not_idle_fraction 0.046721 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.953279 # Percentage of idle cycles -system.cpu0.Branches 5694814 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2096369 5.48% 5.48% # Class of executed instruction -system.cpu0.op_class::IntAlu 24995370 65.29% 70.76% # Class of executed instruction -system.cpu0.op_class::IntMult 39322 0.10% 70.86% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.86% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12602 0.03% 70.90% # Class of executed instruction +system.cpu0.committedInsts 38276405 # Number of instructions committed +system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses +system.cpu0.num_func_calls 936479 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls +system.cpu0.num_int_insts 35596815 # number of integer instructions +system.cpu0.num_fp_insts 153493 # number of float instructions +system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read +system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written +system.cpu0.num_mem_refs 10365856 # number of memory refs +system.cpu0.num_load_insts 6090539 # Number of load instructions +system.cpu0.num_store_insts 4275317 # Number of store instructions +system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles +system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles +system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles +system.cpu0.Branches 5694884 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction +system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction +system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction +system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction @@ -836,37 +832,37 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::MemRead 6233117 16.28% 87.18% # Class of executed instruction -system.cpu0.op_class::MemWrite 4280683 11.18% 98.36% # Class of executed instruction -system.cpu0.op_class::IprAccess 626236 1.64% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction +system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction +system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 38285582 # Class of executed instruction +system.cpu0.op_class::total 38285423 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4866 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 138364 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 44810 38.76% 38.76% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 68668 59.40% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 115600 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 44285 48.84% 48.84% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 44269 48.82% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 90676 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1909704051500 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94854000 0.00% 97.30% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 764030500 0.04% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 52245891000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962821412500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988284 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.644682 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed @@ -903,10 +899,10 @@ system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2218 1.80% 1.88% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed -system.cpu0.kern.callpal::swpipl 109461 88.95% 90.88% # number of callpals executed +system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed @@ -915,21 +911,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.30% # nu system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 123054 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5726 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches +system.cpu0.kern.callpal::total 123047 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1370 -system.cpu0.kern.mode_good::user 1371 +system.cpu0.kern.mode_good::kernel 1371 +system.cpu0.kern.mode_good::user 1372 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.239260 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.386220 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959031016000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3790392000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2219 # number of times the context was actually changed +system.cpu0.kern.swap_context 2217 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -961,42 +957,43 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 108070579 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2148343 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2148328 # Transaction distribution +system.toL2Bus.throughput 109416622 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 850135 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4614 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1062 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5676 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 363639 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 322090 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078600 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181406 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927231 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598323 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5785560 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34514560 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81611821 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29671360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63815893 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 209613634 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 209603138 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2520192 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5075991989 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 209584002 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2429088500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4030648808 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2086694241 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 2646669064 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1391043 # Throughput (bytes/s) +system.iobus.throughput 1391048 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7376 # Transaction distribution system.iobus.trans_dist::ReadResp 7376 # Transaction distribution system.iobus.trans_dist::WriteReq 53966 # Transaction distribution @@ -1056,21 +1053,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380139843 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43231750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 538677 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.393435 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 37746273 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 539189 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.005644 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 538541 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393435 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1079,44 +1076,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 38824893 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 38824893 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 37746273 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 37746273 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 37746273 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 37746273 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 37746273 # number of overall hits -system.cpu0.icache.overall_hits::total 37746273 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539310 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 539310 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539310 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 539310 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539310 # number of overall misses -system.cpu0.icache.overall_misses::total 539310 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7764312000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7764312000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7764312000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7764312000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7764312000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7764312000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285583 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38285583 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38285583 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38285583 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38285583 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38285583 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014087 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014087 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014087 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14396.751405 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14396.751405 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14396.751405 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14396.751405 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14396.751405 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14396.751405 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 38824598 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits +system.cpu0.icache.overall_hits::total 37746250 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses 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37533.515459 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37533.515459 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37533.515459 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 42232679 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 42232679 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5299779 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5299779 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3905718 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3905718 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124794 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 124794 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131579 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 131579 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StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 869501 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 869501 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 869501 # number of overall misses +system.cpu0.dcache.overall_misses::total 869501 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374202500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 23374202500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262527483 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9262527483 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102834500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 102834500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3584562 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3584562 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 32636729983 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 32636729983 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 32636729983 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 32636729983 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945097 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5945097 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4129901 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4129901 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132623 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 132623 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132076 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 132076 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10074998 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10074998 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10074998 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10074998 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108546 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.108546 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054283 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.054283 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059032 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059032 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003763 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003763 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086303 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086303 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086303 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086303 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7212.398390 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7212.398390 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1246,62 +1243,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 405192 # number of writebacks -system.cpu0.dcache.writebacks::total 405192 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 645326 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224198 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 224198 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 495 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 869524 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 869524 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 869524 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 869524 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958342736 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958342736 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8764766768 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8764766768 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87220250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87220250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2576938 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2576938 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723109504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30723109504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723109504 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30723109504 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004924500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004924500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718153000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718153000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723077500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723077500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108544 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108544 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059060 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059060 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003748 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003748 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086302 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086302 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34026.744213 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34026.744213 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39093.866886 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39093.866886 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11134.973829 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11134.973829 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5205.935354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5205.935354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks +system.cpu0.dcache.writebacks::total 405151 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1313,22 +1310,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3617105 # DTB read hits +system.cpu1.dtb.read_hits 3617054 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 2433899 # DTB write hits +system.cpu1.dtb.write_hits 2433875 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 6051004 # DTB hits +system.cpu1.dtb.data_hits 6050929 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1988116 # ITB hits +system.cpu1.itb.fetch_hits 1988100 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1989180 # ITB accesses +system.cpu1.itb.fetch_accesses 1989164 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1341,34 +1338,34 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923841481 # number of cpu cycles simulated +system.cpu1.numCycles 3923841470 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21095606 # Number of instructions committed -system.cpu1.committedOps 21095606 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 19410796 # Number of integer alu accesses +system.cpu1.committedInsts 21095754 # Number of instructions committed +system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses -system.cpu1.num_func_calls 648522 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2286515 # number of instructions that are conditional controls -system.cpu1.num_int_insts 19410796 # number of integer instructions +system.cpu1.num_func_calls 648514 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls +system.cpu1.num_int_insts 19410964 # number of integer instructions system.cpu1.num_fp_insts 175175 # number of float instructions -system.cpu1.num_int_register_reads 26519930 # number of times the integer registers were read -system.cpu1.num_int_register_writes 14289781 # number of times the integer registers were written +system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read +system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written -system.cpu1.num_mem_refs 6073244 # number of memory refs -system.cpu1.num_load_insts 3630952 # Number of load instructions -system.cpu1.num_store_insts 2442292 # Number of store instructions -system.cpu1.num_idle_cycles 3837671905.347151 # Number of idle cycles -system.cpu1.num_busy_cycles 86169575.652849 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021961 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978039 # Percentage of idle cycles -system.cpu1.Branches 3164985 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1250072 5.92% 5.92% # Class of executed instruction -system.cpu1.op_class::IntAlu 13187049 62.50% 68.43% # Class of executed instruction -system.cpu1.op_class::IntMult 30193 0.14% 68.57% # Class of executed instruction +system.cpu1.num_mem_refs 6073169 # number of memory refs +system.cpu1.num_load_insts 3630901 # Number of load instructions +system.cpu1.num_store_insts 2442268 # Number of store instructions +system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles +system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles +system.cpu1.Branches 3165037 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction +system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction +system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13163 0.06% 68.63% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction @@ -1394,34 +1391,34 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::MemRead 3726131 17.66% 86.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 2443312 11.58% 97.88% # Class of executed instruction -system.cpu1.op_class::IprAccess 446806 2.12% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction +system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction +system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21098485 # Class of executed instruction +system.cpu1.op_class::total 21098633 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 100735 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 37219 40.29% 40.29% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 53109 57.49% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 92384 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 36367 48.68% 48.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 36281 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 74704 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1906656399000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 706249000 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54498695500 2.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961920710500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.683142 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808625 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1443,7 +1440,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # nu system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed -system.cpu1.kern.callpal::swpipl 87061 91.90% 94.06% # number of callpals executed +system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed @@ -1452,72 +1449,72 @@ system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # nu system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 94734 # number of callpals executed +system.cpu1.kern.callpal::total 94732 # number of callpals executed system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches -system.cpu1.kern.mode_switch::user 366 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 414 -system.cpu1.kern.mode_good::user 366 +system.cpu1.kern.mode_good::kernel 415 +system.cpu1.kern.mode_good::user 367 system.cpu1.kern.mode_good::idle 48 -system.cpu1.kern.mode_switch_good::kernel 0.171429 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.171856 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 65780447000 3.35% 3.35% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1486717000 0.08% 3.43% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893764152500 96.57% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2021 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 463064 # number of replacements -system.cpu1.icache.tags.tagsinuse 500.061225 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20634869 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463576 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 44.512376 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 463035 # number of replacements +system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061225 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21562101 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21562101 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20634869 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20634869 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20634869 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20634869 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20634869 # number of overall hits -system.cpu1.icache.overall_hits::total 20634869 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463616 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463616 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463616 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463616 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463616 # number of overall misses -system.cpu1.icache.overall_misses::total 463616 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6201828741 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6201828741 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6201828741 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6201828741 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6201828741 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6201828741 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098485 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21098485 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21098485 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21098485 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21098485 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21098485 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021974 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.021974 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021974 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.021974 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021974 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.021974 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13377.080905 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13377.080905 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13377.080905 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13377.080905 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20635046 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20635046 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20635046 # number of overall hits +system.cpu1.icache.overall_hits::total 20635046 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 463587 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 463587 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 463587 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 463587 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 463587 # number of overall misses +system.cpu1.icache.overall_misses::total 463587 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6202855739 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6202855739 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6202855739 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6202855739 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6202855739 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6202855739 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098633 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21098633 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21098633 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21098633 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21098633 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21098633 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021972 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021972 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.021972 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021972 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1526,118 +1523,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463616 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 463616 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 463616 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 463616 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 463616 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 463616 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5273752259 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5273752259 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5273752259 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5273752259 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5273752259 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5273752259 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021974 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021974 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11375.259394 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 463587 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 463587 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 463587 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 463587 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5274833261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5274833261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 581734 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.027113 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5462976 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 582077 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 9.385315 # Average number of references to valid blocks. +system.cpu1.dcache.tags.replacements 581700 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.027042 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5462019 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 582040 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 9.384267 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027113 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027042 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 300 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24828652 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24828652 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3080166 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3080166 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2260006 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2260006 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60928 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 60928 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71558 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71558 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5340172 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5340172 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5340172 # number of overall hits -system.cpu1.dcache.overall_hits::total 5340172 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 473210 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 473210 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 102503 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 102503 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11672 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11672 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 567 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 567 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 575713 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 575713 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 575713 # number of overall misses -system.cpu1.dcache.overall_misses::total 575713 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938920500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5938920500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2340100234 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2340100234 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149905750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 149905750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4163080 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4163080 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8279020734 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8279020734 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8279020734 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8279020734 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553376 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3553376 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362509 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2362509 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72600 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72600 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 72125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5915885 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5915885 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5915885 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5915885 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133172 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.133172 # miss rate for ReadReq accesses +system.cpu1.dcache.tags.occ_task_id_blocks::1024 340 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.664062 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24828314 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24828314 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3080149 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3080149 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2259986 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2259986 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60927 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 60927 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71555 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71555 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5340135 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5340135 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5340135 # number of overall hits +system.cpu1.dcache.overall_hits::total 5340135 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 473178 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 473178 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 102501 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 102501 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11671 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11671 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 568 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 568 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 575679 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 575679 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 575679 # number of overall misses +system.cpu1.dcache.overall_misses::total 575679 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938208750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5938208750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2338814234 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2338814234 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149892750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 149892750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4181580 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8277022984 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8277022984 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8277022984 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3553327 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362487 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2362487 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 72598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72123 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 72123 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5915814 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5915814 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 5915814 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 5915814 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133165 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.133165 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160771 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160771 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007861 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007861 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097316 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.097316 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097316 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.097316 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12550.285286 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12550.285286 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22829.578003 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22829.578003 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.193112 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.193112 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.292769 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.292769 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14380.465152 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14380.465152 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14380.465152 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14380.465152 # average overall miss latency +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160762 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160762 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007875 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007875 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097312 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.097312 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097312 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.097312 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency 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average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1646,62 +1643,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 444943 # number of writebacks -system.cpu1.dcache.writebacks::total 444943 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473210 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 473210 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102503 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 102503 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11672 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11672 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 567 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 567 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 575713 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 575713 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 575713 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 575713 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4992146500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4992146500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2128603766 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2128603766 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126561250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126561250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3028920 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3028920 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7120750266 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7120750266 # number of demand (read+write) MSHR miss cycles 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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3045420 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3045420 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7118815016 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7118815016 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7118815016 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907861000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907861000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387519500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387519500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133172 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133172 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907862000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907862000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387520500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387520500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133165 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133165 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160771 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160771 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007861 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007861 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.097316 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.097316 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10549.537203 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10549.537203 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20766.258217 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20766.258217 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.150274 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.150274 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.010582 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.010582 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.097312 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.097312 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 24f1d16b8..7916cb036 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,127 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.919447 # Number of seconds simulated -sim_ticks 1919446558000 # Number of ticks simulated -final_tick 1919446558000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.919439 # Number of seconds simulated +sim_ticks 1919438772000 # Number of ticks simulated +final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 885398 # Simulator instruction rate (inst/s) -host_op_rate 885398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30291378157 # Simulator tick rate (ticks/s) -host_mem_usage 344696 # Number of bytes of host memory used -host_seconds 63.37 # Real time elapsed on the host -sim_insts 56104177 # Number of instructions simulated -sim_ops 56104177 # Number of ops (including micro ops) simulated +host_inst_rate 1398299 # Simulator instruction rate (inst/s) +host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47840414078 # Simulator tick rate (ticks/s) +host_mem_usage 314348 # Number of bytes of host memory used +host_seconds 40.12 # Real time elapsed on the host +sim_insts 56102112 # Number of instructions simulated +sim_ops 56102112 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858240 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404032 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404032 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388410 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115688 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115688 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12950733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1381832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14775792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3857379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3857379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3857379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12950733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1381832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18633171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443146 # Number of read requests accepted -system.physmem.writeReqs 115688 # Number of write requests accepted -system.physmem.readBursts 443146 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115688 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28353856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 7402304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28361344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7404032 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401996 # Number of read requests accepted +system.physmem.writeReqs 115735 # Number of write requests accepted +system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue +system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27768 # Per bank write bursts -system.physmem.perBankRdBursts::1 28019 # Per bank write bursts -system.physmem.perBankRdBursts::2 28336 # Per bank write bursts -system.physmem.perBankRdBursts::3 28020 # Per bank write bursts -system.physmem.perBankRdBursts::4 27518 # Per bank write bursts -system.physmem.perBankRdBursts::5 27546 # Per bank write bursts -system.physmem.perBankRdBursts::6 26737 # Per bank write bursts -system.physmem.perBankRdBursts::7 26852 # Per bank write bursts -system.physmem.perBankRdBursts::8 27860 # Per bank write bursts -system.physmem.perBankRdBursts::9 27104 # Per bank write bursts -system.physmem.perBankRdBursts::10 27841 # Per bank write bursts -system.physmem.perBankRdBursts::11 27413 # Per bank write bursts -system.physmem.perBankRdBursts::12 27378 # Per bank write bursts -system.physmem.perBankRdBursts::13 28201 # Per bank write bursts -system.physmem.perBankRdBursts::14 28236 # Per bank write bursts -system.physmem.perBankRdBursts::15 28200 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25161 # Per bank write bursts +system.physmem.perBankRdBursts::1 25541 # Per bank write bursts +system.physmem.perBankRdBursts::2 25618 # Per bank write bursts +system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::4 24981 # Per bank write bursts +system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::6 24228 # Per bank write bursts +system.physmem.perBankRdBursts::7 24506 # Per bank write bursts +system.physmem.perBankRdBursts::8 25159 # Per bank write bursts +system.physmem.perBankRdBursts::9 24820 # Per bank write bursts +system.physmem.perBankRdBursts::10 25363 # Per bank write bursts +system.physmem.perBankRdBursts::11 24840 # Per bank write bursts +system.physmem.perBankRdBursts::12 24420 # Per bank write bursts +system.physmem.perBankRdBursts::13 25388 # Per bank write bursts +system.physmem.perBankRdBursts::14 25795 # Per bank write bursts +system.physmem.perBankRdBursts::15 25483 # Per bank write bursts system.physmem.perBankWrBursts::0 7550 # Per bank write bursts system.physmem.perBankWrBursts::1 7529 # Per bank write bursts -system.physmem.perBankWrBursts::2 7869 # Per bank write bursts -system.physmem.perBankWrBursts::3 7540 # Per bank write bursts +system.physmem.perBankWrBursts::2 7880 # Per bank write bursts +system.physmem.perBankWrBursts::3 7553 # Per bank write bursts system.physmem.perBankWrBursts::4 7115 # Per bank write bursts system.physmem.perBankWrBursts::5 6983 # Per bank write bursts system.physmem.perBankWrBursts::6 6321 # Per bank write bursts -system.physmem.perBankWrBursts::7 6313 # Per bank write bursts +system.physmem.perBankWrBursts::7 6319 # Per bank write bursts system.physmem.perBankWrBursts::8 7293 # Per bank write bursts -system.physmem.perBankWrBursts::9 6538 # Per bank write bursts +system.physmem.perBankWrBursts::9 6554 # Per bank write bursts system.physmem.perBankWrBursts::10 7205 # Per bank write bursts system.physmem.perBankWrBursts::11 6861 # Per bank write bursts system.physmem.perBankWrBursts::12 6964 # Per bank write bursts system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7979 # Per bank write bursts +system.physmem.perBankWrBursts::14 7980 # Per bank write bursts system.physmem.perBankWrBursts::15 7780 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1919434637000 # Total gap between requests +system.physmem.totGap 1919426851000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443146 # Read request sizes (log2) +system.physmem.readPktSize::6 401996 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115688 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115735 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,278 +151,267 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4608 # What write queue length does an incoming req see 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length does an incoming req see -system.physmem.wrQLenPdf::57 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 538.261302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 328.855989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.099114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14887 22.41% 22.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11472 17.27% 39.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4684 7.05% 46.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3132 4.71% 51.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3072 4.62% 56.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1874 2.82% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1342 2.02% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1444 2.17% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24522 36.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6775 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 65.389077 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.529238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2564.130292 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6772 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6775 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.071734 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.848509 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.695111 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5062 74.72% 74.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 127 1.87% 76.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1207 17.82% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 25 0.37% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.18% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.24% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 18 0.27% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 98 1.45% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 41 0.61% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.30% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.12% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.10% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 8 0.12% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 7 0.10% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 15 0.22% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 9 0.13% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 9 0.13% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 8 0.12% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 2 0.03% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.01% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 8 0.12% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 7 0.10% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 9 0.13% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6775 # Writes before turning the bus around for reads -system.physmem.totQLat 7315796250 # Total ticks spent queuing -system.physmem.totMemAccLat 15622590000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2215145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16513.13 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see 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172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 104 # What write queue length does an incoming req see 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row activation +system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads +system.physmem.totQLat 2117396500 # Total ticks spent queuing +system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35263.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing -system.physmem.readRowHits 398273 # Number of row buffer hits during reads -system.physmem.writeRowHits 93988 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.24 # Row buffer hit rate for writes -system.physmem.avgGap 3434713.42 # Average gap between requests -system.physmem.pageHitRate 88.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800016178000 # Time in different power states -system.physmem.memoryStateTime::REF 64094420000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing +system.physmem.readRowHits 360116 # Number of row buffer hits during reads +system.physmem.writeRowHits 93539 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes +system.physmem.avgGap 3707382.50 # Average gap between requests +system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states +system.physmem.memoryStateTime::REF 64094160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55332653250 # Time in different power states +system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18674823 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292356 # Transaction distribution -system.membus.trans_dist::ReadResp 292356 # Transaction distribution +system.membus.throughput 17291227 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292357 # Transaction distribution +system.membus.trans_dist::ReadResp 292357 # Transaction distribution system.membus.trans_dist::WriteReq 9649 # Transaction distribution system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115688 # Transaction distribution +system.membus.trans_dist::Writeback 74183 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158273 # Transaction distribution -system.membus.trans_dist::ReadExResp 158273 # Transaction distribution +system.membus.trans_dist::ReadExReq 116727 # Transaction distribution +system.membus.trans_dist::ReadExResp 116727 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035953 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30500812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35809932 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35809932 # Total data (bytes) -system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32376000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33179340 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1491996000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751677600 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376660500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.344872 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525004000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.344872 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084054 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084054 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21253133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21253133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12447285431 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12447285431 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12468538564 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12468538564 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12468538564 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12468538564 # number of overall miss cycles +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122850.479769 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299559.237365 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298826.568340 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298826.568340 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 365803 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28265 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.941907 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12255133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12255133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10284312431 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10284312431 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10296567564 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10296567564 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10296567564 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10296567564 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2506570306 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2506570306 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -438,22 +430,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052923 # DTB read hits -system.cpu.dtb.read_misses 10354 # DTB read misses +system.cpu.dtb.read_hits 9052614 # DTB read hits +system.cpu.dtb.read_misses 10356 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728911 # DTB read accesses -system.cpu.dtb.write_hits 6349403 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.dtb.read_accesses 728915 # DTB read accesses +system.cpu.dtb.write_hits 6349217 # DTB write hits +system.cpu.dtb.write_misses 1144 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15402326 # DTB hits -system.cpu.dtb.data_misses 11497 # DTB misses +system.cpu.dtb.write_accesses 291933 # DTB write accesses +system.cpu.dtb.data_hits 15401831 # DTB hits +system.cpu.dtb.data_misses 11500 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020843 # DTB accesses -system.cpu.itb.fetch_hits 4974965 # ITB hits +system.cpu.dtb.data_accesses 1020848 # DTB accesses +system.cpu.itb.fetch_hits 4974960 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979975 # ITB accesses +system.cpu.itb.fetch_accesses 4979970 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -466,34 +458,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3838893116 # number of cpu cycles simulated +system.cpu.numCycles 3838877544 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56104177 # Number of instructions committed -system.cpu.committedOps 56104177 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51979169 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324594 # Number of float alu accesses -system.cpu.num_func_calls 1481286 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461218 # number of instructions that are conditional controls -system.cpu.num_int_insts 51979169 # number of integer instructions -system.cpu.num_fp_insts 324594 # number of float instructions -system.cpu.num_int_register_reads 71209746 # number of times the integer registers were read -system.cpu.num_int_register_writes 38460532 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163708 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166588 # number of times the floating registers were written -system.cpu.num_mem_refs 15454993 # number of memory refs -system.cpu.num_load_insts 9089820 # Number of load instructions -system.cpu.num_store_insts 6365173 # Number of store instructions -system.cpu.num_idle_cycles 3587243859.498131 # Number of idle cycles -system.cpu.num_busy_cycles 251649256.501869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065553 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934447 # Percentage of idle cycles -system.cpu.Branches 8413035 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197761 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36186344 64.48% 70.18% # Class of executed instruction -system.cpu.op_class::IntMult 61011 0.11% 70.29% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.29% # Class of executed instruction -system.cpu.op_class::FloatAdd 25613 0.05% 70.34% # Class of executed instruction +system.cpu.committedInsts 56102112 # Number of instructions committed +system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1481236 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls +system.cpu.num_int_insts 51977185 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read +system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15454487 # number of memory refs +system.cpu.num_load_insts 9089505 # Number of load instructions +system.cpu.num_store_insts 6364982 # Number of store instructions +system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934449 # Percentage of idle cycles +system.cpu.Branches 8412678 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -519,34 +511,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316905 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371245 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953526 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56116041 # Class of executed instruction +system.cpu.op_class::total 56113979 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106210 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183167 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857252195000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91387500 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737178000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61365063500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1919445824000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692289 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814110 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -582,10 +574,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4179 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175948 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -594,21 +586,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192895 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.callpal::total 192894 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches +system.cpu.kern.mode_switch::user 1742 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1912 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323848 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1742 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392527 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46108525500 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5189217000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868148079500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4180 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -640,7 +632,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409867 # Throughput (bytes/s) +system.iobus.throughput 1409873 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51201 # Transaction distribution @@ -700,21 +692,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380199064 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43233500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 927875 # number of replacements -system.cpu.icache.tags.tagsinuse 508.303976 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55187496 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928386 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.444559 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 927724 # number of replacements +system.cpu.icache.tags.tagsinuse 508.304001 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55185585 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928235 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.452170 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.303976 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 508.304001 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -723,44 +715,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57044588 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57044588 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55187496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55187496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55187496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55187496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55187496 # number of overall hits -system.cpu.icache.overall_hits::total 55187496 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928546 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928546 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928546 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928546 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928546 # number of overall misses -system.cpu.icache.overall_misses::total 928546 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12910342260 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12910342260 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12910342260 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12910342260 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12910342260 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12910342260 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56116042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56116042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56116042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56116042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56116042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56116042 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016547 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016547 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016547 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016547 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016547 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016547 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13903.826262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13903.826262 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57042375 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57042375 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55185585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55185585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55185585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55185585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55185585 # number of overall hits +system.cpu.icache.overall_hits::total 55185585 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928395 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928395 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928395 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928395 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928395 # number of overall misses +system.cpu.icache.overall_misses::total 928395 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12914246500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12914246500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12914246500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12914246500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12914246500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12914246500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56113980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56113980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56113980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56113980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56113980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56113980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016545 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016545 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016545 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016545 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016545 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016545 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13910.293033 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13910.293033 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13910.293033 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13910.293033 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -769,135 +761,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928546 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928546 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928546 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928546 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928546 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928546 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048086740 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11048086740 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048086740 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11048086740 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048086740 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11048086740 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016547 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016547 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016547 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.265396 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.265396 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928395 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928395 # 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of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388800 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402093 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 800656260 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14299493254 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15100149514 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607242375 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607242375 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 800656260 # 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1895432500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229578000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229578000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250313 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141564 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116846 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116846 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13294 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388806 # number of demand (read+write) MSHR misses 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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173374 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173374 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173396 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173396 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -973,13 +965,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390190 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978877 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030691 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390702 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.088927 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1390084 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14030288 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390596 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.089406 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978877 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -987,72 +979,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63076279 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63076279 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802806 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802806 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845593 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845593 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183040 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183040 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199235 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199235 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648399 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648399 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648399 # number of overall hits -system.cpu.dcache.overall_hits::total 13648399 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069264 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069264 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304240 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304240 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17216 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17216 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373504 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373504 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373504 # number of overall misses -system.cpu.dcache.overall_misses::total 1373504 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29001409504 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29001409504 # 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(read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120520 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120520 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049471 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049471 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091433 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091433 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091433 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091433 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29056.421306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29056.421306 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63074137 # Number of tag accesses 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# number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069193 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304207 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304207 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17214 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17214 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373400 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373400 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373400 # number of overall misses +system.cpu.dcache.overall_misses::total 1373400 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28998201750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28998201750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906246382 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10906246382 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228174000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228174000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39904448132 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39904448132 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39904448132 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39904448132 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8871761 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8871761 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149649 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149649 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199227 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199227 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15021410 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15021410 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15021410 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15021410 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120516 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120516 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049467 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085963 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085963 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091429 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091429 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091429 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091429 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29055.226541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1061,54 +1053,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834591 # number of writebacks -system.cpu.dcache.writebacks::total 834591 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069264 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069264 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304240 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304240 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17216 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17216 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373504 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373504 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373504 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373504 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26737269496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26737269496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10246531614 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10246531614 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193767750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193767750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36983801110 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36983801110 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36983801110 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36983801110 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011220500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011220500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435456000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435456000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120520 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120520 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091433 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091433 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834526 # number of writebacks +system.cpu.dcache.writebacks::total 834526 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069193 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069193 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304207 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304207 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373400 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373400 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373400 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373400 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26734131250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26734131250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245126618 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245126618 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36979257868 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36979257868 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36979257868 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36979257868 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435455500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435455500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120516 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120516 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085963 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085963 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091429 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091429 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1116,31 +1108,32 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105186760 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2022129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022112 # Transaction distribution +system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5506418 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59425664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142473420 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 201899084 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 201889036 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2424633500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395400760 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186975140 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 547f88656..df149be6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,73 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.912098 # Number of seconds simulated -sim_ticks 912098398000 # Number of ticks simulated -final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.900855 # Number of seconds simulated +sim_ticks 900854787500 # Number of ticks simulated +final_tick 900854787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1024713 # Simulator instruction rate (inst/s) -host_op_rate 1319299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15163617701 # Simulator tick rate (ticks/s) -host_mem_usage 465872 # Number of bytes of host memory used -host_seconds 60.15 # Real time elapsed on the host -sim_insts 61636937 # Number of instructions simulated -sim_ops 79356422 # Number of ops (including micro ops) simulated +host_inst_rate 875862 # Simulator instruction rate (inst/s) +host_op_rate 1055198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12821864647 # Simulator tick rate (ticks/s) +host_mem_usage 433912 # Number of bytes of host memory used +host_seconds 70.26 # Real time elapsed on the host +sim_insts 61537412 # Number of instructions simulated +sim_ops 74137396 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory -system.physmem.bytes_read::total 49638724 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7222992 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 460108 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6580092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 258564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2992120 # Number of bytes read from this memory +system.physmem.bytes_read::total 49612932 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 460108 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 258564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 718672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4174784 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 7201872 # Number of bytes written to this memory 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-system.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822333 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s) 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responded to by this memory +system.physmem.num_reads::cpu1.inst 4131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 46770 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082398 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65231 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 822003 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43649210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 213 # Total read bandwidth from this memory (bytes/s) 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from this memory (bytes/s) +system.physmem.bw_write::total 7994487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4634247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43649210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 510746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10664471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 287021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3321468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 63067661 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -86,188 +82,180 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 64987015 # Throughput (bytes/s) -system.membus.data_through_bus 59274552 # Total data (bytes) +system.membus.throughput 65740815 # Throughput (bytes/s) +system.membus.data_through_bus 59222928 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 70660 # number of replacements -system.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use -system.l2c.tags.total_refs 1623334 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks. +system.l2c.tags.replacements 70256 # number of replacements +system.l2c.tags.tagsinuse 51491.506872 # Cycle average of tags in use +system.l2c.tags.total_refs 1633923 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 135467 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.061410 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 39155.338647 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.673377 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4830.605577 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5154.208952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1696.649192 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 652.030072 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.597463 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.078647 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025889 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009949 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.785698 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65207 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3771 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 12549 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3953 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 12685 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48286 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per 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# number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses 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# number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 662 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1076 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 94027 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 46518 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140545 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 98857 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 53649 # number of demand (read+write) misses -system.l2c.demand_misses::total 163292 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6774 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 103726 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4034 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 48346 # number of demand (read+write) misses +system.l2c.demand_misses::total 162887 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses -system.l2c.overall_misses::cpu0.data 98857 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses -system.l2c.overall_misses::cpu1.data 53649 # number of overall misses -system.l2c.overall_misses::total 163292 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 181579 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 174786 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1231558 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 567806 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 567806 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150610 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 98586 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 332189 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 273372 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1480754 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 332189 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 273372 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1480754 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.613937 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.565170 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.297593 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.196249 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.110276 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.297593 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.196249 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.110276 # miss rate for overall accesses +system.l2c.overall_misses::cpu0.inst 6774 # number of overall misses +system.l2c.overall_misses::cpu0.data 103726 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4034 # number of overall misses +system.l2c.overall_misses::cpu1.data 48346 # number of overall misses +system.l2c.overall_misses::total 162887 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4302 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1599 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 420018 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 212536 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4578 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 442577 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 148331 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1235884 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 571726 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 571726 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 4172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5430 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9602 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 652 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 700 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1352 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 145526 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 103666 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249192 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4302 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1599 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 420018 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 358062 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4578 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 442577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 251997 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1485076 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4302 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1599 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 420018 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 358062 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4578 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 442577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 251997 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1485076 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001876 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016128 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045635 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009115 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.012324 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018078 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.696548 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.926888 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.826807 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.634969 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945714 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.795858 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.646118 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.448730 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.564003 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001876 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016128 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.289687 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009115 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.191851 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109683 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001876 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016128 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.289687 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009115 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.191851 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109683 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -276,8 +264,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65561 # number of writebacks -system.l2c.writebacks::total 65561 # number of writebacks +system.l2c.writebacks::writebacks 65231 # number of writebacks +system.l2c.writebacks::total 65231 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -285,11 +273,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 154019817 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140481228 # Total data (bytes) +system.toL2Bus.throughput 156214740 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140726796 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 45731035 # Throughput (bytes/s) -system.iobus.data_through_bus 41711204 # Total data (bytes) +system.iobus.throughput 46301771 # Throughput (bytes/s) +system.iobus.data_through_bus 41711172 # Total data (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -313,25 +301,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7977762 # DTB read hits -system.cpu0.dtb.read_misses 3611 # DTB read misses -system.cpu0.dtb.write_hits 5967140 # DTB write hits -system.cpu0.dtb.write_misses 672 # DTB write misses +system.cpu0.dtb.read_hits 7391669 # DTB read hits +system.cpu0.dtb.read_misses 1915 # DTB read misses +system.cpu0.dtb.write_hits 6659638 # DTB write hits +system.cpu0.dtb.write_misses 1130 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7981373 # DTB read accesses -system.cpu0.dtb.write_accesses 5967812 # DTB write accesses +system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7393584 # DTB read accesses +system.cpu0.dtb.write_accesses 6660768 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13944902 # DTB hits -system.cpu0.dtb.misses 4283 # DTB misses -system.cpu0.dtb.accesses 13949185 # DTB accesses +system.cpu0.dtb.hits 14051307 # DTB hits +system.cpu0.dtb.misses 3045 # DTB misses +system.cpu0.dtb.accesses 14054352 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -353,8 +341,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30248608 # ITB inst hits -system.cpu0.itb.inst_misses 2175 # ITB inst misses +system.cpu0.itb.inst_hits 37936012 # ITB inst hits +system.cpu0.itb.inst_misses 1207 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -363,116 +351,118 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30250783 # ITB inst accesses -system.cpu0.itb.hits 30248608 # DTB hits -system.cpu0.itb.misses 2175 # DTB misses -system.cpu0.itb.accesses 30250783 # DTB accesses -system.cpu0.numCycles 1823674676 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37937219 # ITB inst accesses +system.cpu0.itb.hits 37936012 # DTB hits +system.cpu0.itb.misses 1207 # DTB misses +system.cpu0.itb.accesses 37937219 # DTB accesses +system.cpu0.numCycles 1801227301 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29759626 # Number of instructions committed -system.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses -system.cpu0.num_func_calls 1242746 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34755088 # number of integer instructions -system.cpu0.num_fp_insts 5449 # number of float instructions -system.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_mem_refs 14629859 # number of memory refs -system.cpu0.num_load_insts 8359235 # Number of load instructions -system.cpu0.num_store_insts 6270624 # Number of store instructions -system.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles -system.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles -system.cpu0.Branches 5492144 # Number of branches fetched -system.cpu0.op_class::No_OpClass 16326 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 24520115 62.53% 62.57% # Class of executed instruction -system.cpu0.op_class::IntMult 45259 0.12% 62.69% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1421 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::MemRead 8359235 21.32% 84.01% # Class of executed instruction -system.cpu0.op_class::MemWrite 6270624 15.99% 100.00% # Class of executed instruction +system.cpu0.committedInsts 37698803 # Number of instructions committed +system.cpu0.committedOps 44946380 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 39863943 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses +system.cpu0.num_func_calls 1205467 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4697957 # number of instructions that are conditional controls +system.cpu0.num_int_insts 39863943 # number of integer instructions +system.cpu0.num_fp_insts 4171 # number of float instructions +system.cpu0.num_int_register_reads 70363299 # number of times the integer registers were read +system.cpu0.num_int_register_writes 26108579 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 134797325 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 18388517 # number of times the CC registers were written +system.cpu0.num_mem_refs 14597479 # number of memory refs +system.cpu0.num_load_insts 7571296 # Number of load instructions +system.cpu0.num_store_insts 7026183 # Number of store instructions +system.cpu0.num_idle_cycles 1756006001.161348 # Number of idle cycles +system.cpu0.num_busy_cycles 45221299.838652 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025106 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974894 # Percentage of idle cycles +system.cpu0.Branches 6054325 # Number of branches fetched +system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 30338974 67.42% 67.45% # Class of executed instruction +system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::MemRead 7571296 16.82% 84.39% # Class of executed instruction +system.cpu0.op_class::MemWrite 7026183 15.61% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 39212980 # Class of executed instruction +system.cpu0.op_class::total 45002137 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 428546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 42773 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 419775 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.035896 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37516680 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 420287 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 89.264431 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64363581500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.035896 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998117 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998117 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits -system.cpu0.icache.overall_hits::total 29820919 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses -system.cpu0.icache.overall_misses::total 429059 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 38357256 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 38357256 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 37516680 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37516680 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37516680 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37516680 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37516680 # number of overall hits +system.cpu0.icache.overall_hits::total 37516680 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 420288 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 420288 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 420288 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 420288 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 420288 # number of overall misses +system.cpu0.icache.overall_misses::total 420288 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37936968 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37936968 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37936968 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37936968 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37936968 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37936968 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011079 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011079 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011079 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011079 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011079 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011079 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,68 +472,76 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 323608 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits -system.cpu0.dcache.overall_hits::total 12145397 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses -system.cpu0.dcache.overall_misses::total 364517 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses +system.cpu0.dcache.tags.replacements 348431 # number of replacements +system.cpu0.dcache.tags.tagsinuse 471.119339 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12834011 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 348738 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.801298 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.119339 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920155 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.920155 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 53249455 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 53249455 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6868875 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6868875 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5598061 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5598061 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 78744 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 78744 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135195 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 135195 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 136387 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 136387 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12466936 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12466936 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12545680 # number of overall hits +system.cpu0.dcache.overall_hits::total 12545680 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 173318 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 173318 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 159147 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 159147 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50343 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 50343 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9388 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9388 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7646 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7646 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 332465 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 332465 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 382808 # number of overall misses +system.cpu0.dcache.overall_misses::total 382808 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042193 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7042193 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757208 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5757208 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144583 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 144583 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144033 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144033 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12799401 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12799401 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12928488 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12928488 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.024611 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.024611 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027643 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.027643 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389993 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.389993 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064932 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064932 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053085 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053085 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025975 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025975 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029610 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029610 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -552,8 +550,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks -system.cpu0.dcache.writebacks::total 300957 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 321785 # number of writebacks +system.cpu0.dcache.writebacks::total 321785 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -578,25 +576,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7365100 # DTB read hits -system.cpu1.dtb.read_misses 3705 # DTB read misses -system.cpu1.dtb.write_hits 5489754 # DTB write hits -system.cpu1.dtb.write_misses 1595 # DTB write misses +system.cpu1.dtb.read_hits 6028686 # DTB read hits +system.cpu1.dtb.read_misses 5403 # DTB read misses +system.cpu1.dtb.write_hits 4781604 # DTB write hits +system.cpu1.dtb.write_misses 1104 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7368805 # DTB read accesses -system.cpu1.dtb.write_accesses 5491349 # DTB write accesses +system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6034089 # DTB read accesses +system.cpu1.dtb.write_accesses 4782708 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12854854 # DTB hits -system.cpu1.dtb.misses 5300 # DTB misses -system.cpu1.dtb.accesses 12860154 # DTB accesses +system.cpu1.dtb.hits 10810290 # DTB hits +system.cpu1.dtb.misses 6507 # DTB misses +system.cpu1.dtb.accesses 10816797 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -618,8 +616,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 32413691 # ITB inst hits -system.cpu1.itb.inst_misses 2200 # ITB inst misses +system.cpu1.itb.inst_hits 24626141 # ITB inst hits +system.cpu1.itb.inst_misses 3166 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -628,118 +626,120 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses -system.cpu1.itb.hits 32413691 # DTB hits -system.cpu1.itb.misses 2200 # DTB misses -system.cpu1.itb.accesses 32415891 # DTB accesses -system.cpu1.numCycles 1824196797 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 24629307 # ITB inst accesses +system.cpu1.itb.hits 24626141 # DTB hits +system.cpu1.itb.misses 3166 # DTB misses +system.cpu1.itb.accesses 24629307 # DTB accesses +system.cpu1.numCycles 1801709576 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31877311 # Number of instructions committed -system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses -system.cpu1.num_func_calls 955425 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35862250 # number of integer instructions -system.cpu1.num_fp_insts 4436 # number of float instructions -system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written -system.cpu1.num_mem_refs 13371151 # number of memory refs -system.cpu1.num_load_insts 7642991 # Number of load instructions -system.cpu1.num_store_insts 5728160 # Number of store instructions -system.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles -system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles -system.cpu1.Branches 5037975 # Number of branches fetched -system.cpu1.op_class::No_OpClass 12508 0.03% 0.03% # Class of executed instruction -system.cpu1.op_class::IntAlu 26844895 66.65% 66.68% # Class of executed instruction -system.cpu1.op_class::IntMult 49628 0.12% 66.80% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 737 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::MemRead 7642991 18.98% 85.78% # Class of executed instruction -system.cpu1.op_class::MemWrite 5728160 14.22% 100.00% # Class of executed instruction +system.cpu1.committedInsts 23838609 # Number of instructions committed +system.cpu1.committedOps 29191016 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 25547086 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5650 # Number of float alu accesses +system.cpu1.num_func_calls 987842 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2987341 # number of instructions that are conditional controls +system.cpu1.num_int_insts 25547086 # number of integer instructions +system.cpu1.num_fp_insts 5650 # number of float instructions +system.cpu1.num_int_register_reads 48277330 # number of times the integer registers were read +system.cpu1.num_int_register_writes 17495174 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3706 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 86963152 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 11050350 # number of times the CC registers were written +system.cpu1.num_mem_refs 11165955 # number of memory refs +system.cpu1.num_load_insts 6206289 # Number of load instructions +system.cpu1.num_store_insts 4959666 # Number of store instructions +system.cpu1.num_idle_cycles 1771680344.893366 # Number of idle cycles +system.cpu1.num_busy_cycles 30029231.106634 # Number of busy cycles +system.cpu1.not_idle_fraction 0.016667 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.983333 # Percentage of idle cycles +system.cpu1.Branches 4459555 # Number of branches fetched +system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 18046643 61.66% 61.71% # Class of executed instruction +system.cpu1.op_class::IntMult 40424 0.14% 61.85% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1539 0.01% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::MemRead 6206289 21.20% 83.06% # Class of executed instruction +system.cpu1.op_class::MemWrite 4959666 16.94% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 40278919 # Class of executed instruction +system.cpu1.op_class::total 29270113 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 433942 # number of replacements -system.cpu1.icache.tags.tagsinuse 475.447061 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 69969391500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447061 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928608 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.928608 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 48301 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 442993 # number of replacements +system.cpu1.icache.tags.tagsinuse 472.644505 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 24184321 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 443505 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 54.529985 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 254679414000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.644505 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.923134 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.923134 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 257 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits -system.cpu1.icache.overall_hits::total 31980510 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses -system.cpu1.icache.overall_misses::total 434454 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 25071331 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 25071331 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 24184321 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 24184321 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 24184321 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 24184321 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 24184321 # number of overall hits +system.cpu1.icache.overall_hits::total 24184321 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 443505 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 443505 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 443505 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 443505 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 443505 # number of overall misses +system.cpu1.icache.overall_misses::total 443505 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 24627826 # number of ReadReq accesses(hits+misses) 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accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -749,71 +749,79 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 294289 # number of replacements -system.cpu1.dcache.tags.tagsinuse 447.572964 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11708149 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.715432 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67295121500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.572964 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874166 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.874166 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 274056 # number of replacements +system.cpu1.dcache.tags.tagsinuse 468.122166 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 9407683 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 274568 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 34.263581 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 94419429000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.122166 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914301 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.914301 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits -system.cpu1.dcache.overall_hits::total 11522767 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses -system.cpu1.dcache.overall_misses::total 324342 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 39106907 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39106907 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4611957 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4611957 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4543395 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4543395 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35603 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 35603 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94939 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 94939 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95657 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 95657 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9155352 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9155352 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9190955 # number of overall hits +system.cpu1.dcache.overall_hits::total 9190955 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 143554 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 143554 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 130048 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 130048 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 27770 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 27770 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10527 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10527 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9468 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9468 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 273602 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 273602 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 301372 # number of overall misses +system.cpu1.dcache.overall_misses::total 301372 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755511 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4755511 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673443 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4673443 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105466 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105466 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 9428954 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 9428954 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 9492327 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 9492327 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.030187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.030187 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027827 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027827 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.438199 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.438199 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099814 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099814 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090064 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090064 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029017 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031749 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.031749 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,8 +830,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks -system.cpu1.dcache.writebacks::total 266849 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 249941 # number of writebacks +system.cpu1.dcache.writebacks::total 249941 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 04261a831..511b86cf1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,18 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332812 # Number of seconds simulated -sim_ticks 2332811899500 # Number of ticks simulated -final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.321351 # Number of seconds simulated +sim_ticks 2321351025500 # Number of ticks simulated +final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 975328 # Simulator instruction rate (inst/s) -host_op_rate 1254205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37662621026 # Simulator tick rate (ticks/s) -host_mem_usage 462792 # Number of bytes of host memory used -host_seconds 61.94 # Real time elapsed on the host -sim_insts 60411489 # Number of instructions simulated -sim_ops 77685090 # Number of ops (including micro ops) simulated +host_inst_rate 818788 # Simulator instruction rate (inst/s) +host_op_rate 985991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31464875718 # Simulator tick rate (ticks/s) +host_mem_usage 430844 # Number of bytes of host memory used +host_seconds 73.78 # Real time elapsed on the host +sim_insts 60406834 # Number of instructions simulated +sim_ops 72742429 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 705416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071832 # Number of bytes read from this memory +system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719688 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17234 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141773 # Number of read requests responded to by this memory +system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -25,46 +63,8 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071768 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703424 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 6719240 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141782 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57866 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811820 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3888770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1292781 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880318 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5181551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942288 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969769 # Throughput (bytes/s) -system.membus.data_through_bus 130566943 # Total data (bytes) +system.membus.throughput 55568847 # Throughput (bytes/s) +system.membus.data_through_bus 128994799 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -72,8 +72,8 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48895283 # Throughput (bytes/s) -system.iobus.data_through_bus 114063499 # Total data (bytes) +system.iobus.throughput 48459111 # Throughput (bytes/s) +system.iobus.data_through_bus 112490607 # Total data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -98,25 +98,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971763 # DTB read hits -system.cpu.dtb.read_misses 7294 # DTB read misses -system.cpu.dtb.write_hits 11217184 # DTB write hits +system.cpu.dtb.read_hits 13142244 # DTB read hits +system.cpu.dtb.read_misses 7297 # DTB read misses +system.cpu.dtb.write_hits 11216207 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3399 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14979057 # DTB read accesses -system.cpu.dtb.write_accesses 11219365 # DTB write accesses +system.cpu.dtb.read_accesses 13149541 # DTB read accesses +system.cpu.dtb.write_accesses 11218388 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188947 # DTB hits -system.cpu.dtb.misses 9475 # DTB misses -system.cpu.dtb.accesses 26198422 # DTB accesses +system.cpu.dtb.hits 24358451 # DTB hits +system.cpu.dtb.misses 9478 # DTB misses +system.cpu.dtb.accesses 24367929 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -138,7 +138,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61434680 # ITB inst hits +system.cpu.itb.inst_hits 61430007 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -155,105 +155,107 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61439151 # ITB inst accesses -system.cpu.itb.hits 61434680 # DTB hits +system.cpu.itb.inst_accesses 61434478 # ITB inst accesses +system.cpu.itb.hits 61430007 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61439151 # DTB accesses -system.cpu.numCycles 4665623800 # number of cpu cycles simulated +system.cpu.itb.accesses 61434478 # DTB accesses +system.cpu.numCycles 4642702052 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60411489 # Number of instructions committed -system.cpu.committedOps 77685090 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69133554 # Number of integer alu accesses +system.cpu.committedInsts 60406834 # Number of instructions committed +system.cpu.committedOps 72742429 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 64191430 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2136078 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7942566 # number of instructions that are conditional controls -system.cpu.num_int_insts 69133554 # number of integer instructions +system.cpu.num_func_calls 2135762 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7544984 # number of instructions that are conditional controls +system.cpu.num_int_insts 64191430 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 355910547 # number of times the integer registers were read -system.cpu.num_int_register_writes 74442273 # number of times the integer registers were written +system.cpu.num_int_register_reads 116427347 # number of times the integer registers were read +system.cpu.num_int_register_writes 42818107 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27362421 # number of memory refs -system.cpu.num_load_insts 15640088 # Number of load instructions -system.cpu.num_store_insts 11722333 # Number of store instructions -system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles -system.cpu.num_busy_cycles 78801726.992856 # Number of busy cycles -system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983110 # Percentage of idle cycles -system.cpu.Branches 10299261 # Number of branches fetched +system.cpu.num_cc_register_reads 217570004 # number of times the CC registers were read +system.cpu.num_cc_register_writes 28977741 # number of times the CC registers were written +system.cpu.num_mem_refs 25221274 # number of memory refs +system.cpu.num_load_insts 13499937 # Number of load instructions +system.cpu.num_store_insts 11721337 # Number of store instructions +system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles +system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles +system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.984091 # Percentage of idle cycles +system.cpu.Branches 10298517 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 50337551 64.69% 64.72% # Class of executed instruction -system.cpu.op_class::IntMult 87780 0.11% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 2117 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::MemRead 15640088 20.10% 84.94% # Class of executed instruction -system.cpu.op_class::MemWrite 11722333 15.06% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction +system.cpu.op_class::IntMult 87771 0.12% 65.39% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 2113 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::MemRead 13499937 18.52% 83.92% # Class of executed instruction +system.cpu.op_class::MemWrite 11721337 16.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 77818387 # Class of executed instruction +system.cpu.op_class::total 72875708 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 850590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60586338 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.678462 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 850515 # number of replacements +system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62288542 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62288542 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60586338 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60586338 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60586338 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60586338 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60586338 # number of overall hits -system.cpu.icache.overall_hits::total 60586338 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses -system.cpu.icache.overall_misses::total 851102 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 61437440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61437440 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61437440 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits +system.cpu.icache.overall_hits::total 60581740 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses +system.cpu.icache.overall_misses::total 851027 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61432767 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013853 # miss rate for demand accesses @@ -269,115 +271,115 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed 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+system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97635323 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97635323 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13180574 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13180574 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9962233 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9962233 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23142807 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23142807 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23142807 # number of overall hits -system.cpu.dcache.overall_hits::total 23142807 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 365463 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 365463 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250154 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 615617 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 615617 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615617 # number of overall misses -system.cpu.dcache.overall_misses::total 615617 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13546037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13546037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10212387 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23758424 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23758424 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23758424 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23758424 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses +system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits +system.cpu.dcache.overall_hits::total 21312398 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses +system.cpu.dcache.overall_misses::total 615595 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 184298 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -457,11 +467,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592648 # number of writebacks -system.cpu.dcache.writebacks::total 592648 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks +system.cpu.dcache.writebacks::total 592642 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 59102995 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 137876171 # Total data (bytes) +system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 8e4b444a3..051c13810 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.195945 # Number of seconds simulated -sim_ticks 1195945260000 # Number of ticks simulated -final_tick 1195945260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194312 # Number of seconds simulated +sim_ticks 1194312178000 # Number of ticks simulated +final_tick 1194312178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 424891 # Simulator instruction rate (inst/s) -host_op_rate 541366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8267957779 # Simulator tick rate (ticks/s) -host_mem_usage 468940 # Number of bytes of host memory used -host_seconds 144.65 # Real time elapsed on the host -sim_insts 61459750 # Number of instructions simulated -sim_ops 78307634 # Number of ops (including micro ops) simulated +host_inst_rate 475403 # Simulator instruction rate (inst/s) +host_op_rate 567868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9241250441 # Simulator tick rate (ticks/s) +host_mem_usage 438040 # Number of bytes of host memory used +host_seconds 129.24 # Real time elapsed on the host +sim_insts 61439698 # Number of instructions simulated +sim_ops 73389630 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4714684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393932 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4710012 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4804472 # Number of bytes read from this memory -system.physmem.bytes_read::total 62142468 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393612 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 718288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4110592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 323460 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4796088 # Number of bytes read from this memory +system.physmem.bytes_read::total 62128516 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393932 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323460 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4097216 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7137936 # Number of bytes written to this memory +system.physmem.bytes_written::total 7124560 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73741 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73653 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75098 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654453 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64228 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5145 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74957 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654210 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64019 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821064 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43400408 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820855 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43459753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 329122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3942224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 329840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3943703 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 271481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4017301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51960963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 329122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 271481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3437107 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14215 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2517125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5968447 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3437107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43400408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 270834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4015774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52020332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 329840 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 270834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 600674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3430607 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2520567 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5965408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3430607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43459753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 329122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3956439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 329840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3957937 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 271481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6534426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57929411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654453 # Number of read requests accepted -system.physmem.writeReqs 821064 # Number of write requests accepted -system.physmem.readBursts 6654453 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821064 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425841472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43520 # Total number of bytes read from write queue -system.physmem.bytesWritten 7149184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62142468 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7137936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 680 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709327 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12098 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415328 # Per bank write bursts -system.physmem.perBankRdBursts::1 415212 # Per bank write bursts -system.physmem.perBankRdBursts::2 415403 # Per bank write bursts -system.physmem.perBankRdBursts::3 415611 # Per bank write bursts -system.physmem.perBankRdBursts::4 422397 # Per bank write bursts -system.physmem.perBankRdBursts::5 415577 # Per bank write bursts -system.physmem.perBankRdBursts::6 415747 # Per bank write bursts -system.physmem.perBankRdBursts::7 415496 # Per bank write bursts -system.physmem.perBankRdBursts::8 416027 # Per bank write bursts -system.physmem.perBankRdBursts::9 415632 # Per bank write bursts -system.physmem.perBankRdBursts::10 415426 # Per bank write bursts -system.physmem.perBankRdBursts::11 414842 # Per bank write bursts -system.physmem.perBankRdBursts::12 414820 # Per bank write bursts -system.physmem.perBankRdBursts::13 415557 # Per bank write bursts -system.physmem.perBankRdBursts::14 415554 # Per bank write bursts -system.physmem.perBankRdBursts::15 415144 # Per bank write bursts -system.physmem.perBankWrBursts::0 6840 # Per bank write bursts -system.physmem.perBankWrBursts::1 6732 # Per bank write bursts -system.physmem.perBankWrBursts::2 6969 # Per bank write bursts -system.physmem.perBankWrBursts::3 7025 # Per bank write bursts -system.physmem.perBankWrBursts::4 7326 # Per bank write bursts -system.physmem.perBankWrBursts::5 7107 # Per bank write bursts -system.physmem.perBankWrBursts::6 7317 # Per bank write bursts -system.physmem.perBankWrBursts::7 7078 # Per bank write bursts -system.physmem.perBankWrBursts::8 7464 # Per bank write bursts -system.physmem.perBankWrBursts::9 7155 # Per bank write bursts -system.physmem.perBankWrBursts::10 7023 # Per bank write bursts -system.physmem.perBankWrBursts::11 6543 # Per bank write bursts -system.physmem.perBankWrBursts::12 6616 # Per bank write bursts -system.physmem.perBankWrBursts::13 6901 # Per bank write bursts -system.physmem.perBankWrBursts::14 6977 # Per bank write bursts -system.physmem.perBankWrBursts::15 6633 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 270834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6536341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57985740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654210 # Number of read requests accepted +system.physmem.writeReqs 820855 # Number of write requests accepted +system.physmem.readBursts 6654210 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 820855 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425838464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7136448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62128516 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7124560 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709321 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12079 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415236 # Per bank write bursts +system.physmem.perBankRdBursts::1 415218 # Per bank write bursts +system.physmem.perBankRdBursts::2 415240 # Per bank write bursts +system.physmem.perBankRdBursts::3 415658 # Per bank write bursts +system.physmem.perBankRdBursts::4 422402 # Per bank write bursts +system.physmem.perBankRdBursts::5 415506 # Per bank write bursts +system.physmem.perBankRdBursts::6 415779 # Per bank write bursts +system.physmem.perBankRdBursts::7 415682 # Per bank write bursts +system.physmem.perBankRdBursts::8 416047 # Per bank write bursts +system.physmem.perBankRdBursts::9 415577 # Per bank write bursts +system.physmem.perBankRdBursts::10 415398 # Per bank write bursts +system.physmem.perBankRdBursts::11 414862 # Per bank write bursts +system.physmem.perBankRdBursts::12 415007 # Per bank write bursts +system.physmem.perBankRdBursts::13 415552 # Per bank write bursts +system.physmem.perBankRdBursts::14 415496 # Per bank write bursts +system.physmem.perBankRdBursts::15 415066 # Per bank write bursts +system.physmem.perBankWrBursts::0 6763 # Per bank write bursts +system.physmem.perBankWrBursts::1 6728 # Per bank write bursts +system.physmem.perBankWrBursts::2 6819 # Per bank write bursts +system.physmem.perBankWrBursts::3 7055 # Per bank write bursts +system.physmem.perBankWrBursts::4 7301 # Per bank write bursts +system.physmem.perBankWrBursts::5 7028 # Per bank write bursts +system.physmem.perBankWrBursts::6 7316 # Per bank write bursts +system.physmem.perBankWrBursts::7 7231 # Per bank write bursts +system.physmem.perBankWrBursts::8 7485 # Per bank write bursts +system.physmem.perBankWrBursts::9 7107 # Per bank write bursts +system.physmem.perBankWrBursts::10 7000 # Per bank write bursts +system.physmem.perBankWrBursts::11 6549 # Per bank write bursts +system.physmem.perBankWrBursts::12 6696 # Per bank write bursts +system.physmem.perBankWrBursts::13 6902 # Per bank write bursts +system.physmem.perBankWrBursts::14 6960 # Per bank write bursts +system.physmem.perBankWrBursts::15 6567 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1195940759000 # Total gap between requests +system.physmem.totGap 1194307723500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6849 # Read request sizes (log2) -system.physmem.readPktSize::3 6488064 # Read request sizes (log2) +system.physmem.readPktSize::2 6799 # Read request sizes (log2) +system.physmem.readPktSize::3 6488089 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159540 # Read request sizes (log2) +system.physmem.readPktSize::6 159322 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64228 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 572493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 410656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 412880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 461685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 417933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 446395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1149366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1113988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1438120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 64577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 50343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 45843 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 44044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64019 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 572550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 410650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 412558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 460055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 417389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 445707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1151151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1116358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1442650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 62467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 48974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 43130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -180,24 +180,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3903 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 6452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6480 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6484 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6481 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -229,66 +229,67 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 473596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 914.261641 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 784.047795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 289.306705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25239 5.33% 5.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21585 4.56% 9.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5945 1.26% 11.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2453 0.52% 11.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2290 0.48% 12.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1636 0.35% 12.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4075 0.86% 13.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 899 0.19% 13.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 409474 86.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 473596 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1026.497532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 34346.134147 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-131071 6476 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-262143 3 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-655359 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-917503 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.49037e+06-2.62144e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6482 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6482 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.233261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.205432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.970583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2453 37.84% 37.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 80 1.23% 39.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3936 60.72% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 11 0.17% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6482 # Writes before turning the bus around for reads -system.physmem.totQLat 171035006500 # Total ticks spent queuing -system.physmem.totMemAccLat 295793250250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33268865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25704.97 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 473292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 914.815615 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 785.169464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 288.643252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25022 5.29% 5.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21566 4.56% 9.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5869 1.24% 11.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2391 0.51% 11.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2344 0.50% 12.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1629 0.34% 12.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4093 0.86% 13.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 899 0.19% 13.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 409479 86.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 473292 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6481 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1026.648974 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 26505.494009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6473 99.88% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6481 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.205215 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.176618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.984217 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2581 39.82% 39.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.23% 40.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3862 59.59% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 20 0.31% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6481 # Writes before turning the bus around for reads +system.physmem.totQLat 170730095750 # Total ticks spent queuing +system.physmem.totMemAccLat 295487458250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33268630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25659.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44454.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44409.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 52.02 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage -system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 2.79 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 4.89 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.45 # Average write queue length when enqueuing -system.physmem.readRowHits 6199461 # Number of row buffer hits during reads -system.physmem.writeRowHits 92422 # Number of row buffer hits during writes +system.physmem.avgRdQLen 4.36 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing +system.physmem.readRowHits 6199598 # Number of row buffer hits during reads +system.physmem.writeRowHits 92343 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.71 # Row buffer hit rate for writes -system.physmem.avgGap 159981.01 # Average gap between requests +system.physmem.writeRowHitRate 82.79 # Row buffer hit rate for writes +system.physmem.avgGap 159772.22 # Average gap between requests system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 947634468500 # Time in different power states -system.physmem.memoryStateTime::REF 39935220000 # Time in different power states +system.physmem.memoryStateTime::IDLE 945808643750 # Time in different power states +system.physmem.memoryStateTime::REF 39880620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 208375212750 # Time in different power states +system.physmem.memoryStateTime::ACT 208620525000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -308,314 +309,314 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 59946686 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703403 # Transaction distribution -system.membus.trans_dist::ReadResp 7703403 # Transaction distribution -system.membus.trans_dist::WriteReq 767582 # Transaction distribution -system.membus.trans_dist::WriteResp 767582 # Transaction distribution -system.membus.trans_dist::Writeback 64228 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31700 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17261 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12098 # Transaction distribution -system.membus.trans_dist::ReadExReq 137709 # Transaction distribution -system.membus.trans_dist::ReadExResp 137266 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382666 # Packet count per connected master and slave (bytes) +system.membus.throughput 60005732 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703348 # Transaction distribution +system.membus.trans_dist::ReadResp 7703348 # Transaction distribution +system.membus.trans_dist::WriteReq 767581 # Transaction distribution +system.membus.trans_dist::WriteResp 767581 # Transaction distribution +system.membus.trans_dist::Writeback 64019 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31325 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17234 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12079 # Transaction distribution +system.membus.trans_dist::ReadExReq 137481 # Transaction distribution +system.membus.trans_dist::ReadExResp 137066 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10312 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972180 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4364934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17342232 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390035 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17341062 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389989 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375892 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19788443 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17348564 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19761065 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71692955 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71692955 # Total data (bytes) +system.membus.tot_pkt_size::total 71665577 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71665577 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224801000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224785500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9242500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9231500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 784500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 778500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211274000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9212282000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5078680829 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5079172023 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 16046108250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 16050388750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69421 # number of replacements -system.l2c.tags.tagsinuse 53012.823108 # Cycle average of tags in use -system.l2c.tags.total_refs 1672128 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134609 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.422111 # Average number of references to valid blocks. +system.l2c.tags.replacements 69203 # number of replacements +system.l2c.tags.tagsinuse 52959.316379 # Cycle average of tags in use +system.l2c.tags.total_refs 1672724 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134375 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.448179 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40185.217534 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40136.915421 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3710.755623 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4242.358437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2808.724549 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2063.021033 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.613178 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 3716.167205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4233.542603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.741623 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001622 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2809.362324 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2060.583626 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.612441 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056622 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064733 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056704 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064599 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042858 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031479 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808911 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031442 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808095 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8039 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55163 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8176 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55031 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17207703 # Number of tag accesses -system.l2c.tags.data_accesses 17207703 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419090 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205762 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5504 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1909 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464812 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143326 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1245952 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 570869 # number of Writeback hits -system.l2c.Writeback_hits::total 570869 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 561 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1736 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 218 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 106 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 324 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56320 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52713 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109033 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3810 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419090 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262082 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5504 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1909 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464812 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196039 # number of demand (read+write) hits -system.l2c.demand_hits::total 1354985 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3810 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1739 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419090 # number of overall hits -system.l2c.overall_hits::cpu0.data 262082 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5504 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1909 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464812 # number of overall hits -system.l2c.overall_hits::cpu1.data 196039 # number of overall hits -system.l2c.overall_hits::total 1354985 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17204185 # Number of tag accesses +system.l2c.tags.data_accesses 17204185 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 3944 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1786 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419390 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 205855 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1846 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464270 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143434 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1245858 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 570720 # number of Writeback hits +system.l2c.Writeback_hits::total 570720 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1291 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1814 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits 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hits +system.l2c.overall_hits::cpu0.itb.walker 1786 # number of overall hits +system.l2c.overall_hits::cpu0.inst 419390 # number of overall hits +system.l2c.overall_hits::cpu0.data 262194 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5333 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1846 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464270 # number of overall hits +system.l2c.overall_hits::cpu1.data 196151 # number of overall hits +system.l2c.overall_hits::total 1354914 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5736 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7851 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5741 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7844 # number of ReadReq misses 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139713 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 5048 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3616 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22257 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4858 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3744 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8602 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 472 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1039 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 67076 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72428 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139504 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5736 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74978 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5741 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74920 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5067 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76199 # number of demand (read+write) misses -system.l2c.demand_misses::total 161988 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5048 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 76044 # number of demand (read+write) misses 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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 350592250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12457114749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5367250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154289145498 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167102219747 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1046762999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15721978412 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16768741411 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 350592250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13503877748 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5367250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170011123910 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183870961158 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000253 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001119 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013502 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036706 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000749 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000541 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010756 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024590 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017550 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.790047 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.877431 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.825845 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.725992 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.829525 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769630 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543500 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578753 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.561249 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000253 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001119 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013502 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222239 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000749 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010756 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.279373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106654 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000253 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001119 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013502 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222239 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000749 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010756 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.279373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106654 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57887.227550 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61256.750605 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61536.078404 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58768.354056 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64062.621091 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60278.328949 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.058990 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.803445 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10010.350023 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.651327 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.225941 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10004.831256 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54106.359006 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59659.237029 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56991.281699 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64144.911504 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60422.020983 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.865377 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.762019 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.913857 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.109347 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.472458 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.548604 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53749.881836 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59393.523292 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56679.960281 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57887.227550 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54855.081624 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58768.354056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59868.024895 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57443.266676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57887.227550 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54855.081624 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58768.354056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59868.024895 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57443.266676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -809,64 +810,64 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119513329 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535217 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535217 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767582 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767582 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 570869 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30989 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17585 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48574 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260651 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863496 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226215 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12691 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940498 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15421 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7672224 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27215456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41348685 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30072692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39622266 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138310979 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138310979 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4620420 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4758868690 # Layer occupancy (ticks) +system.toL2Bus.throughput 119643708 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2534658 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2534658 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767581 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767581 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 570720 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30701 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17545 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48246 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260694 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260694 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226294 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6184 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12819 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6173 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15243 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7670949 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27234976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41362613 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15780 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30036788 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39599456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7388 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21348 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138285501 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138285501 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4606436 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4757764712 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1923485226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1924888432 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1752589322 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1752701680 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396499 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8880000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8876994 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2117887474 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2115350205 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2927028338 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2925844707 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9913999 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 9906999 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45398856 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671434 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671434 # Transaction distribution -system.iobus.trans_dist::WriteReq 7963 # Transaction distribution -system.iobus.trans_dist::WriteResp 7963 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45460895 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671423 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671423 # Transaction distribution +system.iobus.trans_dist::WriteReq 7962 # Transaction distribution +system.iobus.trans_dist::WriteResp 7962 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8040 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) @@ -886,14 +887,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382666 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382642 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358794 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358770 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40317 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16080 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) @@ -913,18 +914,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390035 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389989 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294547 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294547 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294501 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294501 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21416000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4026000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -966,9 +967,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374703000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374680000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16368811750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16364250250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -993,25 +994,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7064335 # DTB read hits -system.cpu0.dtb.read_misses 3758 # DTB read misses -system.cpu0.dtb.write_hits 5649339 # DTB write hits -system.cpu0.dtb.write_misses 802 # DTB write misses +system.cpu0.dtb.read_hits 6063582 # DTB read hits +system.cpu0.dtb.read_misses 3748 # DTB read misses +system.cpu0.dtb.write_hits 5648980 # DTB write hits +system.cpu0.dtb.write_misses 807 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7068093 # DTB read accesses -system.cpu0.dtb.write_accesses 5650141 # DTB write accesses +system.cpu0.dtb.read_accesses 6067330 # DTB read accesses +system.cpu0.dtb.write_accesses 5649787 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12713674 # DTB hits -system.cpu0.dtb.misses 4560 # DTB misses -system.cpu0.dtb.accesses 12718234 # DTB accesses +system.cpu0.dtb.hits 11712562 # DTB hits +system.cpu0.dtb.misses 4555 # DTB misses +system.cpu0.dtb.accesses 11717117 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1033,7 +1034,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29562995 # ITB inst hits +system.cpu0.itb.inst_hits 29557926 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1050,123 +1051,125 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29565200 # ITB inst accesses -system.cpu0.itb.hits 29562995 # DTB hits +system.cpu0.itb.inst_accesses 29560131 # ITB inst accesses +system.cpu0.itb.hits 29557926 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29565200 # DTB accesses -system.cpu0.numCycles 2391890520 # number of cpu cycles simulated +system.cpu0.itb.accesses 29560131 # DTB accesses +system.cpu0.numCycles 2388624356 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28864889 # Number of instructions committed -system.cpu0.committedOps 37190899 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33115613 # Number of integer alu accesses +system.cpu0.committedInsts 28859743 # Number of instructions committed +system.cpu0.committedOps 34624628 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30439288 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241798 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4372441 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33115613 # number of integer instructions +system.cpu0.num_func_calls 1241573 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4174263 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30439288 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 192173380 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36248506 # number of times the integer registers were written +system.cpu0.num_int_register_reads 53589242 # number of times the integer registers were read +system.cpu0.num_int_register_writes 19764786 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13380838 # number of memory refs -system.cpu0.num_load_insts 7401595 # Number of load instructions -system.cpu0.num_store_insts 5979243 # Number of store instructions -system.cpu0.num_idle_cycles 2246179687.500122 # Number of idle cycles -system.cpu0.num_busy_cycles 145710832.499878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060919 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939081 # Percentage of idle cycles -system.cpu0.Branches 5600259 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14567 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 24478507 64.56% 64.59% # Class of executed instruction -system.cpu0.op_class::IntMult 43773 0.12% 64.71% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 694 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::MemRead 7401595 19.52% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 5979243 15.77% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 123695766 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 15045730 # number of times the CC registers were written +system.cpu0.num_mem_refs 12225186 # number of memory refs +system.cpu0.num_load_insts 6245915 # Number of load instructions +system.cpu0.num_store_insts 5979271 # Number of store instructions +system.cpu0.num_idle_cycles 2246427873.598119 # Number of idle cycles +system.cpu0.num_busy_cycles 142196482.401881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles +system.cpu0.Branches 5599312 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14563 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 22957352 65.14% 65.18% # Class of executed instruction +system.cpu0.op_class::IntMult 43755 0.12% 65.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 692 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::MemRead 6245915 17.72% 83.03% # Class of executed instruction +system.cpu0.op_class::MemWrite 5979271 16.97% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 37918379 # Class of executed instruction +system.cpu0.op_class::total 35241548 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46956 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 424861 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.353809 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29137604 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425373 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.498950 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76246574000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.353809 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994832 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994832 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 47055 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 425168 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.375466 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29132228 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425680 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.436920 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 75988011000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.375466 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994874 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994874 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29988352 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29988352 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29137604 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29137604 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29137604 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29137604 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29137604 # number of overall hits -system.cpu0.icache.overall_hits::total 29137604 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425374 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425374 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425374 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425374 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425374 # number of overall misses -system.cpu0.icache.overall_misses::total 425374 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5893447476 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5893447476 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5893447476 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5893447476 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5893447476 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5893447476 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29562978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29562978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29562978 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29562978 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29562978 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29562978 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014389 # miss rate for ReadReq accesses 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13859.595993 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13859.595993 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13859.595993 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1175,128 +1178,136 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed 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hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227548 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227548 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141421 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141421 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9358 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9358 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7517 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7517 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 368969 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 368969 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 368969 # number of overall misses -system.cpu0.dcache.overall_misses::total 368969 # number of overall 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0.047841 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047841 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029978 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029978 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029978 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029978 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.096577 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.096577 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39956.000247 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39956.000247 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9918.171618 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9918.171618 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5921.519888 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5921.519888 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24250.844941 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24250.844941 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24250.844941 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24250.844941 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 46848154 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 46848154 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5514035 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5514035 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5340154 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5340154 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 64966 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 64966 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148024 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 148024 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149636 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149636 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10854189 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10854189 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10919155 # number of overall hits +system.cpu0.dcache.overall_hits::total 10919155 # number of overall hits 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misses +system.cpu0.dcache.overall_misses::cpu0.data 387440 # number of overall misses +system.cpu0.dcache.overall_misses::total 387440 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2350643732 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 2350643732 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5817567140 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5817567140 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94706749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 94706749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44450567 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44450567 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8168210872 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8168210872 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8168210872 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8168210872 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5693224 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5693224 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5485576 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5485576 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 127795 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 127795 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157463 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157463 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157121 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157121 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11178800 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11178800 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11306595 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11306595 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031474 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031474 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026510 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026510 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.491639 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.491639 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059944 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059944 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047638 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047638 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029038 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029038 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034267 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.034267 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13118.236789 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13118.236789 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40004.725145 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40004.725145 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.557474 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.557474 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5938.619506 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5938.619506 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25163.074794 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25163.074794 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21082.518253 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21082.518253 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1305,62 +1316,78 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305583 # number of writebacks -system.cpu0.dcache.writebacks::total 305583 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227548 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227548 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141421 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141421 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9358 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9358 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7515 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7515 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 368969 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 368969 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 368969 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 368969 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2840145504 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2840145504 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338354489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338354489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 74046750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74046750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29480935 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29480935 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8178499993 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8178499993 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8178499993 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8178499993 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13564071000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13564071000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170919500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170919500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14734990500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14734990500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033356 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033356 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025779 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025779 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059469 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059469 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047828 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047828 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029978 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029978 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029978 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029978 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12481.522597 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12481.522597 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37747.961682 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37747.961682 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.668305 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.668305 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3922.945442 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3922.945442 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22165.818790 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22165.818790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22165.818790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22165.818790 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 305747 # number of writebacks +system.cpu0.dcache.writebacks::total 305747 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR 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1988652518 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1988652518 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5320324110 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5320324110 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 853626758 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 853626758 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 75777251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 75777251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29483433 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29483433 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7308976628 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7308976628 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8162603386 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8162603386 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13564535750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13564535750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170801000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170801000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14735336750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14735336750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031426 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031426 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.379577 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.379577 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059944 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059944 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047626 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047626 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028652 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028652 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032618 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032618 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11115.192960 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11115.192960 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37631.377210 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37631.377210 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17597.649006 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17597.649006 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8028.101600 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8028.101600 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3940.055192 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3940.055192 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22819.657713 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22819.657713 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22132.812509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22132.812509 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1391,25 +1418,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8317790 # DTB read hits -system.cpu1.dtb.read_misses 3645 # DTB read misses -system.cpu1.dtb.write_hits 5833574 # DTB write hits -system.cpu1.dtb.write_misses 1433 # DTB write misses +system.cpu1.dtb.read_hits 7408792 # DTB read hits +system.cpu1.dtb.read_misses 3640 # DTB read misses +system.cpu1.dtb.write_hits 5825509 # DTB write hits +system.cpu1.dtb.write_misses 1435 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1866 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8321435 # DTB read accesses -system.cpu1.dtb.write_accesses 5835007 # DTB write accesses +system.cpu1.dtb.read_accesses 7412432 # DTB read accesses +system.cpu1.dtb.write_accesses 5826944 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14151364 # DTB hits -system.cpu1.dtb.misses 5078 # DTB misses -system.cpu1.dtb.accesses 14156442 # DTB accesses +system.cpu1.dtb.hits 13234301 # DTB hits +system.cpu1.dtb.misses 5075 # DTB misses +system.cpu1.dtb.accesses 13239376 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1431,7 +1458,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33205963 # ITB inst hits +system.cpu1.itb.inst_hits 33190882 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1448,122 +1475,123 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33208134 # ITB inst accesses -system.cpu1.itb.hits 33205963 # DTB hits +system.cpu1.itb.inst_accesses 33193053 # ITB inst accesses +system.cpu1.itb.hits 33190882 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33208134 # DTB accesses -system.cpu1.numCycles 2390414629 # number of cpu cycles simulated +system.cpu1.itb.accesses 33193053 # DTB accesses +system.cpu1.numCycles 2387219429 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32594861 # Number of instructions committed -system.cpu1.committedOps 41116735 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37639270 # Number of integer alu accesses +system.cpu1.committedInsts 32579955 # Number of instructions committed +system.cpu1.committedOps 38765002 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35167643 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962738 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3734786 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37639270 # number of integer instructions +system.cpu1.num_func_calls 962341 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3529676 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35167643 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 218315433 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39777331 # number of times the integer registers were written +system.cpu1.num_int_register_reads 64976079 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23977665 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14690124 # number of memory refs -system.cpu1.num_load_insts 8639728 # Number of load instructions -system.cpu1.num_store_insts 6050396 # Number of store instructions -system.cpu1.num_idle_cycles 1874297798.309079 # Number of idle cycles -system.cpu1.num_busy_cycles 516116830.690921 # Number of busy cycles -system.cpu1.not_idle_fraction 0.215911 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.784089 # Percentage of idle cycles -system.cpu1.Branches 4947313 # Number of branches fetched -system.cpu1.op_class::No_OpClass 14267 0.03% 0.03% # Class of executed instruction -system.cpu1.op_class::IntAlu 26968126 64.63% 64.67% # Class of executed instruction -system.cpu1.op_class::IntMult 50231 0.12% 64.79% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1470 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::MemRead 8639728 20.71% 85.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 6050396 14.50% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 139669414 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 14465628 # number of times the CC registers were written +system.cpu1.num_mem_refs 13620676 # number of memory refs +system.cpu1.num_load_insts 7578910 # Number of load instructions +system.cpu1.num_store_insts 6041766 # Number of store instructions +system.cpu1.num_idle_cycles 1873842319.884373 # Number of idle cycles +system.cpu1.num_busy_cycles 513377109.115627 # Number of busy cycles +system.cpu1.not_idle_fraction 0.215052 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.784948 # Percentage of idle cycles +system.cpu1.Branches 4944984 # Number of branches fetched +system.cpu1.op_class::No_OpClass 14265 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 25564023 65.13% 65.17% # Class of executed instruction +system.cpu1.op_class::IntMult 50133 0.13% 65.29% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1482 0.00% 65.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.30% # Class of executed instruction +system.cpu1.op_class::MemRead 7578910 19.31% 84.61% # Class of executed instruction +system.cpu1.op_class::MemWrite 6041766 15.39% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 41724218 # Class of executed instruction +system.cpu1.op_class::total 39250579 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 44363 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469889 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.549875 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32735558 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470401 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.590749 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93998064500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.549875 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934668 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934668 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 44258 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 469324 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.642267 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32721042 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 469836 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.643539 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 93149552500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.642267 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934848 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934848 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 456 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33676360 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33676360 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32735558 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32735558 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32735558 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32735558 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32735558 # number of overall hits -system.cpu1.icache.overall_hits::total 32735558 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470401 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470401 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470401 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470401 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470401 # number of overall misses -system.cpu1.icache.overall_misses::total 470401 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443025224 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6443025224 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6443025224 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6443025224 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6443025224 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6443025224 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33205959 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33205959 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33205959 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33205959 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33205959 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33205959 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13696.878246 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13696.878246 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13696.878246 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13696.878246 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13696.878246 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13696.878246 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33660714 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33660714 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32721042 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32721042 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32721042 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32721042 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32721042 # number of overall hits +system.cpu1.icache.overall_hits::total 32721042 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469836 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469836 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469836 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 469836 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 469836 # number of overall misses +system.cpu1.icache.overall_misses::total 469836 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6435695955 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6435695955 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6435695955 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6435695955 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6435695955 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6435695955 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33190878 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33190878 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33190878 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33190878 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33190878 # number of overall (read+write) accesses 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overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13697.749757 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1572,190 +1600,214 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470401 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 470401 # number of ReadReq MSHR misses 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26734.599949 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26734.599949 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26734.599949 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 292234 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.923930 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11040887 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 292603 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.733335 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 84705826250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.923930 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921726 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.921726 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 45818347 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 45818347 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 6006097 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6006097 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4823101 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4823101 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 22483 # number 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ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1718496498 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6437170330 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6437170330 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 96291249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 96291249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52005971 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 52005971 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8155666828 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8155666828 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8155666828 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8155666828 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6150150 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6150150 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4975183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 64358 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 64358 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 93158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92771 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92771 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 11125333 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11125333 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11189691 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11189691 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023423 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023423 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030568 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030568 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.650657 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.650657 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108482 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108482 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026618 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026618 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030207 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030207 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11929.612698 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11929.612698 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42326.970516 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 42326.970516 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8580.578239 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8580.578239 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5167.524940 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5167.524940 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27540.367832 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27540.367832 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24128.477939 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24128.477939 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265286 # number of writebacks -system.cpu1.dcache.writebacks::total 265286 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170655 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170655 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150219 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150219 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11301 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11301 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320874 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320874 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320874 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320874 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1870737503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1870737503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6042583473 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6042583473 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74594250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74594250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32041523 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32041523 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7913320976 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7913320976 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7913320976 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7913320976 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608523750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608523750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187494163 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187494163 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193796017913 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193796017913 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023957 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023957 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121109 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121109 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108473 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108473 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026504 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026504 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026504 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026504 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10962.101919 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10962.101919 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40225.161085 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40225.161085 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6600.676931 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6600.676931 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3181.879146 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3181.879146 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24661.770589 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24661.770589 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24661.770589 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24661.770589 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 264973 # number of writebacks +system.cpu1.dcache.writebacks::total 264973 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 2067 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 2067 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 2446 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 2446 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 2446 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 2446 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143674 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 143674 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150015 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150015 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 26855 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 26855 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11222 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11222 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 293689 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 293689 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320544 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320544 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1427169251 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1427169251 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6022199670 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6022199670 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 445093004 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 445093004 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73834751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73834751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31881029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31881029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7449368921 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7449368921 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7894461925 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7894461925 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187299088 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187299088 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030153 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030153 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.417275 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.417275 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120462 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120462 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108461 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108461 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026398 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026398 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.028646 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9933.385658 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9933.385658 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6579.464534 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6579.464534 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3168.458458 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3168.458458 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1779,10 +1831,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745373562750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 745373562750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745373562750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 745373562750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 745112259250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 41f066b07..563f1978d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,146 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616230 # Number of seconds simulated -sim_ticks 2616229847000 # Number of ticks simulated -final_tick 2616229847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.614581 # Number of seconds simulated +sim_ticks 2614581252500 # Number of ticks simulated +final_tick 2614581252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 375445 # Simulator instruction rate (inst/s) -host_op_rate 477768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16316419265 # Simulator tick rate (ticks/s) -host_mem_usage 464828 # Number of bytes of host memory used -host_seconds 160.34 # Real time elapsed on the host -sim_insts 60200042 # Number of instructions simulated -sim_ops 76606857 # Number of ops (including micro ops) simulated +host_inst_rate 331710 # Simulator instruction rate (inst/s) +host_op_rate 396174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14409825510 # Simulator tick rate (ticks/s) +host_mem_usage 433940 # Number of bytes of host memory used +host_seconds 181.44 # Real time elapsed on the host +sim_insts 60186875 # Number of instructions simulated +sim_ops 71883476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 703560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089944 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 703560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 703560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9109080 # Number of bytes read from this memory +system.physmem.bytes_read::total 132497440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3720512 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory +system.physmem.bytes_written::total 6736584 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142066 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142355 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15495006 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58133 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46893201 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 812151 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46922769 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3474444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50636737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268921 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268921 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1416658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1152831 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2569490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1416658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46893201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3483954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50676352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1422986 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2576544 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1422986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46922769 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4627275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53206227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494702 # Number of read requests accepted -system.physmem.writeReqs 811929 # Number of write requests accepted -system.physmem.readBursts 15494702 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991533248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 127680 # Total number of bytes read from write queue -system.physmem.bytesWritten 6729728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1995 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706751 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 967982 # Per bank write bursts -system.physmem.perBankRdBursts::1 967715 # Per bank write bursts -system.physmem.perBankRdBursts::2 967669 # Per bank write bursts -system.physmem.perBankRdBursts::3 967754 # Per bank write bursts -system.physmem.perBankRdBursts::4 974564 # Per bank write bursts -system.physmem.perBankRdBursts::5 968184 # Per bank write bursts -system.physmem.perBankRdBursts::6 967779 # Per bank write bursts -system.physmem.perBankRdBursts::7 967692 # Per bank write bursts -system.physmem.perBankRdBursts::8 968544 # Per bank write bursts -system.physmem.perBankRdBursts::9 968137 # Per bank write bursts -system.physmem.perBankRdBursts::10 967949 # Per bank write bursts -system.physmem.perBankRdBursts::11 967746 # Per bank write bursts -system.physmem.perBankRdBursts::12 967851 # Per bank write bursts -system.physmem.perBankRdBursts::13 967741 # Per bank write bursts -system.physmem.perBankRdBursts::14 967800 # Per bank write bursts -system.physmem.perBankRdBursts::15 967600 # Per bank write bursts -system.physmem.perBankWrBursts::0 6503 # Per bank write bursts -system.physmem.perBankWrBursts::1 6305 # Per bank write bursts -system.physmem.perBankWrBursts::2 6309 # Per bank write bursts -system.physmem.perBankWrBursts::3 6231 # Per bank write bursts -system.physmem.perBankWrBursts::4 6800 # Per bank write bursts -system.physmem.perBankWrBursts::5 6982 # Per bank write bursts -system.physmem.perBankWrBursts::6 6786 # Per bank write bursts -system.physmem.perBankWrBursts::7 6777 # Per bank write bursts -system.physmem.perBankWrBursts::8 7080 # Per bank write bursts -system.physmem.perBankWrBursts::9 6733 # Per bank write bursts -system.physmem.perBankWrBursts::10 6548 # Per bank write bursts -system.physmem.perBankWrBursts::11 6441 # Per bank write bursts -system.physmem.perBankWrBursts::12 6486 # Per bank write bursts -system.physmem.perBankWrBursts::13 6281 # Per bank write bursts -system.physmem.perBankWrBursts::14 6425 # Per bank write bursts -system.physmem.perBankWrBursts::15 6465 # Per bank write bursts +system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4637512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53252896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15495006 # Number of read requests accepted +system.physmem.writeReqs 812151 # Number of write requests accepted +system.physmem.readBursts 15495006 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812151 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991553920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 126464 # Total number of bytes read from write queue +system.physmem.bytesWritten 6744512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132497440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6736584 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1976 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706747 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 968147 # Per bank write bursts +system.physmem.perBankRdBursts::1 967810 # Per bank write bursts +system.physmem.perBankRdBursts::2 967673 # Per bank write bursts +system.physmem.perBankRdBursts::3 967915 # Per bank write bursts +system.physmem.perBankRdBursts::4 974375 # Per bank write bursts +system.physmem.perBankRdBursts::5 968054 # Per bank write bursts +system.physmem.perBankRdBursts::6 967653 # Per bank write bursts +system.physmem.perBankRdBursts::7 967480 # Per bank write bursts +system.physmem.perBankRdBursts::8 968459 # Per bank write bursts +system.physmem.perBankRdBursts::9 968209 # Per bank write bursts +system.physmem.perBankRdBursts::10 967967 # Per bank write bursts +system.physmem.perBankRdBursts::11 967960 # Per bank write bursts +system.physmem.perBankRdBursts::12 967929 # Per bank write bursts +system.physmem.perBankRdBursts::13 967878 # Per bank write bursts +system.physmem.perBankRdBursts::14 967953 # Per bank write bursts +system.physmem.perBankRdBursts::15 967568 # Per bank write bursts +system.physmem.perBankWrBursts::0 6652 # Per bank write bursts +system.physmem.perBankWrBursts::1 6388 # Per bank write bursts +system.physmem.perBankWrBursts::2 6319 # Per bank write bursts +system.physmem.perBankWrBursts::3 6364 # Per bank write bursts +system.physmem.perBankWrBursts::4 6622 # Per bank write bursts +system.physmem.perBankWrBursts::5 6858 # Per bank write bursts +system.physmem.perBankWrBursts::6 6646 # Per bank write bursts +system.physmem.perBankWrBursts::7 6573 # Per bank write bursts +system.physmem.perBankWrBursts::8 7007 # Per bank write bursts +system.physmem.perBankWrBursts::9 6769 # Per bank write bursts +system.physmem.perBankWrBursts::10 6571 # Per bank write bursts +system.physmem.perBankWrBursts::11 6647 # Per bank write bursts +system.physmem.perBankWrBursts::12 6565 # Per bank write bursts +system.physmem.perBankWrBursts::13 6381 # Per bank write bursts +system.physmem.perBankWrBursts::14 6555 # Per bank write bursts +system.physmem.perBankWrBursts::15 6466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2616225486000 # Total gap between requests +system.physmem.totGap 2614576987500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6664 # Read request sizes (log2) -system.physmem.readPktSize::3 15335424 # Read request sizes (log2) +system.physmem.readPktSize::2 6644 # Read request sizes (log2) +system.physmem.readPktSize::3 15335434 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152614 # Read request sizes (log2) +system.physmem.readPktSize::6 152928 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57911 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1126567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 970563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1090618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 986596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1051326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2724005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2632042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3421723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 136210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 113171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 104737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 101252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 86 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58133 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1126497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 970808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1092616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 986699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1053397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2722203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2628336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3415970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 138177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 115073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 106569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -171,24 +159,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6121 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -220,124 +208,136 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1027354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.683544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.447521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.224200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22943 2.23% 2.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22460 2.19% 4.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8461 0.82% 5.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2563 0.25% 5.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2504 0.24% 5.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1783 0.17% 5.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8706 0.85% 6.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 969 0.09% 6.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 956965 93.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1027354 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6094 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2542.286675 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 118884.715097 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6090 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1027240 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.825895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.842120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.903622 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22776 2.22% 2.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22448 2.19% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8450 0.82% 5.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2555 0.25% 5.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2575 0.25% 5.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1819 0.18% 5.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8664 0.84% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 942 0.09% 6.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957011 93.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1027240 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2531.539869 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116318.280129 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6115 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6094 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6094 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.255005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.227328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.967528 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2261 37.10% 37.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 29 0.48% 37.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3794 62.26% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 9 0.15% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.219444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.191199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.977796 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2386 38.99% 38.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 19 0.31% 39.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3702 60.49% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 12 0.20% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6094 # Writes before turning the bus around for reads -system.physmem.totQLat 400062590250 # Total ticks spent queuing -system.physmem.totMemAccLat 690550846500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77463535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25822.64 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6120 # Writes before turning the bus around for reads +system.physmem.totQLat 400457727500 # Total ticks spent queuing +system.physmem.totMemAccLat 690952040000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465150000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25847.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44572.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 378.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44597.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 379.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.98 # Data bus utilization in percentage system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.59 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing -system.physmem.readRowHits 14482119 # Number of row buffer hits during reads -system.physmem.writeRowHits 88386 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.67 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing +system.physmem.readRowHits 14482583 # Number of row buffer hits during reads +system.physmem.writeRowHits 88590 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.03 # Row buffer hit rate for writes -system.physmem.avgGap 160439.36 # Average gap between requests +system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes +system.physmem.avgGap 160333.10 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2245273695250 # Time in different power states -system.physmem.memoryStateTime::REF 87361560000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2239817846000 # Time in different power states +system.physmem.memoryStateTime::REF 87306440000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 283591722250 # Time in different power states +system.physmem.memoryStateTime::ACT 287452006500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54122917 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546592 # Transaction distribution -system.membus.trans_dist::ReadResp 16546592 # Transaction distribution -system.membus.trans_dist::WriteReq 763385 # Transaction distribution -system.membus.trans_dist::WriteResp 763385 # Transaction distribution -system.membus.trans_dist::Writeback 57911 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 132219 # Transaction distribution -system.membus.trans_dist::ReadExResp 132219 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383090 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54170150 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546653 # Transaction distribution +system.membus.trans_dist::ReadResp 16546653 # Transaction distribution +system.membus.trans_dist::WriteReq 763381 # Transaction distribution +system.membus.trans_dist::WriteResp 763381 # Transaction distribution +system.membus.trans_dist::Writeback 58133 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution +system.membus.trans_dist::ReadExReq 132457 # Transaction distribution +system.membus.trans_dist::ReadExResp 132457 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893535 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280487 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894355 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281289 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951335 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390546 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34952137 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516328 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914598 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16550632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18948866 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141597990 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141597990 # Total data (bytes) +system.membus.tot_pkt_size::total 141632258 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141632258 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206224000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1207280500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3616500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3534000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17911182500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17916889500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4951111812 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4952195664 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37928474750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.respLayer2.occupancy 37921268500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47806938 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518786 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518786 # Transaction distribution -system.iobus.trans_dist::WriteReq 8183 # Transaction distribution -system.iobus.trans_dist::WriteResp 8183 # Transaction distribution +system.iobus.throughput 47837076 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution +system.iobus.trans_dist::WriteReq 8182 # Transaction distribution +system.iobus.trans_dist::WriteResp 8182 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 532 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1040 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -357,14 +357,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383082 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -384,18 +384,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073938 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073938 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073922 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 532000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 526000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -437,9 +437,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374907000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38686102250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38692913500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -465,25 +465,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996190 # DTB read hits -system.cpu.dtb.read_misses 7339 # DTB read misses -system.cpu.dtb.write_hits 11230344 # DTB write hits -system.cpu.dtb.write_misses 2214 # DTB write misses +system.cpu.dtb.read_hits 13160128 # DTB read hits +system.cpu.dtb.read_misses 7329 # DTB read misses +system.cpu.dtb.write_hits 11227968 # DTB write hits +system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003529 # DTB read accesses -system.cpu.dtb.write_accesses 11232558 # DTB write accesses +system.cpu.dtb.read_accesses 13167457 # DTB read accesses +system.cpu.dtb.write_accesses 11230180 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226534 # DTB hits -system.cpu.dtb.misses 9553 # DTB misses -system.cpu.dtb.accesses 26236087 # DTB accesses +system.cpu.dtb.hits 24388096 # DTB hits +system.cpu.dtb.misses 9541 # DTB misses +system.cpu.dtb.accesses 24397637 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -505,7 +505,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61493913 # ITB inst hits +system.cpu.itb.inst_hits 61480692 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -522,123 +522,125 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61498384 # ITB inst accesses -system.cpu.itb.hits 61493913 # DTB hits +system.cpu.itb.inst_accesses 61485163 # ITB inst accesses +system.cpu.itb.hits 61480692 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61498384 # DTB accesses -system.cpu.numCycles 5232459694 # number of cpu cycles simulated +system.cpu.itb.accesses 61485163 # DTB accesses +system.cpu.numCycles 5229162505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60200042 # Number of instructions committed -system.cpu.committedOps 76606857 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69208585 # Number of integer alu accesses +system.cpu.committedInsts 60186875 # Number of instructions committed +system.cpu.committedOps 71883476 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 64248071 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140468 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948679 # number of instructions that are conditional controls -system.cpu.num_int_insts 69208585 # number of integer instructions +system.cpu.num_func_calls 2139776 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7549008 # number of instructions that are conditional controls +system.cpu.num_int_insts 64248071 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 401368270 # number of times the integer registers were read -system.cpu.num_int_register_writes 74518872 # number of times the integer registers were written +system.cpu.num_int_register_reads 116109819 # number of times the integer registers were read +system.cpu.num_int_register_writes 42862791 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394017 # number of memory refs -system.cpu.num_load_insts 15660224 # Number of load instructions -system.cpu.num_store_insts 11733793 # Number of store instructions -system.cpu.num_idle_cycles 4581582300.610249 # Number of idle cycles -system.cpu.num_busy_cycles 650877393.389751 # Number of busy cycles -system.cpu.not_idle_fraction 0.124392 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875608 # Percentage of idle cycles -system.cpu.Branches 10308802 # Number of branches fetched +system.cpu.num_cc_register_reads 257767219 # number of times the CC registers were read +system.cpu.num_cc_register_writes 28995131 # number of times the CC registers were written +system.cpu.num_mem_refs 25244051 # number of memory refs +system.cpu.num_load_insts 13512687 # Number of load instructions +system.cpu.num_store_insts 11731364 # Number of store instructions +system.cpu.num_idle_cycles 4584182254.578246 # Number of idle cycles +system.cpu.num_busy_cycles 644980250.421753 # Number of busy cycles +system.cpu.not_idle_fraction 0.123343 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.876657 # Percentage of idle cycles +system.cpu.Branches 10306559 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 50389316 64.68% 64.72% # Class of executed instruction -system.cpu.op_class::IntMult 87585 0.11% 64.83% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 2109 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::MemRead 15660224 20.10% 84.94% # Class of executed instruction -system.cpu.op_class::MemWrite 11733793 15.06% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47576706 65.23% 65.27% # Class of executed instruction +system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::MemRead 13512687 18.53% 83.92% # Class of executed instruction +system.cpu.op_class::MemWrite 11731364 16.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 77901545 # Class of executed instruction +system.cpu.op_class::total 72938935 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83017 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856351 # number of replacements -system.cpu.icache.tags.tagsinuse 510.866135 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60637050 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856863 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.766330 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20005377250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.866135 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997785 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 83001 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 855859 # number of replacements +system.cpu.icache.tags.tagsinuse 510.877209 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60624321 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856371 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.792123 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19627747250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.877209 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62350776 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62350776 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60637050 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60637050 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60637050 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60637050 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60637050 # number of overall hits -system.cpu.icache.overall_hits::total 60637050 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856863 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856863 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856863 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856863 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856863 # number of overall misses -system.cpu.icache.overall_misses::total 856863 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766560750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11766560750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11766560750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11766560750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11766560750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11766560750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61493913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61493913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61493913 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61493913 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61493913 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61493913 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13732.137751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13732.137751 # average overall miss latency +system.cpu.icache.tags.tag_accesses 62337063 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62337063 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60624321 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60624321 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60624321 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60624321 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60624321 # number of overall hits +system.cpu.icache.overall_hits::total 60624321 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856371 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856371 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856371 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856371 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856371 # number of overall misses +system.cpu.icache.overall_misses::total 856371 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11763954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11763954000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11763954000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11763954000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11763954000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11763954000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61480692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61480692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61480692 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61480692 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61480692 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61480692 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013929 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013929 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013929 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13736.983153 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13736.983153 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13736.983153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13736.983153 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,186 +649,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856863 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856863 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856863 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856863 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856863 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856863 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10048829250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10048829250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10048829250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10048829250 # number of demand (read+write) MSHR miss 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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58038.465169 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57321.777973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57370.690455 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -930,143 +932,166 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626320 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.875633 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655948 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626832 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.738897 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.875633 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 625842 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.875658 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21786000 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626354 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.782248 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.875658 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11249339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9965366 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9965366 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 84253 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 84253 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236457 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236457 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247663 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247663 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21214705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21214705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21298958 # number of overall hits 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15573507260 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11544002 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11544002 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10220663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10220663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 184359 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 184359 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247664 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247664 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247663 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247663 # 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13846.881413 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13846.881413 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28317.527202 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28317.527202 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.809401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23956.809401 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595396 # number of writebacks -system.cpu.dcache.writebacks::total 595396 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368196 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368196 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250157 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250157 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11407 # number of LoadLockedReq MSHR misses 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-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135458250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15392937734 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15392937734 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15392937734 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15392937734 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242925328 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242925328 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027144 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027144 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046036 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046036 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025995 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025995 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 594981 # number of writebacks +system.cpu.dcache.writebacks::total 594981 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 534 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 534 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4836 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 4836 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5370 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5370 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5370 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5370 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294129 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 294129 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250461 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250461 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 73479 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 73479 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11207 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11207 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 544590 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 544590 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618069 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618069 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3445567250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3445567250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10763005489 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10763005489 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1228271500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1228271500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132710000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132710000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14208572739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14208572739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15436844239 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15436844239 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058544250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058544250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242551425 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242551425 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301095675 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301095675 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398565 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398565 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045251 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045251 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025022 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025022 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11714.476471 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11714.476471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42972.780149 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42972.780149 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16715.952857 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16715.952857 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11841.706077 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11841.706077 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26090.403311 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26090.403311 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24975.923787 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24975.923787 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1074,37 +1099,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52982138 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2928 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2928 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247229 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725354 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12465 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27449 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7515238 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54761180 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83637066 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14156 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138447274 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138447274 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166176 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009006000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 52981595 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2453579 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2453579 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 594981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247539 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748549 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7511231 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54730908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83579878 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138353418 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138353418 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 171268 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3007873000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295477750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1294746250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533767938 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2533153086 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18731500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18709500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use @@ -1122,10 +1147,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1759698189250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1760059764500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1760059764500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 203fb6e65..a9cd1b1ac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,18 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332812 # Number of seconds simulated -sim_ticks 2332811899500 # Number of ticks simulated -final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.321351 # Number of seconds simulated +sim_ticks 2321351025500 # Number of ticks simulated +final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 860450 # Simulator instruction rate (inst/s) -host_op_rate 1106481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33226597982 # Simulator tick rate (ticks/s) -host_mem_usage 465868 # Number of bytes of host memory used -host_seconds 70.21 # Real time elapsed on the host -sim_insts 60411489 # Number of instructions simulated -sim_ops 77685090 # Number of ops (including micro ops) simulated +host_inst_rate 709541 # Simulator instruction rate (inst/s) +host_op_rate 854435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27266672116 # Simulator tick rate (ticks/s) +host_mem_usage 431868 # Number of bytes of host memory used +host_seconds 85.14 # Real time elapsed on the host +sim_insts 60406834 # Number of instructions simulated +sim_ops 72742429 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 508168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5844952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 197248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3227072 # Number of bytes read from this memory +system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 508168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 197248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703808 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1462736 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1553080 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719624 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14152 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 91353 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 50423 # Number of read requests responded to by this memory +system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57872 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 365684 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 388270 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811826 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 83 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 218910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2517910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 84971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1390170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 218910 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 84971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1595540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 630123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 669041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2894704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1595540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 218910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3148032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 84971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2059211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54536286 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -25,218 +76,167 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 492808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6490264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 212352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2581696 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 492808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 212352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1405780 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1610036 # Number of bytes written to this memory -system.physmem.bytes_written::total 6719176 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 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(bytes/s) -system.physmem.bw_total::cpu1.inst 91028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1796858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942261 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969742 # Throughput (bytes/s) -system.membus.data_through_bus 130566879 # Total data (bytes) +system.membus.throughput 55568819 # Throughput (bytes/s) +system.membus.data_through_bus 128994735 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62245 # number of replacements -system.l2c.tags.tagsinuse 50006.493098 # Cycle average of tags in use -system.l2c.tags.total_refs 1678467 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127630 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.151038 # Average number of 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demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 261312 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492508 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9010 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3282 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 480346 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 362543 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4855 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2031 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 369129 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 261312 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492508 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000914 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028618 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008989 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023397 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992193 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990057 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.603520 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.423713 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539917 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000914 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.281967 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008989 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.157360 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103151 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000914 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.281967 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008989 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.157360 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103151 # miss rate for overall accesses +system.l2c.overall_misses::cpu0.inst 7526 # number of overall misses +system.l2c.overall_misses::cpu0.data 92158 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3082 # number of overall misses +system.l2c.overall_misses::cpu1.data 51191 # number of overall misses +system.l2c.overall_misses::total 153962 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8777 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3266 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 459281 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 195045 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5151 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2105 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 390120 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 181611 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1245356 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592686 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592686 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1521 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1422 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 148092 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 99093 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247185 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8777 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3266 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 459281 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 343137 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5151 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2105 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 390120 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 280704 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492541 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8777 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3266 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 459281 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 343137 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5151 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2105 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 390120 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 280704 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492541 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000919 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016386 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.031244 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007900 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020803 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016449 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989481 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992968 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.581152 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.478470 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539988 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000919 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016386 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.268575 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007900 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.182366 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103154 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000919 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016386 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.268575 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007900 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.182366 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103154 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57865 # number of writebacks -system.l2c.writebacks::total 57865 # number of writebacks +system.l2c.writebacks::writebacks 57872 # number of writebacks +system.l2c.writebacks::total 57872 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -254,11 +254,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59119724 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137915195 # Total data (bytes) +system.toL2Bus.throughput 59409488 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137910275 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 48895283 # Throughput (bytes/s) -system.iobus.data_through_bus 114063499 # Total data (bytes) +system.iobus.throughput 48459111 # Throughput (bytes/s) +system.iobus.data_through_bus 112490607 # Total data (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -282,25 +282,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7929658 # DTB read hits -system.cpu0.dtb.read_misses 6455 # DTB read misses -system.cpu0.dtb.write_hits 6435419 # DTB write hits -system.cpu0.dtb.write_misses 1929 # DTB write misses -system.cpu0.dtb.flush_tlb 2334 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 6811742 # DTB read hits +system.cpu0.dtb.read_misses 6183 # DTB read misses +system.cpu0.dtb.write_hits 6269363 # DTB write hits +system.cpu0.dtb.write_misses 2047 # DTB write misses +system.cpu0.dtb.flush_tlb 2324 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5575 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5527 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7936113 # DTB read accesses -system.cpu0.dtb.write_accesses 6437348 # DTB write accesses +system.cpu0.dtb.perms_faults 235 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6817925 # DTB read accesses +system.cpu0.dtb.write_accesses 6271410 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14365077 # DTB hits -system.cpu0.dtb.misses 8384 # DTB misses -system.cpu0.dtb.accesses 14373461 # DTB accesses +system.cpu0.dtb.hits 13081105 # DTB hits +system.cpu0.dtb.misses 8230 # DTB misses +system.cpu0.dtb.accesses 13089335 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -322,141 +322,143 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32541992 # ITB inst hits -system.cpu0.itb.inst_misses 3717 # ITB inst misses +system.cpu0.itb.inst_hits 32133466 # ITB inst hits +system.cpu0.itb.inst_misses 3581 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2334 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2324 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2662 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32545709 # ITB inst accesses -system.cpu0.itb.hits 32541992 # DTB hits -system.cpu0.itb.misses 3717 # DTB misses -system.cpu0.itb.accesses 32545709 # DTB accesses -system.cpu0.numCycles 4625561989 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32137047 # ITB inst accesses +system.cpu0.itb.hits 32133466 # DTB hits +system.cpu0.itb.misses 3581 # DTB misses +system.cpu0.itb.accesses 32137047 # DTB accesses +system.cpu0.numCycles 4608021079 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31996828 # Number of instructions committed -system.cpu0.committedOps 41898003 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37241416 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses -system.cpu0.num_func_calls 1207166 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4285035 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37241416 # number of integer instructions -system.cpu0.num_fp_insts 5364 # number of float instructions -system.cpu0.num_int_register_reads 192512823 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39713188 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu0.num_mem_refs 15011832 # number of memory refs -system.cpu0.num_load_insts 8305325 # Number of load instructions -system.cpu0.num_store_insts 6706507 # Number of store instructions -system.cpu0.num_idle_cycles 4549718927.235470 # Number of idle cycles -system.cpu0.num_busy_cycles 75843061.764530 # Number of busy cycles -system.cpu0.not_idle_fraction 0.016397 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.983603 # Percentage of idle cycles -system.cpu0.Branches 5613326 # Number of branches fetched -system.cpu0.op_class::No_OpClass 16463 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 26898614 64.08% 64.12% # Class of executed instruction -system.cpu0.op_class::IntMult 45874 0.11% 64.23% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1340 0.00% 64.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 64.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.24% # Class of executed instruction -system.cpu0.op_class::MemRead 8305325 19.79% 84.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 6706507 15.98% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31639227 # Number of instructions committed +system.cpu0.committedOps 38587883 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34004805 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5482 # Number of float alu accesses +system.cpu0.num_func_calls 1192523 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4010781 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34004805 # number of integer instructions +system.cpu0.num_fp_insts 5482 # number of float instructions +system.cpu0.num_int_register_reads 62290177 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22551825 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3925 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1558 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 115496065 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 15262729 # number of times the CC registers were written +system.cpu0.num_mem_refs 13528824 # number of memory refs +system.cpu0.num_load_insts 6988108 # Number of load instructions +system.cpu0.num_store_insts 6540716 # Number of store instructions +system.cpu0.num_idle_cycles 4534732444.570566 # Number of idle cycles +system.cpu0.num_busy_cycles 73288634.429434 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015905 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984095 # Percentage of idle cycles +system.cpu0.Branches 5541899 # Number of branches fetched +system.cpu0.op_class::No_OpClass 16090 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 25070156 64.84% 64.89% # Class of executed instruction +system.cpu0.op_class::IntMult 45827 0.12% 65.00% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.00% # Class of executed instruction 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65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1368 0.00% 65.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.01% # Class of executed instruction +system.cpu0.op_class::MemRead 6988108 18.07% 83.08% # Class of executed instruction +system.cpu0.op_class::MemWrite 6540716 16.92% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 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67.177938 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868165 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131207 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 82781 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 850515 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60581740 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 446.344221 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.345372 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.871766 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127628 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62288542 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62288542 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32063555 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 28522783 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60586338 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32063555 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 28522783 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60586338 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32063555 # number of overall hits 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62283794 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62283794 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31676072 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 28905668 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60581740 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31676072 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 28905668 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60581740 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31676072 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 28905668 # number of overall hits +system.cpu0.icache.overall_hits::total 60581740 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 460107 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 390920 # number of ReadReq misses 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for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013344 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014787 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012802 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014317 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013344 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -467,90 +469,102 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number 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Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5835707 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 5404504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11240211 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5610278 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4351033 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9961311 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 52098 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58749 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 110847 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136238 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 99769 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236007 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142767 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 104429 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11445985 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 9755537 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21201522 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11498083 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 9814286 # number of overall hits +system.cpu0.dcache.overall_hits::total 21312369 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 155593 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 136452 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 292045 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 149613 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 100515 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250128 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 32922 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 40499 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 73421 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6530 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4660 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11190 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 305206 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 236967 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 542173 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 338128 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 277466 # number of overall misses +system.cpu0.dcache.overall_misses::total 615594 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5991300 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 5540956 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5759891 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4451548 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 85020 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 99248 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 184268 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142768 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 104429 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142767 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 104429 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11751191 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 9992504 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11836211 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10091752 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21927963 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025970 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.024626 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.025324 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025975 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.022580 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045538 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044807 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045239 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027225 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024289 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027225 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024289 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.387227 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.408059 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.398447 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045739 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044624 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045268 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025972 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023714 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024935 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028567 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027494 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,8 +573,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 592692 # number of writebacks -system.cpu0.dcache.writebacks::total 592692 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 592686 # number of writebacks +system.cpu0.dcache.writebacks::total 592686 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -585,25 +599,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7038699 # DTB read hits -system.cpu1.dtb.read_misses 4194 # DTB read misses -system.cpu1.dtb.write_hits 4780763 # DTB write hits -system.cpu1.dtb.write_misses 1254 # DTB write misses -system.cpu1.dtb.flush_tlb 2332 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 6327054 # DTB read hits +system.cpu1.dtb.read_misses 4532 # DTB read misses +system.cpu1.dtb.write_hits 4945852 # DTB write hits +system.cpu1.dtb.write_misses 1126 # DTB write misses +system.cpu1.dtb.flush_tlb 2320 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2928 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 3028 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 87 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7042893 # DTB read accesses -system.cpu1.dtb.write_accesses 4782017 # DTB write accesses +system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6331586 # DTB read accesses +system.cpu1.dtb.write_accesses 4946978 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 11819462 # DTB hits -system.cpu1.dtb.misses 5448 # DTB misses -system.cpu1.dtb.accesses 11824910 # DTB accesses +system.cpu1.dtb.hits 11272906 # DTB hits +system.cpu1.dtb.misses 5658 # DTB misses +system.cpu1.dtb.accesses 11278564 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -625,85 +639,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28890998 # ITB inst hits -system.cpu1.itb.inst_misses 2444 # ITB inst misses +system.cpu1.itb.inst_hits 29294834 # ITB inst hits +system.cpu1.itb.inst_misses 2597 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2332 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2320 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1642 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 1660 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28893442 # ITB inst accesses -system.cpu1.itb.hits 28890998 # DTB hits -system.cpu1.itb.misses 2444 # DTB misses -system.cpu1.itb.accesses 28893442 # DTB accesses -system.cpu1.numCycles 4282034895 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 29297431 # ITB inst accesses +system.cpu1.itb.hits 29294834 # DTB hits +system.cpu1.itb.misses 2597 # DTB misses +system.cpu1.itb.accesses 29297431 # DTB accesses +system.cpu1.numCycles 141054432 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 28414661 # Number of instructions committed -system.cpu1.committedOps 35787087 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31892138 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses -system.cpu1.num_func_calls 928912 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3657531 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31892138 # number of integer instructions -system.cpu1.num_fp_insts 4905 # number of float instructions -system.cpu1.num_int_register_reads 163397724 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34729085 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written -system.cpu1.num_mem_refs 12350589 # number of memory refs -system.cpu1.num_load_insts 7334763 # Number of load instructions -system.cpu1.num_store_insts 5015826 # Number of store instructions -system.cpu1.num_idle_cycles 4212351630.069436 # Number of idle cycles -system.cpu1.num_busy_cycles 69683264.930565 # Number of busy cycles -system.cpu1.not_idle_fraction 0.016273 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.983727 # Percentage of idle cycles -system.cpu1.Branches 4685935 # Number of branches fetched -system.cpu1.op_class::No_OpClass 12055 0.03% 0.03% # Class of executed instruction -system.cpu1.op_class::IntAlu 23438937 65.39% 65.42% # Class of executed instruction -system.cpu1.op_class::IntMult 41906 0.12% 65.54% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 777 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::MemRead 7334763 20.46% 86.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 5015826 13.99% 100.00% # Class of executed instruction +system.cpu1.committedInsts 28767607 # Number of instructions committed +system.cpu1.committedOps 34154546 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 30186625 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4787 # Number of float alu accesses +system.cpu1.num_func_calls 943239 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3534203 # number of instructions that are conditional controls +system.cpu1.num_int_insts 30186625 # number of integer instructions +system.cpu1.num_fp_insts 4787 # number of float instructions +system.cpu1.num_int_register_reads 54137170 # number of times the integer registers were read +system.cpu1.num_int_register_writes 20266282 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3568 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1222 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102073939 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 13715012 # number of times the CC registers were written +system.cpu1.num_mem_refs 11692450 # number of memory refs +system.cpu1.num_load_insts 6511829 # Number of load instructions +system.cpu1.num_store_insts 5180621 # Number of store instructions +system.cpu1.num_idle_cycles 138966556.858503 # Number of idle cycles +system.cpu1.num_busy_cycles 2087875.141497 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014802 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985198 # Percentage of idle cycles +system.cpu1.Branches 4756618 # Number of branches fetched +system.cpu1.op_class::No_OpClass 12428 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 22465876 65.66% 65.70% # Class of executed instruction +system.cpu1.op_class::IntMult 41944 0.12% 65.82% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 745 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::MemRead 6511829 19.03% 84.86% # Class of executed instruction +system.cpu1.op_class::MemWrite 5180621 15.14% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 35844264 # Class of executed instruction +system.cpu1.op_class::total 34213443 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 07ebe167c..b0c415fa9 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,63 +1,66 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.112126 # Number of seconds simulated -sim_ticks 5112126264500 # Number of ticks simulated -final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5112125984500 # Number of ticks simulated +final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1285356 # Simulator instruction rate (inst/s) -host_op_rate 2631685 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32866027497 # Simulator tick rate (ticks/s) -host_mem_usage 626676 # Number of bytes of host memory used -host_seconds 155.54 # Real time elapsed on the host -sim_insts 199929810 # Number of instructions simulated -sim_ops 409343850 # Number of ops (including micro ops) simulated +host_inst_rate 1274105 # Simulator instruction rate (inst/s) +host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32578287771 # Simulator tick rate (ticks/s) +host_mem_usage 593532 # Number of bytes of host memory used +host_seconds 156.92 # Real time elapsed on the host +sim_insts 199930130 # Number of instructions simulated +sim_ops 409344539 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory -system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory -system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory +system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory +system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory +system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory +system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory +system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2715827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9634332 # Throughput (bytes/s) -system.membus.data_through_bus 49251923 # Total data (bytes) +system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9050072 # Throughput (bytes/s) +system.membus.data_through_bus 46265107 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -65,26 +68,24 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 428616 # Number of tag accesses system.iocache.tags.data_accesses 428616 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses system.iocache.ReadReq_misses::total 904 # number of ReadReq misses -system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses -system.iocache.demand_misses::total 47624 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses -system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses +system.iocache.demand_misses::total 904 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses +system.iocache.overall_misses::total 904 # number of overall misses system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses @@ -95,10 +96,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -116,34 +115,34 @@ system.iobus.throughput 2555207 # Th system.iobus.data_through_bus 13062542 # Total data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10224253904 # number of cpu cycles simulated +system.cpu.numCycles 10224253344 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199929810 # Number of instructions committed -system.cpu.committedOps 409343850 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374364636 # Number of integer alu accesses +system.cpu.committedInsts 199930130 # Number of instructions committed +system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2307717 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39976328 # number of instructions that are conditional controls -system.cpu.num_int_insts 374364636 # number of integer instructions +system.cpu.num_func_calls 2307745 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls +system.cpu.num_int_insts 374365317 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 682285475 # number of times the integer registers were read -system.cpu.num_int_register_writes 323369236 # number of times the integer registers were written +system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read +system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 233715040 # number of times the CC registers were read -system.cpu.num_cc_register_writes 157233555 # number of times the CC registers were written -system.cpu.num_mem_refs 35660913 # number of memory refs -system.cpu.num_load_insts 27238816 # Number of load instructions -system.cpu.num_store_insts 8422097 # Number of store instructions -system.cpu.num_idle_cycles 9770518213.691833 # Number of idle cycles -system.cpu.num_busy_cycles 453735690.308166 # Number of busy cycles +system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written +system.cpu.num_mem_refs 35661072 # number of memory refs +system.cpu.num_load_insts 27238907 # Number of load instructions +system.cpu.num_store_insts 8422165 # Number of store instructions +system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles +system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955622 # Percentage of idle cycles -system.cpu.Branches 43125514 # Number of branches fetched -system.cpu.op_class::No_OpClass 175310 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 373241321 91.18% 91.22% # Class of executed instruction -system.cpu.op_class::IntMult 144368 0.04% 91.26% # Class of executed instruction +system.cpu.Branches 43125613 # Number of branches fetched +system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction +system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction @@ -171,18 +170,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::MemRead 27238816 6.65% 97.94% # Class of executed instruction -system.cpu.op_class::MemWrite 8422097 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 409344880 # Class of executed instruction +system.cpu.op_class::total 409345569 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 790558 # number of replacements +system.cpu.icache.tags.replacements 790679 # number of replacements system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243525778 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791070 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.843526 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy @@ -192,26 +191,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 87 system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 245107932 # Number of tag accesses -system.cpu.icache.tags.data_accesses 245107932 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243525778 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243525778 # number of overall hits -system.cpu.icache.overall_hits::total 243525778 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791077 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791077 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791077 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791077 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791077 # number of overall misses -system.cpu.icache.overall_misses::total 791077 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244316855 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244316855 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244316855 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244316855 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244316855 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244316855 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits +system.cpu.icache.overall_hits::total 243526070 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses +system.cpu.icache.overall_misses::total 791198 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses @@ -228,12 +227,12 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026303 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.tagsinuse 3.026310 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026310 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id @@ -283,12 +282,12 @@ system.cpu.itb_walker_cache.writebacks::writebacks 526 system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 5.014183 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12951 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.avg_refs 1.694270 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014183 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id @@ -296,32 +295,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52398 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52398 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits +system.cpu.dtb_walker_cache.tags.tag_accesses 52390 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52390 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12959 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12959 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12959 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12959 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12959 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12959 # number of overall hits system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21783 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21783 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21783 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21783 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21783 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21783 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405087 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405087 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405087 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405087 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405087 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405087 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -333,11 +332,11 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622097 # number of replacements +system.cpu.dcache.tags.replacements 1622084 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20175179 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622609 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.433790 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 20175355 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622596 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.433998 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -347,40 +346,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88813841 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88813841 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8095378 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20172909 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20172909 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20172909 # number of overall hits -system.cpu.dcache.overall_hits::total 20172909 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308430 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308430 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316465 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316465 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624895 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624895 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624895 # number of overall misses -system.cpu.dcache.overall_misses::total 1624895 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses +system.cpu.dcache.tags.tag_accesses 88814480 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88814480 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12018728 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12018728 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8095451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8095451 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58906 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58906 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20114179 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20114179 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20173085 # number of overall hits +system.cpu.dcache.overall_hits::total 20173085 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905666 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905666 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316462 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316462 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402754 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402754 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1222128 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1222128 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624882 # number of overall misses +system.cpu.dcache.overall_misses::total 1624882 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12924394 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12924394 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8411913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461660 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461660 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21336307 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21336307 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21797967 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21797967 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070074 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070074 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872404 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872404 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074543 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074543 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,23 +396,23 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535825 # number of writebacks -system.cpu.dcache.writebacks::total 1535825 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535815 # number of writebacks +system.cpu.dcache.writebacks::total 1535815 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 54625221 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 279225555 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) -system.cpu.l2cache.tags.replacements 105999 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64822.034013 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3456623 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.317898 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 55211163 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 3014592 # Total snoop data (bytes) +system.cpu.l2cache.tags.replacements 105997 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64822.035422 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3456726 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170125 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.318742 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.539598 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.541573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.519483 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy @@ -416,32 +423,32 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20892 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39453 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20884 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39461 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32198887 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32198887 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 32199668 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32199668 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275554 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062599 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538784 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538784 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777860 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062710 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538774 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538774 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179732 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179732 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179729 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179729 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777739 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1455286 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2242331 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777860 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1455273 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2242439 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777739 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1455286 # number of overall hits -system.cpu.l2cache.overall_hits::total 2242331 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777860 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1455273 # number of overall hits +system.cpu.l2cache.overall_hits::total 2242439 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses @@ -463,44 +470,44 @@ system.cpu.l2cache.overall_misses::cpu.data 166704 # system.cpu.l2cache.overall_misses::total 180035 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791064 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307800 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108176 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538784 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538784 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108287 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538774 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538774 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314190 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314190 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314187 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314187 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791064 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621990 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422366 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791185 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621977 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422474 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791064 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621990 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422366 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791185 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621977 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422474 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016842 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021618 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427951 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.427951 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427955 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.427955 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102777 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074322 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016842 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074319 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102777 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074322 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016842 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074319 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,8 +516,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks -system.cpu.l2cache.writebacks::total 98156 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks +system.cpu.l2cache.writebacks::total 98154 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 60b3a8779..015764a13 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,135 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.200396 # Number of seconds simulated -sim_ticks 5200396150000 # Number of ticks simulated -final_tick 5200396150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.192526 # Number of seconds simulated +sim_ticks 5192526233000 # Number of ticks simulated +final_tick 5192526233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 778841 # Simulator instruction rate (inst/s) -host_op_rate 1501355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31560622919 # Simulator tick rate (ticks/s) -host_mem_usage 627712 # Number of bytes of host memory used -host_seconds 164.77 # Real time elapsed on the host -sim_insts 128333376 # Number of instructions simulated -sim_ops 247385531 # Number of ops (including micro ops) simulated +host_inst_rate 1492668 # Simulator instruction rate (inst/s) +host_op_rate 2877328 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60393582039 # Simulator tick rate (ticks/s) +host_mem_usage 592376 # Number of bytes of host memory used +host_seconds 85.98 # Real time elapsed on the host +sim_insts 128336778 # Number of instructions simulated +sim_ops 247387190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2886336 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8967296 # Number of bytes read from this memory -system.physmem.bytes_read::total 12679232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8106560 # Number of bytes written to this memory -system.physmem.bytes_written::total 8106560 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45099 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 829632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9090688 # Number of bytes read from this memory +system.physmem.bytes_read::total 9949056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 829632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 829632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5138240 # Number of bytes written to this memory +system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory +system.physmem.bytes_written::total 8128320 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140114 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198113 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126665 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126665 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 555022 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142042 # Number of read requests responded to by this memory +system.physmem.num_reads::total 155454 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 80285 # Number of write requests responded to by this memory +system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127005 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158683 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1724349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2438128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158683 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158683 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1558835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1558835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1558835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 555022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1750725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1916034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 989545 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 575843 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1565388 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 989545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158683 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1724349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3996963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198113 # Number of read requests accepted -system.physmem.writeReqs 126665 # Number of write requests accepted -system.physmem.readBursts 198113 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 126665 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue -system.physmem.bytesWritten 8105536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12679232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8106560 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 159774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1750725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3481422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 155454 # Number of read requests accepted +system.physmem.writeReqs 127005 # Number of write requests accepted +system.physmem.readBursts 155454 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 127005 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9932928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16128 # Total number of bytes read from write queue +system.physmem.bytesWritten 8126720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9949056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8128320 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 252 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1623 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12177 # Per bank write bursts -system.physmem.perBankRdBursts::1 12548 # Per bank write bursts -system.physmem.perBankRdBursts::2 13053 # Per bank write bursts -system.physmem.perBankRdBursts::3 12620 # Per bank write bursts -system.physmem.perBankRdBursts::4 12592 # Per bank write bursts -system.physmem.perBankRdBursts::5 12288 # Per bank write bursts -system.physmem.perBankRdBursts::6 11961 # Per bank write bursts -system.physmem.perBankRdBursts::7 12236 # Per bank write bursts -system.physmem.perBankRdBursts::8 11972 # Per bank write bursts -system.physmem.perBankRdBursts::9 11957 # Per bank write bursts -system.physmem.perBankRdBursts::10 12338 # Per bank write bursts -system.physmem.perBankRdBursts::11 12177 # Per bank write bursts -system.physmem.perBankRdBursts::12 12807 # Per bank write bursts -system.physmem.perBankRdBursts::13 12813 # Per bank write bursts -system.physmem.perBankRdBursts::14 12433 # Per bank write bursts -system.physmem.perBankRdBursts::15 12012 # Per bank write bursts -system.physmem.perBankWrBursts::0 7757 # Per bank write bursts -system.physmem.perBankWrBursts::1 8145 # Per bank write bursts -system.physmem.perBankWrBursts::2 8603 # Per bank write bursts -system.physmem.perBankWrBursts::3 8164 # Per bank write bursts -system.physmem.perBankWrBursts::4 8201 # Per bank write bursts -system.physmem.perBankWrBursts::5 7973 # Per bank write bursts -system.physmem.perBankWrBursts::6 7511 # Per bank write bursts -system.physmem.perBankWrBursts::7 7789 # Per bank write bursts -system.physmem.perBankWrBursts::8 7356 # Per bank write bursts -system.physmem.perBankWrBursts::9 7523 # Per bank write bursts -system.physmem.perBankWrBursts::10 7874 # Per bank write bursts -system.physmem.perBankWrBursts::11 7684 # Per bank write bursts -system.physmem.perBankWrBursts::12 8313 # Per bank write bursts -system.physmem.perBankWrBursts::13 8300 # Per bank write bursts -system.physmem.perBankWrBursts::14 7968 # Per bank write bursts -system.physmem.perBankWrBursts::15 7488 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1602 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10234 # Per bank write bursts +system.physmem.perBankRdBursts::1 9830 # Per bank write bursts +system.physmem.perBankRdBursts::2 10412 # Per bank write bursts +system.physmem.perBankRdBursts::3 9937 # Per bank write bursts +system.physmem.perBankRdBursts::4 9788 # Per bank write bursts +system.physmem.perBankRdBursts::5 9348 # Per bank write bursts +system.physmem.perBankRdBursts::6 9238 # Per bank write bursts +system.physmem.perBankRdBursts::7 9473 # Per bank write bursts +system.physmem.perBankRdBursts::8 9270 # Per bank write bursts +system.physmem.perBankRdBursts::9 9085 # Per bank write bursts +system.physmem.perBankRdBursts::10 9528 # Per bank write bursts +system.physmem.perBankRdBursts::11 9619 # Per bank write bursts +system.physmem.perBankRdBursts::12 9707 # Per bank write bursts +system.physmem.perBankRdBursts::13 10058 # Per bank write bursts +system.physmem.perBankRdBursts::14 9877 # Per bank write bursts +system.physmem.perBankRdBursts::15 9798 # Per bank write bursts +system.physmem.perBankWrBursts::0 8316 # Per bank write bursts +system.physmem.perBankWrBursts::1 7729 # Per bank write bursts +system.physmem.perBankWrBursts::2 8212 # Per bank write bursts +system.physmem.perBankWrBursts::3 7860 # Per bank write bursts +system.physmem.perBankWrBursts::4 8063 # Per bank write bursts +system.physmem.perBankWrBursts::5 7657 # Per bank write bursts +system.physmem.perBankWrBursts::6 7184 # Per bank write bursts +system.physmem.perBankWrBursts::7 7824 # Per bank write bursts +system.physmem.perBankWrBursts::8 7616 # Per bank write bursts +system.physmem.perBankWrBursts::9 7570 # Per bank write bursts +system.physmem.perBankWrBursts::10 7824 # Per bank write bursts +system.physmem.perBankWrBursts::11 7928 # Per bank write bursts +system.physmem.perBankWrBursts::12 8040 # Per bank write bursts +system.physmem.perBankWrBursts::13 8642 # Per bank write bursts +system.physmem.perBankWrBursts::14 8420 # Per bank write bursts +system.physmem.perBankWrBursts::15 8095 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5200396086500 # Total gap between requests +system.physmem.totGap 5192526169500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 198113 # Read request sizes (log2) +system.physmem.readPktSize::6 155454 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126665 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 153621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see +system.physmem.writePktSize::6 127005 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54 # 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queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,274 +159,272 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 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accessed per row activation -system.physmem.bytesPerActivate::640-767 1591 2.68% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1115 1.88% 81.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 921 1.55% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10061 16.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59433 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6976 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.380447 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 572.057676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6975 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6976 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6976 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.154960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.623474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.583584 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 4785 68.59% 68.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1454 20.84% 89.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 33 0.47% 89.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 125 1.79% 91.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 57 0.82% 92.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 47 0.67% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 75 1.08% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 59 0.85% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 41 0.59% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 19 0.27% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 30 0.43% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 56 0.80% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 145 2.08% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 17 0.24% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 4 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 11 0.16% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 3 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 3 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6976 # Writes before turning the bus around for reads -system.physmem.totQLat 5514862500 # Total ticks spent queuing -system.physmem.totMemAccLat 9227062500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27855.09 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7175 # What write queue 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queue length does an incoming req see +system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 56259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.007910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.347718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.337897 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20082 35.70% 35.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13652 24.27% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5681 10.10% 70.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3443 6.12% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2317 4.12% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1632 2.90% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1101 1.96% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1008 1.79% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7343 13.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 56259 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5896 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.315638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 622.349689 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5895 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5896 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5896 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.536635 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.431893 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.049302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4860 82.43% 82.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 44 0.75% 83.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 38 0.64% 83.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 287 4.87% 88.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 272 4.61% 93.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.34% 93.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 25 0.42% 94.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.19% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 27 0.46% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.07% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 223 3.78% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.10% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 20 0.34% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 10 0.17% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.14% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 4 0.07% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.22% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5896 # Writes before turning the bus around for reads +system.physmem.totQLat 1473683250 # Total ticks spent queuing +system.physmem.totMemAccLat 4383720750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 776010000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9495.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46605.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28245.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing -system.physmem.readRowHits 166366 # Number of row buffer hits during reads -system.physmem.writeRowHits 98833 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes -system.physmem.avgGap 16012156.26 # Average gap between requests -system.physmem.pageHitRate 81.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4979189621500 # Time in different power states -system.physmem.memoryStateTime::REF 173652440000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.52 # Average write queue length when enqueuing +system.physmem.readRowHits 127189 # Number of row buffer hits during reads +system.physmem.writeRowHits 98733 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes +system.physmem.avgGap 18383291.63 # Average gap between requests +system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4971157882750 # Time in different power states +system.physmem.memoryStateTime::REF 173389840000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 47553973500 # Time in different power states +system.physmem.memoryStateTime::ACT 47978395250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 4356964 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623381 # Transaction distribution -system.membus.trans_dist::ReadResp 623381 # Transaction distribution -system.membus.trans_dist::WriteReq 13777 # Transaction distribution -system.membus.trans_dist::WriteResp 13777 # Transaction distribution -system.membus.trans_dist::Writeback 126665 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1641 # Transaction distribution -system.membus.trans_dist::ReadExReq 159285 # Transaction distribution -system.membus.trans_dist::ReadExResp 159285 # Transaction distribution -system.membus.trans_dist::MessageReq 1656 # Transaction distribution -system.membus.trans_dist::MessageResp 1656 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) +system.membus.throughput 3808612 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623901 # Transaction distribution +system.membus.trans_dist::ReadResp 623901 # Transaction distribution +system.membus.trans_dist::WriteReq 13773 # Transaction distribution +system.membus.trans_dist::WriteResp 13773 # Transaction distribution +system.membus.trans_dist::Writeback 80285 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1602 # Transaction distribution +system.membus.trans_dist::ReadExReq 113400 # Transaction distribution +system.membus.trans_dist::ReadExResp 113400 # Transaction distribution +system.membus.trans_dist::MessageReq 1654 # Transaction distribution +system.membus.trans_dist::MessageResp 1654 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 139322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1723534 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394055 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94727 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94727 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1682528 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420233 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14912768 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16579445 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5873024 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5873024 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22459093 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22459093 # Total data (bytes) -system.membus.snoop_data_through_bus 198848 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 256797000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15058944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16725605 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 19750653 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 19750653 # Total data (bytes) +system.membus.snoop_data_through_bus 25664 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 359321500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3312000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1351243000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1309717000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2609486505 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2621518398 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429020250 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54330498 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47501 # number of replacements -system.iocache.tags.tagsinuse 0.128246 # Cycle average of tags in use +system.iocache.tags.replacements 47509 # number of replacements +system.iocache.tags.tagsinuse 0.112613 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47525 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5049779388000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128246 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008015 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.008015 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045777659000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112613 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007038 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007038 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428004 # Number of tag accesses -system.iocache.tags.data_accesses 428004 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 836 # number of ReadReq misses -system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses -system.iocache.demand_misses::total 47556 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses -system.iocache.overall_misses::total 47556 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140309686 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 140309686 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12229393602 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12229393602 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 12369703288 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12369703288 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 12369703288 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12369703288 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 428076 # Number of tag accesses +system.iocache.tags.data_accesses 428076 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses +system.iocache.demand_misses::total 844 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses +system.iocache.overall_misses::total 844 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141199186 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 141199186 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 141199186 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 141199186 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 141199186 # number of overall miss cycles +system.iocache.overall_miss_latency::total 141199186 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167834.552632 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167834.552632 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 261759.280865 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 261759.280865 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 260108.152242 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 260108.152242 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 207651 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167297.613744 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167297.613744 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167297.613744 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 17427 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.915476 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96812686 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96812686 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9797946102 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9797946102 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9894758788 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9894758788 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 97286186 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2834928162 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2834928162 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 97286186 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 97286186 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115804.648325 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115804.648325 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 209716.312115 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 209716.312115 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115267.992891 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60679.113057 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60679.113057 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -437,13 +438,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 630779 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230141 # Transaction distribution -system.iobus.trans_dist::ReadResp 230141 # Transaction distribution +system.iobus.throughput 631746 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230149 # Transaction distribution +system.iobus.trans_dist::ReadResp 230149 # Transaction distribution system.iobus.trans_dist::WriteReq 57579 # Transaction distribution system.iobus.trans_dist::WriteResp 57579 # Transaction distribution -system.iobus.trans_dist::MessageReq 1656 # Transaction distribution -system.iobus.trans_dist::MessageResp 1656 # Transaction distribution +system.iobus.trans_dist::MessageReq 1654 # Transaction distribution +system.iobus.trans_dist::MessageResp 1654 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -463,11 +464,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578764 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -487,13 +488,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280300 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280300 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3954900 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3280356 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280356 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -529,47 +530,47 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424640038 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 421898846 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53686750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52228502 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10400792300 # number of cpu cycles simulated +system.cpu.numCycles 10385052466 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128333376 # Number of instructions committed -system.cpu.committedOps 247385531 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231978349 # Number of integer alu accesses +system.cpu.committedInsts 128336778 # Number of instructions committed +system.cpu.committedOps 247387190 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231979854 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299991 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23168967 # number of instructions that are conditional controls -system.cpu.num_int_insts 231978349 # number of integer instructions +system.cpu.num_func_calls 2299861 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23168822 # number of instructions that are conditional controls +system.cpu.num_int_insts 231979854 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434511356 # number of times the integer registers were read -system.cpu.num_int_register_writes 197852349 # number of times the integer registers were written +system.cpu.num_int_register_reads 434516750 # number of times the integer registers were read +system.cpu.num_int_register_writes 197854064 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132811982 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95533715 # number of times the CC registers were written -system.cpu.num_mem_refs 22244872 # number of memory refs -system.cpu.num_load_insts 13879055 # Number of load instructions -system.cpu.num_store_insts 8365817 # Number of store instructions -system.cpu.num_idle_cycles 9793794512.998117 # Number of idle cycles -system.cpu.num_busy_cycles 606997787.001883 # Number of busy cycles -system.cpu.not_idle_fraction 0.058361 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941639 # Percentage of idle cycles -system.cpu.Branches 26307123 # Number of branches fetched -system.cpu.op_class::No_OpClass 174810 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 224704553 90.83% 90.90% # Class of executed instruction -system.cpu.op_class::IntMult 139755 0.06% 90.96% # Class of executed instruction -system.cpu.op_class::IntDiv 123089 0.05% 91.01% # Class of executed instruction +system.cpu.num_cc_register_reads 132811657 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95534544 # number of times the CC registers were written +system.cpu.num_mem_refs 22246380 # number of memory refs +system.cpu.num_load_insts 13880618 # Number of load instructions +system.cpu.num_store_insts 8365762 # Number of store instructions +system.cpu.num_idle_cycles 9788359567.998116 # Number of idle cycles +system.cpu.num_busy_cycles 596692898.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057457 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942543 # Percentage of idle cycles +system.cpu.Branches 26306776 # Number of branches fetched +system.cpu.op_class::No_OpClass 174693 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224704760 90.83% 90.90% # Class of executed instruction +system.cpu.op_class::IntMult 139946 0.06% 90.96% # Class of executed instruction +system.cpu.op_class::IntDiv 122983 0.05% 91.01% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction @@ -596,66 +597,66 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::MemRead 13879055 5.61% 96.62% # Class of executed instruction -system.cpu.op_class::MemWrite 8365817 3.38% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13880618 5.61% 96.62% # Class of executed instruction +system.cpu.op_class::MemWrite 8365762 3.38% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247387079 # Class of executed instruction +system.cpu.op_class::total 247388762 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 791030 # number of replacements -system.cpu.icache.tags.tagsinuse 510.352813 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144579864 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791542 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.655960 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161437750250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.352813 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996783 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996783 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 794564 # number of replacements +system.cpu.icache.tags.tagsinuse 510.353610 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144580687 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 795076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 181.845115 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161037642250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.353610 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146162962 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146162962 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144579864 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144579864 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144579864 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144579864 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144579864 # number of overall hits -system.cpu.icache.overall_hits::total 144579864 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791549 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791549 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791549 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791549 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791549 # number of overall misses -system.cpu.icache.overall_misses::total 791549 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108553755 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11108553755 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11108553755 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11108553755 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11108553755 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11108553755 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145371413 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145371413 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145371413 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145371413 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145371413 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145371413 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005445 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005445 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005445 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005445 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005445 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005445 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14033.943262 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14033.943262 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14033.943262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14033.943262 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146170853 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146170853 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144580687 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144580687 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144580687 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144580687 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144580687 # number of overall hits +system.cpu.icache.overall_hits::total 144580687 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 795083 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 795083 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 795083 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 795083 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 795083 # number of overall misses +system.cpu.icache.overall_misses::total 795083 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11158319369 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11158319369 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11158319369 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11158319369 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11158319369 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11158319369 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145375770 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145375770 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145375770 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145375770 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145375770 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145375770 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005469 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005469 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005469 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005469 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005469 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005469 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.156647 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14034.156647 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14034.156647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14034.156647 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -664,88 +665,87 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791549 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791549 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791549 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791549 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791549 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791549 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9520697745 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9520697745 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9520697745 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9520697745 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9520697745 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9520697745 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005445 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005445 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005445 # mshr miss rate for overall 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(read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 795083 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 795083 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9563233631 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9563233631 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9563233631 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9563233631 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9563233631 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9563233631 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005469 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005469 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005469 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.968943 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.968943 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 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cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3511 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.067889 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7844 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3523 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.226511 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5164932679000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.067889 # Average occupied blocks per requestor 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-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7937 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7937 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 28837 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28837 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7845 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7845 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7939 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7939 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7939 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7939 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4280 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4280 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4280 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4280 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4280 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4280 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42457500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42457500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42457500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 42457500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42457500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 42457500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7847 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7847 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7847 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7847 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4381 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4381 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4381 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4381 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4381 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4381 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43773750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43773750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43773750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 43773750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43773750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 43773750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12226 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.350332 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.350332 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.350274 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.350274 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.350274 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.350274 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9919.976636 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9919.976636 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9919.976636 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9919.976636 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12228 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12228 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358335 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358335 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358276 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.358276 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358276 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.358276 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9991.725633 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9991.725633 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9991.725633 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9991.725633 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,86 +754,86 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 704 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 704 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4280 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4280 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4280 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4280 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4280 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4280 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33895500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33895500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33895500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33895500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33895500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33895500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.350332 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.350332 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.350274 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.350274 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7919.509346 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 771 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 771 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4381 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4381 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4381 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4381 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4381 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35010250 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35010250 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35010250 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35010250 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35010250 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35010250 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358335 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358335 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358276 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358276 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7991.383246 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7502 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.061351 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13282 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7516 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.767163 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5167976228000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061351 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316334 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316334 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7447 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.051866 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13273 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7461 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.778984 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163481853000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051866 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52668 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52668 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13284 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13284 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13284 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13284 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13284 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13284 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8700 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8700 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8700 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8700 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8700 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8700 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92345000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92345000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92345000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 92345000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92345000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 92345000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21984 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21984 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21984 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21984 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21984 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21984 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395742 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395742 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395742 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395742 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395742 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395742 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10614.367816 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10614.367816 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10614.367816 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10614.367816 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 52546 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52546 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13289 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13289 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13289 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13289 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13289 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13289 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8656 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8656 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8656 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8656 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8656 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8656 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91979000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91979000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91979000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 91979000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91979000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 91979000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21945 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21945 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21945 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21945 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21945 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21945 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394441 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394441 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394441 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394441 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.394441 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394441 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10626.039741 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10626.039741 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10626.039741 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10626.039741 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -842,146 +842,170 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3054 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3054 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8700 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8700 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8700 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8700 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8700 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8700 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74944500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74944500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74944500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74944500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74944500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74944500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395742 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395742 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395742 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8614.310345 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2980 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2980 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8656 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8656 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8656 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8656 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8656 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8656 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74666500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74666500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74666500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74666500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74666500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74666500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.394441 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394441 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.394441 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8625.981978 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1620643 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997078 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20036158 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1621155 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.359187 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1620883 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997130 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20027756 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1621395 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.352176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997078 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997130 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88250512 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88250512 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11993410 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11993410 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8040535 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8040535 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20033945 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20033945 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20033945 # number of overall hits -system.cpu.dcache.overall_hits::total 20033945 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308416 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308416 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314973 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314973 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623389 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623389 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623389 # number of overall misses -system.cpu.dcache.overall_misses::total 1623389 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18840132304 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18840132304 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10814294936 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10814294936 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29654427240 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29654427240 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29654427240 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29654427240 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13301826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13301826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8355508 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8355508 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21657334 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21657334 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21657334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21657334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098364 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098364 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037696 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037696 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074958 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074958 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074958 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074958 # miss rate for overall accesses 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accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11935486 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11935486 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8030839 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8030839 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59261 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59261 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19966325 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19966325 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20025586 # number of overall hits +system.cpu.dcache.overall_hits::total 20025586 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906294 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906294 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 324617 # number of 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accesses +system.cpu.dcache.demand_miss_rate::total 0.058069 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075407 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075407 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14027.410255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14027.410255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34938.776552 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34938.776552 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19542.175330 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19542.175330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14728.340128 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14728.340128 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7655 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.863014 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1537613 # number of writebacks -system.cpu.dcache.writebacks::total 1537613 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308416 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308416 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314973 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314973 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1623389 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1623389 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1623389 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1623389 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16214330696 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16214330696 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10132215064 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10132215064 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26346545760 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26346545760 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26346545760 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26346545760 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537738000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537738000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752410500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752410500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098364 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098364 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037696 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037696 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12392.335997 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12392.335997 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32168.519410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32168.519410 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1537682 # number of writebacks +system.cpu.dcache.writebacks::total 1537682 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9297 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9297 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9584 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9584 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9584 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9584 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906007 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906007 # number of ReadReq MSHR misses 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10209797624 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10209797624 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5351981750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5351981750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21103367124 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21103367124 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26455348874 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26455348874 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537257000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537257000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751929000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751929000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070552 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070552 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037738 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037738 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871535 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871535 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057617 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057617 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074963 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074963 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.714497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.714497 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32379.162831 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32379.162831 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13304.187030 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13304.187030 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17279.047400 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17279.047400 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16294.202638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16294.202638 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -989,184 +1013,185 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49146383 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2695227 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2694701 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1541371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 359480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 312780 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583085 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5973901 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18139 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7582889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50658304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203802165 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 222976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 604096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 255287541 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255266421 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 314240 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3830515500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 49844829 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2698695 # Transaction distribution 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Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3051756740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3051993102 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6421000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6572250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13050250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 12984250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 86651 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64733.611120 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3487942 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151340 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.047060 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87211 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64746.136544 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3491181 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151954 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.975249 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50209.763854 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.027833 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3434.458363 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11089.219598 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.766140 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50332.685507 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141265 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3220.709839 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11192.593518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768016 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64743 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4651 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57056 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987900 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32212608 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32212608 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6366 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2878 # number of ReadReq hits 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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.064039 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60525.341356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.252496 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61869.631828 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.679245 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.679245 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56692.990024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56692.990024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 8539a1890..403e6b21a 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu sim_ticks 200409284500 # Number of ticks simulated final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 14275836 # Simulator instruction rate (inst/s) -host_op_rate 14275831 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5462126987 # Simulator tick rate (ticks/s) -host_mem_usage 513712 # Number of bytes of host memory used -host_seconds 36.69 # Real time elapsed on the host +host_inst_rate 23274047 # Simulator instruction rate (inst/s) +host_op_rate 23274036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8904961694 # Simulator tick rate (ticks/s) +host_mem_usage 483300 # Number of bytes of host memory used +host_seconds 22.51 # Real time elapsed on the host sim_insts 523790075 # Number of instructions simulated sim_ops 523790075 # Number of ops (including micro ops) simulated testsys.voltage_domain.voltage 1 # Voltage in Volts @@ -114,10 +114,10 @@ testsys.cpu.not_idle_fraction 0.050555 # Pe testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles testsys.cpu.Branches 2929848 # Number of branches fetched testsys.cpu.op_class::No_OpClass 712819 3.52% 3.52% # Class of executed instruction -testsys.cpu.op_class::IntAlu 12147340 59.95% 63.47% # Class of executed instruction +testsys.cpu.op_class::IntAlu 12147338 59.95% 63.47% # Class of executed instruction testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatAdd 4653 0.02% 63.60% # Class of executed instruction +testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction @@ -372,10 +372,10 @@ drivesys.cpu.not_idle_fraction 0.023766 # Pe drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles drivesys.cpu.Branches 2793313 # Number of branches fetched drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction -drivesys.cpu.op_class::IntAlu 11538630 60.57% 63.84% # Class of executed instruction +drivesys.cpu.op_class::IntAlu 11538627 60.57% 63.84% # Class of executed instruction drivesys.cpu.op_class::IntMult 20663 0.11% 63.95% # Class of executed instruction drivesys.cpu.op_class::IntDiv 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatAdd 138 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatAdd 141 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction drivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction @@ -525,11 +525,11 @@ sim_seconds 0.000407 # Nu sim_ticks 407341500 # Number of ticks simulated final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 7312019890 # Simulator instruction rate (inst/s) -host_op_rate 7310591323 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5683411932 # Simulator tick rate (ticks/s) -host_mem_usage 513712 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 11799945954 # Simulator instruction rate (inst/s) +host_op_rate 11797124974 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9171074905 # Simulator tick rate (ticks/s) +host_mem_usage 483300 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 523862353 # Number of instructions simulated sim_ops 523862353 # Number of ops (including micro ops) simulated testsys.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1f269f774..f7bb9a203 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21025000 # Number of ticks simulated -final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20537500 # Number of ticks simulated +final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63804 # Simulator instruction rate (inst/s) -host_op_rate 63793 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 210460029 # Simulator tick rate (ticks/s) -host_mem_usage 221600 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 46749 # Simulator instruction rate (inst/s) +host_op_rate 46745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 150649735 # Simulator tick rate (ticks/s) +host_mem_usage 236424 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,40 +21,40 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 488 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 975386488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 542227632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1517614121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975386488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975386488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975386488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 542227632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1517614121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 487 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 487 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 31168 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side +system.physmem.bytesReadSys 31168 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 69 # Per bank write bursts -system.physmem.perBankRdBursts::1 34 # Per bank write bursts +system.physmem.perBankRdBursts::1 33 # Per bank write bursts system.physmem.perBankRdBursts::2 32 # Per bank write bursts system.physmem.perBankRdBursts::3 47 # Per bank write bursts -system.physmem.perBankRdBursts::4 43 # Per bank write bursts -system.physmem.perBankRdBursts::5 21 # Per bank write bursts +system.physmem.perBankRdBursts::4 42 # Per bank write bursts +system.physmem.perBankRdBursts::5 20 # Per bank write bursts system.physmem.perBankRdBursts::6 1 # Per bank write bursts system.physmem.perBankRdBursts::7 3 # Per bank write bursts system.physmem.perBankRdBursts::8 0 # Per bank write bursts system.physmem.perBankRdBursts::9 1 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts -system.physmem.perBankRdBursts::11 24 # Per bank write bursts +system.physmem.perBankRdBursts::11 25 # Per bank write bursts system.physmem.perBankRdBursts::12 14 # Per bank write bursts -system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::13 120 # Per bank write bursts system.physmem.perBankRdBursts::14 45 # Per bank write bursts system.physmem.perBankRdBursts::15 12 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20992000 # Total gap between requests +system.physmem.totGap 20412000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 488 # Read request sizes (log2) +system.physmem.readPktSize::6 487 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 222.888418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.838248 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22 27.85% 27.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 22.78% 50.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 4169250 # Total ticks spent queuing -system.physmem.totMemAccLat 13319250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8543.55 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.853659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 204.819475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.253502 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 34.15% 34.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 20.73% 54.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 10.98% 65.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 9.76% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 4.88% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.22% 81.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation +system.physmem.totQLat 4551750 # Total ticks spent queuing +system.physmem.totMemAccLat 13683000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9346.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27293.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28096.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.61 # Data bus utilization in percentage -system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.86 # Data bus utilization in percentage +system.physmem.busUtilRead 11.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 394 # Number of row buffer hits during reads +system.physmem.readRowHits 390 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43016.39 # Average gap between requests -system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined +system.physmem.avgGap 41913.76 # Average gap between requests +system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 22000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15304250 # Time in different power states +system.physmem.memoryStateTime::ACT 15339250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1482425684 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 416 # Transaction distribution +system.membus.throughput 1517614121 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 415 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2922 # Number of BP lookups -system.cpu.branchPred.condPredicted 1714 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 512 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2236 # Number of BTB lookups -system.cpu.branchPred.BTBHits 763 # Number of BTB hits +system.cpu.branchPred.lookups 2806 # Number of BP lookups +system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups +system.cpu.branchPred.BTBHits 686 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.123435 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 417 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2080 # DTB read hits -system.cpu.dtb.read_misses 47 # DTB read misses +system.cpu.dtb.read_hits 2085 # DTB read hits +system.cpu.dtb.read_misses 55 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2127 # DTB read accesses -system.cpu.dtb.write_hits 1064 # DTB write hits -system.cpu.dtb.write_misses 31 # DTB write misses +system.cpu.dtb.read_accesses 2140 # DTB read accesses +system.cpu.dtb.write_hits 1069 # DTB write hits +system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1095 # DTB write accesses -system.cpu.dtb.data_hits 3144 # DTB hits -system.cpu.dtb.data_misses 78 # DTB misses +system.cpu.dtb.write_accesses 1099 # DTB write accesses +system.cpu.dtb.data_hits 3154 # DTB hits +system.cpu.dtb.data_misses 85 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3222 # DTB accesses -system.cpu.itb.fetch_hits 2403 # ITB hits -system.cpu.itb.fetch_misses 39 # ITB misses +system.cpu.dtb.data_accesses 3239 # DTB accesses +system.cpu.itb.fetch_hits 2196 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2442 # ITB accesses +system.cpu.itb.fetch_accesses 2234 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,238 +285,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42051 # number of cpu cycles simulated +system.cpu.numCycles 41076 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8528 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16754 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2922 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2995 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1927 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1100 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8744 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16221 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2806 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1081 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4165 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2403 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 389 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14718 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.138334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.533627 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 801 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2196 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14255 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137917 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547719 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11723 79.65% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 324 2.20% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.59% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 214 1.45% 84.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.73% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 243 1.65% 88.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.79% 90.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 187 1.27% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1274 8.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11405 80.01% 80.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 289 2.03% 82.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 215 1.51% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 201 1.41% 84.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 243 1.70% 86.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 210 1.47% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 240 1.68% 89.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 179 1.26% 91.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1273 8.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14718 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.069487 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.398421 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9297 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1311 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2827 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1242 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 247 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15491 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1242 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9496 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2672 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 534 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14802 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 481 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11114 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18470 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18461 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14255 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.068312 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.394902 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8821 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2387 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2410 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 194 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 229 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14785 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8987 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1032 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 429 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2422 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 942 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14195 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 42 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 850 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10723 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17814 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17805 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6544 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 484 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1358 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6153 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 504 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2660 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1309 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13092 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10822 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 61 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6316 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14718 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.735290 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.419888 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10718 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6142 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3483 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14255 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.751877 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.485144 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10506 71.38% 71.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1362 9.25% 80.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 966 6.56% 87.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 797 5.42% 92.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 583 3.96% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 288 1.96% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 161 1.09% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 41 0.28% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10249 71.90% 71.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1278 8.97% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 900 6.31% 87.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 686 4.81% 91.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 522 3.66% 95.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 330 2.31% 97.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 212 1.49% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.36% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14718 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14255 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 18 15.38% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 61 52.14% 67.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 32.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 30 20.69% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 50.34% 71.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 42 28.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7283 67.30% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2401 22.19% 89.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1133 10.47% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7258 67.72% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2331 21.75% 89.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1124 10.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10822 # Type of FU issued -system.cpu.iq.rate 0.257354 # Inst issue rate -system.cpu.iq.fu_busy_cnt 117 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010811 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36519 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19441 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9646 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10718 # Type of FU issued +system.cpu.iq.rate 0.260931 # Inst issue rate +system.cpu.iq.fu_busy_cnt 145 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013529 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35836 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19060 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9783 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10926 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10850 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 74 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1607 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 493 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1477 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 444 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 138 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1242 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 105 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13210 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1358 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 383 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10117 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2138 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 705 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1002 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12999 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2660 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1309 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 470 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10224 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2143 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3235 # number of memory reference insts executed -system.cpu.iew.exec_branches 1594 # Number of branches executed -system.cpu.iew.exec_stores 1097 # Number of stores executed -system.cpu.iew.exec_rate 0.240589 # Inst execution rate -system.cpu.iew.wb_sent 9800 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9656 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5168 # num instructions producing a value -system.cpu.iew.wb_consumers 7004 # num instructions consuming a value +system.cpu.iew.exec_refs 3244 # number of memory reference insts executed +system.cpu.iew.exec_branches 1603 # Number of branches executed +system.cpu.iew.exec_stores 1101 # Number of stores executed +system.cpu.iew.exec_rate 0.248904 # Inst execution rate +system.cpu.iew.wb_sent 9953 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9793 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5300 # num instructions producing a value +system.cpu.iew.wb_consumers 7279 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.229626 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737864 # average fanout of values written-back +system.cpu.iew.wb_rate 0.238412 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.728122 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6822 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6609 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13476 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.474102 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.366169 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.489541 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.404135 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10977 81.46% 81.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1202 8.92% 90.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 500 3.71% 94.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 222 1.65% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 141 1.05% 96.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 79 0.59% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 99 0.73% 98.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 80 0.59% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 176 1.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10600 81.22% 81.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1162 8.90% 90.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 501 3.84% 93.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 211 1.62% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 133 1.02% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 75 0.57% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 89 0.68% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 89 0.68% 98.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 191 1.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13051 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -562,94 +561,94 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction -system.cpu.commit.bw_lim_events 176 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 191 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26160 # The number of ROB reads -system.cpu.rob.rob_writes 27673 # The number of ROB writes -system.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25507 # The number of ROB reads +system.cpu.rob.rob_writes 27214 # The number of ROB writes +system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26821 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12844 # number of integer regfile reads -system.cpu.int_regfile_writes 7306 # number of integer regfile writes +system.cpu.cpi 6.446328 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads +system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12991 # number of integer regfile reads +system.cpu.int_regfile_writes 7455 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 417 # Transaction distribution +system.cpu.toL2Bus.throughput 1520730371 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.493349 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1913 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.092357 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.471338 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.493349 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077878 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077878 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.374396 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077331 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077331 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5120 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5120 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1913 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1913 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1913 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1913 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1913 # number of overall hits -system.cpu.icache.overall_hits::total 1913 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses -system.cpu.icache.overall_misses::total 490 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31404750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31404750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31404750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31404750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31404750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31404750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2403 # number of demand (read+write) accesses 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of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2196 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2196 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2196 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2196 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2196 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2196 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217668 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.217668 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.217668 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.217668 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.217668 # miss rate for overall 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13324500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35315000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21990500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13324500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35315000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 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miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69167.197452 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76465.686275 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70956.730769 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74843.750000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74843.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency 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ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6661250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24704250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4522750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4522750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11184000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29227000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11184000 # number of overall MSHR miss cycles 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mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62579.861111 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56576.433121 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63518.678161 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59051.741803 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56576.433121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63518.678161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59051.741803 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57645.367412 # average ReadReq mshr miss latency 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blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026192 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026192 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5696 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5696 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1725 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1725 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2231 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2231 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2231 # number of overall hits -system.cpu.dcache.overall_hits::total 2231 # number of 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0.184062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.900000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses @@ -907,30 +906,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7909000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7909000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5463750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5463750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13372750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13372750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13372750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13372750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053797 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053797 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77539.215686 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77539.215686 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75885.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75885.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 477ffe800..a87953c0f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11975500 # Number of ticks simulated -final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11765500 # Number of ticks simulated +final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10130 # Simulator instruction rate (inst/s) -host_op_rate 10129 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50814142 # Simulator tick rate (ticks/s) -host_mem_usage 221260 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 45706 # Simulator instruction rate (inst/s) +host_op_rate 45696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 225189511 # Simulator tick rate (ticks/s) +host_mem_usage 236100 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 17472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 17408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1004717966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 454260782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1458978748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1004717966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1004717966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1004717966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 454260782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1458978748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 273 # Number of read requests accepted +system.physmem.num_reads::total 272 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017211338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 462368790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479580128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017211338 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017211338 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017211338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 462368790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479580128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 17472 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 17408 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 17472 # Total read bytes from the system interface side +system.physmem.bytesReadSys 17408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -49,12 +49,12 @@ system.physmem.perBankRdBursts::4 18 # Pe system.physmem.perBankRdBursts::5 0 # Per bank write bursts system.physmem.perBankRdBursts::6 24 # Per bank write bursts system.physmem.perBankRdBursts::7 37 # Per bank write bursts -system.physmem.perBankRdBursts::8 61 # Per bank write bursts +system.physmem.perBankRdBursts::8 60 # Per bank write bursts system.physmem.perBankRdBursts::9 2 # Per bank write bursts -system.physmem.perBankRdBursts::10 14 # Per bank write bursts +system.physmem.perBankRdBursts::10 15 # Per bank write bursts system.physmem.perBankRdBursts::11 9 # Per bank write bursts system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::13 50 # Per bank write bursts system.physmem.perBankRdBursts::14 12 # Per bank write bursts system.physmem.perBankRdBursts::15 1 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11886000 # Total gap between requests +system.physmem.totGap 11676000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 273 # Read request sizes (log2) +system.physmem.readPktSize::6 272 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.368421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 224.223359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 366.580725 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14 36.84% 36.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5 13.16% 50.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 10.53% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 5.26% 65.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.26% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 5.26% 76.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 5.26% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.63% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 15.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38 # Bytes accessed per row activation -system.physmem.totQLat 2067500 # Total ticks spent queuing -system.physmem.totMemAccLat 7186250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7573.26 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 39 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 379.076923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 220.895953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 363.044972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 33.33% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7 17.95% 51.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3 7.69% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 7.69% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 5.13% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 7.69% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 2.56% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation +system.physmem.totQLat 1710500 # Total ticks spent queuing +system.physmem.totMemAccLat 6810500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6288.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26323.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1458.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25038.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1458.98 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.40 # Data bus utilization in percentage -system.physmem.busUtilRead 11.40 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.56 # Data bus utilization in percentage +system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 225 # Number of row buffer hits during reads +system.physmem.readRowHits 223 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43538.46 # Average gap between requests -system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined +system.physmem.avgGap 42926.47 # Average gap between requests +system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 22000 # Time in different power states system.physmem.memoryStateTime::REF 260000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7796750 # Time in different power states +system.physmem.memoryStateTime::ACT 7778000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1458978748 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 249 # Transaction distribution -system.membus.trans_dist::ReadResp 249 # Transaction distribution +system.membus.throughput 1479580128 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 546 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17472 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17408 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2554750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 1179 # Number of BP lookups -system.cpu.branchPred.condPredicted 620 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups -system.cpu.branchPred.BTBHits 254 # Number of BTB hits +system.cpu.branchPred.lookups 1090 # Number of BP lookups +system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 734 # Number of BTB lookups +system.cpu.branchPred.BTBHits 202 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.513648 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 712 # DTB read hits -system.cpu.dtb.read_misses 31 # DTB read misses +system.cpu.dtb.read_hits 689 # DTB read hits +system.cpu.dtb.read_misses 23 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 743 # DTB read accesses -system.cpu.dtb.write_hits 368 # DTB write hits -system.cpu.dtb.write_misses 20 # DTB write misses +system.cpu.dtb.read_accesses 712 # DTB read accesses +system.cpu.dtb.write_hits 352 # DTB write hits +system.cpu.dtb.write_misses 18 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 388 # DTB write accesses -system.cpu.dtb.data_hits 1080 # DTB hits -system.cpu.dtb.data_misses 51 # DTB misses +system.cpu.dtb.write_accesses 370 # DTB write accesses +system.cpu.dtb.data_hits 1041 # DTB hits +system.cpu.dtb.data_misses 41 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1131 # DTB accesses -system.cpu.itb.fetch_hits 1070 # ITB hits -system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.dtb.data_accesses 1082 # DTB accesses +system.cpu.itb.fetch_hits 938 # ITB hits +system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1100 # ITB accesses +system.cpu.itb.fetch_accesses 964 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,237 +285,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23952 # number of cpu cycles simulated +system.cpu.numCycles 23532 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7041 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1179 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 466 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1215 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 516 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4442 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6549 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1090 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 401 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1376 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1070 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.913704 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.320621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 938 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 155 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.908196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.330561 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6491 84.23% 84.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.69% 84.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117 1.52% 86.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 96 1.25% 87.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 176 2.28% 89.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 76 0.99% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.83% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 66 0.86% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 567 7.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6093 84.50% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 49 0.68% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 123 1.71% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 84 1.16% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 131 1.82% 89.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 58 0.80% 90.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 67 0.93% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 62 0.86% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 544 7.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049223 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.293963 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5479 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 562 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1164 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 497 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6225 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 497 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5576 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 257 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 7211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.046320 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.278302 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5244 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 757 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 975 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 55 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 180 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 156 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 5674 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 180 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5327 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 452 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1068 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 28 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5913 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 4287 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6690 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6683 # Number of integer rename lookups +system.cpu.rename.RunCycles 942 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 30 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5438 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3913 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6138 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6131 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2519 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2145 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 93 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4974 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 115 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 883 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4685 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4048 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2349 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1396 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3891 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2057 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1216 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7706 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.525305 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.241065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.539592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.280898 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6082 78.93% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 198 2.57% 97.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.57% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48 0.62% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5712 79.21% 79.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 492 6.82% 86.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 353 4.90% 90.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 253 3.51% 94.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 197 2.73% 97.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 1.68% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 52 0.72% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19 0.26% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7211 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2866 70.80% 70.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 786 19.42% 90.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 395 9.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2776 71.34% 71.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 739 18.99% 90.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 375 9.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4048 # Type of FU issued -system.cpu.iq.rate 0.169005 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010870 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15887 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7327 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3891 # Type of FU issued +system.cpu.iq.rate 0.165349 # Inst issue rate +system.cpu.iq.fu_busy_cnt 51 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013107 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15045 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6745 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3580 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4085 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3935 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 468 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 176 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 497 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 231 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5316 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 180 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 393 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5027 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 883 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3860 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 744 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 188 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 22 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 169 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 191 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3755 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 713 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 136 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 336 # number of nop insts executed -system.cpu.iew.exec_refs 1132 # number of memory reference insts executed -system.cpu.iew.exec_branches 644 # Number of branches executed -system.cpu.iew.exec_stores 388 # Number of stores executed -system.cpu.iew.exec_rate 0.161156 # Inst execution rate -system.cpu.iew.wb_sent 3742 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3661 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1713 # num instructions producing a value -system.cpu.iew.wb_consumers 2215 # num instructions consuming a value +system.cpu.iew.exec_refs 1083 # number of memory reference insts executed +system.cpu.iew.exec_branches 638 # Number of branches executed +system.cpu.iew.exec_stores 370 # Number of stores executed +system.cpu.iew.exec_rate 0.159570 # Inst execution rate +system.cpu.iew.wb_sent 3650 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3586 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1711 # num instructions producing a value +system.cpu.iew.wb_consumers 2190 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152847 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.773363 # average fanout of values written-back +system.cpu.iew.wb_rate 0.152388 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.781279 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2734 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2437 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.357331 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.199884 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 157 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6757 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.381234 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.252230 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6340 87.95% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 25 0.35% 99.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5909 87.45% 87.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193 2.86% 90.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 297 4.40% 94.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 108 1.60% 96.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.07% 97.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.78% 98.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.49% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22 0.33% 98.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70 1.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6757 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -561,182 +560,182 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12209 # The number of ROB reads -system.cpu.rob.rob_writes 11130 # The number of ROB writes -system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16246 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11453 # The number of ROB reads +system.cpu.rob.rob_writes 10498 # The number of ROB writes +system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16321 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads -system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4675 # number of integer regfile reads -system.cpu.int_regfile_writes 2829 # number of integer regfile writes +system.cpu.cpi 9.858400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.858400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.101436 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.101436 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4543 # number of integer regfile reads +system.cpu.int_regfile_writes 2774 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1458978748 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution +system.cpu.toL2Bus.throughput 1479580128 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 546 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 316750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 93.052678 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 820 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.361702 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.663102 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 93.052678 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.091797 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2328 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2328 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 820 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 820 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 820 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 820 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 820 # number of overall hits -system.cpu.icache.overall_hits::total 820 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses 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+system.cpu.l2cache.demand_avg_miss_latency::total 69301.470588 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69301.470588 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,28 +766,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of 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MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1398750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5100750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15449500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5100750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15449500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -800,97 +799,97 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56105.053191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64016.393443 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58043.172691 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58062.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58062.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use 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overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63615.384615 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63615.384615 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65481.481481 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65481.481481 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64378.787879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64378.787879 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 111 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -899,30 +898,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6426500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6426500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6230250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6230250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6230250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6230250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.088819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.088819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77262.295082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77262.295082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75605.882353 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75605.882353 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75605.882353 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75605.882353 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71572.916667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71572.916667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index e6065a0ab..65ff8dd3e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,532 +1,51 @@ ---------- Begin Simulation Statistics ---------- -final_tick 27963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 75358 # Simulator instruction rate (inst/s) -host_mem_usage 292860 # Number of bytes of host memory used -host_op_rate 93985 # Simulator op (including micro ops) rate (op/s) -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 457698243 # Simulator tick rate (ticks/s) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27911000 # Number of ticks simulated +final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 66829 # Simulator instruction rate (inst/s) +host_op_rate 78212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 404876453 # Simulator tick rate (ticks/s) +host_mem_usage 278412 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated -sim_ops 5742 # Number of ops (including micro ops) simulated -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27963000 # Number of ticks simulated +sim_ops 5390 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 21.219512 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 348 # Number of BTB hits -system.cpu.branchPred.BTBLookups 1640 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 1370 # Number of conditional branches predicted -system.cpu.branchPred.lookups 2005 # Number of BP lookups -system.cpu.branchPred.usedRAS 202 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 4604 # Number of instructions committed -system.cpu.committedOps 5742 # Number of ops (including micro ops) committed -system.cpu.cpi 12.147263 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 1318 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1318 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60367.304348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60367.304348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60667.563107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60667.563107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 1203 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1203 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6942240 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6942240 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.087253 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087253 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6248759 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6248759 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.078149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.078149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.179104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.179104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66843.023256 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66843.023256 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4600500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4600500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2874250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2874250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2231 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63421.648352 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63421.648352 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62486.363014 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62486.363014 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 2049 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2049 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 11542740 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11542740 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.081578 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081578 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9123009 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9123009 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.065442 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.065442 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 2231 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2231 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63421.648352 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63421.648352 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62486.363014 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62486.363014 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 2049 # number of overall hits -system.cpu.dcache.overall_hits::total 2049 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 11542740 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11542740 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.081578 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081578 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses -system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9123009 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9123009 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.065442 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.065442 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 14.184932 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 4652 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 86.831207 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.021199 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021199 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 4652 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 86.831207 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2071 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.discardedOps 1297 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 2307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66806.250000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66806.250000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64396.875000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64396.875000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 1987 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1987 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21378000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21378000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138708 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138708 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 320 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 320 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20607000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20607000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138708 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 320 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 320 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 2307 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2307 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66806.250000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66806.250000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64396.875000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64396.875000 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 1987 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1987 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 21378000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21378000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.138708 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138708 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 320 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 320 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20607000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20607000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138708 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 320 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 2307 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2307 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66806.250000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66806.250000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64396.875000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64396.875000 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 1987 # number of overall hits -system.cpu.icache.overall_hits::total 1987 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 21378000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21378000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.138708 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138708 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 320 # number of overall misses -system.cpu.icache.overall_misses::total 320 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20607000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20607000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138708 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 320 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 320 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 6.209375 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 4934 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 161.718196 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078964 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078964 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.sampled_refs 320 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 4934 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 161.718196 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1987 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 44980 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.082323 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65831.395349 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65831.395349 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53308.139535 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53308.139535 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2830750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2830750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2292250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2292250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 423 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 423 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67507.124352 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67507.124352 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55150.530504 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55150.530504 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 37 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26057750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26057750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.912530 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.912530 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20791750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891253 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.891253 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 466 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 466 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67339.160839 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67339.160839 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54961.904762 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54961.904762 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 28888500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28888500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.920601 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.920601 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23084000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23084000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.901288 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901288 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67339.160839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67339.160839 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54961.904762 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54961.904762 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits -system.cpu.l2cache.overall_hits::total 37 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 28888500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28888500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.920601 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.920601 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses -system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23084000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23084000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.901288 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901288 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 0.098143 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 4148 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.926239 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005979 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005979 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 4148 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 195.926239 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 37 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 55926 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 10946 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 29824 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 233000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 545500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234491 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 1066552230 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 423 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 423 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 26880 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3923500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 961270250 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 377 # Transaction distribution -system.membus.trans_dist::ReadResp 377 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 66375.00 # Average gap between requests -system.physmem.avgMemAccLat 24369.64 # Average memory access latency per DRAM burst -system.physmem.avgQLat 5619.64 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 961.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 961.27 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 7.51 # Data bus utilization in percentage -system.physmem.busUtilRead 7.51 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 695776562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 695776562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 961270250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 961270250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 961270250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 961270250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 389.907692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 267.054058 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.238562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 16.92% 16.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 26.15% 43.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 18.46% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 10.77% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.62% 76.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.08% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.62% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation +system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory +system.physmem.bytes_read::total 26880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory +system.physmem.num_reads::total 420 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 420 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory -system.physmem.bytes_read::total 26880 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 12000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22869500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory -system.physmem.num_reads::total 420 # Number of read requests responded to by this memory -system.physmem.pageHitRate 82.62 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.perBankRdBursts::0 91 # Per bank write bursts system.physmem.perBankRdBursts::1 51 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 42 # Per bank write bursts -system.physmem.perBankRdBursts::4 22 # Per bank write bursts +system.physmem.perBankRdBursts::4 23 # Per bank write bursts system.physmem.perBankRdBursts::5 41 # Per bank write bursts system.physmem.perBankRdBursts::6 36 # Per bank write bursts system.physmem.perBankRdBursts::7 12 # Per bank write bursts -system.physmem.perBankRdBursts::8 6 # Per bank write bursts +system.physmem.perBankRdBursts::8 5 # Per bank write bursts system.physmem.perBankRdBursts::9 6 # Per bank write bursts system.physmem.perBankRdBursts::10 27 # Per bank write bursts system.physmem.perBankRdBursts::11 42 # Per bank write bursts @@ -550,8 +69,25 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 27825500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 420 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -582,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 420 # Read request sizes (log2) -system.physmem.readReqs 420 # Number of read requests accepted -system.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads -system.physmem.readRowHits 347 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers -system.physmem.totGap 27877500 # Total gap between requests -system.physmem.totMemAccLat 10235250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 2360250 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -662,17 +182,497 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation +system.physmem.totQLat 2525000 # Total ticks spent queuing +system.physmem.totMemAccLat 10400000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6011.90 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24761.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.52 # Data bus utilization in percentage +system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 66251.19 # Average gap between requests +system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 963061159 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 377 # Transaction distribution +system.membus.trans_dist::ReadResp 377 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26880 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 1905 # Number of BP lookups +system.cpu.branchPred.condPredicted 1139 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1574 # Number of BTB lookups +system.cpu.branchPred.BTBHits 325 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 20.648030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 223 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.numCycles 55822 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 4604 # Number of instructions committed +system.cpu.committedOps 5390 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 12.124674 # CPI: cycles per instruction +system.cpu.ipc 0.082476 # IPC: instructions per cycle +system.cpu.tickCycles 10535 # Number of cycles that the object actually ticked +system.cpu.idleCycles 45287 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 162.198888 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1923 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.990654 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 162.198888 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079199 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079199 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4809 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4809 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1923 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1923 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1923 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1923 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1923 # number of overall hits +system.cpu.icache.overall_hits::total 1923 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses +system.cpu.icache.overall_misses::total 321 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21494250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21494250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21494250 # number of demand (read+write) miss cycles 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Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1070832288 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 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420 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20973000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20973000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23257000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23257000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23257000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23257000 # number of overall MSHR miss cycles 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 86.663656 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.021158 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021158 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses 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# number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63435.390110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63435.390110 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6265258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6265258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9132258 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9132258 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9132258 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9132258 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index d39b9c7ba..a4baa9644 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16786000 # Number of ticks simulated -final_tick 16786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16223000 # Number of ticks simulated +final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36444 # Simulator instruction rate (inst/s) -host_op_rate 45472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133219523 # Simulator tick rate (ticks/s) -host_mem_usage 259336 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 32617 # Simulator instruction rate (inst/s) +host_op_rate 38195 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115221437 # Simulator tick rate (ticks/s) +host_mem_usage 253076 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated -sim_ops 5729 # Number of ops (including micro ops) simulated +sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1029429286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 465149529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1494578816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1029429286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1029429286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1029429286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 465149529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1494578816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.num_reads::total 397 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::0 90 # Per bank write bursts system.physmem.perBankRdBursts::1 46 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 42 # Per bank write bursts -system.physmem.perBankRdBursts::4 17 # Per bank write bursts -system.physmem.perBankRdBursts::5 33 # Per bank write bursts +system.physmem.perBankRdBursts::3 43 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 32 # Per bank write bursts system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16721500 # Total gap between requests +system.physmem.totGap 16156000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.readPktSize::6 397 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,72 +186,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.387097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.062800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.835382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 27.42% 45.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.90% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.29% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.23% 72.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 8.06% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.61% 87.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 3300000 # Total ticks spent queuing -system.physmem.totMemAccLat 10650000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8418.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 2970000 # Total ticks spent queuing +system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27168.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1494.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1494.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.68 # Data bus utilization in percentage -system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads +system.physmem.busUtil 12.24 # Data bus utilization in percentage +system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 326 # Number of row buffer hits during reads +system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42656.89 # Average gap between requests -system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined +system.physmem.avgGap 40695.21 # Average gap between requests +system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1494578816 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 350 # Transaction distribution -system.membus.trans_dist::ReadResp 350 # Transaction distribution +system.membus.throughput 1566171485 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 355 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 784 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25088 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25088 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25408 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 479500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3655500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2517 # Number of BP lookups -system.cpu.branchPred.condPredicted 1805 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2002 # Number of BTB lookups -system.cpu.branchPred.BTBHits 714 # Number of BTB hits +system.cpu.branchPred.lookups 2638 # Number of BP lookups +system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 783 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.664336 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 294 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,7 +336,7 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.numCycles 5742 # number of cpu cycles simulated +system.cpu.checker.numCycles 5390 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -424,489 +423,491 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 33573 # number of cpu cycles simulated +system.cpu.numCycles 32447 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6921 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1008 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2659 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2378 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.162808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.572483 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10430 79.69% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.73% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.55% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 238 1.82% 84.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 231 1.76% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.06% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 93 0.71% 89.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.11% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1254 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.074971 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.359604 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6910 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2688 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2492 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 31 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 385 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13358 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 539 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7139 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 151 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2277 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2296 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 258 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12614 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 195 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 12625 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57590 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 52228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 47 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6952 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 41 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 329 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2826 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1583 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11316 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8961 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 149 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14803 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.684621 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.402607 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2145 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2064 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9594 73.30% 73.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1210 9.24% 82.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 823 6.29% 88.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 494 3.77% 92.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 3.66% 96.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 298 2.28% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 131 1.00% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 49 0.37% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.71% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.44% 65.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 34.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5369 59.92% 59.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2357 26.30% 86.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8961 # Type of FU issued -system.cpu.iq.rate 0.266911 # Inst issue rate -system.cpu.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31345 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16624 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8077 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9162 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 8358 # Type of FU issued +system.cpu.iq.rate 0.257589 # Inst issue rate +system.cpu.iq.fu_busy_cnt 169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1626 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 645 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11366 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2826 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1583 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 266 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 376 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8568 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 393 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3332 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed -system.cpu.iew.exec_stores 1172 # Number of stores executed -system.cpu.iew.exec_rate 0.255205 # Inst execution rate -system.cpu.iew.wb_sent 8256 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8093 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3919 # num instructions producing a value -system.cpu.iew.wb_consumers 8062 # num instructions consuming a value +system.cpu.iew.exec_nop 11 # number of nop insts executed +system.cpu.iew.exec_refs 3148 # number of memory reference insts executed +system.cpu.iew.exec_branches 1457 # Number of branches executed +system.cpu.iew.exec_stores 1240 # Number of stores executed +system.cpu.iew.exec_rate 0.248498 # Inst execution rate +system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7601 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3572 # num instructions producing a value +system.cpu.iew.wb_consumers 6998 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.241057 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.486108 # average fanout of values written-back +system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5642 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.472651 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.325156 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9924 81.87% 81.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 978 8.07% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.32% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 224 1.85% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 175 1.44% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.75% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.41% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.27% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 123 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12121 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2138 # Number of memory references committed -system.cpu.commit.loads 1200 # Number of loads committed +system.cpu.commit.refs 1965 # Number of memory references committed +system.cpu.commit.loads 1027 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed system.cpu.commit.branches 1007 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4976 # Number of committed integer instructions. +system.cpu.commit.int_insts 4624 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5729 # Class of committed instruction -system.cpu.commit.bw_lim_events 123 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 5377 # Class of committed instruction +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23212 # The number of ROB reads -system.cpu.rob.rob_writes 23723 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20484 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22692 # The number of ROB reads +system.cpu.rob.rob_writes 21719 # The number of ROB writes +system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.312786 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.312786 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136747 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136747 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39407 # number of integer regfile reads -system.cpu.int_regfile_writes 7992 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 3253 # number of misc regfile reads +system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads +system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7944 # number of integer regfile reads +system.cpu.int_regfile_writes 4420 # number of integer regfile writes +system.cpu.fp_regfile_reads 31 # number of floating regfile reads +system.cpu.cc_regfile_reads 28734 # number of cc regfile reads +system.cpu.cc_regfile_writes 3302 # number of cc regfile writes +system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1662337662 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 394 # Transaction distribution +system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 870 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27712 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 480500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) +system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 148.488883 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1601 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.520690 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 148.488883 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.141113 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4226 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4226 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits -system.cpu.icache.overall_hits::total 1601 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses -system.cpu.icache.overall_misses::total 367 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23960000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23960000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23960000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23960000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23960000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23960000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186484 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186484 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186484 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186484 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186484 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186484 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65286.103542 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65286.103542 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65286.103542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65286.103542 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4430 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits +system.cpu.icache.overall_hits::total 1666 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses +system.cpu.icache.overall_misses::total 402 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 53.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19152500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19152500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19152500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19152500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19152500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19152500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147358 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.147358 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.147358 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66043.103448 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66043.103448 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66043.103448 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66043.103448 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66043.103448 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66043.103448 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 185.364644 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 37 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.105714 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.907401 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.457243 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004239 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001418 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005657 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3864 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3864 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 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number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits +system.cpu.dcache.overall_hits::total 2146 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 507 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 507 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 507 # number of overall misses -system.cpu.dcache.overall_misses::total 507 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20684250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20684250 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32297743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32297743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32297743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32297743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses +system.cpu.dcache.overall_misses::total 521 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2885 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2885 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2885 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2885 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.096349 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175737 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175737 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175737 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175737 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65250 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65250 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63703.635108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63703.635108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 118 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -1071,30 +1072,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6871755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6871755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3151750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3151750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10023505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10023505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.050953 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.050953 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 4a87577c2..adfd7b504 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16786000 # Number of ticks simulated -final_tick 16786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16223000 # Number of ticks simulated +final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42967 # Simulator instruction rate (inst/s) -host_op_rate 53611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 157060125 # Simulator tick rate (ticks/s) -host_mem_usage 258920 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 35590 # Simulator instruction rate (inst/s) +host_op_rate 41676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 125719954 # Simulator tick rate (ticks/s) +host_mem_usage 252016 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated -sim_ops 5729 # Number of ops (including micro ops) simulated +sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1029429286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 465149529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1494578816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1029429286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1029429286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1029429286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 465149529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1494578816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.num_reads::total 397 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::0 90 # Per bank write bursts system.physmem.perBankRdBursts::1 46 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 42 # Per bank write bursts -system.physmem.perBankRdBursts::4 17 # Per bank write bursts -system.physmem.perBankRdBursts::5 33 # Per bank write bursts +system.physmem.perBankRdBursts::3 43 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 32 # Per bank write bursts system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16721500 # Total gap between requests +system.physmem.totGap 16156000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.readPktSize::6 397 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,72 +186,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.387097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.062800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.835382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 27.42% 45.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.90% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.29% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.23% 72.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 8.06% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.61% 87.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 3300000 # Total ticks spent queuing -system.physmem.totMemAccLat 10650000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8418.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 2970000 # Total ticks spent queuing +system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27168.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1494.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1494.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.68 # Data bus utilization in percentage -system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads +system.physmem.busUtil 12.24 # Data bus utilization in percentage +system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 326 # Number of row buffer hits during reads +system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42656.89 # Average gap between requests -system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined +system.physmem.avgGap 40695.21 # Average gap between requests +system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1494578816 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 350 # Transaction distribution -system.membus.trans_dist::ReadResp 350 # Transaction distribution +system.membus.throughput 1566171485 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 355 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 784 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25088 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25088 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25408 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 479500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3655500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2517 # Number of BP lookups -system.cpu.branchPred.condPredicted 1805 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2002 # Number of BTB lookups -system.cpu.branchPred.BTBHits 714 # Number of BTB hits +system.cpu.branchPred.lookups 2638 # Number of BP lookups +system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 783 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.664336 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 294 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,489 +336,491 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 33573 # number of cpu cycles simulated +system.cpu.numCycles 32447 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6921 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1008 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2659 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2378 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.162808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.572483 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10430 79.69% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.73% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.55% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 238 1.82% 84.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 231 1.76% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.06% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 93 0.71% 89.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.11% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1254 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.074971 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.359604 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6910 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2688 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2492 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 31 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 385 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13358 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 539 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7139 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 151 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2277 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2296 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 258 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12614 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 195 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 12625 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57590 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 52228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 47 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6952 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 41 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 329 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2826 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1583 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11316 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8961 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 149 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14803 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.684621 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.402607 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2145 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2064 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9594 73.30% 73.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1210 9.24% 82.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 823 6.29% 88.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 494 3.77% 92.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 3.66% 96.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 298 2.28% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 131 1.00% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 49 0.37% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.71% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.44% 65.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 34.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5369 59.92% 59.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2357 26.30% 86.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8961 # Type of FU issued -system.cpu.iq.rate 0.266911 # Inst issue rate -system.cpu.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31345 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16624 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8077 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9162 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 8358 # Type of FU issued +system.cpu.iq.rate 0.257589 # Inst issue rate +system.cpu.iq.fu_busy_cnt 169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1626 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 645 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11366 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2826 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1583 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 266 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 376 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8568 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 393 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3332 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed -system.cpu.iew.exec_stores 1172 # Number of stores executed -system.cpu.iew.exec_rate 0.255205 # Inst execution rate -system.cpu.iew.wb_sent 8256 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8093 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3919 # num instructions producing a value -system.cpu.iew.wb_consumers 8062 # num instructions consuming a value +system.cpu.iew.exec_nop 11 # number of nop insts executed +system.cpu.iew.exec_refs 3148 # number of memory reference insts executed +system.cpu.iew.exec_branches 1457 # Number of branches executed +system.cpu.iew.exec_stores 1240 # Number of stores executed +system.cpu.iew.exec_rate 0.248498 # Inst execution rate +system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7601 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3572 # num instructions producing a value +system.cpu.iew.wb_consumers 6998 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.241057 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.486108 # average fanout of values written-back +system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5642 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.472651 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.325156 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9924 81.87% 81.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 978 8.07% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.32% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 224 1.85% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 175 1.44% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.75% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.41% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.27% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 123 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12121 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2138 # Number of memory references committed -system.cpu.commit.loads 1200 # Number of loads committed +system.cpu.commit.refs 1965 # Number of memory references committed +system.cpu.commit.loads 1027 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed system.cpu.commit.branches 1007 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4976 # Number of committed integer instructions. +system.cpu.commit.int_insts 4624 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5729 # Class of committed instruction -system.cpu.commit.bw_lim_events 123 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 5377 # Class of committed instruction +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23212 # The number of ROB reads -system.cpu.rob.rob_writes 23723 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20484 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22692 # The number of ROB reads +system.cpu.rob.rob_writes 21719 # The number of ROB writes +system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.312786 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.312786 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136747 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136747 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39407 # number of integer regfile reads -system.cpu.int_regfile_writes 7992 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 3253 # number of misc regfile reads +system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads +system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7944 # number of integer regfile reads +system.cpu.int_regfile_writes 4420 # number of integer regfile writes +system.cpu.fp_regfile_reads 31 # number of floating regfile reads +system.cpu.cc_regfile_reads 28734 # number of cc regfile reads +system.cpu.cc_regfile_writes 3302 # number of cc regfile writes +system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1662337662 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 394 # Transaction distribution +system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 870 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27712 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 480500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) +system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 148.488883 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1601 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.520690 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 148.488883 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.141113 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4226 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4226 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits -system.cpu.icache.overall_hits::total 1601 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses -system.cpu.icache.overall_misses::total 367 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23960000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23960000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23960000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23960000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23960000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23960000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186484 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186484 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186484 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186484 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186484 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186484 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65286.103542 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65286.103542 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65286.103542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65286.103542 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4430 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits +system.cpu.icache.overall_hits::total 1666 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses +system.cpu.icache.overall_misses::total 402 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 53.500000 # average number of cycles each access was blocked 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misses -system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19152500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19152500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19152500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19152500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19152500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19152500 # number of overall MSHR miss cycles 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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903226 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903226 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56633.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66815.625000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58960.714286 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61815.476190 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61815.476190 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.019573 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.438356 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.019573 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021245 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021245 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5964 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5964 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1782 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1782 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits 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-system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits +system.cpu.dcache.overall_hits::total 2146 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 507 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 507 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 507 # number of overall misses -system.cpu.dcache.overall_misses::total 507 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20684250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20684250 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32297743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32297743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32297743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32297743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses +system.cpu.dcache.overall_misses::total 521 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2885 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2885 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2885 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2885 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.096349 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175737 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175737 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175737 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175737 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65250 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65250 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63703.635108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63703.635108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 118 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -984,30 +985,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6871755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6871755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3151750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3151750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10023505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10023505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.050953 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.050953 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index fe7b25846..f5795e533 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2870500 # Number of ticks simulated -final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2694500 # Number of ticks simulated +final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 790734 # Simulator instruction rate (inst/s) -host_op_rate 984195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 492029482 # Simulator tick rate (ticks/s) -host_mem_usage 297624 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 109620 # Simulator instruction rate (inst/s) +host_op_rate 128318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64270947 # Simulator tick rate (ticks/s) +host_mem_usage 268656 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated -sim_ops 5729 # Number of ops (including micro ops) simulated +sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 18416 # Nu system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9251001568 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9855260716 # Throughput (bytes/s) system.membus.data_through_bus 26555 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -211,63 +211,65 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 5742 # number of cpu cycles simulated +system.cpu.numCycles 5390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4591 # Number of instructions committed -system.cpu.committedOps 5729 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses +system.cpu.committedOps 5377 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls -system.cpu.num_int_insts 4976 # number of integer instructions +system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls +system.cpu.num_int_insts 4624 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25360 # number of times the integer registers were read -system.cpu.num_int_register_writes 5334 # number of times the integer registers were written +system.cpu.num_int_register_reads 7607 # number of times the integer registers were read +system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2138 # number of memory refs -system.cpu.num_load_insts 1200 # Number of load instructions +system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read +system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written +system.cpu.num_mem_refs 1965 # number of memory refs +system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5742 # Number of busy cycles +system.cpu.num_busy_cycles 5390 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction -system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction +system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5742 # Class of executed instruction +system.cpu.op_class::total 5390 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 2a0a91e3f..efe28c206 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2870500 # Number of ticks simulated -final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2694500 # Number of ticks simulated +final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 770690 # Simulator instruction rate (inst/s) -host_op_rate 959471 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 479615706 # Simulator tick rate (ticks/s) -host_mem_usage 296608 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 133655 # Simulator instruction rate (inst/s) +host_op_rate 156442 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78348823 # Simulator tick rate (ticks/s) +host_mem_usage 267596 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated -sim_ops 5729 # Number of ops (including micro ops) simulated +sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 18416 # Nu system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9251001568 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9855260716 # Throughput (bytes/s) system.membus.data_through_bus 26555 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 5742 # number of cpu cycles simulated +system.cpu.numCycles 5390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4591 # Number of instructions committed -system.cpu.committedOps 5729 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses +system.cpu.committedOps 5377 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls -system.cpu.num_int_insts 4976 # number of integer instructions +system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls +system.cpu.num_int_insts 4624 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25360 # number of times the integer registers were read -system.cpu.num_int_register_writes 5334 # number of times the integer registers were written +system.cpu.num_int_register_reads 7607 # number of times the integer registers were read +system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2138 # number of memory refs -system.cpu.num_load_insts 1200 # Number of load instructions +system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read +system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written +system.cpu.num_mem_refs 1965 # number of memory refs +system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5742 # Number of busy cycles +system.cpu.num_busy_cycles 5390 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction -system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction +system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5742 # Class of executed instruction +system.cpu.op_class::total 5390 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index ba11ac8e8..f26a07dcf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25969000 # Number of ticks simulated -final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25815000 # Number of ticks simulated +final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376681 # Simulator instruction rate (inst/s) -host_op_rate 467447 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2137718143 # Simulator tick rate (ticks/s) -host_mem_usage 306356 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 85918 # Simulator instruction rate (inst/s) +host_op_rate 100276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 485659481 # Simulator tick rate (ticks/s) +host_mem_usage 277384 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated -sim_ops 5672 # Number of ops (including micro ops) simulated +sim_ops 5329 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 862566907 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 867712570 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 307 # Transaction distribution system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution @@ -40,10 +40,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 22400 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51938 # number of cpu cycles simulated +system.cpu.numCycles 51630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed -system.cpu.committedOps 5672 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses +system.cpu.committedOps 5329 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls -system.cpu.num_int_insts 4976 # number of integer instructions +system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls +system.cpu.num_int_insts 4624 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 28821 # number of times the integer registers were read -system.cpu.num_int_register_writes 5334 # number of times the integer registers were written +system.cpu.num_int_register_reads 7573 # number of times the integer registers were read +system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2138 # number of memory refs -system.cpu.num_load_insts 1200 # Number of load instructions +system.cpu.num_cc_register_reads 19184 # number of times the CC registers were read +system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written +system.cpu.num_mem_refs 1965 # number of memory refs +system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 51938 # Number of busy cycles +system.cpu.num_busy_cycles 51630 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction -system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction -system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction +system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5742 # Class of executed instruction +system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -215,12 +217,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses @@ -233,12 +235,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,36 +255,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id @@ -309,17 +311,17 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) @@ -342,17 +344,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,32 +409,32 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4303 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4303 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits -system.cpu.dcache.overall_hits::total 1918 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits +system.cpu.dcache.overall_hits::total 1764 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses @@ -449,26 +451,26 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7083000 system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency @@ -501,14 +503,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency @@ -518,7 +520,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 941430167 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 947046291 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 46dc5a264..8c5d2b15c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21842500 # Number of ticks simulated -final_tick 21842500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21611500 # Number of ticks simulated +final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54203 # Simulator instruction rate (inst/s) -host_op_rate 54195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 229554116 # Simulator tick rate (ticks/s) -host_mem_usage 222444 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 39362 # Simulator instruction rate (inst/s) +host_op_rate 39354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 164927772 # Simulator tick rate (ticks/s) +host_mem_usage 235848 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 30464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 981572622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 413139522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1394712144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 981572622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 981572622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 981572622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 413139522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1394712144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 30656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 479 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 997987183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 420516854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1418504037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 997987183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 997987183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 997987183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 420516854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1418504037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 479 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 476 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 479 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30656 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -49,13 +49,13 @@ system.physmem.perBankRdBursts::4 7 # Pe system.physmem.perBankRdBursts::5 3 # Per bank write bursts system.physmem.perBankRdBursts::6 13 # Per bank write bursts system.physmem.perBankRdBursts::7 54 # Per bank write bursts -system.physmem.perBankRdBursts::8 63 # Per bank write bursts +system.physmem.perBankRdBursts::8 64 # Per bank write bursts system.physmem.perBankRdBursts::9 77 # Per bank write bursts -system.physmem.perBankRdBursts::10 44 # Per bank write bursts +system.physmem.perBankRdBursts::10 43 # Per bank write bursts system.physmem.perBankRdBursts::11 20 # Per bank write bursts system.physmem.perBankRdBursts::12 51 # Per bank write bursts system.physmem.perBankRdBursts::13 29 # Per bank write bursts -system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::14 80 # Per bank write bursts system.physmem.perBankRdBursts::15 7 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21770000 # Total gap between requests +system.physmem.totGap 21538500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476 # Read request sizes (log2) +system.physmem.readPktSize::6 479 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,72 +186,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 255.407407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.497802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.634672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 31 28.70% 28.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 36.11% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 14.81% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 7.41% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.70% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 0.93% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 2.78% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.93% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 108 # Bytes accessed per row activation -system.physmem.totQLat 4718000 # Total ticks spent queuing -system.physmem.totMemAccLat 13643000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9911.76 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 255.412844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.780194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 251.892291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 32 29.36% 29.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38 34.86% 64.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15 13.76% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 10.09% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 2.75% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.75% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation +system.physmem.totQLat 5548500 # Total ticks spent queuing +system.physmem.totMemAccLat 14529750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2395000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11583.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28661.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1394.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30333.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1394.71 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.90 # Data bus utilization in percentage -system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.08 # Data bus utilization in percentage +system.physmem.busUtilRead 11.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 358 # Number of row buffer hits during reads +system.physmem.readRowHits 360 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.21 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45735.29 # Average gap between requests -system.physmem.pageHitRate 75.21 # Row buffer hit rate, read and write combined +system.physmem.avgGap 44965.55 # Average gap between requests +system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15316000 # Time in different power states +system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1394712144 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 425 # Transaction distribution -system.membus.trans_dist::ReadResp 425 # Transaction distribution +system.membus.throughput 1418504037 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 428 # Transaction distribution +system.membus.trans_dist::ReadResp 428 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 952 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 30464 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30464 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 958 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4464750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4492750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2178 # Number of BP lookups -system.cpu.branchPred.condPredicted 1497 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups -system.cpu.branchPred.BTBHits 491 # Number of BTB hits +system.cpu.branchPred.lookups 2196 # Number of BP lookups +system.cpu.branchPred.condPredicted 1454 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 435 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1700 # Number of BTB lookups +system.cpu.branchPred.BTBHits 564 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.596142 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 33.176471 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 277 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 69 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -271,236 +270,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43686 # number of cpu cycles simulated +system.cpu.numCycles 43224 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8839 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13190 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2178 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 749 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1378 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1314 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14424 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.914448 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.226738 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 9138 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13312 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.905393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.198604 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11210 77.72% 77.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1316 9.12% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 106 0.73% 87.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.91% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 113 0.78% 91.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 150 1.04% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 1.11% 93.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 933 6.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11282 76.73% 76.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1513 10.29% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 130 0.88% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 159 1.08% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 291 1.98% 90.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 99 0.67% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 152 1.03% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 125 0.85% 93.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 952 6.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14424 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049856 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.301927 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8852 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1624 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3059 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 872 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12284 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 872 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9006 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 365 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2923 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 285 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11879 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 266 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14112 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13884 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.050805 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.307977 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8679 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2634 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2860 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 400 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 179 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12297 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 180 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 400 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8850 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 975 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2807 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1169 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11801 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 281 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 7107 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13927 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13678 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3709 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 151 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2543 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1213 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9223 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9299 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8300 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3436 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2075 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8548 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3486 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1874 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14424 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.575430 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.252383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.581378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.331585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10895 75.53% 75.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1375 9.53% 85.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 844 5.85% 90.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 571 3.96% 94.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 375 2.60% 97.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.56% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 91 0.63% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11282 76.73% 76.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1346 9.15% 85.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 761 5.18% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 427 2.90% 93.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 364 2.48% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 316 2.15% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 114 0.78% 99.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 65 0.44% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14424 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14703 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 3.09% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 102 62.96% 66.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 55 33.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.96% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 135 66.83% 70.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 59 29.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4936 59.47% 59.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2249 27.10% 86.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1106 13.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5034 58.89% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2396 28.03% 87.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1109 12.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8300 # Type of FU issued -system.cpu.iq.rate 0.189992 # Inst issue rate -system.cpu.iq.fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019518 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31229 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12679 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8548 # Type of FU issued +system.cpu.iq.rate 0.197761 # Inst issue rate +system.cpu.iq.fu_busy_cnt 202 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023631 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32026 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12803 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7708 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8460 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8748 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 86 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1305 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1380 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 270 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 288 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 872 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 287 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10750 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 400 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 479 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10879 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2543 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1213 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 365 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7921 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 379 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 464 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8213 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2257 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 335 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1515 # number of nop insts executed -system.cpu.iew.exec_refs 3187 # number of memory reference insts executed -system.cpu.iew.exec_branches 1350 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.181317 # Inst execution rate -system.cpu.iew.wb_sent 7554 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7469 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2985 # num instructions producing a value -system.cpu.iew.wb_consumers 4341 # num instructions consuming a value +system.cpu.iew.exec_nop 1568 # number of nop insts executed +system.cpu.iew.exec_refs 3348 # number of memory reference insts executed +system.cpu.iew.exec_branches 1425 # Number of branches executed +system.cpu.iew.exec_stores 1091 # Number of stores executed +system.cpu.iew.exec_rate 0.190010 # Inst execution rate +system.cpu.iew.wb_sent 7817 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7710 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2989 # num instructions producing a value +system.cpu.iew.wb_consumers 4523 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.170970 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.687630 # average fanout of values written-back +system.cpu.iew.wb_rate 0.178373 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660845 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4930 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.428940 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.213640 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 392 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13824 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.420501 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238844 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11200 82.64% 82.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 943 6.96% 89.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 594 4.38% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 344 2.54% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 162 1.20% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 97 0.72% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 69 0.51% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11590 83.84% 83.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 886 6.41% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 537 3.88% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 260 1.88% 96.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.07% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 189 1.37% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 68 0.49% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13824 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -546,98 +545,98 @@ system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5813 # Class of committed instruction -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24180 # The number of ROB reads -system.cpu.rob.rob_writes 22370 # The number of ROB writes -system.cpu.timesIdled 295 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29262 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24581 # The number of ROB reads +system.cpu.rob.rob_writes 22642 # The number of ROB writes +system.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28521 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.472847 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.472847 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118024 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.118024 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10764 # number of integer regfile reads -system.cpu.int_regfile_writes 5241 # number of integer regfile writes +system.cpu.cpi 8.383243 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.383243 # CPI: Total CPI of All Threads +system.cpu.ipc 0.119286 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.119286 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11114 # number of integer regfile reads +system.cpu.int_regfile_writes 5412 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1403502346 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 428 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution +system.cpu.misc_regfile_reads 164 # number of misc regfile reads +system.cpu.toL2Bus.throughput 1427388196 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 431 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 431 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 958 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30656 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 680 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30848 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 571750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 575000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 161.396825 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1520 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.497041 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.374264 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1615 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 340 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.750000 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.396825 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078807 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078807 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4280 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4280 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1520 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1520 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1520 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1520 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1520 # number of overall hits -system.cpu.icache.overall_hits::total 1520 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses -system.cpu.icache.overall_misses::total 451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31166000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31166000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31166000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31166000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31166000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31166000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228818 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228818 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228818 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228818 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228818 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228818 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69104.212860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69104.212860 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69104.212860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69104.212860 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 161.374264 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078796 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078796 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 323 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.157715 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4476 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4476 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1615 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1615 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1615 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1615 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1615 # number of overall hits +system.cpu.icache.overall_hits::total 1615 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses +system.cpu.icache.overall_misses::total 453 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31448500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31448500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31448500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31448500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31448500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31448500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219052 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.219052 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.219052 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.219052 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.219052 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.219052 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69422.737307 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69422.737307 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69422.737307 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69422.737307 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -647,109 +646,109 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 113 system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24162750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24162750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24162750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24162750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24162750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24162750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.171487 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.171487 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.171487 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71487.426036 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71487.426036 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24624500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24624500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24624500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24624500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24624500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24624500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164410 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.164410 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.164410 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72425 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72425 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency 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blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810199 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 425 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012970 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4308 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4308 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.614658 # Average occupied blocks per requestor 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rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993039 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991176 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.993776 # miss rate for demand accesses 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+system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.661972 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.608220 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022365 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022365 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 92.430317 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5965 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5965 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 6220 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6220 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1945 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1945 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 150 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 150 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2508 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2508 # number of overall hits +system.cpu.dcache.overall_hits::total 2508 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses -system.cpu.dcache.overall_misses::total 512 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10436500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10436500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22532249 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22532249 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32968749 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32968749 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32968749 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32968749 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1987 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1987 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 531 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses +system.cpu.dcache.overall_misses::total 531 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11709000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23266249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23266249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34975249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34975249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34975249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34975249 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2912 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2912 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2912 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2912 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075491 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075491 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 3039 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3039 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3039 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3039 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079943 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079943 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175824 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175824 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175824 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175824 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69576.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69576.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62243.781768 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62243.781768 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64392.087891 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64392.087891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64392.087891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64392.087891 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.174729 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69284.023669 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69284.023669 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64271.406077 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64271.406077 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65866.758945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65866.758945 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 389 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 389 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 389 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 389 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7079250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7079250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10907499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10907499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10907499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10907499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045294 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045294 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7382750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7382750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4109999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4109999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11492749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11492749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11492749 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11492749 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048420 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048420 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78658.333333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78658.333333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81129.120879 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81129.120879 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80588.215686 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80588.215686 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index ca8bce664..895c59829 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19030500 # Number of ticks simulated -final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18857500 # Number of ticks simulated +final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 17395 # Simulator instruction rate (inst/s) -host_op_rate 17394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57147442 # Simulator tick rate (ticks/s) -host_mem_usage 218304 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 41326 # Simulator instruction rate (inst/s) +host_op_rate 41320 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134509153 # Simulator tick rate (ticks/s) +host_mem_usage 232584 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446 # Number of read requests accepted +system.physmem.num_reads::total 444 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 70 # Per bank write bursts +system.physmem.perBankRdBursts::0 71 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 54 # Per bank write bursts -system.physmem.perBankRdBursts::3 59 # Per bank write bursts +system.physmem.perBankRdBursts::2 55 # Per bank write bursts +system.physmem.perBankRdBursts::3 58 # Per bank write bursts system.physmem.perBankRdBursts::4 53 # Per bank write bursts system.physmem.perBankRdBursts::5 61 # Per bank write bursts system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 13 # Per bank write bursts -system.physmem.perBankRdBursts::8 8 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 9 # Per bank write bursts system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts system.physmem.perBankRdBursts::11 0 # Per bank write bursts system.physmem.perBankRdBursts::12 0 # Per bank write bursts system.physmem.perBankRdBursts::13 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18902000 # Total gap between requests +system.physmem.totGap 18724000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 446 # Read request sizes (log2) +system.physmem.readPktSize::6 444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,71 +186,72 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.719469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 351.121005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27 35.06% 35.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 23.38% 58.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation -system.physmem.totQLat 3354000 # Total ticks spent queuing -system.physmem.totMemAccLat 11716500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7520.18 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation +system.physmem.totQLat 3609000 # Total ticks spent queuing +system.physmem.totMemAccLat 11934000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8128.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26270.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26878.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.72 # Data bus utilization in percentage -system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.77 # Data bus utilization in percentage +system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 358 # Number of row buffer hits during reads +system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42381.17 # Average gap between requests -system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined +system.physmem.avgGap 42171.17 # Average gap between requests +system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1499908042 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 399 # Transaction distribution -system.membus.trans_dist::ReadResp 399 # Transaction distribution +system.membus.throughput 1506880552 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 397 # Transaction distribution +system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 28544 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28416 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2252 # Number of BP lookups -system.cpu.branchPred.condPredicted 1816 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1865 # Number of BTB lookups -system.cpu.branchPred.BTBHits 610 # Number of BTB hits +system.cpu.branchPred.lookups 2332 # Number of BP lookups +system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups +system.cpu.branchPred.BTBHits 661 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.707775 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -270,235 +271,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 38062 # number of cpu cycles simulated +system.cpu.numCycles 37716 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7462 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13226 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2252 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 809 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2276 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1296 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 871 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.152492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.564431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9200 80.17% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 1.55% 81.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 178 1.55% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 145 1.26% 84.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 228 1.99% 86.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.16% 87.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 261 2.27% 89.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.96% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1043 9.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.059167 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.347486 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7479 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1089 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2174 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 714 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11804 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 714 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7660 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2016 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 428 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11368 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 165 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 241 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9753 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18286 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18260 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1951 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1916 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4755 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 259 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2025 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1841 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10356 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8929 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4296 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778059 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.545863 # Number of insts issued each cycle +system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8265 72.02% 72.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1011 8.81% 80.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 683 5.95% 86.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 469 4.09% 90.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 473 4.12% 94.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 313 2.73% 97.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 182 1.59% 99.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.38% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 6.21% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 75 42.37% 48.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 91 51.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5495 61.54% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1798 20.14% 81.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1634 18.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8929 # Type of FU issued -system.cpu.iq.rate 0.234591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019823 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29690 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14680 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9108 # Type of FU issued +system.cpu.iq.rate 0.241489 # Inst issue rate +system.cpu.iq.fu_busy_cnt 251 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9072 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1064 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 795 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 714 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 160 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10413 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2025 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1841 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8526 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1682 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3211 # number of memory reference insts executed -system.cpu.iew.exec_branches 1353 # Number of branches executed -system.cpu.iew.exec_stores 1529 # Number of stores executed -system.cpu.iew.exec_rate 0.224003 # Inst execution rate -system.cpu.iew.wb_sent 8294 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8178 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4388 # num instructions producing a value -system.cpu.iew.wb_consumers 6958 # num instructions consuming a value +system.cpu.iew.exec_refs 3329 # number of memory reference insts executed +system.cpu.iew.exec_branches 1361 # Number of branches executed +system.cpu.iew.exec_stores 1554 # Number of stores executed +system.cpu.iew.exec_rate 0.230724 # Inst execution rate +system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8300 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4483 # num instructions producing a value +system.cpu.iew.wb_consumers 7102 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.214860 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.630641 # average fanout of values written-back +system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4620 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.538190 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.389247 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11593 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.499612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.370164 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8538 79.33% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 887 8.24% 87.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 552 5.13% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 240 2.23% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.64% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 96 0.89% 97.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 1.10% 98.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 47 0.44% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9440 81.43% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 839 7.24% 88.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 524 4.52% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11593 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -544,148 +547,148 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21067 # The number of ROB reads -system.cpu.rob.rob_writes 21539 # The number of ROB writes -system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26586 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21861 # The number of ROB reads +system.cpu.rob.rob_writes 21469 # The number of ROB writes +system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads -system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13502 # number of integer regfile reads -system.cpu.int_regfile_writes 7065 # number of integer regfile writes +system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads +system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13743 # number of integer regfile reads +system.cpu.int_regfile_writes 7176 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution +system.cpu.toL2Bus.throughput 1530637677 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28864 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 588250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.076059 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1380 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.931624 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.076059 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082557 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082557 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3997 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3997 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1380 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1380 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1380 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1380 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1380 # number of overall hits -system.cpu.icache.overall_hits::total 1380 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 443 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 443 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 443 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 443 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 443 # number of overall misses -system.cpu.icache.overall_misses::total 443 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29586250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29586250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29586250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29586250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29586250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29586250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.243006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.243006 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.243006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.243006 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.243006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66786.117381 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66786.117381 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66786.117381 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66786.117381 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4007 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits +system.cpu.icache.overall_hits::total 1391 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses +system.cpu.icache.overall_misses::total 438 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24098750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24098750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24098750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24098750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24098750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24098750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192540 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.192540 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.192540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68657.407407 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68657.407407 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.437860 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.936913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.500947 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005125 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006086 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 215 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor 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Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -695,61 +698,61 @@ system.cpu.l2cache.demand_hits::total 7 # nu system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 7 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 345 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses +system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses -system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23687250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4073750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27761000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3627250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23687250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7701000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31388250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23687250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7701000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31388250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 445 # number of overall misses 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31532250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 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rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68658.695652 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75439.814815 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69576.441103 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77175.531915 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77175.531915 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70377.242152 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70377.242152 # average overall miss latency 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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,130 +761,130 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19339750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3409250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22749000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3052750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3052750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19339750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6462000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25801750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19339750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6462000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25801750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses 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-system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2180 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2180 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2180 # number of overall hits -system.cpu.dcache.overall_hits::total 2180 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses -system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7380250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7380250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21128996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21128996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28509246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28509246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28509246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28509246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits +system.cpu.dcache.overall_hits::total 2261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses +system.cpu.dcache.overall_misses::total 452 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066284 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066284 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166348 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166348 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166348 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166348 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70963.942308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70963.942308 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63833.824773 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63833.824773 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65538.496552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65538.496552 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -890,30 +893,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4139250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4139250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3677248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3677248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7816498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7816498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7816498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035054 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035054 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.039006 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.039006 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75259.090909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75259.090909 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78239.319149 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78239.319149 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index be2005774..f7173c445 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19813000 # Number of ticks simulated -final_tick 19813000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19744000 # Number of ticks simulated +final_tick 19744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35950 # Simulator instruction rate (inst/s) -host_op_rate 65125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132368943 # Simulator tick rate (ticks/s) -host_mem_usage 240140 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 27433 # Simulator instruction rate (inst/s) +host_op_rate 49695 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 100653274 # Simulator tick rate (ticks/s) +host_mem_usage 249652 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 885075456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 458688740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1343764195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 885075456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 885075456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 885075456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 458688740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1343764195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 891410049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 457050243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1348460292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 891410049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 891410049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 891410049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 457050243 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1348460292 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -46,11 +46,11 @@ system.physmem.perBankRdBursts::1 1 # Pe system.physmem.perBankRdBursts::2 6 # Per bank write bursts system.physmem.perBankRdBursts::3 8 # Per bank write bursts system.physmem.perBankRdBursts::4 50 # Per bank write bursts -system.physmem.perBankRdBursts::5 44 # Per bank write bursts +system.physmem.perBankRdBursts::5 45 # Per bank write bursts system.physmem.perBankRdBursts::6 21 # Per bank write bursts -system.physmem.perBankRdBursts::7 36 # Per bank write bursts +system.physmem.perBankRdBursts::7 34 # Per bank write bursts system.physmem.perBankRdBursts::8 22 # Per bank write bursts -system.physmem.perBankRdBursts::9 73 # Per bank write bursts +system.physmem.perBankRdBursts::9 74 # Per bank write bursts system.physmem.perBankRdBursts::10 63 # Per bank write bursts system.physmem.perBankRdBursts::11 17 # Per bank write bursts system.physmem.perBankRdBursts::12 2 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19764000 # Total gap between requests +system.physmem.totGap 19695500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,50 +186,50 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.075563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 270.532528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 36 37.11% 71.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 9.28% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 5.15% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation -system.physmem.totQLat 3851250 # Total ticks spent queuing -system.physmem.totMemAccLat 11670000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.132678 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.193096 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35 35.71% 35.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32 32.65% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 12.24% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation +system.physmem.totQLat 4076000 # Total ticks spent queuing +system.physmem.totMemAccLat 11894750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9235.61 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9774.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27985.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1346.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28524.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1351.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1346.99 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1351.70 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.52 # Data bus utilization in percentage -system.physmem.busUtilRead 10.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.56 # Data bus utilization in percentage +system.physmem.busUtilRead 10.56 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 310 # Number of row buffer hits during reads +system.physmem.readRowHits 309 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.34 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47395.68 # Average gap between requests -system.physmem.pageHitRate 74.34 # Row buffer hit rate, read and write combined +system.physmem.avgGap 47231.41 # Average gap between requests +system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315750 # Time in different power states +system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1343764195 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 340 # Transaction distribution -system.membus.trans_dist::ReadResp 339 # Transaction distribution -system.membus.trans_dist::ReadExReq 77 # Transaction distribution -system.membus.trans_dist::ReadExResp 77 # Transaction distribution +system.membus.throughput 1348460292 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 339 # Transaction distribution +system.membus.trans_dist::ReadResp 338 # Transaction distribution +system.membus.trans_dist::ReadExReq 78 # Transaction distribution +system.membus.trans_dist::ReadExResp 78 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) @@ -238,250 +238,250 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 26624 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 508000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3892500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 3151 # Number of BP lookups -system.cpu.branchPred.condPredicted 3151 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 538 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2362 # Number of BTB lookups -system.cpu.branchPred.BTBHits 784 # Number of BTB hits +system.cpu.branchPred.lookups 3423 # Number of BP lookups +system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups +system.cpu.branchPred.BTBHits 864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.192210 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 213 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 80 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39627 # number of cpu cycles simulated +system.cpu.numCycles 39489 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10249 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14342 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3151 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 997 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4009 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2516 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5030 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 499 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21739 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.176503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.686230 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1202 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.CacheLines 2168 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21893 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.270406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.764504 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17828 82.01% 82.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 213 0.98% 82.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 156 0.72% 83.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.04% 84.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 194 0.89% 85.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 208 0.96% 86.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 291 1.34% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 168 0.77% 88.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2454 11.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17618 80.47% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 236 1.08% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 174 0.79% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 259 1.18% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 208 0.95% 84.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21739 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079516 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.361925 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11168 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4895 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3648 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1891 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24503 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1891 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11399 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 477 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 595 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3548 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3829 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 23145 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 51 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 3750 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 25950 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56380 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 31990 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.086682 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.393223 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3336 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2194 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 719 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3480 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3970 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24219 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 3820 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 27591 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 59364 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 33558 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14887 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1258 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 16528 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 29 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1503 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2441 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1612 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20529 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17116 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10025 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14683 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21739 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.787341 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.689074 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 21443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17897 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11052 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16525 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.817476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.773238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16539 76.08% 76.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1246 5.73% 81.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 983 4.52% 86.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 694 3.19% 89.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 782 3.60% 93.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 618 2.84% 95.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 580 2.67% 98.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 252 1.16% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 45 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16772 76.61% 76.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1137 5.19% 81.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 886 4.05% 85.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 636 2.91% 88.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 833 3.80% 92.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 590 2.69% 95.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 599 2.74% 97.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 316 1.44% 99.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124 0.57% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21739 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21893 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 136 76.40% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.61% 91.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 16 8.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13738 80.26% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.03% 80.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1970 11.51% 91.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1393 8.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14382 80.36% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17116 # Type of FU issued -system.cpu.iq.rate 0.431928 # Inst issue rate -system.cpu.iq.fu_busy_cnt 178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010400 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56452 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30591 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15728 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17897 # Type of FU issued +system.cpu.iq.rate 0.453215 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17287 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18114 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 197 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 228 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1240 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1388 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 684 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 677 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1891 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 262 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20557 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 31 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 697 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16214 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1838 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 902 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 601 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1862 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21468 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2441 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1612 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3129 # number of memory reference insts executed -system.cpu.iew.exec_branches 1636 # Number of branches executed -system.cpu.iew.exec_stores 1291 # Number of stores executed -system.cpu.iew.exec_rate 0.409165 # Inst execution rate -system.cpu.iew.wb_sent 15955 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15732 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10485 # num instructions producing a value -system.cpu.iew.wb_consumers 16294 # num instructions consuming a value +system.cpu.iew.exec_refs 3251 # number of memory reference insts executed +system.cpu.iew.exec_branches 1662 # Number of branches executed +system.cpu.iew.exec_stores 1282 # Number of stores executed +system.cpu.iew.exec_rate 0.428626 # Inst execution rate +system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16374 # cumulative count of insts written-back +system.cpu.iew.wb_producers 11006 # num instructions producing a value +system.cpu.iew.wb_consumers 17135 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.397002 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643488 # average fanout of values written-back +system.cpu.iew.wb_rate 0.414647 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10809 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 19848 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.491082 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.377621 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 19925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.489184 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.394250 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16557 83.42% 83.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1016 5.12% 88.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 561 2.83% 91.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 767 3.86% 95.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 387 1.95% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 137 0.69% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 0.59% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.37% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 232 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16685 83.74% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 365 1.83% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 142 0.71% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.57% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.37% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 19848 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19925 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -527,95 +527,95 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40172 # The number of ROB reads -system.cpu.rob.rob_writes 43025 # The number of ROB writes -system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17888 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 41132 # The number of ROB reads +system.cpu.rob.rob_writes 44928 # The number of ROB writes +system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17596 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.365613 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.365613 # CPI: Total CPI of All Threads -system.cpu.ipc 0.135766 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.135766 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20766 # number of integer regfile reads -system.cpu.int_regfile_writes 12432 # number of integer regfile writes +system.cpu.cpi 7.339963 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.339963 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136240 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136240 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21340 # number of integer regfile reads +system.cpu.int_regfile_writes 13120 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8051 # number of cc regfile reads -system.cpu.cc_regfile_writes 4869 # number of cc regfile writes -system.cpu.misc_regfile_reads 7177 # number of misc regfile reads +system.cpu.cc_regfile_reads 8069 # number of cc regfile reads +system.cpu.cc_regfile_writes 5036 # number of cc regfile writes +system.cpu.misc_regfile_reads 7491 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1346994398 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.throughput 1351701783 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 461000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 462750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.410773 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.967273 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 131.753616 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.410773 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064165 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064165 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 275 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.134277 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4301 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4301 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits -system.cpu.icache.overall_hits::total 1641 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses -system.cpu.icache.overall_misses::total 372 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25012250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25012250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25012250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25012250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25012250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25012250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184799 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184799 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184799 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184799 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184799 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184799 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67237.231183 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67237.231183 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67237.231183 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67237.231183 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67237.231183 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67237.231183 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 131.753616 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064333 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064333 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4612 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits +system.cpu.icache.overall_hits::total 1800 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25386000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25386000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25386000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25386000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25386000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25386000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68983.695652 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68983.695652 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68983.695652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68983.695652 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,52 +624,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 97 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 97 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 97 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19562000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19562000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19562000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19562000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19562000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19562000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136612 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136612 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136612 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71134.545455 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71134.545455 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71134.545455 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71134.545455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71134.545455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71134.545455 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 276 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19887250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19887250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19887250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19887250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19887250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19887250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72055.253623 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72055.253623 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 164.472388 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.478116 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002950 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.481156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.991232 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004012 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001007 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005019 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010345 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.827183 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.650934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004023 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000966 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004989 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits @@ -678,61 +678,61 @@ system.cpu.l2cache.demand_hits::cpu.inst 1 # nu system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 340 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 339 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 78 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 78 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses 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15584750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15584750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2518 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2518 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2518 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2518 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084018 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.083400 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.083400 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.083400 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.083400 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71236.842105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71236.842105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74178.571429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74178.571429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72315.476190 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72315.476190 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72315.476190 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72315.476190 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73964.743590 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73964.743590 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72825.934579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72825.934579 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 67 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5115250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5115250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5531250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5531250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10646500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10646500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10646500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10646500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041693 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041693 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056791 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056791 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056791 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77503.787879 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77503.787879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71834.415584 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71834.415584 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74451.048951 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74451.048951 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74451.048951 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74451.048951 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5586750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5586750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10596250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10596250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10596250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10596250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71625 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index c6213fa68..921de5f0b 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24521000 # Number of ticks simulated -final_tick 24521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 23170000 # Number of ticks simulated +final_tick 23170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36221 # Simulator instruction rate (inst/s) -host_op_rate 36219 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69681363 # Simulator tick rate (ticks/s) -host_mem_usage 222160 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host -sim_insts 12745 # Number of instructions simulated -sim_ops 12745 # Number of ops (including micro ops) simulated +host_inst_rate 44420 # Simulator instruction rate (inst/s) +host_op_rate 44416 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 80747825 # Simulator tick rate (ticks/s) +host_mem_usage 237048 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host +sim_insts 12744 # Number of instructions simulated +sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40128 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 627 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 977 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1636474858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 913502712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2549977570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1636474858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1636474858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1636474858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 913502712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2549977570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 977 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory +system.physmem.bytes_read::total 62656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40384 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory +system.physmem.num_reads::total 979 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1742943461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 961242987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2704186448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1742943461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1742943461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1742943461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 961242987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2704186448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 979 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 977 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 979 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62656 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 83 # Per bank write bursts -system.physmem.perBankRdBursts::1 153 # Per bank write bursts -system.physmem.perBankRdBursts::2 77 # Per bank write bursts -system.physmem.perBankRdBursts::3 59 # Per bank write bursts -system.physmem.perBankRdBursts::4 87 # Per bank write bursts -system.physmem.perBankRdBursts::5 49 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 50 # Per bank write bursts +system.physmem.perBankRdBursts::0 84 # Per bank write bursts +system.physmem.perBankRdBursts::1 151 # Per bank write bursts +system.physmem.perBankRdBursts::2 78 # Per bank write bursts +system.physmem.perBankRdBursts::3 58 # Per bank write bursts +system.physmem.perBankRdBursts::4 88 # Per bank write bursts +system.physmem.perBankRdBursts::5 48 # Per bank write bursts +system.physmem.perBankRdBursts::6 33 # Per bank write bursts +system.physmem.perBankRdBursts::7 51 # Per bank write bursts system.physmem.perBankRdBursts::8 42 # Per bank write bursts system.physmem.perBankRdBursts::9 39 # Per bank write bursts system.physmem.perBankRdBursts::10 31 # Per bank write bursts -system.physmem.perBankRdBursts::11 33 # Per bank write bursts +system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 121 # Per bank write bursts +system.physmem.perBankRdBursts::13 120 # Per bank write bursts system.physmem.perBankRdBursts::14 70 # Per bank write bursts -system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24370500 # Total gap between requests +system.physmem.totGap 23015000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 977 # Read request sizes (log2) +system.physmem.readPktSize::6 979 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 75 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 282.666667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.603788 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 291.640046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 78 36.11% 36.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 56 25.93% 62.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 23 10.65% 72.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 15 6.94% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 3.70% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13 6.02% 89.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 1.85% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 2.78% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13 6.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 216 # Bytes accessed per row activation -system.physmem.totQLat 13158000 # Total ticks spent queuing -system.physmem.totMemAccLat 31476750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13467.76 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 196 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.959184 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.164854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 288.512504 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 61 31.12% 31.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60 30.61% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 22 11.22% 72.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 4.59% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16 8.16% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 3.06% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 2.55% 91.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 2.04% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13 6.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 196 # Bytes accessed per row activation +system.physmem.totQLat 11386250 # Total ticks spent queuing +system.physmem.totMemAccLat 29742500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4895000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11630.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32217.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2549.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30380.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2704.19 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2549.98 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2704.19 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 19.92 # Data bus utilization in percentage -system.physmem.busUtilRead 19.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 21.13 # Data bus utilization in percentage +system.physmem.busUtilRead 21.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.45 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 752 # Number of row buffer hits during reads +system.physmem.readRowHits 767 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.97 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 24944.22 # Average gap between requests -system.physmem.pageHitRate 76.97 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.avgGap 23508.68 # Average gap between requests +system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 25750 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22830500 # Time in different power states +system.physmem.memoryStateTime::ACT 15300500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2549977570 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 832 # Transaction distribution -system.membus.trans_dist::ReadResp 832 # Transaction distribution -system.membus.trans_dist::ReadExReq 145 # Transaction distribution -system.membus.trans_dist::ReadExResp 145 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 62528 # Total data (bytes) +system.membus.throughput 2704186448 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 833 # Transaction distribution +system.membus.trans_dist::ReadResp 833 # Transaction distribution +system.membus.trans_dist::ReadExReq 146 # Transaction distribution +system.membus.trans_dist::ReadExResp 146 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1958 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 62656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 9060500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 36.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1208500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 9081250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 39.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 7716 # Number of BP lookups -system.cpu.branchPred.condPredicted 4270 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1557 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5587 # Number of BTB lookups -system.cpu.branchPred.BTBHits 1032 # Number of BTB hits +system.cpu.branchPred.lookups 7166 # Number of BP lookups +system.cpu.branchPred.condPredicted 4000 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1467 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5305 # Number of BTB lookups +system.cpu.branchPred.BTBHits 908 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.471452 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 986 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 191 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 17.115928 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 981 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4952 # DTB read hits -system.cpu.dtb.read_misses 97 # DTB read misses +system.cpu.dtb.read_hits 4855 # DTB read hits +system.cpu.dtb.read_misses 98 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 5049 # DTB read accesses -system.cpu.dtb.write_hits 2131 # DTB write hits -system.cpu.dtb.write_misses 85 # DTB write misses +system.cpu.dtb.read_accesses 4953 # DTB read accesses +system.cpu.dtb.write_hits 2092 # DTB write hits +system.cpu.dtb.write_misses 62 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2216 # DTB write accesses -system.cpu.dtb.data_hits 7083 # DTB hits -system.cpu.dtb.data_misses 182 # DTB misses +system.cpu.dtb.write_accesses 2154 # DTB write accesses +system.cpu.dtb.data_hits 6947 # DTB hits +system.cpu.dtb.data_misses 160 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 7265 # DTB accesses -system.cpu.itb.fetch_hits 5823 # ITB hits -system.cpu.itb.fetch_misses 63 # ITB misses +system.cpu.dtb.data_accesses 7107 # DTB accesses +system.cpu.itb.fetch_hits 5289 # ITB hits +system.cpu.itb.fetch_misses 59 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5886 # ITB accesses +system.cpu.itb.fetch_accesses 5348 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -286,324 +286,324 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 49043 # number of cpu cycles simulated +system.cpu.numCycles 46341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1643 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 42292 # Number of instructions fetch has processed -system.cpu.fetch.Branches 7716 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2018 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7014 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1937 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 939 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28717 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.472717 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.866777 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1308 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 39806 # Number of instructions fetch has processed +system.cpu.fetch.Branches 7166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1889 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 11048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1548 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 233 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5289 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 806 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.397977 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.796585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21703 75.58% 75.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 628 2.19% 77.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 370 1.29% 79.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 488 1.70% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 478 1.66% 82.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 438 1.53% 83.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 544 1.89% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 450 1.57% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3618 12.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21786 76.51% 76.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 553 1.94% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 412 1.45% 79.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 526 1.85% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 512 1.80% 83.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 421 1.48% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 497 1.75% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 420 1.48% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3347 11.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28717 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.157331 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.862345 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40485 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6963 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 6425 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 184 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3240 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 753 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 442 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 37312 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 851 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3240 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 41162 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2710 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1573 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2696 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 34656 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 211 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 347 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1943 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 26052 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 42763 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 42745 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.154636 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.858980 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37975 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11845 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5079 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 648 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1147 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 634 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 427 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 32375 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 893 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1147 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38612 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4919 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1229 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5110 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5677 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30348 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 343 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 655 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4509 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 22899 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37890 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37872 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16912 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 53 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1929 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3424 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1551 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3264 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1487 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 43 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 29904 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 80 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 23616 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 291 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16167 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10244 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28717 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.822370 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.487550 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 13759 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 60 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2110 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2877 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1488 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2903 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1354 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 27058 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 22518 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 66 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13496 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7946 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.790827 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.507053 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19680 68.53% 68.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2792 9.72% 78.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2104 7.33% 85.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1715 5.97% 91.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1290 4.49% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 654 2.28% 98.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 354 1.23% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 107 0.37% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 21 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20065 70.47% 70.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2633 9.25% 79.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1896 6.66% 86.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1407 4.94% 91.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1291 4.53% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 643 2.26% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 327 1.15% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 165 0.58% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 47 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28474 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 15 7.43% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 116 57.43% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 35.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 21 6.95% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 199 65.89% 72.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 82 27.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7921 66.06% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2841 23.69% 89.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 10.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7409 65.93% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2656 23.63% 89.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1168 10.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11990 # Type of FU issued +system.cpu.iq.FU_type_0::total 11238 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7753 66.69% 66.70% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.71% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.71% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.73% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2675 23.01% 89.74% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1193 10.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7461 66.14% 66.16% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.17% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2675 23.71% 89.90% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1139 10.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11626 # Type of FU issued -system.cpu.iq.FU_type::total 23616 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.481537 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 102 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 202 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004319 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004234 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008554 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76400 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 46161 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11280 # Type of FU issued +system.cpu.iq.FU_type::total 22518 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.485920 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 151 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 151 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.006706 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.006706 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.013411 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73836 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 40624 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19843 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 23792 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22794 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 93 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2241 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 686 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1694 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 623 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 422 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 321 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 81 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 2081 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 622 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1720 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 489 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 310 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 265 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3240 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 485 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 30193 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6688 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 3038 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1147 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2751 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 416 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27257 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 298 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5780 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2842 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 461 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 265 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1140 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1405 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 21973 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2613 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2460 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 5073 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1643 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 391 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 140 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1160 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1300 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 21263 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2485 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2477 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4962 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1255 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 117 # number of nop insts executed -system.cpu.iew.exec_nop::1 92 # number of nop insts executed -system.cpu.iew.exec_nop::total 209 # number of nop insts executed -system.cpu.iew.exec_refs::0 3756 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3554 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 7310 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1740 # Number of branches executed -system.cpu.iew.exec_branches::1 1743 # Number of branches executed -system.cpu.iew.exec_branches::total 3483 # Number of branches executed -system.cpu.iew.exec_stores::0 1143 # Number of stores executed -system.cpu.iew.exec_stores::1 1094 # Number of stores executed -system.cpu.iew.exec_stores::total 2237 # Number of stores executed -system.cpu.iew.exec_rate 0.448035 # Inst execution rate -system.cpu.iew.wb_sent::0 10504 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 10265 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 20769 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 10336 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 10085 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 20421 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5409 # num instructions producing a value -system.cpu.iew.wb_producers::1 5311 # num instructions producing a value -system.cpu.iew.wb_producers::total 10720 # num instructions producing a value -system.cpu.iew.wb_consumers::0 7242 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 7116 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 14358 # num instructions consuming a value +system.cpu.iew.exec_nop::0 73 # number of nop insts executed +system.cpu.iew.exec_nop::1 73 # number of nop insts executed +system.cpu.iew.exec_nop::total 146 # number of nop insts executed +system.cpu.iew.exec_refs::0 3579 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3558 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7137 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1685 # Number of branches executed +system.cpu.iew.exec_branches::1 1728 # Number of branches executed +system.cpu.iew.exec_branches::total 3413 # Number of branches executed +system.cpu.iew.exec_stores::0 1094 # Number of stores executed +system.cpu.iew.exec_stores::1 1081 # Number of stores executed +system.cpu.iew.exec_stores::total 2175 # Number of stores executed +system.cpu.iew.exec_rate 0.458838 # Inst execution rate +system.cpu.iew.wb_sent::0 10071 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 10174 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 20245 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9887 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9976 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19863 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5227 # num instructions producing a value +system.cpu.iew.wb_producers::1 5224 # num instructions producing a value +system.cpu.iew.wb_producers::total 10451 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6995 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6944 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13939 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.210754 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.205636 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.416390 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.746893 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.746346 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.746622 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.213353 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.215274 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.428627 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.747248 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.752304 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.749767 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17385 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14469 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1147 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28645 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.446116 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297173 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1066 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.449898 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.318202 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23444 81.84% 81.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2590 9.04% 90.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1028 3.59% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 428 1.49% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 310 1.08% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 198 0.69% 97.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 191 0.67% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 175 0.61% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 281 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23341 82.18% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2401 8.45% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1094 3.85% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 390 1.37% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 322 1.13% 96.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 184 0.65% 97.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 208 0.73% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 133 0.47% 98.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 329 1.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28645 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28402 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed -system.cpu.commit.committedInsts::1 6390 # Number of instructions committed -system.cpu.commit.committedInsts::total 12779 # Number of instructions committed +system.cpu.commit.committedInsts::1 6389 # Number of instructions committed +system.cpu.commit.committedInsts::total 12778 # Number of instructions committed system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed @@ -664,258 +664,258 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_1::IntAlu 4320 67.61% 67.90% # Class of committed instruction -system.cpu.commit.op_class_1::IntMult 1 0.02% 67.92% # Class of committed instruction -system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.92% # Class of committed instruction -system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::MemRead 1183 18.51% 86.46% # Class of committed instruction +system.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction +system.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction +system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction +system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_1::total 6390 # Class of committed instruction -system.cpu.commit.op_class::total 12779 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 281 # number cycles where commit BW limit reached +system.cpu.commit.op_class_1::total 6389 # Class of committed instruction +system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction +system.cpu.commit.bw_lim_events 329 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140714 # The number of ROB reads -system.cpu.rob.rob_writes 63601 # The number of ROB writes -system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20326 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131970 # The number of ROB reads +system.cpu.rob.rob_writes 57167 # The number of ROB writes +system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17867 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated -system.cpu.committedInsts::1 6373 # Number of Instructions Simulated -system.cpu.committedInsts::total 12745 # Number of Instructions Simulated +system.cpu.committedInsts::1 6372 # Number of Instructions Simulated +system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::total 12745 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.696642 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.695434 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.848019 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.129927 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.129947 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.259874 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 27593 # number of integer regfile reads -system.cpu.int_regfile_writes 15533 # number of integer regfile writes +system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated +system.cpu.cpi::0 7.272599 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.272599 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.636299 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.137502 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.137502 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.275005 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 26712 # number of integer regfile reads +system.cpu.int_regfile_writes 15170 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.throughput 2555197586 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1958 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 62656 # Total data (bytes) +system.cpu.toL2Bus.throughput 2709710833 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1266 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 62784 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 489500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1029000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 559500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.cpu.icache.tags.replacements::0 8 # number of replacements +system.cpu.toL2Bus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1042000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 4.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 550750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.4 # Layer utilization (%) +system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements -system.cpu.icache.tags.replacements::total 8 # number of replacements -system.cpu.icache.tags.tagsinuse 316.348744 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4766 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 629 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.577107 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements::total 7 # number of replacements +system.cpu.icache.tags.tagsinuse 316.397057 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4348 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 633 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.868878 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 316.348744 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.154467 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.154467 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12259 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12259 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4766 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4766 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4766 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4766 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4766 # number of overall hits -system.cpu.icache.overall_hits::total 4766 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses -system.cpu.icache.overall_misses::total 1049 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 70831996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 70831996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 70831996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 70831996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 70831996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 70831996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5815 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5815 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5815 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5815 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5815 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5815 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180396 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.180396 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.180396 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.180396 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.180396 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.180396 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67523.351764 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67523.351764 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67523.351764 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67523.351764 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67523.351764 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67523.351764 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2854 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 316.397057 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.154491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.154491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11201 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11201 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4348 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4348 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4348 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4348 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4348 # number of overall hits +system.cpu.icache.overall_hits::total 4348 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 936 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 936 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 936 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 936 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 936 # number of overall misses +system.cpu.icache.overall_misses::total 936 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64563991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64563991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64563991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64563991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64563991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64563991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5284 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5284 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5284 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5284 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177139 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.177139 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.177139 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.177139 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.177139 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.177139 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68978.622863 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68978.622863 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68978.622863 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68978.622863 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68978.622863 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68978.622863 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3153 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 69 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.362319 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.987952 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 420 # number of ReadReq MSHR hits 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47492998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47492998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47492998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47492998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47492998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47492998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108169 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108169 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108169 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108169 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108169 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108169 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75505.561208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75505.561208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75505.561208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75505.561208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75505.561208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75505.561208 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 303 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 303 # number of ReadReq MSHR hits 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+system.cpu.icache.ReadReq_mshr_miss_latency::total 46517493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46517493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46517493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46517493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46517493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119796 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.119796 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.119796 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73487.350711 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73487.350711 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73487.350711 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73487.350711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73487.350711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73487.350711 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 437.665813 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 435.916526 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 832 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002404 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 833 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002401 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.125803 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 120.540010 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009678 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013357 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 832 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 324 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 508 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 8809 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 8809 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.007070 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 118.909455 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009674 # Average percentage of cache occupancy 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overall hits -system.cpu.dcache.overall_hits::total 4807 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 336 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 336 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1044 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1044 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1044 # number of overall misses -system.cpu.dcache.overall_misses::total 1044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24770500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24770500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 51632692 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 51632692 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76403192 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76403192 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76403192 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76403192 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 4121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 212.136486 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.051791 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.051791 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 12242 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 12242 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3896 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1024 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4920 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4920 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4920 # number of overall hits +system.cpu.dcache.overall_hits::total 4920 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 321 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 321 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 706 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 706 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses +system.cpu.dcache.overall_misses::total 1027 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23379250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23379250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 51507169 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 51507169 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74886419 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74886419 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74886419 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74886419 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4217 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4217 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5851 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5851 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5851 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5851 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081534 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081534 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.178431 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.178431 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.178431 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.178431 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73721.726190 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73721.726190 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72927.531073 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72927.531073 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73183.134100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73183.134100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73183.134100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73183.134100 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4134 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5947 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5947 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5947 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5947 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076120 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076120 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.408092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.172692 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172692 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172692 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172692 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72832.554517 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72832.554517 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72956.330028 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72956.330028 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72917.642648 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72917.642648 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72917.642648 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72917.642648 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5674 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 118 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.033898 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.820144 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 131 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 131 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 694 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 694 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 694 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 694 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17244500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17244500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11834247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11834247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29078747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29078747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29078747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29078747 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.049745 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.049745 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84119.512195 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84119.512195 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81615.496552 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81615.496552 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83082.134286 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83082.134286 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83082.134286 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83082.134286 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 560 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 679 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 679 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 679 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 679 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16537500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16537500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11999490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11999490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28536990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28536990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047901 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047901 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058517 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.058517 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058517 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.058517 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81868.811881 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81868.811881 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82188.287671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82188.287671 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.844828 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.844828 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.844828 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.844828 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index d600e3436..07c326366 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26706500 # Number of ticks simulated -final_tick 26706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000026 # Number of seconds simulated +sim_ticks 25944000 # Number of ticks simulated +final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22395 # Simulator instruction rate (inst/s) -host_op_rate 22394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41428038 # Simulator tick rate (ticks/s) -host_mem_usage 228784 # Number of bytes of host memory used -host_seconds 0.64 # Real time elapsed on the host +host_inst_rate 14664 # Simulator instruction rate (inst/s) +host_op_rate 14664 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26353337 # Simulator tick rate (ticks/s) +host_mem_usage 237548 # Number of bytes of host memory used +host_seconds 0.98 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 805197237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 352273791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1157471028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 805197237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 805197237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 805197237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 352273791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1157471028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 483 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory +system.physmem.bytes_read::total 31488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22016 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory +system.physmem.num_reads::total 492 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 848596978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 365094049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1213691027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 848596978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 848596978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 848596978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 365094049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1213691027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 492 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 483 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30912 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30912 # Total read bytes from the system interface side +system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 102 # Per bank write bursts -system.physmem.perBankRdBursts::1 29 # Per bank write bursts +system.physmem.perBankRdBursts::0 107 # Per bank write bursts +system.physmem.perBankRdBursts::1 28 # Per bank write bursts system.physmem.perBankRdBursts::2 51 # Per bank write bursts system.physmem.perBankRdBursts::3 24 # Per bank write bursts -system.physmem.perBankRdBursts::4 19 # Per bank write bursts +system.physmem.perBankRdBursts::4 20 # Per bank write bursts system.physmem.perBankRdBursts::5 0 # Per bank write bursts system.physmem.perBankRdBursts::6 32 # Per bank write bursts system.physmem.perBankRdBursts::7 35 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::9 2 # Per bank write bursts system.physmem.perBankRdBursts::10 1 # Per bank write bursts system.physmem.perBankRdBursts::11 0 # Per bank write bursts system.physmem.perBankRdBursts::12 57 # Per bank write bursts system.physmem.perBankRdBursts::13 31 # Per bank write bursts system.physmem.perBankRdBursts::14 61 # Per bank write bursts -system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankRdBursts::15 39 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26545500 # Total gap between requests +system.physmem.totGap 25892500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 483 # Read request sizes (log2) +system.physmem.readPktSize::6 492 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,299 +186,299 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.114286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 265.832819 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.256092 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22 31.43% 48.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 12.86% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 4.29% 65.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.71% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.29% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 7.14% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.86% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation -system.physmem.totQLat 2649500 # Total ticks spent queuing -system.physmem.totMemAccLat 11705750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5485.51 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 72 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.444444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 264.526762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 350.678412 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 16.67% 16.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 24 33.33% 50.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation +system.physmem.totQLat 2648500 # Total ticks spent queuing +system.physmem.totMemAccLat 11873500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5383.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24235.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1157.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24133.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1157.47 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.04 # Data bus utilization in percentage -system.physmem.busUtilRead 9.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.48 # Data bus utilization in percentage +system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 404 # Number of row buffer hits during reads +system.physmem.readRowHits 411 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54959.63 # Average gap between requests -system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1553250 # Time in different power states +system.physmem.avgGap 52627.03 # Average gap between requests +system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 279250 # Time in different power states system.physmem.memoryStateTime::REF 780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 21299250 # Time in different power states +system.physmem.memoryStateTime::ACT 22761250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1157471028 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 400 # Transaction distribution -system.membus.trans_dist::ReadResp 400 # Transaction distribution +system.membus.throughput 1211224175 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409 # Transaction distribution +system.membus.trans_dist::ReadResp 408 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 966 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 966 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30912 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 31424 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4506000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 16.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 6723 # Number of BP lookups -system.cpu.branchPred.condPredicted 4462 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5029 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2435 # Number of BTB hits +system.cpu.branchPred.lookups 8578 # Number of BP lookups +system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3046 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.419169 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 53414 # number of cpu cycles simulated +system.cpu.numCycles 51889 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12428 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31151 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6723 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2879 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9139 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3047 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8960 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33327 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.934708 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.127415 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed +system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2310 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24188 72.58% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4512 13.54% 86.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 474 1.42% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 392 1.18% 88.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 683 2.05% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 706 2.12% 92.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.71% 93.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 253 0.76% 94.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1884 5.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33327 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125866 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.583199 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12851 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10052 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8399 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 150 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1875 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29050 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13476 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 163 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9186 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7977 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 650 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26689 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 339 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 23975 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49504 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 40958 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 6844 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 6918 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10156 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 691 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2667 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2291 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 768 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22544 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21140 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7925 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5519 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33327 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.634321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.264898 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24173 72.53% 72.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3454 10.36% 82.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2274 6.82% 89.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1733 5.20% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 917 2.75% 97.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 470 1.41% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 241 0.72% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33327 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 17.69% 48.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15664 74.10% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3362 15.90% 90.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2114 10.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21140 # Type of FU issued -system.cpu.iq.rate 0.395776 # Inst issue rate -system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006954 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75851 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31150 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19533 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21921 # Type of FU issued +system.cpu.iq.rate 0.422459 # Inst issue rate +system.cpu.iq.fu_busy_cnt 226 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21287 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 843 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1875 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24333 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2291 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 947 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1211 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20085 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1055 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1134 # number of nop insts executed -system.cpu.iew.exec_refs 5227 # number of memory reference insts executed -system.cpu.iew.exec_branches 4240 # Number of branches executed -system.cpu.iew.exec_stores 2025 # Number of stores executed -system.cpu.iew.exec_rate 0.376025 # Inst execution rate -system.cpu.iew.wb_sent 19760 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19533 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9201 # num instructions producing a value -system.cpu.iew.wb_consumers 11404 # num instructions consuming a value +system.cpu.iew.exec_nop 1127 # number of nop insts executed +system.cpu.iew.exec_refs 5373 # number of memory reference insts executed +system.cpu.iew.exec_branches 4425 # Number of branches executed +system.cpu.iew.exec_stores 2024 # Number of stores executed +system.cpu.iew.exec_rate 0.402956 # Inst execution rate +system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 20237 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9846 # num instructions producing a value +system.cpu.iew.wb_consumers 12767 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.365691 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.806822 # average fanout of values written-back +system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9073 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31452 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.482068 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.184176 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24226 77.03% 77.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3950 12.56% 89.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1330 4.23% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 819 2.60% 96.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 349 1.11% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 271 0.86% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 322 1.02% 99.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -524,209 +524,209 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54747 # The number of ROB reads -system.cpu.rob.rob_writes 50353 # The number of ROB writes -system.cpu.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20087 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54809 # The number of ROB reads +system.cpu.rob.rob_writes 52996 # The number of ROB writes +system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.700055 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.700055 # CPI: Total CPI of All Threads -system.cpu.ipc 0.270266 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.270266 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32058 # number of integer regfile reads -system.cpu.int_regfile_writes 17849 # number of integer regfile writes -system.cpu.misc_regfile_reads 6922 # number of misc regfile reads +system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads +system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 33400 # number of integer regfile reads +system.cpu.int_regfile_writes 18599 # number of integer regfile writes +system.cpu.misc_regfile_reads 7136 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1162263868 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution +system.cpu.toL2Bus.throughput 1216157879 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 31040 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 31552 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 566000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 188.199882 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.414201 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 192.510615 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 188.199882 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091894 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091894 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.165039 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11098 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11098 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits -system.cpu.icache.overall_hits::total 4872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 508 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 508 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 508 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 508 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 508 # number of overall misses -system.cpu.icache.overall_misses::total 508 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31702750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31702750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31702750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31702750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31702750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31702750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094424 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094424 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094424 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094424 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094424 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094424 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62406.988189 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62406.988189 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62406.988189 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62406.988189 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62406.988189 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62406.988189 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 192.510615 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13252 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits +system.cpu.icache.overall_hits::total 5925 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses +system.cpu.icache.overall_misses::total 528 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32454000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32454000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32454000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32454000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32454000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32454000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61465.909091 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61465.909091 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 170 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 170 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 170 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22584000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22584000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22584000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22584000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22584000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22584000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062825 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.062825 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.062825 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66816.568047 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66816.568047 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66816.568047 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66816.568047 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66816.568047 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66816.568047 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 182 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 182 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23048750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23048750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23048750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23048750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23048750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23048750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66614.884393 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66614.884393 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 222.048188 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.592876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.455312 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005725 # Average percentage of cache occupancy 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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66148.809524 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72457.031250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.125000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73195.783133 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73195.783133 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66148.809524 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72874.149660 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68195.652174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66148.809524 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72874.149660 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68195.652174 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.773256 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71807.692308 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -735,166 +735,166 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of 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3880500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18356250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18356250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles 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occupancy -system.cpu.dcache.tags.occ_percent::total 0.024183 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.823641 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9219 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9219 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3995 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3995 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3995 # number of overall hits -system.cpu.dcache.overall_hits::total 3995 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits +system.cpu.dcache.overall_hits::total 4118 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses -system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7969250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7969250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25782224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25782224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33751474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33751474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33751474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33751474 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses +system.cpu.dcache.overall_misses::total 548 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8661750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8661750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34754974 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34754974 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34754974 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34754974 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4530 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4530 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4530 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4530 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63248.015873 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63248.015873 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63037.222494 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63037.222494 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63086.867290 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63086.867290 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63086.867290 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63086.867290 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 851 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63421.485401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63421.485401 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.392857 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 388 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 388 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 388 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4701750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4701750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6159250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6159250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10861000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10861000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4732000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4732000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10967500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10967500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10967500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10967500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73464.843750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73464.843750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74207.831325 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74207.831325 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73884.353741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73884.353741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73884.353741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73884.353741 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72800 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index f14e8cf51..3dcd489a6 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 110970500 # Number of ticks simulated -final_tick 110970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000106 # Number of seconds simulated +sim_ticks 105639000 # Number of ticks simulated +final_tick 105639000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128659 # Simulator instruction rate (inst/s) -host_op_rate 128659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13699808 # Simulator tick rate (ticks/s) -host_mem_usage 244656 # Number of bytes of host memory used -host_seconds 8.10 # Real time elapsed on the host -sim_insts 1042156 # Number of instructions simulated -sim_ops 1042156 # Number of ops (including micro ops) simulated +host_inst_rate 115016 # Simulator instruction rate (inst/s) +host_op_rate 115016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12246117 # Simulator tick rate (ticks/s) +host_mem_usage 253808 # Number of bytes of host memory used +host_seconds 8.63 # Real time elapsed on the host +sim_insts 992165 # Number of instructions simulated +sim_ops 992165 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4928 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4608 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 42752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4928 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 77 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205315827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 96890615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 7497488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7497488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 41524549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11534597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2306919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7497488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380064972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205315827 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 7497488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 41524549 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2306919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 256644784 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205315827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 96890615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 7497488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7497488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 41524549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11534597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2306919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7497488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380064972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 660 # Number of read requests accepted +system.physmem.num_reads::total 668 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 218707106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101780592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 7270042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7875879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 46649438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 12116737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2423347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7875879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 404699022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 218707106 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 7270042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 46649438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2423347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 275049934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 218707106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101780592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 7270042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7875879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 46649438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 12116737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2423347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7875879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 404699022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 669 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 669 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 42816 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side +system.physmem.bytesReadSys 42816 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 77 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 115 # Per bank write bursts -system.physmem.perBankRdBursts::1 39 # Per bank write bursts -system.physmem.perBankRdBursts::2 29 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 114 # Per bank write bursts +system.physmem.perBankRdBursts::1 42 # Per bank write bursts +system.physmem.perBankRdBursts::2 30 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts system.physmem.perBankRdBursts::4 65 # Per bank write bursts -system.physmem.perBankRdBursts::5 27 # Per bank write bursts +system.physmem.perBankRdBursts::5 28 # Per bank write bursts system.physmem.perBankRdBursts::6 18 # Per bank write bursts system.physmem.perBankRdBursts::7 24 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts system.physmem.perBankRdBursts::9 28 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts -system.physmem.perBankRdBursts::11 12 # Per bank write bursts -system.physmem.perBankRdBursts::12 60 # Per bank write bursts +system.physmem.perBankRdBursts::11 13 # Per bank write bursts +system.physmem.perBankRdBursts::12 65 # Per bank write bursts system.physmem.perBankRdBursts::13 38 # Per bank write bursts system.physmem.perBankRdBursts::14 17 # Per bank write bursts -system.physmem.perBankRdBursts::15 98 # Per bank write bursts +system.physmem.perBankRdBursts::15 97 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 110942500 # Total gap between requests +system.physmem.totGap 105611000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 660 # Read request sizes (log2) +system.physmem.readPktSize::6 669 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -121,11 +121,11 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -216,305 +216,305 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 274.594595 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.768834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.591879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47 31.76% 31.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 26.35% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 23 15.54% 73.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 3.38% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation -system.physmem.totQLat 5904750 # Total ticks spent queuing -system.physmem.totMemAccLat 18279750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8946.59 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 278.222222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.203281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.152031 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39 27.08% 56.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24 16.67% 73.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 13 9.03% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 4.17% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 4.17% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 4.17% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.39% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation +system.physmem.totQLat 6117250 # Total ticks spent queuing +system.physmem.totMemAccLat 18661000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9143.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27696.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27893.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 405.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 405.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.97 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.17 # Data bus utilization in percentage +system.physmem.busUtilRead 3.17 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 505 # Number of row buffer hits during reads +system.physmem.readRowHits 514 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 168094.70 # Average gap between requests -system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 48408000 # Time in different power states -system.physmem.memoryStateTime::REF 3640000 # Time in different power states +system.physmem.avgGap 157863.98 # Average gap between requests +system.physmem.pageHitRate 76.83 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 46009250 # Time in different power states +system.physmem.memoryStateTime::REF 3380000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 57233250 # Time in different power states +system.physmem.memoryStateTime::ACT 52645250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 380064972 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 529 # Transaction distribution -system.membus.trans_dist::ReadResp 528 # Transaction distribution -system.membus.trans_dist::UpgradeReq 287 # Transaction distribution -system.membus.trans_dist::UpgradeResp 77 # Transaction distribution -system.membus.trans_dist::ReadExReq 162 # Transaction distribution +system.membus.throughput 404699022 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 538 # Transaction distribution +system.membus.trans_dist::ReadResp 537 # Transaction distribution +system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 78 # Transaction distribution +system.membus.trans_dist::ReadExReq 182 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 42176 # Total data (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1738 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 42752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 921500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6294424 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 937500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 6389922 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 416.952741 # Cycle average of tags in use -system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 424.251527 # Cycle average of tags in use +system.l2c.tags.total_refs 1658 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 535 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.099065 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.799591 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 285.006820 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.406933 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 8.706163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.731992 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 54.635838 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.407858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.562888 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.694658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.793481 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 289.756161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.232417 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 9.250622 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.723175 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 57.184063 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.359898 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.266069 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.685642 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004349 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000133 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004421 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000141 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000834 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000039 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006362 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18236 # Number of tag accesses -system.l2c.tags.data_accesses 18236 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu2.inst 0.000873 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006474 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 535 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008163 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 20037 # Number of tag accesses +system.l2c.tags.data_accesses 20037 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 250 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 409 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 481 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 423 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 486 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1658 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 250 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 481 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 11 # number 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accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.030374 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024145 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.169811 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.157143 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009302 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.008114 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.311909 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.286020 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.030374 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024145 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.169811 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.157143 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009302 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.008114 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.311909 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60263.513514 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.286020 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64057.432432 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 64625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57191.871456 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 58597.583643 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10405.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.376623 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62680.851064 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61916.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 92076.923077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 59416.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 65229.007634 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61616.071429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61961.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80287.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59653.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58787.121212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61616.071429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61961.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80287.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59653.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58787.121212 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58437.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 57250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61358.778626 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62510.416667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59138.266069 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56542.817680 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62510.416667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59938.311688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59138.266069 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1688665006 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution +system.toL2Bus.throughput 1921108681 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2758 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2757 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 358 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5414 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 413 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 413 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1225 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 135424 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1625975 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2708248 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1463019 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1929745 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1153498 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1921995 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1183735 # Layer occupancy (ticks) +system.toL2Bus.tot_pkt_size::total 149696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 149696 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 53248 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1733986 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2820249 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1469763 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 2240244 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1184253 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 2220245 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 1188993 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1936494 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1159999 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 83070 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80870 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80399 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78350 # Number of BTB hits +system.toL2Bus.respLayer6.occupancy 2220246 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1196995 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) +system.cpu0.branchPred.lookups 81365 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78481 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1187 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 78090 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75342 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.451461 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 96.480983 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 733 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 221942 # number of cpu cycles simulated +system.cpu0.numCycles 211279 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17233 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 493008 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 83070 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78862 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161826 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3812 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13755 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1482 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 491 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196747 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.505797 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.214858 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 20058 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 480743 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81365 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76075 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 164045 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2674 # Number of cycles fetch has spent squashing +system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 658 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 187323 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.566385 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.225399 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34921 17.75% 17.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 80152 40.74% 58.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 578 0.29% 58.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 974 0.50% 59.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 477 0.24% 59.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76267 38.76% 98.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2459 1.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30153 16.10% 16.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77599 41.43% 57.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 823 0.44% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1078 0.58% 58.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 72927 38.93% 97.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 691 0.37% 98.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 437 0.23% 98.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2991 1.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196747 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.374287 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.221337 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17711 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15452 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160920 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 218 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2446 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 490118 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2446 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18323 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 441 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14289 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160585 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 663 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 487271 # Number of instructions processed by rename -system.cpu0.rename.SQFullEvents 294 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 333181 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 971741 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 733988 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 320207 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12974 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 868 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 890 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3239 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155891 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78785 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 76033 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75852 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 407472 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 912 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 404753 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 136 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10781 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9726 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 353 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196747 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.057226 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.098946 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 187323 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.385107 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.275394 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15731 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 17849 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 151731 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 675 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1337 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 468882 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1337 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16349 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2025 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14605 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 151742 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1265 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 465427 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 318792 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 928161 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 701504 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 304835 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13957 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 896 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 905 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4588 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148468 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75131 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72391 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72142 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 389496 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 964 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 386182 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 12213 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11099 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 405 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 187323 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.061583 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.125394 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34174 17.37% 17.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4673 2.38% 19.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77781 39.53% 59.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77469 39.37% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1629 0.83% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 654 0.33% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 260 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 91 0.05% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33109 17.67% 17.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4301 2.30% 19.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73576 39.28% 59.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73130 39.04% 98.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1662 0.89% 99.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 894 0.48% 99.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 408 0.22% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 171 0.09% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 72 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196747 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 187323 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 60 26.43% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 55 24.23% 50.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 49.34% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 97 34.15% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 34.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 84 29.58% 63.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 36.27% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 171127 42.28% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155427 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 78199 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 163788 42.41% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.41% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 147930 38.31% 80.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74464 19.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 404753 # Type of FU issued -system.cpu0.iq.rate 1.823688 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 227 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1006616 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 419219 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 402934 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 386182 # Type of FU issued +system.cpu0.iq.rate 1.827830 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 284 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000735 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 959994 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 402726 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 384333 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 404980 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 386466 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75562 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71762 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2461 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 397 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 484968 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 314 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155891 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78785 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 800 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1337 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1986 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 463277 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148468 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75131 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 843 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 403684 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 155095 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 323 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1099 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1422 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 385174 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147630 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76584 # number of nop insts executed -system.cpu0.iew.exec_refs 233191 # number of memory reference insts executed -system.cpu0.iew.exec_branches 80195 # Number of branches executed -system.cpu0.iew.exec_stores 78096 # Number of stores executed -system.cpu0.iew.exec_rate 1.818872 # Inst execution rate -system.cpu0.iew.wb_sent 403263 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 402934 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238926 # num instructions producing a value -system.cpu0.iew.wb_consumers 241439 # num instructions consuming a value +system.cpu0.iew.exec_nop 72817 # number of nop insts executed +system.cpu0.iew.exec_refs 221956 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76403 # Number of branches executed +system.cpu0.iew.exec_stores 74326 # Number of stores executed +system.cpu0.iew.exec_rate 1.823059 # Inst execution rate +system.cpu0.iew.wb_sent 384701 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 384333 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 227933 # num instructions producing a value +system.cpu0.iew.wb_consumers 231165 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.815492 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989592 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.819078 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986019 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12279 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13622 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194301 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432628 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.139595 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1187 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 184699 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.434252 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.147591 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34596 17.81% 17.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79813 41.08% 58.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2261 1.16% 60.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 671 0.35% 60.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 526 0.27% 60.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75370 38.79% 99.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 456 0.23% 99.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 240 0.12% 99.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 368 0.19% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33306 18.03% 18.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75499 40.88% 58.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2011 1.09% 60.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 643 0.35% 60.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71457 38.69% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 519 0.28% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194301 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 472662 # Number of instructions committed -system.cpu0.commit.committedOps 472662 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 184699 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 449604 # Number of instructions committed +system.cpu0.commit.committedOps 449604 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 231046 # Number of memory references committed -system.cpu0.commit.loads 153693 # Number of loads committed +system.cpu0.commit.refs 219517 # Number of memory references committed +system.cpu0.commit.loads 146007 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79240 # Number of branches committed +system.cpu0.commit.branches 75397 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 318538 # Number of committed integer instructions. +system.cpu0.commit.int_insts 303166 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 75972 16.07% 16.07% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 165560 35.03% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 153777 32.53% 83.63% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77353 16.37% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72129 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 157874 35.11% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 146091 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73510 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 472662 # Class of committed instruction -system.cpu0.commit.bw_lim_events 368 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 449604 # Class of committed instruction +system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 677713 # The number of ROB reads -system.cpu0.rob.rob_writes 972345 # The number of ROB writes -system.cpu0.timesIdled 334 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25195 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 396606 # Number of Instructions Simulated -system.cpu0.committedOps 396606 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.559603 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559603 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.786980 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.786980 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 722190 # number of integer regfile reads -system.cpu0.int_regfile_writes 325483 # number of integer regfile writes +system.cpu0.rob.rob_reads 646276 # The number of ROB reads +system.cpu0.rob.rob_writes 929096 # The number of ROB writes +system.cpu0.timesIdled 317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23956 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 377391 # Number of Instructions Simulated +system.cpu0.committedOps 377391 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.559841 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559841 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.786221 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.786221 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 688854 # number of integer regfile reads +system.cpu0.int_regfile_writes 310766 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 235015 # number of misc regfile reads +system.cpu0.misc_regfile_reads 223843 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.252317 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 322 # number of replacements +system.cpu0.icache.tags.tagsinuse 240.566848 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6326 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 612 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.336601 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.252317 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471196 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471196 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.566848 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469857 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.469857 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 6422 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 6422 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits -system.cpu0.icache.overall_hits::total 5079 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses -system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35519995 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35519995 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35519995 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35519995 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35519995 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35519995 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46984.120370 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46984.120370 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46984.120370 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46984.120370 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46984.120370 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46984.120370 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 7735 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7735 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6326 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6326 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6326 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6326 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6326 # number of overall hits +system.cpu0.icache.overall_hits::total 6326 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses +system.cpu0.icache.overall_misses::total 797 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36681496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 36681496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 36681496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 36681496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 36681496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 36681496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7123 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7123 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7123 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7123 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7123 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7123 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111891 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111891 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111891 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111891 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111891 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111891 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46024.461731 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46024.461731 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46024.461731 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46024.461731 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46024.461731 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46024.461731 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27366252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27366252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27366252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27366252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27366252 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27366252 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46541.244898 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 46541.244898 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 46541.244898 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 613 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 613 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 613 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 613 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 613 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 613 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 28176251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 28176251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 28176251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 28176251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 28176251 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 28176251 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45964.520392 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 45964.520392 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45964.520392 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 45964.520392 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.985956 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155741 # Total number of references to valid blocks. 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occupancy +system.cpu0.dcache.tags.occ_percent::total 0.276397 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 627612 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 627612 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79059 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79059 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76768 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76768 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155827 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155827 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155827 # number of overall hits -system.cpu0.dcache.overall_hits::total 155827 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 413 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 413 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 956 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 956 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 956 # number of overall misses -system.cpu0.dcache.overall_misses::total 956 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 12955987 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12955987 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33432506 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 33432506 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 46388493 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 46388493 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 46388493 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 46388493 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79472 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79472 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77311 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77311 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 597526 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 597526 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75309 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75309 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72924 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72924 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148233 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 148233 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148233 # number of overall hits +system.cpu0.dcache.overall_hits::total 148233 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 484 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 484 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1028 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1028 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1028 # number of overall misses +system.cpu0.dcache.overall_misses::total 1028 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15258131 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 15258131 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32871763 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32871763 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 427750 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 427750 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 48129894 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 48129894 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 48129894 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 48129894 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75793 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75793 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73468 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73468 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156783 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156783 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156783 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156783 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005197 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005197 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007024 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007024 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006098 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006098 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006098 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006098 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31370.428571 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31370.428571 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 61569.992634 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 61569.992634 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48523.528243 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 48523.528243 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48523.528243 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 48523.528243 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 149261 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149261 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 149261 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 149261 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006386 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006386 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007405 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007405 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006887 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006887 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006887 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006887 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31525.064050 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31525.064050 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60426.034926 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 60426.034926 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46818.963035 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46818.963035 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46818.963035 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46818.963035 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.833333 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 226 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 594 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 594 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 301 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 666 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 666 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 666 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 666 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5995003 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5995003 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7531728 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7531728 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13526731 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13526731 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13526731 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13526731 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002353 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002353 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002264 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32058.839572 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32058.839572 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43038.445714 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43038.445714 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37366.660221 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37366.660221 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37366.660221 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37366.660221 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6274260 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6274260 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7393227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7393227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 382250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 382250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13667487 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13667487 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13667487 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13667487 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002414 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002414 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002425 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002425 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002425 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002425 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34285.573770 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34285.573770 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41302.944134 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41302.944134 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17375 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17375 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37755.488950 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37755.488950 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37755.488950 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37755.488950 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52187 # Number of BP lookups -system.cpu1.branchPred.condPredicted 49510 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1259 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46153 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 45385 # Number of BTB hits +system.cpu1.branchPred.lookups 54588 # Number of BP lookups +system.cpu1.branchPred.condPredicted 51200 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1286 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 47257 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 46317 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.335969 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 643 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 177799 # number of cpu cycles simulated +system.cpu1.branchPred.BTBHitPct 98.010877 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 875 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu1.numCycles 167979 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 28925 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 291186 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52187 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46028 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 103264 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3653 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 32544 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7803 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 20583 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 175643 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.657829 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.130344 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 29917 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 303462 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 54588 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 47192 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 126841 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2730 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 7060 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 21062 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 421 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 166282 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.824984 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.191628 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 72379 41.21% 41.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52711 30.01% 71.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6570 3.74% 74.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3206 1.83% 76.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 681 0.39% 77.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 34861 19.85% 97.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1219 0.69% 97.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 754 0.43% 98.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3262 1.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 60365 36.30% 36.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 53424 32.13% 68.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6309 3.79% 72.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3483 2.09% 74.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1022 0.61% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 35711 21.48% 96.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1327 0.80% 97.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 762 0.46% 97.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3879 2.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 175643 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.293517 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.637726 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 34549 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 28563 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 96884 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5527 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2317 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 287488 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2317 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 35238 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 16093 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11725 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 91623 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 10844 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 285400 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RenamedOperands 199084 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 545686 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 424083 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 186368 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12716 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1090 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1211 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13408 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 80706 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38119 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 38742 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 33075 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 236041 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6768 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 238678 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10581 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10451 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 175643 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.358881 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.308073 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 166282 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.324969 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.806547 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17455 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 52641 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 84496 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3265 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1365 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 289136 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1365 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18178 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 24205 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 12371 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 85331 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 17772 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 285586 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15350 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 200979 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 548958 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 426905 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 186309 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14670 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1186 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 22653 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 80668 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38514 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 38418 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 33330 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 237514 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6089 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 238789 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11558 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 166282 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.436048 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.378738 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 69713 39.69% 39.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 23816 13.56% 53.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 38346 21.83% 75.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 38982 22.19% 97.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1165 0.66% 99.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 266 0.15% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 63923 38.44% 38.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20825 12.52% 50.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 37813 22.74% 73.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 37389 22.49% 96.19% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3420 2.06% 98.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1614 0.97% 99.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 862 0.52% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 239 0.14% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 175643 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 166282 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 6.42% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 38 14.34% 20.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 79.25% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 89 25.65% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 49 14.12% 39.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 60.23% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 115728 48.49% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.49% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 85517 35.83% 84.32% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37433 15.68% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 116312 48.71% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 84679 35.46% 84.17% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37798 15.83% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 238678 # Type of FU issued -system.cpu1.iq.rate 1.342404 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 265 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001110 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 653323 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 253430 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 236861 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 238789 # Type of FU issued +system.cpu1.iq.rate 1.421541 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 347 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001453 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 644240 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 256392 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 237045 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 238943 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 239136 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 32850 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 33095 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2336 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2693 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1422 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2317 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 666 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 282498 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 80706 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38119 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1050 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1365 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6579 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 282823 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 167 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 80668 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38514 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1105 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 907 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 237512 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 79760 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1037 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1507 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 237631 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 79596 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 39689 # number of nop insts executed -system.cpu1.iew.exec_refs 117113 # number of memory reference insts executed -system.cpu1.iew.exec_branches 48963 # Number of branches executed -system.cpu1.iew.exec_stores 37353 # Number of stores executed -system.cpu1.iew.exec_rate 1.335846 # Inst execution rate -system.cpu1.iew.wb_sent 237151 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 236861 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 133843 # num instructions producing a value -system.cpu1.iew.wb_consumers 138503 # num instructions consuming a value +system.cpu1.iew.exec_nop 39220 # number of nop insts executed +system.cpu1.iew.exec_refs 117284 # number of memory reference insts executed +system.cpu1.iew.exec_branches 48640 # Number of branches executed +system.cpu1.iew.exec_stores 37688 # Number of stores executed +system.cpu1.iew.exec_rate 1.414647 # Inst execution rate +system.cpu1.iew.wb_sent 237349 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 237045 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 134973 # num instructions producing a value +system.cpu1.iew.wb_consumers 141559 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.332184 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.966355 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.411159 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.953475 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12124 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6196 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1259 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 165523 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.633344 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.016153 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14310 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5477 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1286 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 156616 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.714129 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.075319 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 67946 41.05% 41.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47096 28.45% 69.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6082 3.67% 73.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7142 4.31% 77.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1575 0.95% 78.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 33355 20.15% 98.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1001 0.60% 99.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61979 39.57% 39.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 45369 28.97% 68.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5243 3.35% 71.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6285 4.01% 75.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1549 0.99% 76.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 33128 21.15% 98.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 818 0.52% 98.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 954 0.61% 99.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1291 0.82% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 165523 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 270356 # Number of instructions committed -system.cpu1.commit.committedOps 270356 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 156616 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 268460 # Number of instructions committed +system.cpu1.commit.committedOps 268460 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 115067 # Number of memory references committed -system.cpu1.commit.loads 78370 # Number of loads committed -system.cpu1.commit.membars 5484 # Number of memory barriers committed -system.cpu1.commit.branches 48146 # Number of branches committed +system.cpu1.commit.refs 114842 # Number of memory references committed +system.cpu1.commit.loads 77975 # Number of loads committed +system.cpu1.commit.membars 4761 # Number of memory barriers committed +system.cpu1.commit.branches 47591 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 185335 # Number of committed integer instructions. +system.cpu1.commit.int_insts 184553 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 38938 14.40% 14.40% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 110867 41.01% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.41% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 83854 31.02% 86.43% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 36697 13.57% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 38379 14.30% 14.30% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 110478 41.15% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.45% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82736 30.82% 86.27% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 36867 13.73% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 270356 # Class of committed instruction -system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 268460 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1291 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 446600 # The number of ROB reads -system.cpu1.rob.rob_writes 567283 # The number of ROB writes -system.cpu1.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2156 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 44141 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 225934 # Number of Instructions Simulated -system.cpu1.committedOps 225934 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.786951 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.786951 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.270727 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.270727 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 409872 # number of integer regfile reads -system.cpu1.int_regfile_writes 191136 # number of integer regfile writes +system.cpu1.rob.rob_reads 437508 # The number of ROB reads +system.cpu1.rob.rob_writes 568153 # The number of ROB writes +system.cpu1.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1697 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 225320 # Number of Instructions Simulated +system.cpu1.committedOps 225320 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.745513 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.745513 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.341358 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.341358 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 411671 # number of integer regfile reads +system.cpu1.int_regfile_writes 192443 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 118682 # number of misc regfile reads +system.cpu1.misc_regfile_reads 118908 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 79.885573 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20107 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 46.978972 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 388 # number of replacements +system.cpu1.icache.tags.tagsinuse 78.688259 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20497 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 41.241449 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.885573 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.156027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21011 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21011 # Number of data accesses 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of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7353244 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7353244 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7353244 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7353244 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7353244 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20583 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20583 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20583 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20583 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20583 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20583 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023126 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023126 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023126 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023126 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023126 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023126 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15447.991597 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15447.991597 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15447.991597 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15447.991597 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15447.991597 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15447.991597 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.tags.occ_blocks::cpu1.inst 78.688259 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.153688 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.153688 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 21559 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21559 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20497 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20497 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20497 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20497 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20497 # number of overall hits +system.cpu1.icache.overall_hits::total 20497 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 565 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 565 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 565 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 565 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 565 # number of overall misses +system.cpu1.icache.overall_misses::total 565 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8463744 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8463744 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8463744 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8463744 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8463744 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8463744 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21062 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21062 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21062 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21062 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21062 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21062 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026826 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.026826 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026826 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.026826 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026826 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.026826 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14980.077876 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14980.077876 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14980.077876 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14980.077876 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14980.077876 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14980.077876 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5927255 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5927255 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5927255 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5927255 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5927255 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5927255 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020794 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.020794 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.020794 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13848.726636 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13848.726636 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13848.726636 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 68 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 68 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 68 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6616756 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6616756 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6616756 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6616756 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6616756 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6616756 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023597 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023597 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13313.392354 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13313.392354 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13313.392354 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13313.392354 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.706566 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 42694 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1524.785714 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 24.399537 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 43036 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1484 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.706566 # Average occupied blocks per requestor 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WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 36631 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 83526 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 83526 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 83526 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 83526 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007506 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.007506 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003822 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003822 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.818182 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005890 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005890 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005890 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005890 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12848.286932 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12848.286932 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21669.728571 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21669.728571 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9916.814815 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9916.814815 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15358.453252 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15358.453252 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15358.453252 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15358.453252 # average overall miss latency +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 567 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 567 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 567 # number of overall misses +system.cpu1.dcache.overall_misses::total 567 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5717104 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5717104 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2840511 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2840511 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 466006 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 466006 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8557615 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8557615 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8557615 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8557615 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 46486 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 46486 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 36797 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 36797 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 83283 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 83283 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 83283 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 83283 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009186 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009186 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003805 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003805 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006808 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006808 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006808 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006808 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13389.002342 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13389.002342 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20289.364286 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20289.364286 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8175.543860 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 8175.543860 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15092.795414 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15092.795414 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15092.795414 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15092.795414 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1726,517 +1729,519 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 195 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 227 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 227 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 157 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1099522 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1099522 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1387488 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1387488 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 427492 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 427492 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2487010 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2487010 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2487010 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2487010 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003348 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002948 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002948 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.818182 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.818182 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003173 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003173 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003173 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003173 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7003.324841 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7003.324841 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12847.111111 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12847.111111 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7916.518519 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7916.518519 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9384.943396 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9384.943396 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9384.943396 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9384.943396 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 269 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 269 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 35 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 304 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 304 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 304 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1020514 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1020514 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1289239 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1289239 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 351994 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 351994 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2309753 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2309753 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2309753 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2309753 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003399 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003399 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003158 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003158 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003158 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003158 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6458.949367 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6458.949367 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12278.466667 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12278.466667 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6175.333333 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6175.333333 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8782.330798 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8782.330798 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8782.330798 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8782.330798 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51191 # Number of BP lookups -system.cpu2.branchPred.condPredicted 48468 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 44993 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 44297 # Number of BTB hits +system.cpu2.branchPred.lookups 50591 # Number of BP lookups +system.cpu2.branchPred.condPredicted 46824 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1298 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 43166 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 41772 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.453093 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 177434 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 96.770606 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu2.numCycles 167617 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28865 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 285908 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51191 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 44981 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 100768 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3816 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31184 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 31796 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 277876 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 50591 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 42676 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 121192 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2752 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7805 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1366 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19788 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172424 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.658168 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.138146 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 7062 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 22366 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 459 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 162543 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.709554 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.176994 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 71656 41.56% 41.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51257 29.73% 71.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6128 3.55% 74.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3186 1.85% 76.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 695 0.40% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 34284 19.88% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1167 0.68% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 773 0.45% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3278 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 64711 39.81% 39.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 49634 30.54% 70.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6798 4.18% 74.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3442 2.12% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 952 0.59% 77.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 30771 18.93% 96.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1187 0.73% 96.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 849 0.52% 97.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 4199 2.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172424 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288507 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.611348 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 34386 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 27902 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 94859 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5040 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2432 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 282267 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2432 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 35111 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14773 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12374 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90050 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 9879 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 280008 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu2.rename.RenamedOperands 196247 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 536665 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 417354 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 183125 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13122 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1115 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12503 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79020 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 37489 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 37725 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 32426 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 232155 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6357 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234096 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11107 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11056 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 607 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172424 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.357676 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.313193 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 162543 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.301825 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.657803 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17997 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 57677 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 74910 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3521 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1376 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 262355 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1376 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18679 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 27128 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12799 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 76466 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 19033 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 259235 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 17033 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 182575 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 494395 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 386046 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 167620 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14955 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1235 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 23554 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 71776 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33725 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34298 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 28594 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 214929 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6621 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 216336 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13228 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 162543 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.330946 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.384454 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 69134 40.10% 40.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22467 13.03% 53.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37714 21.87% 75.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38330 22.23% 97.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3239 1.88% 99.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1151 0.67% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68368 42.06% 42.06% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22285 13.71% 55.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 32950 20.27% 76.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 32546 20.02% 96.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3459 2.13% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1594 0.98% 99.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 245 0.15% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172424 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 162543 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 12 4.40% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 51 18.68% 23.08% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 76.92% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 90 24.93% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 62 17.17% 42.11% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 57.89% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114033 48.71% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83276 35.57% 84.29% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 36787 15.71% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 107190 49.55% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.55% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 76124 35.19% 84.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 33022 15.26% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234096 # Type of FU issued -system.cpu2.iq.rate 1.319341 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 273 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001166 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 640996 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 249665 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 232273 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 216336 # Type of FU issued +system.cpu2.iq.rate 1.290657 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 361 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001669 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 595623 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 234822 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 214628 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 234369 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 216697 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 32149 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28314 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2502 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2909 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1485 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1648 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2432 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 787 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277138 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79020 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 37489 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1072 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1376 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 7567 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 67 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 256538 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 192 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 71776 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33725 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1099 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 971 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1435 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 232944 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77967 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1152 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1533 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 215226 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 70571 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 38626 # number of nop insts executed -system.cpu2.iew.exec_refs 114664 # number of memory reference insts executed -system.cpu2.iew.exec_branches 47841 # Number of branches executed -system.cpu2.iew.exec_stores 36697 # Number of stores executed -system.cpu2.iew.exec_rate 1.312849 # Inst execution rate -system.cpu2.iew.wb_sent 232563 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 232273 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 131430 # num instructions producing a value -system.cpu2.iew.wb_consumers 136123 # num instructions consuming a value +system.cpu2.iew.exec_nop 34988 # number of nop insts executed +system.cpu2.iew.exec_refs 103485 # number of memory reference insts executed +system.cpu2.iew.exec_branches 44292 # Number of branches executed +system.cpu2.iew.exec_stores 32914 # Number of stores executed +system.cpu2.iew.exec_rate 1.284034 # Inst execution rate +system.cpu2.iew.wb_sent 214935 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 214628 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 121102 # num instructions producing a value +system.cpu2.iew.wb_consumers 127756 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.309067 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.965524 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.280467 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.947916 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12771 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5750 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 162187 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.630001 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.017893 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14883 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5947 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1298 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152800 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.581165 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.037167 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 66847 41.22% 41.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46010 28.37% 69.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6109 3.77% 73.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6666 4.11% 77.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1557 0.96% 78.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 32708 20.17% 98.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 471 0.29% 98.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1007 0.62% 99.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 66891 43.78% 43.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 41018 26.84% 70.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5166 3.38% 74.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6776 4.43% 78.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1516 0.99% 79.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28304 18.52% 97.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 869 0.57% 98.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 954 0.62% 99.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1306 0.85% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 162187 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 264365 # Number of instructions committed -system.cpu2.commit.committedOps 264365 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152800 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 241602 # Number of instructions committed +system.cpu2.commit.committedOps 241602 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 112522 # Number of memory references committed -system.cpu2.commit.loads 76518 # Number of loads committed -system.cpu2.commit.membars 5033 # Number of memory barriers committed -system.cpu2.commit.branches 47000 # Number of branches committed +system.cpu2.commit.refs 100944 # Number of memory references committed +system.cpu2.commit.loads 68867 # Number of loads committed +system.cpu2.commit.membars 5232 # Number of memory barriers committed +system.cpu2.commit.branches 43270 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 181641 # Number of committed integer instructions. +system.cpu2.commit.int_insts 166336 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 37787 14.29% 14.29% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 109023 41.24% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 81551 30.85% 86.38% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 36004 13.62% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 34059 14.10% 14.10% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 101367 41.96% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 74099 30.67% 86.72% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 32077 13.28% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 264365 # Class of committed instruction -system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 241602 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1306 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 437924 # The number of ROB reads -system.cpu2.rob.rob_writes 556709 # The number of ROB writes -system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5010 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44506 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 221545 # Number of Instructions Simulated -system.cpu2.committedOps 221545 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.800894 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.800894 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.248605 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.248605 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 402715 # number of integer regfile reads -system.cpu2.int_regfile_writes 188101 # number of integer regfile writes +system.cpu2.rob.rob_reads 407392 # The number of ROB reads +system.cpu2.rob.rob_writes 515662 # The number of ROB writes +system.cpu2.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 43660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 202311 # Number of Instructions Simulated +system.cpu2.committedOps 202311 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.828512 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.828512 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.206984 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.206984 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 370344 # number of integer regfile reads +system.cpu2.int_regfile_writes 173891 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 116228 # number of misc regfile reads +system.cpu2.misc_regfile_reads 105089 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 81.450670 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19300 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 424 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.518868 # Average number of references to valid blocks. +system.cpu2.icache.tags.replacements 378 # number of replacements +system.cpu2.icache.tags.tagsinuse 84.908829 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 21796 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 44.481633 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 81.450670 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.159083 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.159083 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 107 # Occupied blocks per task id +system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.908829 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165838 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.165838 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.208984 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 20212 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 20212 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 19300 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19300 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19300 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19300 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19300 # number of overall hits -system.cpu2.icache.overall_hits::total 19300 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 488 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 488 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 488 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 488 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 488 # number of overall misses -system.cpu2.icache.overall_misses::total 488 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11534741 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11534741 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11534741 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11534741 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11534741 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11534741 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19788 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19788 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19788 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19788 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19788 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19788 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024661 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024661 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024661 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024661 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024661 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024661 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23636.764344 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+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3658011 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3658011 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 499506 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 499506 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 10949570 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 10949570 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 10949570 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 10949570 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42239 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42239 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 32008 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 32008 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 74247 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 74247 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 74247 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 74247 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009991 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009991 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004561 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004561 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.797101 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007650 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007650 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007650 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007650 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17278.575829 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17278.575829 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25054.869863 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 25054.869863 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9081.927273 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9081.927273 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19277.411972 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 19277.411972 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19277.411972 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 19277.411972 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2245,404 +2250,405 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 184 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 217 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 217 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 261 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 261 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 40 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 301 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 301 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1467781 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1467781 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1796490 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1796490 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 444994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 444994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3264271 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3264271 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3264271 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3264271 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003515 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003515 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002950 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002950 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003267 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003267 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003267 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003267 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9116.652174 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9116.652174 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16948.018868 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16948.018868 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7672.310345 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7672.310345 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12225.734082 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12225.734082 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12225.734082 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12225.734082 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1541774 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1541774 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1509739 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1509739 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 389494 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 389494 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3051513 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3051513 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3051513 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3051513 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003812 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003812 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003312 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003312 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.797101 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003596 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003596 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003596 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003596 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9576.236025 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9576.236025 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14242.820755 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14242.820755 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7081.709091 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7081.709091 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11428.887640 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11428.887640 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11428.887640 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11428.887640 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 47572 # Number of BP lookups -system.cpu3.branchPred.condPredicted 44838 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1269 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 41556 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 40675 # Number of BTB hits +system.cpu3.branchPred.lookups 48151 # Number of BP lookups +system.cpu3.branchPred.condPredicted 44685 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1287 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 41038 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 39836 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.879969 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 177088 # number of cpu cycles simulated +system.cpu3.branchPred.BTBHitPct 97.071007 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 888 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu3.numCycles 167273 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 31611 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 260615 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 47572 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 41325 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 95272 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3721 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 37783 # Number of cycles fetch has spent blocked -system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7803 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 23344 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 175638 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.483819 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.061741 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 33692 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 260486 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 48151 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 40724 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 122974 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2726 # Number of cycles fetch has spent squashing +system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.NoActiveThreadStallCycles 7060 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1076 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24907 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 418 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 166168 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.567606 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.102870 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 80366 45.76% 45.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 49379 28.11% 73.87% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7947 4.52% 78.40% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3182 1.81% 80.21% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 669 0.38% 80.59% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 28809 16.40% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1228 0.70% 97.69% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 757 0.43% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3301 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 71279 42.90% 42.90% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 48852 29.40% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8282 4.98% 77.28% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3511 2.11% 79.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1059 0.64% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 27347 16.46% 96.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1190 0.72% 97.20% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 758 0.46% 97.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3890 2.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 175638 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.268635 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.471669 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 38601 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 32457 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 87595 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 6808 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2374 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 256826 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2374 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 39299 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 20012 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11695 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 81034 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13421 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 254587 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.RenamedOperands 176229 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 478476 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 373673 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 163264 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12965 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1216 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16061 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69948 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32037 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 34088 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 26994 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 208399 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8161 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 212159 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10835 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11026 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 608 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 175638 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.207933 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.292111 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 166168 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.287859 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.557251 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17558 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 68128 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 67891 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4168 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1363 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 246104 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1363 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18233 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 33368 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12463 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 69060 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 24621 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 242881 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 21589 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full +system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 169259 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 456177 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 357242 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 154687 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14572 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1184 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1245 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 29195 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 65863 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 30140 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 31966 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 25009 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 199372 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7958 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 202308 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12859 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11887 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 166168 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.217491 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.364227 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 77942 44.38% 44.38% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 27771 15.81% 60.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 32234 18.35% 78.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 32910 18.74% 97.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1156 0.66% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 263 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 75148 45.22% 45.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 26256 15.80% 61.02% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 29417 17.70% 78.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 29010 17.46% 96.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3447 2.07% 98.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1582 0.95% 99.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 873 0.53% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 228 0.14% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 207 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 175638 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 166168 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 12 4.44% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 48 17.78% 22.22% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 77.78% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 93 25.83% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.83% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 58 16.11% 41.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 58.06% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 104799 49.40% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 76027 35.83% 85.23% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31333 14.77% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 101290 50.07% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.07% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 71575 35.38% 85.45% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 29443 14.55% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 212159 # Type of FU issued -system.cpu3.iq.rate 1.198043 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 270 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001273 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 600350 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 227441 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 210302 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 202308 # Type of FU issued +system.cpu3.iq.rate 1.209448 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 360 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001779 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 571177 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 220229 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 200600 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 212429 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 202668 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26730 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 24749 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2459 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2800 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1627 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2374 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 705 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 251552 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69948 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32037 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1046 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1363 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8604 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 240098 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 65863 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 30140 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1100 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 910 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1374 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 210966 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 68906 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1193 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1038 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 201185 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 64698 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1123 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34992 # number of nop insts executed -system.cpu3.iew.exec_refs 100151 # number of memory reference insts executed -system.cpu3.iew.exec_branches 44184 # Number of branches executed -system.cpu3.iew.exec_stores 31245 # Number of stores executed -system.cpu3.iew.exec_rate 1.191306 # Inst execution rate -system.cpu3.iew.wb_sent 210604 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 210302 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 116846 # num instructions producing a value -system.cpu3.iew.wb_consumers 121503 # num instructions consuming a value +system.cpu3.iew.exec_nop 32768 # number of nop insts executed +system.cpu3.iew.exec_refs 94032 # number of memory reference insts executed +system.cpu3.iew.exec_branches 42068 # Number of branches executed +system.cpu3.iew.exec_stores 29334 # Number of stores executed +system.cpu3.iew.exec_rate 1.202734 # Inst execution rate +system.cpu3.iew.wb_sent 200904 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 200600 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 111689 # num instructions producing a value +system.cpu3.iew.wb_consumers 118263 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.187556 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961672 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.199237 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.944412 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12453 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7553 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1269 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165461 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.444927 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.940782 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14520 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7275 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1287 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 156480 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.441238 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.976154 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 77418 46.79% 46.79% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 42307 25.57% 72.36% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6087 3.68% 76.04% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8486 5.13% 81.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1577 0.95% 82.12% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 27301 16.50% 98.62% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 474 0.29% 98.91% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1005 0.61% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 74989 47.92% 47.92% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 38816 24.81% 72.73% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5199 3.32% 76.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8093 5.17% 81.22% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1536 0.98% 82.20% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 24757 15.82% 98.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 830 0.53% 98.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165461 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 239079 # Number of instructions committed -system.cpu3.commit.committedOps 239079 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 156480 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 225525 # Number of instructions committed +system.cpu3.commit.committedOps 225525 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 98079 # Number of memory references committed -system.cpu3.commit.loads 67489 # Number of loads committed -system.cpu3.commit.membars 6836 # Number of memory barriers committed -system.cpu3.commit.branches 43385 # Number of branches committed +system.cpu3.commit.refs 91576 # Number of memory references committed +system.cpu3.commit.loads 63063 # Number of loads committed +system.cpu3.commit.membars 6559 # Number of memory barriers committed +system.cpu3.commit.branches 41035 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 163585 # Number of committed integer instructions. +system.cpu3.commit.int_insts 154730 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 34172 14.29% 14.29% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 99992 41.82% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.12% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 74325 31.09% 87.21% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 30590 12.79% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 31823 14.11% 14.11% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 95567 42.38% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.49% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 69622 30.87% 87.36% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 28513 12.64% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 239079 # Class of committed instruction -system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 225525 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 415600 # The number of ROB reads -system.cpu3.rob.rob_writes 505444 # The number of ROB writes -system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1450 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 198071 # Number of Instructions Simulated -system.cpu3.committedOps 198071 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.894063 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.894063 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.118489 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.118489 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 358875 # number of integer regfile reads -system.cpu3.int_regfile_writes 168004 # number of integer regfile writes +system.cpu3.rob.rob_reads 394635 # The number of ROB reads +system.cpu3.rob.rob_writes 482728 # The number of ROB writes +system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1105 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44004 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 187143 # Number of Instructions Simulated +system.cpu3.committedOps 187143 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.893825 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.893825 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.118788 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.118788 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 341840 # number of integer regfile reads +system.cpu3.int_regfile_writes 160726 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 101700 # number of misc regfile reads +system.cpu3.misc_regfile_reads 95629 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.082229 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 22869 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 53.183721 # Average number of references to valid blocks. +system.cpu3.icache.tags.replacements 380 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.789470 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 24352 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 493 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 49.395538 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.082229 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.150551 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.150551 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.789470 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151933 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151933 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 23774 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 23774 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 22869 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 22869 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 22869 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 22869 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 22869 # number of overall hits -system.cpu3.icache.overall_hits::total 22869 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses -system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6365994 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6365994 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6365994 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6365994 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6365994 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6365994 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 23344 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 23344 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 23344 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 23344 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 23344 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 23344 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020348 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020348 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020348 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020348 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020348 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020348 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13402.092632 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13402.092632 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13402.092632 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13402.092632 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13402.092632 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13402.092632 # average overall miss latency +system.cpu3.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 25400 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 25400 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 24352 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 24352 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 24352 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 24352 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 24352 # number of overall hits +system.cpu3.icache.overall_hits::total 24352 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 555 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 555 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 555 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 555 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 555 # number of overall misses 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accesses +system.cpu3.icache.overall_accesses::cpu3.inst 24907 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 24907 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022283 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.022283 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022283 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.022283 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022283 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.022283 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13198.189189 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13198.189189 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13198.189189 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13198.189189 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13198.189189 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13198.189189 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2651,112 +2657,111 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits 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access was blocked @@ -2765,54 +2770,54 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 173 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 204 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 204 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 261 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 261 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1077518 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1077518 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1290489 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1290489 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 398994 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 398994 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2368007 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2368007 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2368007 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2368007 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003819 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003819 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003277 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.788732 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6692.658385 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6692.658385 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12904.890000 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12904.890000 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7124.892857 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7124.892857 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9072.823755 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9072.823755 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9072.823755 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9072.823755 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 269 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 269 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1168525 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1168525 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1299988 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1299988 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 401492 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 401492 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2468513 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2468513 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2468513 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2468513 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004083 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004083 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003762 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003762 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.814286 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003949 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003949 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003949 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003949 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7168.865031 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7168.865031 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12149.420561 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12149.420561 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7043.719298 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7043.719298 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9142.640741 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9142.640741 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9142.640741 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9142.640741 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 284fa3b0e..61ee516ee 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007260 # Number of seconds simulated -sim_ticks 7259586 # Number of ticks simulated -final_tick 7259586 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007430 # Number of seconds simulated +sim_ticks 7430292 # Number of ticks simulated +final_tick 7430292 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 53557 # Simulator tick rate (ticks/s) -host_mem_usage 304720 # Number of bytes of host memory used -host_seconds 135.55 # Real time elapsed on the host +host_tick_rate 111636 # Simulator tick rate (ticks/s) +host_mem_usage 267664 # Number of bytes of host memory used +host_seconds 66.56 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1024 # delay histogram for all message system.ruby.delayHist::max_bucket 10239 # delay histogram for all message -system.ruby.delayHist::samples 4831117 # delay histogram for all message -system.ruby.delayHist::mean 139.352740 # delay histogram for all message -system.ruby.delayHist::stdev 395.959906 # delay histogram for all message -system.ruby.delayHist | 4566883 94.53% 94.53% | 228712 4.73% 99.26% | 33514 0.69% 99.96% | 1886 0.04% 100.00% | 92 0.00% 100.00% | 18 0.00% 100.00% | 9 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 4831117 # delay histogram for all message +system.ruby.delayHist::samples 4929359 # delay histogram for all message +system.ruby.delayHist::mean 137.276961 # delay histogram for all message +system.ruby.delayHist::stdev 391.112700 # delay histogram for all message +system.ruby.delayHist | 4668304 94.70% 94.70% | 226078 4.59% 99.29% | 33026 0.67% 99.96% | 1833 0.04% 100.00% | 87 0.00% 100.00% | 19 0.00% 100.00% | 6 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 4929359 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 608766 -system.ruby.outstanding_req_hist::mean 15.998421 -system.ruby.outstanding_req_hist::gmean 15.997120 -system.ruby.outstanding_req_hist::stdev 0.127650 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 17 0.00% 0.02% | 608645 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 608766 +system.ruby.outstanding_req_hist::samples 621693 +system.ruby.outstanding_req_hist::mean 15.998454 +system.ruby.outstanding_req_hist::gmean 15.997180 +system.ruby.outstanding_req_hist::stdev 0.126316 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 17 0.00% 0.02% | 621572 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 621693 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 608638 -system.ruby.latency_hist::mean 1526.519325 -system.ruby.latency_hist::gmean 1179.356884 -system.ruby.latency_hist::stdev 896.379526 -system.ruby.latency_hist | 103323 16.98% 16.98% | 110835 18.21% 35.19% | 99547 16.36% 51.54% | 97251 15.98% 67.52% | 102045 16.77% 84.29% | 74139 12.18% 96.47% | 20094 3.30% 99.77% | 1390 0.23% 100.00% | 14 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 608638 +system.ruby.latency_hist::samples 621565 +system.ruby.latency_hist::mean 1529.874977 +system.ruby.latency_hist::gmean 1159.409755 +system.ruby.latency_hist::stdev 924.561318 +system.ruby.latency_hist | 114606 18.44% 18.44% | 111166 17.88% 36.32% | 93173 14.99% 51.31% | 92857 14.94% 66.25% | 103677 16.68% 82.93% | 81446 13.10% 96.04% | 23108 3.72% 99.75% | 1514 0.24% 100.00% | 18 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 621565 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 9 +system.ruby.hit_latency_hist::samples 12 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 9 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 12 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 12 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 608629 -system.ruby.miss_latency_hist::mean 1526.541854 -system.ruby.miss_latency_hist::gmean 1179.461074 -system.ruby.miss_latency_hist::stdev 896.367007 -system.ruby.miss_latency_hist | 103314 16.97% 16.97% | 110835 18.21% 35.19% | 99547 16.36% 51.54% | 97251 15.98% 67.52% | 102045 16.77% 84.29% | 74139 12.18% 96.47% | 20094 3.30% 99.77% | 1390 0.23% 100.00% | 14 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 608629 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 76033 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76034 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 621553 +system.ruby.miss_latency_hist::mean 1529.904455 +system.ruby.miss_latency_hist::gmean 1159.543107 +system.ruby.miss_latency_hist::stdev 924.545901 +system.ruby.miss_latency_hist | 114594 18.44% 18.44% | 111166 17.89% 36.32% | 93173 14.99% 51.31% | 92857 14.94% 66.25% | 103677 16.68% 82.93% | 81446 13.10% 96.04% | 23108 3.72% 99.75% | 1514 0.24% 100.00% | 18 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 621553 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 77337 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77337 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -65,8 +65,8 @@ system.ruby.l1_cntrl4.prefetcher.partial_hits 0 system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl5.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 75626 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 75627 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78248 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78249 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -79,9 +79,9 @@ system.ruby.l1_cntrl5.prefetcher.hits 0 # nu system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl6.L1Dcache.demand_hits 2 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 75751 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 75753 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 3 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 77661 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77664 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -95,8 +95,8 @@ system.ruby.l1_cntrl6.prefetcher.partial_hits 0 system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl7.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 76551 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 76552 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_misses 77688 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77689 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -109,9 +109,9 @@ system.ruby.l1_cntrl7.prefetcher.hits 0 # nu system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 76245 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 76246 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 77618 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 77618 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -124,26 +124,26 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers00.percent_links_utilized 5.423784 -system.ruby.network.routers00.msg_count.Control::0 76245 -system.ruby.network.routers00.msg_count.Request_Control::2 73752 -system.ruby.network.routers00.msg_count.Response_Data::1 76793 -system.ruby.network.routers00.msg_count.Response_Control::1 63355 -system.ruby.network.routers00.msg_count.Response_Control::2 75593 -system.ruby.network.routers00.msg_count.Writeback_Data::0 14015 -system.ruby.network.routers00.msg_count.Writeback_Data::1 49278 -system.ruby.network.routers00.msg_count.Writeback_Control::0 25258 -system.ruby.network.routers00.msg_bytes.Control::0 609960 -system.ruby.network.routers00.msg_bytes.Request_Control::2 590016 -system.ruby.network.routers00.msg_bytes.Response_Data::1 5529096 -system.ruby.network.routers00.msg_bytes.Response_Control::1 506840 -system.ruby.network.routers00.msg_bytes.Response_Control::2 604744 -system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1009080 -system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3548016 -system.ruby.network.routers00.msg_bytes.Writeback_Control::0 202064 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 3 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 76099 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 76102 # Number of cache demand accesses +system.ruby.network.routers00.percent_links_utilized 5.388577 +system.ruby.network.routers00.msg_count.Control::0 77618 +system.ruby.network.routers00.msg_count.Request_Control::2 75225 +system.ruby.network.routers00.msg_count.Response_Data::1 78135 +system.ruby.network.routers00.msg_count.Response_Control::1 64408 +system.ruby.network.routers00.msg_count.Response_Control::2 76967 +system.ruby.network.routers00.msg_count.Writeback_Data::0 14088 +system.ruby.network.routers00.msg_count.Writeback_Data::1 50186 +system.ruby.network.routers00.msg_count.Writeback_Control::0 25649 +system.ruby.network.routers00.msg_bytes.Control::0 620944 +system.ruby.network.routers00.msg_bytes.Request_Control::2 601800 +system.ruby.network.routers00.msg_bytes.Response_Data::1 5625720 +system.ruby.network.routers00.msg_bytes.Response_Control::1 515264 +system.ruby.network.routers00.msg_bytes.Response_Control::2 615736 +system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1014336 +system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3613392 +system.ruby.network.routers00.msg_bytes.Writeback_Control::0 205192 +system.ruby.l1_cntrl1.L1Dcache.demand_hits 2 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 77551 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77553 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -156,26 +156,26 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers01.percent_links_utilized 5.417940 -system.ruby.network.routers01.msg_count.Control::0 76099 -system.ruby.network.routers01.msg_count.Request_Control::2 73821 -system.ruby.network.routers01.msg_count.Response_Data::1 76634 -system.ruby.network.routers01.msg_count.Response_Control::1 63212 -system.ruby.network.routers01.msg_count.Response_Control::2 75499 -system.ruby.network.routers01.msg_count.Writeback_Data::0 13920 -system.ruby.network.routers01.msg_count.Writeback_Data::1 49382 -system.ruby.network.routers01.msg_count.Writeback_Control::0 25225 -system.ruby.network.routers01.msg_bytes.Control::0 608792 -system.ruby.network.routers01.msg_bytes.Request_Control::2 590568 -system.ruby.network.routers01.msg_bytes.Response_Data::1 5517648 -system.ruby.network.routers01.msg_bytes.Response_Control::1 505696 -system.ruby.network.routers01.msg_bytes.Response_Control::2 603992 -system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1002240 -system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3555504 -system.ruby.network.routers01.msg_bytes.Writeback_Control::0 201800 -system.ruby.l1_cntrl2.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 75982 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 75982 # Number of cache demand accesses +system.ruby.network.routers01.percent_links_utilized 5.383194 +system.ruby.network.routers01.msg_count.Control::0 77551 +system.ruby.network.routers01.msg_count.Request_Control::2 75182 +system.ruby.network.routers01.msg_count.Response_Data::1 78051 +system.ruby.network.routers01.msg_count.Response_Control::1 64185 +system.ruby.network.routers01.msg_count.Response_Control::2 76934 +system.ruby.network.routers01.msg_count.Writeback_Data::0 14225 +system.ruby.network.routers01.msg_count.Writeback_Data::1 50047 +system.ruby.network.routers01.msg_count.Writeback_Control::0 25189 +system.ruby.network.routers01.msg_bytes.Control::0 620408 +system.ruby.network.routers01.msg_bytes.Request_Control::2 601456 +system.ruby.network.routers01.msg_bytes.Response_Data::1 5619672 +system.ruby.network.routers01.msg_bytes.Response_Control::1 513480 +system.ruby.network.routers01.msg_bytes.Response_Control::2 615472 +system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1024200 +system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3603384 +system.ruby.network.routers01.msg_bytes.Writeback_Control::0 201512 +system.ruby.l1_cntrl2.L1Dcache.demand_hits 3 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 77720 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77723 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -188,26 +188,26 @@ system.ruby.l1_cntrl2.prefetcher.hits 0 # nu system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers02.percent_links_utilized 5.406755 -system.ruby.network.routers02.msg_count.Control::0 75982 -system.ruby.network.routers02.msg_count.Request_Control::2 73694 -system.ruby.network.routers02.msg_count.Response_Data::1 76434 -system.ruby.network.routers02.msg_count.Response_Control::1 63174 -system.ruby.network.routers02.msg_count.Response_Control::2 75307 -system.ruby.network.routers02.msg_count.Writeback_Data::0 13836 -system.ruby.network.routers02.msg_count.Writeback_Data::1 49347 -system.ruby.network.routers02.msg_count.Writeback_Control::0 25322 -system.ruby.network.routers02.msg_bytes.Control::0 607856 -system.ruby.network.routers02.msg_bytes.Request_Control::2 589552 -system.ruby.network.routers02.msg_bytes.Response_Data::1 5503248 -system.ruby.network.routers02.msg_bytes.Response_Control::1 505392 -system.ruby.network.routers02.msg_bytes.Response_Control::2 602456 -system.ruby.network.routers02.msg_bytes.Writeback_Data::0 996192 -system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3552984 -system.ruby.network.routers02.msg_bytes.Writeback_Control::0 202576 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 76366 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 76366 # Number of cache demand accesses +system.ruby.network.routers02.percent_links_utilized 5.401120 +system.ruby.network.routers02.msg_count.Control::0 77720 +system.ruby.network.routers02.msg_count.Request_Control::2 75340 +system.ruby.network.routers02.msg_count.Response_Data::1 78201 +system.ruby.network.routers02.msg_count.Response_Control::1 64595 +system.ruby.network.routers02.msg_count.Response_Control::2 77107 +system.ruby.network.routers02.msg_count.Writeback_Data::0 14370 +system.ruby.network.routers02.msg_count.Writeback_Data::1 50215 +system.ruby.network.routers02.msg_count.Writeback_Control::0 25440 +system.ruby.network.routers02.msg_bytes.Control::0 621760 +system.ruby.network.routers02.msg_bytes.Request_Control::2 602720 +system.ruby.network.routers02.msg_bytes.Response_Data::1 5630472 +system.ruby.network.routers02.msg_bytes.Response_Control::1 516760 +system.ruby.network.routers02.msg_bytes.Response_Control::2 616856 +system.ruby.network.routers02.msg_bytes.Writeback_Data::0 1034640 +system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3615480 +system.ruby.network.routers02.msg_bytes.Writeback_Control::0 203520 +system.ruby.l1_cntrl3.L1Dcache.demand_hits 2 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 77752 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 77754 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -220,534 +220,534 @@ system.ruby.l1_cntrl3.prefetcher.hits 0 # nu system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers03.percent_links_utilized 5.433505 -system.ruby.network.routers03.msg_count.Control::0 76366 -system.ruby.network.routers03.msg_count.Request_Control::2 73906 -system.ruby.network.routers03.msg_count.Response_Data::1 76879 -system.ruby.network.routers03.msg_count.Response_Control::1 63521 -system.ruby.network.routers03.msg_count.Response_Control::2 75747 -system.ruby.network.routers03.msg_count.Writeback_Data::0 13928 -system.ruby.network.routers03.msg_count.Writeback_Data::1 49494 -system.ruby.network.routers03.msg_count.Writeback_Control::0 25551 -system.ruby.network.routers03.msg_bytes.Control::0 610928 -system.ruby.network.routers03.msg_bytes.Request_Control::2 591248 -system.ruby.network.routers03.msg_bytes.Response_Data::1 5535288 -system.ruby.network.routers03.msg_bytes.Response_Control::1 508168 -system.ruby.network.routers03.msg_bytes.Response_Control::2 605976 -system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1002816 -system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3563568 -system.ruby.network.routers03.msg_bytes.Writeback_Control::0 204408 -system.ruby.network.routers04.percent_links_utilized 5.395387 -system.ruby.network.routers04.msg_count.Control::0 76033 -system.ruby.network.routers04.msg_count.Request_Control::2 73600 -system.ruby.network.routers04.msg_count.Response_Data::1 76524 -system.ruby.network.routers04.msg_count.Response_Control::1 63335 -system.ruby.network.routers04.msg_count.Response_Control::2 75393 -system.ruby.network.routers04.msg_count.Writeback_Data::0 13720 -system.ruby.network.routers04.msg_count.Writeback_Data::1 48981 -system.ruby.network.routers04.msg_count.Writeback_Control::0 25345 -system.ruby.network.routers04.msg_bytes.Control::0 608264 -system.ruby.network.routers04.msg_bytes.Request_Control::2 588800 -system.ruby.network.routers04.msg_bytes.Response_Data::1 5509728 -system.ruby.network.routers04.msg_bytes.Response_Control::1 506680 -system.ruby.network.routers04.msg_bytes.Response_Control::2 603144 -system.ruby.network.routers04.msg_bytes.Writeback_Data::0 987840 -system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3526632 -system.ruby.network.routers04.msg_bytes.Writeback_Control::0 202760 -system.ruby.network.routers05.percent_links_utilized 5.367062 -system.ruby.network.routers05.msg_count.Control::0 75626 -system.ruby.network.routers05.msg_count.Request_Control::2 73320 -system.ruby.network.routers05.msg_count.Response_Data::1 76116 -system.ruby.network.routers05.msg_count.Response_Control::1 62950 -system.ruby.network.routers05.msg_count.Response_Control::2 74958 -system.ruby.network.routers05.msg_count.Writeback_Data::0 13608 -system.ruby.network.routers05.msg_count.Writeback_Data::1 48776 -system.ruby.network.routers05.msg_count.Writeback_Control::0 25152 -system.ruby.network.routers05.msg_bytes.Control::0 605008 -system.ruby.network.routers05.msg_bytes.Request_Control::2 586560 -system.ruby.network.routers05.msg_bytes.Response_Data::1 5480352 -system.ruby.network.routers05.msg_bytes.Response_Control::1 503600 -system.ruby.network.routers05.msg_bytes.Response_Control::2 599664 -system.ruby.network.routers05.msg_bytes.Writeback_Data::0 979776 -system.ruby.network.routers05.msg_bytes.Writeback_Data::1 3511872 -system.ruby.network.routers05.msg_bytes.Writeback_Control::0 201216 -system.ruby.network.routers06.percent_links_utilized 5.371797 -system.ruby.network.routers06.msg_count.Control::0 75751 -system.ruby.network.routers06.msg_count.Request_Control::2 73431 -system.ruby.network.routers06.msg_count.Response_Data::1 76221 -system.ruby.network.routers06.msg_count.Response_Control::1 63027 -system.ruby.network.routers06.msg_count.Response_Control::2 75095 -system.ruby.network.routers06.msg_count.Writeback_Data::0 13703 -system.ruby.network.routers06.msg_count.Writeback_Data::1 48704 -system.ruby.network.routers06.msg_count.Writeback_Control::0 24925 -system.ruby.network.routers06.msg_bytes.Control::0 606008 -system.ruby.network.routers06.msg_bytes.Request_Control::2 587448 -system.ruby.network.routers06.msg_bytes.Response_Data::1 5487912 -system.ruby.network.routers06.msg_bytes.Response_Control::1 504216 -system.ruby.network.routers06.msg_bytes.Response_Control::2 600760 -system.ruby.network.routers06.msg_bytes.Writeback_Data::0 986616 -system.ruby.network.routers06.msg_bytes.Writeback_Data::1 3506688 -system.ruby.network.routers06.msg_bytes.Writeback_Control::0 199400 -system.ruby.network.routers07.percent_links_utilized 5.448957 -system.ruby.network.routers07.msg_count.Control::0 76551 -system.ruby.network.routers07.msg_count.Request_Control::2 74163 -system.ruby.network.routers07.msg_count.Response_Data::1 77065 -system.ruby.network.routers07.msg_count.Response_Control::1 63812 -system.ruby.network.routers07.msg_count.Response_Control::2 75941 -system.ruby.network.routers07.msg_count.Writeback_Data::0 13974 -system.ruby.network.routers07.msg_count.Writeback_Data::1 49643 -system.ruby.network.routers07.msg_count.Writeback_Control::0 25684 -system.ruby.network.routers07.msg_bytes.Control::0 612408 -system.ruby.network.routers07.msg_bytes.Request_Control::2 593304 -system.ruby.network.routers07.msg_bytes.Response_Data::1 5548680 -system.ruby.network.routers07.msg_bytes.Response_Control::1 510496 -system.ruby.network.routers07.msg_bytes.Response_Control::2 607528 -system.ruby.network.routers07.msg_bytes.Writeback_Data::0 1006128 -system.ruby.network.routers07.msg_bytes.Writeback_Data::1 3574296 -system.ruby.network.routers07.msg_bytes.Writeback_Control::0 205472 -system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 608605 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 608635 # Number of cache demand accesses -system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions -system.ruby.network.routers08.percent_links_utilized 73.788082 -system.ruby.network.routers08.msg_count.Control::0 1211833 -system.ruby.network.routers08.msg_count.Request_Control::2 585965 -system.ruby.network.routers08.msg_count.Response_Data::1 1420506 -system.ruby.network.routers08.msg_count.Response_Control::1 1499731 -system.ruby.network.routers08.msg_count.Response_Control::2 603532 -system.ruby.network.routers08.msg_count.Writeback_Data::0 110703 -system.ruby.network.routers08.msg_count.Writeback_Data::1 393605 -system.ruby.network.routers08.msg_count.Writeback_Control::0 202462 -system.ruby.network.routers08.msg_bytes.Control::0 9694664 -system.ruby.network.routers08.msg_bytes.Request_Control::2 4687720 -system.ruby.network.routers08.msg_bytes.Response_Data::1 102276432 -system.ruby.network.routers08.msg_bytes.Response_Control::1 11997848 -system.ruby.network.routers08.msg_bytes.Response_Control::2 4828256 -system.ruby.network.routers08.msg_bytes.Writeback_Data::0 7970616 -system.ruby.network.routers08.msg_bytes.Writeback_Data::1 28339560 -system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1619696 +system.ruby.network.routers03.percent_links_utilized 5.405376 +system.ruby.network.routers03.msg_count.Control::0 77752 +system.ruby.network.routers03.msg_count.Request_Control::2 75338 +system.ruby.network.routers03.msg_count.Response_Data::1 78287 +system.ruby.network.routers03.msg_count.Response_Control::1 64277 +system.ruby.network.routers03.msg_count.Response_Control::2 77086 +system.ruby.network.routers03.msg_count.Writeback_Data::0 14417 +system.ruby.network.routers03.msg_count.Writeback_Data::1 50285 +system.ruby.network.routers03.msg_count.Writeback_Control::0 25187 +system.ruby.network.routers03.msg_bytes.Control::0 622016 +system.ruby.network.routers03.msg_bytes.Request_Control::2 602704 +system.ruby.network.routers03.msg_bytes.Response_Data::1 5636664 +system.ruby.network.routers03.msg_bytes.Response_Control::1 514216 +system.ruby.network.routers03.msg_bytes.Response_Control::2 616688 +system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1038024 +system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3620520 +system.ruby.network.routers03.msg_bytes.Writeback_Control::0 201496 +system.ruby.network.routers04.percent_links_utilized 5.370206 +system.ruby.network.routers04.msg_count.Control::0 77337 +system.ruby.network.routers04.msg_count.Request_Control::2 74942 +system.ruby.network.routers04.msg_count.Response_Data::1 77832 +system.ruby.network.routers04.msg_count.Response_Control::1 64045 +system.ruby.network.routers04.msg_count.Response_Control::2 76706 +system.ruby.network.routers04.msg_count.Writeback_Data::0 14274 +system.ruby.network.routers04.msg_count.Writeback_Data::1 49893 +system.ruby.network.routers04.msg_count.Writeback_Control::0 25067 +system.ruby.network.routers04.msg_bytes.Control::0 618696 +system.ruby.network.routers04.msg_bytes.Request_Control::2 599536 +system.ruby.network.routers04.msg_bytes.Response_Data::1 5603904 +system.ruby.network.routers04.msg_bytes.Response_Control::1 512360 +system.ruby.network.routers04.msg_bytes.Response_Control::2 613648 +system.ruby.network.routers04.msg_bytes.Writeback_Data::0 1027728 +system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3592296 +system.ruby.network.routers04.msg_bytes.Writeback_Control::0 200536 +system.ruby.network.routers05.percent_links_utilized 5.437902 +system.ruby.network.routers05.msg_count.Control::0 78248 +system.ruby.network.routers05.msg_count.Request_Control::2 75756 +system.ruby.network.routers05.msg_count.Response_Data::1 78726 +system.ruby.network.routers05.msg_count.Response_Control::1 64879 +system.ruby.network.routers05.msg_count.Response_Control::2 77614 +system.ruby.network.routers05.msg_count.Writeback_Data::0 14469 +system.ruby.network.routers05.msg_count.Writeback_Data::1 50596 +system.ruby.network.routers05.msg_count.Writeback_Control::0 25597 +system.ruby.network.routers05.msg_bytes.Control::0 625984 +system.ruby.network.routers05.msg_bytes.Request_Control::2 606048 +system.ruby.network.routers05.msg_bytes.Response_Data::1 5668272 +system.ruby.network.routers05.msg_bytes.Response_Control::1 519032 +system.ruby.network.routers05.msg_bytes.Response_Control::2 620912 +system.ruby.network.routers05.msg_bytes.Writeback_Data::0 1041768 +system.ruby.network.routers05.msg_bytes.Writeback_Data::1 3642912 +system.ruby.network.routers05.msg_bytes.Writeback_Control::0 204776 +system.ruby.network.routers06.percent_links_utilized 5.392954 +system.ruby.network.routers06.msg_count.Control::0 77661 +system.ruby.network.routers06.msg_count.Request_Control::2 75223 +system.ruby.network.routers06.msg_count.Response_Data::1 78177 +system.ruby.network.routers06.msg_count.Response_Control::1 64312 +system.ruby.network.routers06.msg_count.Response_Control::2 77032 +system.ruby.network.routers06.msg_count.Writeback_Data::0 14283 +system.ruby.network.routers06.msg_count.Writeback_Data::1 50131 +system.ruby.network.routers06.msg_count.Writeback_Control::0 25302 +system.ruby.network.routers06.msg_bytes.Control::0 621288 +system.ruby.network.routers06.msg_bytes.Request_Control::2 601784 +system.ruby.network.routers06.msg_bytes.Response_Data::1 5628744 +system.ruby.network.routers06.msg_bytes.Response_Control::1 514496 +system.ruby.network.routers06.msg_bytes.Response_Control::2 616256 +system.ruby.network.routers06.msg_bytes.Writeback_Data::0 1028376 +system.ruby.network.routers06.msg_bytes.Writeback_Data::1 3609432 +system.ruby.network.routers06.msg_bytes.Writeback_Control::0 202416 +system.ruby.network.routers07.percent_links_utilized 5.402086 +system.ruby.network.routers07.msg_count.Control::0 77688 +system.ruby.network.routers07.msg_count.Request_Control::2 75301 +system.ruby.network.routers07.msg_count.Response_Data::1 78207 +system.ruby.network.routers07.msg_count.Response_Control::1 64323 +system.ruby.network.routers07.msg_count.Response_Control::2 77070 +system.ruby.network.routers07.msg_count.Writeback_Data::0 14297 +system.ruby.network.routers07.msg_count.Writeback_Data::1 50355 +system.ruby.network.routers07.msg_count.Writeback_Control::0 25450 +system.ruby.network.routers07.msg_bytes.Control::0 621504 +system.ruby.network.routers07.msg_bytes.Request_Control::2 602408 +system.ruby.network.routers07.msg_bytes.Response_Data::1 5630904 +system.ruby.network.routers07.msg_bytes.Response_Control::1 514584 +system.ruby.network.routers07.msg_bytes.Response_Control::2 616560 +system.ruby.network.routers07.msg_bytes.Writeback_Data::0 1029384 +system.ruby.network.routers07.msg_bytes.Writeback_Data::1 3625560 +system.ruby.network.routers07.msg_bytes.Writeback_Control::0 203600 +system.ruby.l2_cntrl0.L2cache.demand_hits 27 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 621533 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 621560 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions +system.ruby.network.routers08.percent_links_utilized 73.742176 +system.ruby.network.routers08.msg_count.Control::0 1237703 +system.ruby.network.routers08.msg_count.Request_Control::2 598605 +system.ruby.network.routers08.msg_count.Response_Data::1 1454436 +system.ruby.network.routers08.msg_count.Response_Control::1 1526235 +system.ruby.network.routers08.msg_count.Response_Control::2 616516 +system.ruby.network.routers08.msg_count.Writeback_Data::0 114423 +system.ruby.network.routers08.msg_count.Writeback_Data::1 401708 +system.ruby.network.routers08.msg_count.Writeback_Control::0 202881 +system.ruby.network.routers08.msg_bytes.Control::0 9901624 +system.ruby.network.routers08.msg_bytes.Request_Control::2 4788840 +system.ruby.network.routers08.msg_bytes.Response_Data::1 104719392 +system.ruby.network.routers08.msg_bytes.Response_Control::1 12209880 +system.ruby.network.routers08.msg_bytes.Response_Control::2 4932128 +system.ruby.network.routers08.msg_bytes.Writeback_Data::0 8238456 +system.ruby.network.routers08.msg_bytes.Writeback_Data::1 28922976 +system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1623048 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 816132 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 603181 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 212949 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 50414 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 5087209 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 208626 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 421577 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 5717412 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 7.005499 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 996551 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 1584957 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 931983 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 411910 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 974568 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memNotOld 187240 # memory stalls due to anti starvation -system.ruby.dir_cntrl0.memBuffer.memBankCount | 25732 3.15% 3.15% | 25542 3.13% 6.28% | 25558 3.13% 9.41% | 25419 3.11% 12.53% | 25578 3.13% 15.66% | 25569 3.13% 18.80% | 25355 3.11% 21.90% | 25427 3.12% 25.02% | 25577 3.13% 28.15% | 25273 3.10% 31.25% | 25829 3.16% 34.41% | 25738 3.15% 37.57% | 25452 3.12% 40.69% | 25562 3.13% 43.82% | 25175 3.08% 46.90% | 25281 3.10% 50.00% | 25608 3.14% 53.14% | 25089 3.07% 56.21% | 25653 3.14% 59.36% | 25208 3.09% 62.44% | 25307 3.10% 65.54% | 25373 3.11% 68.65% | 25373 3.11% 71.76% | 25618 3.14% 74.90% | 25513 3.13% 78.03% | 26009 3.19% 81.21% | 25574 3.13% 84.35% | 25719 3.15% 87.50% | 25435 3.12% 90.62% | 25580 3.13% 93.75% | 25654 3.14% 96.89% | 25352 3.11% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 816132 # Number of accesses per bank -system.ruby.network.routers09.percent_links_utilized 30.792875 -system.ruby.network.routers09.msg_count.Control::0 603181 -system.ruby.network.routers09.msg_count.Response_Data::1 816130 -system.ruby.network.routers09.msg_count.Response_Control::1 993390 -system.ruby.network.routers09.msg_bytes.Control::0 4825448 -system.ruby.network.routers09.msg_bytes.Response_Data::1 58761360 -system.ruby.network.routers09.msg_bytes.Response_Control::1 7947120 -system.ruby.network.routers10.percent_links_utilized 14.793798 -system.ruby.network.routers10.msg_count.Control::0 1211833 -system.ruby.network.routers10.msg_count.Request_Control::2 589687 -system.ruby.network.routers10.msg_count.Response_Data::1 1425926 -system.ruby.network.routers10.msg_count.Response_Control::1 1499753 -system.ruby.network.routers10.msg_count.Response_Control::2 603532 -system.ruby.network.routers10.msg_count.Writeback_Data::0 110703 -system.ruby.network.routers10.msg_count.Writeback_Data::1 393605 -system.ruby.network.routers10.msg_count.Writeback_Control::0 202462 -system.ruby.network.routers10.msg_bytes.Control::0 9694664 -system.ruby.network.routers10.msg_bytes.Request_Control::2 4717496 -system.ruby.network.routers10.msg_bytes.Response_Data::1 102666672 -system.ruby.network.routers10.msg_bytes.Response_Control::1 11998024 -system.ruby.network.routers10.msg_bytes.Response_Control::2 4828256 -system.ruby.network.routers10.msg_bytes.Writeback_Data::0 7970616 -system.ruby.network.routers10.msg_bytes.Writeback_Data::1 28339560 -system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1619696 -system.ruby.network.msg_count.Control 3635500 -system.ruby.network.msg_count.Request_Control 1765339 -system.ruby.network.msg_count.Response_Data 4275228 -system.ruby.network.msg_count.Response_Control 6309857 -system.ruby.network.msg_count.Writeback_Data 1512925 -system.ruby.network.msg_count.Writeback_Control 607386 -system.ruby.network.msg_byte.Control 29084000 -system.ruby.network.msg_byte.Request_Control 14122712 -system.ruby.network.msg_byte.Response_Data 307816416 -system.ruby.network.msg_byte.Response_Control 50478856 -system.ruby.network.msg_byte.Writeback_Data 108930600 -system.ruby.network.msg_byte.Writeback_Control 4859088 +system.ruby.dir_cntrl0.memBuffer.memReq 837117 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 616125 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 220987 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 51600 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 5282130 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 213418 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 448771 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 5944319 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 7.100942 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 1034385 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 1644850 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 969543 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 420455 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 1013454 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memNotOld 199443 # memory stalls due to anti starvation +system.ruby.dir_cntrl0.memBuffer.memBankCount | 26053 3.11% 3.11% | 26238 3.13% 6.25% | 26476 3.16% 9.41% | 26000 3.11% 12.52% | 26163 3.13% 15.64% | 26349 3.15% 18.79% | 26252 3.14% 21.92% | 26118 3.12% 25.04% | 26155 3.12% 28.17% | 25974 3.10% 31.27% | 26485 3.16% 34.44% | 26013 3.11% 37.54% | 26239 3.13% 40.68% | 25904 3.09% 43.77% | 26148 3.12% 46.90% | 26248 3.14% 50.03% | 26068 3.11% 53.14% | 26508 3.17% 56.31% | 25945 3.10% 59.41% | 26211 3.13% 62.54% | 25779 3.08% 65.62% | 25834 3.09% 68.71% | 26282 3.14% 71.85% | 26037 3.11% 74.96% | 26294 3.14% 78.10% | 26232 3.13% 81.23% | 25842 3.09% 84.32% | 26144 3.12% 87.44% | 26060 3.11% 90.55% | 26651 3.18% 93.74% | 26042 3.11% 96.85% | 26373 3.15% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 837117 # Number of accesses per bank +system.ruby.network.routers09.percent_links_utilized 30.824398 +system.ruby.network.routers09.msg_count.Control::0 616128 +system.ruby.network.routers09.msg_count.Response_Data::1 837111 +system.ruby.network.routers09.msg_count.Response_Control::1 1011244 +system.ruby.network.routers09.msg_bytes.Control::0 4929024 +system.ruby.network.routers09.msg_bytes.Response_Data::1 60271992 +system.ruby.network.routers09.msg_bytes.Response_Control::1 8089952 +system.ruby.network.routers10.percent_links_utilized 14.783673 +system.ruby.network.routers10.msg_count.Control::0 1237703 +system.ruby.network.routers10.msg_count.Request_Control::2 602307 +system.ruby.network.routers10.msg_count.Response_Data::1 1459841 +system.ruby.network.routers10.msg_count.Response_Control::1 1526251 +system.ruby.network.routers10.msg_count.Response_Control::2 616516 +system.ruby.network.routers10.msg_count.Writeback_Data::0 114423 +system.ruby.network.routers10.msg_count.Writeback_Data::1 401708 +system.ruby.network.routers10.msg_count.Writeback_Control::0 202881 +system.ruby.network.routers10.msg_bytes.Control::0 9901624 +system.ruby.network.routers10.msg_bytes.Request_Control::2 4818456 +system.ruby.network.routers10.msg_bytes.Response_Data::1 105108552 +system.ruby.network.routers10.msg_bytes.Response_Control::1 12210008 +system.ruby.network.routers10.msg_bytes.Response_Control::2 4932128 +system.ruby.network.routers10.msg_bytes.Writeback_Data::0 8238456 +system.ruby.network.routers10.msg_bytes.Writeback_Data::1 28922976 +system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1623048 +system.ruby.network.msg_count.Control 3713109 +system.ruby.network.msg_count.Request_Control 1803219 +system.ruby.network.msg_count.Response_Data 4377004 +system.ruby.network.msg_count.Response_Control 6428302 +system.ruby.network.msg_count.Writeback_Data 1548393 +system.ruby.network.msg_count.Writeback_Control 608643 +system.ruby.network.msg_byte.Control 29704872 +system.ruby.network.msg_byte.Request_Control 14425752 +system.ruby.network.msg_byte.Response_Data 315144288 +system.ruby.network.msg_byte.Response_Control 51426416 +system.ruby.network.msg_byte.Writeback_Data 111484296 +system.ruby.network.msg_byte.Writeback_Control 4869144 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) -system.cpu0.num_reads 98705 # number of read accesses completed -system.cpu0.num_writes 53811 # number of write accesses completed +system.cpu0.num_reads 99258 # number of read accesses completed +system.cpu0.num_writes 54534 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98323 # number of read accesses completed -system.cpu1.num_writes 53379 # number of write accesses completed +system.cpu1.num_reads 98654 # number of read accesses completed +system.cpu1.num_writes 54809 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98444 # number of read accesses completed -system.cpu2.num_writes 53127 # number of write accesses completed +system.cpu2.num_reads 99249 # number of read accesses completed +system.cpu2.num_writes 54599 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98629 # number of read accesses completed -system.cpu3.num_writes 53267 # number of write accesses completed +system.cpu3.num_reads 98783 # number of read accesses completed +system.cpu3.num_writes 54952 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98161 # number of read accesses completed -system.cpu4.num_writes 53090 # number of write accesses completed +system.cpu4.num_reads 98121 # number of read accesses completed +system.cpu4.num_writes 54478 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 98401 # number of read accesses completed -system.cpu5.num_writes 52796 # number of write accesses completed +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 55112 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98263 # number of read accesses completed -system.cpu6.num_writes 53278 # number of write accesses completed +system.cpu6.num_reads 98611 # number of read accesses completed +system.cpu6.num_writes 54867 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 53646 # number of write accesses completed +system.cpu7.num_reads 99371 # number of read accesses completed +system.cpu7.num_writes 54915 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers00.throttle0.link_utilization 5.504536 -system.ruby.network.routers00.throttle0.msg_count.Request_Control::2 73752 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::1 76243 -system.ruby.network.routers00.throttle0.msg_count.Response_Control::1 39274 -system.ruby.network.routers00.throttle0.msg_bytes.Request_Control::2 590016 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::1 5489496 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::1 314192 -system.ruby.network.routers00.throttle1.link_utilization 5.343032 -system.ruby.network.routers00.throttle1.msg_count.Control::0 76245 -system.ruby.network.routers00.throttle1.msg_count.Response_Data::1 550 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::1 24081 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::2 75593 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::0 14015 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::1 49278 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Control::0 25258 -system.ruby.network.routers00.throttle1.msg_bytes.Control::0 609960 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::1 39600 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::1 192648 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::2 604744 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::0 1009080 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::1 3548016 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Control::0 202064 -system.ruby.network.routers01.throttle0.link_utilization 5.494969 -system.ruby.network.routers01.throttle0.msg_count.Request_Control::2 73821 -system.ruby.network.routers01.throttle0.msg_count.Response_Data::1 76095 -system.ruby.network.routers01.throttle0.msg_count.Response_Control::1 39148 -system.ruby.network.routers01.throttle0.msg_bytes.Request_Control::2 590568 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::1 5478840 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::1 313184 -system.ruby.network.routers01.throttle1.link_utilization 5.340911 -system.ruby.network.routers01.throttle1.msg_count.Control::0 76099 -system.ruby.network.routers01.throttle1.msg_count.Response_Data::1 539 -system.ruby.network.routers01.throttle1.msg_count.Response_Control::1 24064 -system.ruby.network.routers01.throttle1.msg_count.Response_Control::2 75499 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::0 13920 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::1 49382 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Control::0 25225 -system.ruby.network.routers01.throttle1.msg_bytes.Control::0 608792 -system.ruby.network.routers01.throttle1.msg_bytes.Response_Data::1 38808 -system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::1 192512 -system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::2 603992 -system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::0 1002240 -system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::1 3555504 -system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Control::0 201800 -system.ruby.network.routers02.throttle0.link_utilization 5.486924 -system.ruby.network.routers02.throttle0.msg_count.Request_Control::2 73694 -system.ruby.network.routers02.throttle0.msg_count.Response_Data::1 75978 -system.ruby.network.routers02.throttle0.msg_count.Response_Control::1 39160 -system.ruby.network.routers02.throttle0.msg_bytes.Request_Control::2 589552 -system.ruby.network.routers02.throttle0.msg_bytes.Response_Data::1 5470416 -system.ruby.network.routers02.throttle0.msg_bytes.Response_Control::1 313280 -system.ruby.network.routers02.throttle1.link_utilization 5.326585 -system.ruby.network.routers02.throttle1.msg_count.Control::0 75982 -system.ruby.network.routers02.throttle1.msg_count.Response_Data::1 456 -system.ruby.network.routers02.throttle1.msg_count.Response_Control::1 24014 -system.ruby.network.routers02.throttle1.msg_count.Response_Control::2 75307 -system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::0 13836 -system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::1 49347 -system.ruby.network.routers02.throttle1.msg_count.Writeback_Control::0 25322 -system.ruby.network.routers02.throttle1.msg_bytes.Control::0 607856 -system.ruby.network.routers02.throttle1.msg_bytes.Response_Data::1 32832 -system.ruby.network.routers02.throttle1.msg_bytes.Response_Control::1 192112 -system.ruby.network.routers02.throttle1.msg_bytes.Response_Control::2 602456 -system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::0 996192 -system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::1 3552984 -system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Control::0 202576 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+system.ruby.network.routers10.throttle6.msg_count.Response_Control::1 39585 +system.ruby.network.routers10.throttle6.msg_bytes.Request_Control::2 601784 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::1 5591448 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::1 316680 +system.ruby.network.routers10.throttle7.link_utilization 5.479078 +system.ruby.network.routers10.throttle7.msg_count.Request_Control::2 75301 +system.ruby.network.routers10.throttle7.msg_count.Response_Data::1 77686 +system.ruby.network.routers10.throttle7.msg_count.Response_Control::1 39748 +system.ruby.network.routers10.throttle7.msg_bytes.Request_Control::2 602408 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::1 5593392 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::1 317984 +system.ruby.network.routers10.throttle8.link_utilization 83.816693 +system.ruby.network.routers10.throttle8.msg_count.Control::0 621575 +system.ruby.network.routers10.throttle8.msg_count.Response_Data::1 617299 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::1 813811 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::2 616516 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::0 114423 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::1 401708 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0 202881 +system.ruby.network.routers10.throttle8.msg_bytes.Control::0 4972600 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::1 44445528 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::1 6510488 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::2 4932128 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::0 8238456 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::1 28922976 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 1623048 +system.ruby.network.routers10.throttle9.link_utilization 20.188695 +system.ruby.network.routers10.throttle9.msg_count.Control::0 616128 +system.ruby.network.routers10.throttle9.msg_count.Response_Data::1 220989 +system.ruby.network.routers10.throttle9.msg_count.Response_Control::1 395129 +system.ruby.network.routers10.throttle9.msg_bytes.Control::0 4929024 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1 15911208 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3161032 system.ruby.delayVCHist.vnet_0::bucket_size 1024 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 10239 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 1525319 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 436.653207 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 606.114709 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1261085 82.68% 82.68% | 228712 14.99% 97.67% | 33514 2.20% 99.87% | 1886 0.12% 99.99% | 92 0.01% 100.00% | 18 0.00% 100.00% | 9 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 1525319 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 1555371 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 430.379487 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 599.375282 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 1294316 83.22% 83.22% | 226078 14.54% 97.75% | 33026 2.12% 99.87% | 1833 0.12% 99.99% | 87 0.01% 100.00% | 19 0.00% 100.00% | 6 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 1555371 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 8 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 79 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 2716111 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 2.646488 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 4.287866 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 2267179 83.47% 83.47% | 385375 14.19% 97.66% | 58403 2.15% 99.81% | 4927 0.18% 99.99% | 220 0.01% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 2716111 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 2771681 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 2.627178 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 4.263769 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 2317910 83.63% 83.63% | 390114 14.07% 97.70% | 58568 2.11% 99.82% | 4852 0.18% 99.99% | 227 0.01% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 2771681 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 589687 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.009836 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.140055 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 586790 99.51% 99.51% | 0 0.00% 99.51% | 2894 0.49% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 589687 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 602307 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.009879 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.140403 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 599336 99.51% 99.51% | 0 0.00% 99.51% | 2967 0.49% 100.00% | 0 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 602307 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 395022 -system.ruby.LD.latency_hist::mean 1526.257907 -system.ruby.LD.latency_hist::gmean 1178.948125 -system.ruby.LD.latency_hist::stdev 896.605628 -system.ruby.LD.latency_hist | 67167 17.00% 17.00% | 71841 18.19% 35.19% | 64604 16.35% 51.54% | 63098 15.97% 67.52% | 66230 16.77% 84.28% | 48099 12.18% 96.46% | 13081 3.31% 99.77% | 895 0.23% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 395022 +system.ruby.LD.latency_hist::samples 399945 +system.ruby.LD.latency_hist::mean 1530.593369 +system.ruby.LD.latency_hist::gmean 1160.417441 +system.ruby.LD.latency_hist::stdev 924.127804 +system.ruby.LD.latency_hist | 73625 18.41% 18.41% | 71506 17.88% 36.29% | 59841 14.96% 51.25% | 59858 14.97% 66.22% | 66785 16.70% 82.92% | 52514 13.13% 96.05% | 14850 3.71% 99.76% | 957 0.24% 100.00% | 9 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 399945 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 6 +system.ruby.LD.hit_latency_hist::samples 9 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 6 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 9 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 395016 -system.ruby.LD.miss_latency_hist::mean 1526.281044 -system.ruby.LD.miss_latency_hist::gmean 1179.055104 -system.ruby.LD.miss_latency_hist::stdev 896.592783 -system.ruby.LD.miss_latency_hist | 67161 17.00% 17.00% | 71841 18.19% 35.19% | 64604 16.35% 51.54% | 63098 15.97% 67.52% | 66230 16.77% 84.28% | 48099 12.18% 96.46% | 13081 3.31% 99.77% | 895 0.23% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 395016 +system.ruby.LD.miss_latency_hist::samples 399936 +system.ruby.LD.miss_latency_hist::mean 1530.627745 +system.ruby.LD.miss_latency_hist::gmean 1160.573034 +system.ruby.LD.miss_latency_hist::stdev 924.109789 +system.ruby.LD.miss_latency_hist | 73616 18.41% 18.41% | 71506 17.88% 36.29% | 59841 14.96% 51.25% | 59858 14.97% 66.22% | 66785 16.70% 82.91% | 52514 13.13% 96.05% | 14850 3.71% 99.76% | 957 0.24% 100.00% | 9 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 399936 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 213616 -system.ruby.ST.latency_hist::mean 1527.002743 -system.ruby.ST.latency_hist::gmean 1180.113141 -system.ruby.ST.latency_hist::stdev 895.963161 -system.ruby.ST.latency_hist | 36156 16.93% 16.93% | 38994 18.25% 35.18% | 34943 16.36% 51.54% | 34153 15.99% 67.53% | 35815 16.77% 84.29% | 26040 12.19% 96.48% | 7013 3.28% 99.76% | 495 0.23% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 213616 +system.ruby.ST.latency_hist::samples 221620 +system.ruby.ST.latency_hist::mean 1528.578535 +system.ruby.ST.latency_hist::gmean 1157.593457 +system.ruby.ST.latency_hist::stdev 925.343815 +system.ruby.ST.latency_hist | 40981 18.49% 18.49% | 39660 17.90% 36.39% | 33332 15.04% 51.43% | 32999 14.89% 66.32% | 36892 16.65% 82.96% | 28932 13.05% 96.02% | 8258 3.73% 99.74% | 557 0.25% 100.00% | 9 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 221620 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 system.ruby.ST.hit_latency_hist::samples 3 @@ -757,211 +757,211 @@ system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | system.ruby.ST.hit_latency_hist::total 3 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 213613 -system.ruby.ST.miss_latency_hist::mean 1527.024146 -system.ruby.ST.miss_latency_hist::gmean 1180.212168 -system.ruby.ST.miss_latency_hist::stdev 895.951249 -system.ruby.ST.miss_latency_hist | 36153 16.92% 16.92% | 38994 18.25% 35.18% | 34943 16.36% 51.54% | 34153 15.99% 67.53% | 35815 16.77% 84.29% | 26040 12.19% 96.48% | 7013 3.28% 99.76% | 495 0.23% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 213613 -system.ruby.L1Cache_Controller.Load | 49252 12.47% 12.47% | 49194 12.45% 24.92% | 49273 12.47% 37.39% | 49508 12.53% 49.93% | 49535 12.54% 62.46% | 49268 12.47% 74.94% | 49241 12.46% 87.40% | 49772 12.60% 100.00% -system.ruby.L1Cache_Controller.Load::total 395043 -system.ruby.L1Cache_Controller.Store | 26995 12.64% 12.64% | 26908 12.60% 25.23% | 26710 12.50% 37.73% | 26861 12.57% 50.31% | 26500 12.40% 62.71% | 26362 12.34% 75.05% | 26514 12.41% 87.46% | 26781 12.54% 100.00% -system.ruby.L1Cache_Controller.Store::total 213631 -system.ruby.L1Cache_Controller.Inv | 73359 12.50% 12.50% | 73446 12.52% 25.02% | 73361 12.50% 37.52% | 73535 12.53% 50.05% | 73248 12.48% 62.53% | 72966 12.43% 74.97% | 73104 12.46% 87.42% | 73798 12.58% 100.00% -system.ruby.L1Cache_Controller.Inv::total 586817 -system.ruby.L1Cache_Controller.L1_Replacement | 531811 12.53% 12.53% | 530092 12.49% 25.02% | 529431 12.47% 37.49% | 530614 12.50% 49.99% | 530965 12.51% 62.50% | 529839 12.48% 74.98% | 528537 12.45% 87.44% | 533293 12.56% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 4244582 -system.ruby.L1Cache_Controller.Fwd_GETX | 236 13.86% 13.86% | 211 12.39% 26.25% | 210 12.33% 38.58% | 225 13.21% 51.79% | 211 12.39% 64.18% | 216 12.68% 76.86% | 180 10.57% 87.43% | 214 12.57% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1703 -system.ruby.L1Cache_Controller.Fwd_GETS | 157 13.45% 13.45% | 164 14.05% 27.51% | 123 10.54% 38.05% | 146 12.51% 50.56% | 141 12.08% 62.64% | 138 11.83% 74.46% | 147 12.60% 87.06% | 151 12.94% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 1167 -system.ruby.L1Cache_Controller.Data | 1 9.09% 9.09% | 2 18.18% 27.27% | 2 18.18% 45.45% | 2 18.18% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Data::total 11 -system.ruby.L1Cache_Controller.Data_Exclusive | 48438 12.46% 12.46% | 48471 12.47% 24.93% | 48461 12.47% 37.39% | 48749 12.54% 49.93% | 48742 12.54% 62.47% | 48430 12.46% 74.93% | 48444 12.46% 87.39% | 49018 12.61% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 388753 -system.ruby.L1Cache_Controller.DataS_fromL1 | 161 13.80% 13.80% | 121 10.37% 24.16% | 137 11.74% 35.90% | 142 12.17% 48.07% | 154 13.20% 61.27% | 167 14.31% 75.58% | 141 12.08% 87.66% | 144 12.34% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 1167 -system.ruby.L1Cache_Controller.Data_all_Acks | 27643 12.64% 12.64% | 27501 12.57% 25.21% | 27378 12.52% 37.73% | 27469 12.56% 50.29% | 27133 12.41% 62.70% | 27025 12.36% 75.06% | 27162 12.42% 87.48% | 27387 12.52% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 218698 -system.ruby.L1Cache_Controller.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 2 18.18% 45.45% | 2 18.18% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Ack::total 11 -system.ruby.L1Cache_Controller.Ack_all | 1 9.09% 9.09% | 2 18.18% 27.27% | 2 18.18% 45.45% | 2 18.18% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 11 -system.ruby.L1Cache_Controller.WB_Ack | 39272 12.54% 12.54% | 39144 12.50% 25.04% | 39156 12.50% 37.54% | 39476 12.61% 50.15% | 39064 12.47% 62.62% | 38757 12.38% 75.00% | 38627 12.33% 87.34% | 39657 12.66% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 313153 -system.ruby.L1Cache_Controller.NP.Load | 49241 12.47% 12.47% | 49181 12.45% 24.92% | 49262 12.47% 37.39% | 49502 12.53% 49.92% | 49529 12.54% 62.46% | 49255 12.47% 74.94% | 49238 12.47% 87.40% | 49760 12.60% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 394968 -system.ruby.L1Cache_Controller.NP.Store | 26992 12.64% 12.64% | 26905 12.60% 25.23% | 26705 12.50% 37.74% | 26855 12.57% 50.31% | 26496 12.40% 62.71% | 26357 12.34% 75.05% | 26509 12.41% 87.47% | 26773 12.53% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 213592 -system.ruby.L1Cache_Controller.NP.Inv | 208 13.88% 13.88% | 188 12.54% 26.42% | 157 10.47% 36.89% | 198 13.21% 50.10% | 184 12.27% 62.37% | 217 14.48% 76.85% | 178 11.87% 88.73% | 169 11.27% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 1499 -system.ruby.L1Cache_Controller.I.Load | 9 14.52% 14.52% | 10 16.13% 30.65% | 10 16.13% 46.77% | 5 8.06% 54.84% | 6 9.68% 64.52% | 10 16.13% 80.65% | 1 1.61% 82.26% | 11 17.74% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 62 -system.ruby.L1Cache_Controller.I.Store | 3 9.68% 9.68% | 3 9.68% 19.35% | 5 16.13% 35.48% | 4 12.90% 48.39% | 2 6.45% 54.84% | 4 12.90% 67.74% | 3 9.68% 77.42% | 7 22.58% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 31 -system.ruby.L1Cache_Controller.I.L1_Replacement | 36814 12.51% 12.51% | 36809 12.51% 25.02% | 36687 12.47% 37.48% | 36740 12.48% 49.97% | 36828 12.51% 62.48% | 36690 12.47% 74.95% | 36978 12.57% 87.51% | 36747 12.49% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 294293 -system.ruby.L1Cache_Controller.S.Inv | 689 12.91% 12.91% | 611 11.44% 24.35% | 695 13.02% 37.37% | 637 11.93% 49.30% | 678 12.70% 62.00% | 676 12.66% 74.66% | 689 12.91% 87.56% | 664 12.44% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 5339 -system.ruby.L1Cache_Controller.S.L1_Replacement | 142 13.28% 13.28% | 128 11.97% 25.26% | 118 11.04% 36.30% | 134 12.54% 48.83% | 128 11.97% 60.80% | 158 14.78% 75.58% | 137 12.82% 88.40% | 124 11.60% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1069 -system.ruby.L1Cache_Controller.E.Load | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 2 -system.ruby.L1Cache_Controller.E.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::samples 221617 +system.ruby.ST.miss_latency_hist::mean 1528.599187 +system.ruby.ST.miss_latency_hist::gmean 1157.686785 +system.ruby.ST.miss_latency_hist::stdev 925.333054 +system.ruby.ST.miss_latency_hist | 40978 18.49% 18.49% | 39660 17.90% 36.39% | 33332 15.04% 51.43% | 32999 14.89% 66.32% | 36892 16.65% 82.96% | 28932 13.05% 96.02% | 8258 3.73% 99.74% | 557 0.25% 100.00% | 9 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 221617 +system.ruby.L1Cache_Controller.Load | 50236 12.56% 12.56% | 49894 12.47% 25.03% | 50153 12.54% 37.57% | 49767 12.44% 50.02% | 49684 12.42% 62.44% | 50353 12.59% 75.03% | 49936 12.48% 87.51% | 49945 12.49% 100.00% +system.ruby.L1Cache_Controller.Load::total 399968 +system.ruby.L1Cache_Controller.Store | 27386 12.36% 12.36% | 27661 12.48% 24.84% | 27570 12.44% 37.28% | 27987 12.63% 49.90% | 27654 12.48% 62.38% | 27899 12.59% 74.97% | 27728 12.51% 87.48% | 27746 12.52% 100.00% +system.ruby.L1Cache_Controller.Store::total 221631 +system.ruby.L1Cache_Controller.Inv | 74856 12.49% 12.49% | 74820 12.48% 24.97% | 74997 12.51% 37.48% | 74956 12.50% 49.99% | 74597 12.44% 62.43% | 75407 12.58% 75.01% | 74858 12.49% 87.50% | 74930 12.50% 100.00% +system.ruby.L1Cache_Controller.Inv::total 599421 +system.ruby.L1Cache_Controller.L1_Replacement | 542695 12.51% 12.51% | 541445 12.48% 24.99% | 542478 12.51% 37.50% | 543601 12.53% 50.03% | 541049 12.47% 62.50% | 543626 12.53% 75.03% | 541855 12.49% 87.52% | 541193 12.48% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 4337942 +system.ruby.L1Cache_Controller.Fwd_GETX | 217 12.70% 12.70% | 220 12.87% 25.57% | 202 11.82% 37.39% | 225 13.17% 50.56% | 192 11.23% 61.79% | 220 12.87% 74.66% | 212 12.40% 87.07% | 221 12.93% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1709 +system.ruby.L1Cache_Controller.Fwd_GETS | 152 12.91% 12.91% | 142 12.06% 24.98% | 141 11.98% 36.96% | 157 13.34% 50.30% | 153 13.00% 63.30% | 129 10.96% 74.26% | 153 13.00% 87.26% | 150 12.74% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 1177 +system.ruby.L1Cache_Controller.Data | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.Data::total 8 +system.ruby.L1Cache_Controller.Data_Exclusive | 49440 12.56% 12.56% | 49131 12.48% 25.04% | 49410 12.55% 37.59% | 48945 12.43% 50.02% | 48917 12.42% 62.44% | 49564 12.59% 75.03% | 49152 12.48% 87.51% | 49164 12.49% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 393723 +system.ruby.L1Cache_Controller.DataS_fromL1 | 142 12.06% 12.06% | 147 12.49% 24.55% | 130 11.05% 35.60% | 156 13.25% 48.85% | 135 11.47% 60.32% | 153 13.00% 73.32% | 154 13.08% 86.41% | 160 13.59% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 1177 +system.ruby.L1Cache_Controller.Data_all_Acks | 28031 12.37% 12.37% | 28268 12.47% 24.84% | 28175 12.43% 37.27% | 28645 12.64% 49.91% | 28282 12.48% 62.39% | 28530 12.59% 74.98% | 28353 12.51% 87.49% | 28361 12.51% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 226645 +system.ruby.L1Cache_Controller.Ack | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.Ack::total 8 +system.ruby.L1Cache_Controller.Ack_all | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 8 +system.ruby.L1Cache_Controller.WB_Ack | 39736 12.52% 12.52% | 39410 12.42% 24.94% | 39809 12.55% 37.49% | 39602 12.48% 49.97% | 39341 12.40% 62.37% | 40066 12.63% 75.00% | 39585 12.48% 87.47% | 39746 12.53% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 317295 +system.ruby.L1Cache_Controller.NP.Load | 50223 12.56% 12.56% | 49884 12.47% 25.03% | 50144 12.54% 37.57% | 49760 12.44% 50.02% | 49674 12.42% 62.44% | 50340 12.59% 75.03% | 49925 12.48% 87.51% | 49934 12.49% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 399884 +system.ruby.L1Cache_Controller.NP.Store | 27380 12.36% 12.36% | 27654 12.48% 24.84% | 27568 12.44% 37.28% | 27981 12.63% 49.91% | 27651 12.48% 62.38% | 27892 12.59% 74.97% | 27718 12.51% 87.48% | 27743 12.52% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 221587 +system.ruby.L1Cache_Controller.NP.Inv | 202 12.95% 12.95% | 197 12.63% 25.58% | 189 12.12% 37.69% | 201 12.88% 50.58% | 175 11.22% 61.79% | 194 12.44% 74.23% | 210 13.46% 87.69% | 192 12.31% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 1560 +system.ruby.L1Cache_Controller.I.Load | 10 15.15% 15.15% | 8 12.12% 27.27% | 7 10.61% 37.88% | 6 9.09% 46.97% | 9 13.64% 60.61% | 10 15.15% 75.76% | 8 12.12% 87.88% | 8 12.12% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 66 +system.ruby.L1Cache_Controller.I.Store | 5 13.16% 13.16% | 5 13.16% 26.32% | 1 2.63% 28.95% | 5 13.16% 42.11% | 3 7.89% 50.00% | 6 15.79% 65.79% | 10 26.32% 92.11% | 3 7.89% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 38 +system.ruby.L1Cache_Controller.I.L1_Replacement | 37717 12.45% 12.45% | 37982 12.53% 24.98% | 37762 12.46% 37.44% | 38005 12.54% 49.98% | 37865 12.49% 62.48% | 38010 12.54% 75.02% | 37909 12.51% 87.53% | 37797 12.47% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 303047 +system.ruby.L1Cache_Controller.S.Inv | 645 12.46% 12.46% | 625 12.07% 24.53% | 615 11.88% 36.40% | 691 13.34% 49.75% | 653 12.61% 62.36% | 646 12.48% 74.84% | 652 12.59% 87.43% | 651 12.57% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 5178 +system.ruby.L1Cache_Controller.S.L1_Replacement | 145 13.33% 13.33% | 138 12.68% 26.01% | 136 12.50% 38.51% | 128 11.76% 50.28% | 115 10.57% 60.85% | 152 13.97% 74.82% | 145 13.33% 88.14% | 129 11.86% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1088 +system.ruby.L1Cache_Controller.E.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 6 +system.ruby.L1Cache_Controller.E.Store | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.E.Store::total 3 -system.ruby.L1Cache_Controller.E.Inv | 23113 12.44% 12.44% | 23183 12.48% 24.92% | 23083 12.42% 37.34% | 23138 12.45% 49.80% | 23334 12.56% 62.36% | 23218 12.50% 74.86% | 23460 12.63% 87.48% | 23252 12.52% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 185781 -system.ruby.L1Cache_Controller.E.L1_Replacement | 25258 12.48% 12.48% | 25225 12.46% 24.93% | 25322 12.51% 37.44% | 25551 12.62% 50.06% | 25345 12.52% 62.58% | 25152 12.42% 75.00% | 24925 12.31% 87.31% | 25684 12.69% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 202462 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 57 13.41% 13.41% | 57 13.41% 26.82% | 48 11.29% 38.12% | 52 12.24% 50.35% | 49 11.53% 61.88% | 54 12.71% 74.59% | 46 10.82% 85.41% | 62 14.59% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 425 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 10 12.35% 12.35% | 6 7.41% 19.75% | 8 9.88% 29.63% | 8 9.88% 39.51% | 13 16.05% 55.56% | 5 6.17% 61.73% | 12 14.81% 76.54% | 19 23.46% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 81 -system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 3 75.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 4 -system.ruby.L1Cache_Controller.M.Inv | 12878 12.61% 12.61% | 12884 12.61% 25.22% | 12783 12.51% 37.73% | 12837 12.57% 50.30% | 12701 12.43% 62.73% | 12661 12.39% 75.12% | 12709 12.44% 87.56% | 12708 12.44% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 102161 -system.ruby.L1Cache_Controller.M.L1_Replacement | 14015 12.66% 12.66% | 13920 12.57% 25.23% | 13836 12.50% 37.73% | 13928 12.58% 50.31% | 13720 12.39% 62.71% | 13608 12.29% 75.00% | 13703 12.38% 87.38% | 13974 12.62% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 110704 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 39 13.68% 13.68% | 33 11.58% 25.26% | 41 14.39% 39.65% | 37 12.98% 52.63% | 32 11.23% 63.86% | 36 12.63% 76.49% | 30 10.53% 87.02% | 37 12.98% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 285 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 62 13.33% 13.33% | 70 15.05% 28.39% | 49 10.54% 38.92% | 54 11.61% 50.54% | 45 9.68% 60.22% | 57 12.26% 72.47% | 69 14.84% 87.31% | 59 12.69% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 465 -system.ruby.L1Cache_Controller.IS.Inv | 52 12.97% 12.97% | 54 13.47% 26.43% | 52 12.97% 39.40% | 48 11.97% 51.37% | 44 10.97% 62.34% | 61 15.21% 77.56% | 48 11.97% 89.53% | 42 10.47% 100.00% -system.ruby.L1Cache_Controller.IS.Inv::total 401 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 294115 12.47% 12.47% | 293860 12.46% 24.92% | 293400 12.44% 37.36% | 295550 12.53% 49.89% | 297332 12.60% 62.49% | 295579 12.53% 75.02% | 293015 12.42% 87.44% | 296279 12.56% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2359130 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 48438 12.46% 12.46% | 48471 12.47% 24.93% | 48461 12.47% 37.39% | 48749 12.54% 49.93% | 48742 12.54% 62.47% | 48430 12.46% 74.93% | 48444 12.46% 87.39% | 49018 12.61% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 388753 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 161 13.80% 13.80% | 121 10.37% 24.16% | 137 11.74% 35.90% | 142 12.17% 48.07% | 154 13.20% 61.27% | 167 14.31% 75.58% | 141 12.08% 87.66% | 144 12.34% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1167 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 598 12.74% 12.74% | 542 11.54% 24.28% | 619 13.18% 37.47% | 567 12.08% 49.54% | 594 12.65% 62.19% | 605 12.89% 75.08% | 604 12.86% 87.94% | 566 12.06% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4695 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 161466 12.64% 12.64% | 160150 12.54% 25.19% | 160068 12.54% 37.72% | 158711 12.43% 50.15% | 157612 12.34% 62.49% | 158652 12.42% 74.92% | 159779 12.51% 87.43% | 160485 12.57% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1276923 -system.ruby.L1Cache_Controller.IM.Data | 1 9.09% 9.09% | 2 18.18% 27.27% | 2 18.18% 45.45% | 2 18.18% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 11 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 26993 12.64% 12.64% | 26905 12.60% 25.23% | 26707 12.50% 37.74% | 26854 12.57% 50.31% | 26495 12.40% 62.71% | 26359 12.34% 75.05% | 26510 12.41% 87.46% | 26779 12.54% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 213602 -system.ruby.L1Cache_Controller.SM.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 2 18.18% 45.45% | 2 18.18% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 11 -system.ruby.L1Cache_Controller.SM.Ack_all | 1 9.09% 9.09% | 2 18.18% 27.27% | 2 18.18% 45.45% | 2 18.18% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 11 -system.ruby.L1Cache_Controller.IS_I.L1_Replacement | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_I.L1_Replacement::total 1 -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 52 12.97% 12.97% | 54 13.47% 26.43% | 52 12.97% 39.40% | 48 11.97% 51.37% | 44 10.97% 62.34% | 61 15.21% 77.56% | 48 11.97% 89.53% | 42 10.47% 100.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 401 +system.ruby.L1Cache_Controller.E.Inv | 23729 12.47% 12.47% | 23871 12.54% 25.01% | 23901 12.56% 37.57% | 23696 12.45% 50.02% | 23788 12.50% 62.52% | 23896 12.56% 75.07% | 23793 12.50% 87.57% | 23649 12.43% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 190323 +system.ruby.L1Cache_Controller.E.L1_Replacement | 25649 12.64% 12.64% | 25189 12.42% 25.06% | 25440 12.54% 37.60% | 25187 12.41% 50.01% | 25067 12.36% 62.37% | 25597 12.62% 74.98% | 25302 12.47% 87.46% | 25450 12.54% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 202881 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 53 11.75% 11.75% | 63 13.97% 25.72% | 61 13.53% 39.25% | 55 12.20% 51.44% | 48 10.64% 62.08% | 64 14.19% 76.27% | 50 11.09% 87.36% | 57 12.64% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 451 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 9 14.06% 14.06% | 7 10.94% 25.00% | 7 10.94% 35.94% | 6 9.38% 45.31% | 14 21.88% 67.19% | 6 9.38% 76.56% | 7 10.94% 87.50% | 8 12.50% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 64 +system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 3 +system.ruby.L1Cache_Controller.M.Inv | 13206 12.40% 12.40% | 13343 12.53% 24.93% | 13115 12.32% 37.25% | 13481 12.66% 49.91% | 13301 12.49% 62.40% | 13334 12.52% 74.92% | 13349 12.54% 87.45% | 13362 12.55% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 106491 +system.ruby.L1Cache_Controller.M.L1_Replacement | 14088 12.31% 12.31% | 14225 12.43% 24.74% | 14370 12.56% 37.30% | 14417 12.60% 49.90% | 14274 12.47% 62.38% | 14469 12.65% 75.02% | 14283 12.48% 87.51% | 14297 12.49% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 114423 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 35 13.73% 13.73% | 31 12.16% 25.88% | 27 10.59% 36.47% | 33 12.94% 49.41% | 26 10.20% 59.61% | 36 14.12% 73.73% | 35 13.73% 87.45% | 32 12.55% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 255 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 56 12.42% 12.42% | 58 12.86% 25.28% | 56 12.42% 37.69% | 55 12.20% 49.89% | 53 11.75% 61.64% | 59 13.08% 74.72% | 59 13.08% 87.80% | 55 12.20% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 451 +system.ruby.L1Cache_Controller.IS.Inv | 64 13.85% 13.85% | 62 13.42% 27.27% | 52 11.26% 38.53% | 60 12.99% 51.52% | 62 13.42% 64.94% | 53 11.47% 76.41% | 50 10.82% 87.23% | 59 12.77% 100.00% +system.ruby.L1Cache_Controller.IS.Inv::total 462 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 301738 12.61% 12.61% | 299281 12.51% 25.13% | 299379 12.52% 37.64% | 298179 12.47% 50.11% | 298458 12.48% 62.58% | 299615 12.53% 75.11% | 297962 12.46% 87.56% | 297489 12.44% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2392101 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49440 12.56% 12.56% | 49131 12.48% 25.04% | 49410 12.55% 37.59% | 48945 12.43% 50.02% | 48917 12.42% 62.44% | 49564 12.59% 75.03% | 49152 12.48% 87.51% | 49164 12.49% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 393723 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 142 12.06% 12.06% | 147 12.49% 24.55% | 130 11.05% 35.60% | 156 13.25% 48.85% | 135 11.47% 60.32% | 153 13.00% 73.32% | 154 13.08% 86.41% | 160 13.59% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1177 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 583 12.75% 12.75% | 551 12.05% 24.79% | 558 12.20% 36.99% | 602 13.16% 50.15% | 566 12.37% 62.53% | 580 12.68% 75.21% | 577 12.61% 87.82% | 557 12.18% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4574 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 163358 12.33% 12.33% | 164630 12.43% 24.76% | 165391 12.49% 37.25% | 167685 12.66% 49.91% | 165270 12.48% 62.39% | 165783 12.52% 74.91% | 166254 12.55% 87.46% | 166031 12.54% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1324402 +system.ruby.L1Cache_Controller.IM.Data | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 8 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27384 12.36% 12.36% | 27655 12.48% 24.84% | 27565 12.44% 37.27% | 27983 12.63% 49.90% | 27654 12.48% 62.38% | 27897 12.59% 74.97% | 27726 12.51% 87.48% | 27745 12.52% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 221609 +system.ruby.L1Cache_Controller.SM.Ack | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 8 +system.ruby.L1Cache_Controller.SM.Ack_all | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 8 +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 64 13.85% 13.85% | 62 13.42% 27.27% | 52 11.26% 38.53% | 60 12.99% 51.52% | 62 13.42% 64.94% | 53 11.47% 76.41% | 50 10.82% 87.23% | 59 12.77% 100.00% +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 462 system.ruby.L1Cache_Controller.M_I.Load | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M_I.Load::total 1 -system.ruby.L1Cache_Controller.M_I.Inv | 36400 12.49% 12.49% | 36498 12.52% 25.01% | 36564 12.55% 37.56% | 36657 12.58% 50.14% | 36280 12.45% 62.58% | 36116 12.39% 74.98% | 35995 12.35% 87.33% | 36935 12.67% 100.00% -system.ruby.L1Cache_Controller.M_I.Inv::total 291445 -system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 140 14.10% 14.10% | 121 12.19% 26.28% | 121 12.19% 38.47% | 136 13.70% 52.17% | 130 13.09% 65.26% | 126 12.69% 77.95% | 104 10.47% 88.42% | 115 11.58% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 993 -system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 85 13.69% 13.69% | 88 14.17% 27.86% | 66 10.63% 38.49% | 84 13.53% 52.01% | 83 13.37% 65.38% | 76 12.24% 77.62% | 66 10.63% 88.24% | 73 11.76% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 621 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 2648 13.17% 13.17% | 2438 12.13% 25.29% | 2407 11.97% 37.27% | 2602 12.94% 50.21% | 2572 12.79% 63.00% | 2442 12.15% 75.14% | 2463 12.25% 87.39% | 2535 12.61% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 20107 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 3 50.00% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 6 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 5 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 19 9.95% 9.95% | 28 14.66% 24.61% | 27 14.14% 38.74% | 20 10.47% 49.21% | 27 14.14% 63.35% | 17 8.90% 72.25% | 25 13.09% 85.34% | 28 14.66% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 191 -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 36624 12.50% 12.50% | 36706 12.53% 25.02% | 36749 12.54% 37.56% | 36874 12.58% 50.15% | 36492 12.45% 62.60% | 36315 12.39% 74.99% | 36164 12.34% 87.33% | 37122 12.67% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 293046 -system.ruby.L2Cache_Controller.L1_GETS 396762 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 216001 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 21849 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 297986 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 8404 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 4560569 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 603179 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 603168 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 205785 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 188987 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 3711 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 189477 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 1167 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 602364 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 391290 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 211894 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 277792 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 11 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX 437 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.Inv | 36980 12.53% 12.53% | 36704 12.43% 24.96% | 37100 12.57% 37.53% | 36804 12.47% 49.99% | 36592 12.39% 62.39% | 37262 12.62% 75.01% | 36782 12.46% 87.47% | 36993 12.53% 100.00% +system.ruby.L1Cache_Controller.M_I.Inv::total 295217 +system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 129 12.86% 12.86% | 126 12.56% 25.42% | 114 11.37% 36.79% | 137 13.66% 50.45% | 118 11.76% 62.21% | 120 11.96% 74.18% | 127 12.66% 86.84% | 132 13.16% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1003 +system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 87 13.14% 13.14% | 77 11.63% 24.77% | 78 11.78% 36.56% | 96 14.50% 51.06% | 86 12.99% 64.05% | 64 9.67% 73.72% | 87 13.14% 86.86% | 87 13.14% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 662 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 2541 12.44% 12.44% | 2507 12.28% 24.72% | 2518 12.33% 37.05% | 2567 12.57% 49.62% | 2545 12.46% 62.08% | 2620 12.83% 74.91% | 2589 12.68% 87.59% | 2535 12.41% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 20422 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 2 25.00% 25.00% | 1 12.50% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 1 12.50% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 8 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 3 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 30 15.79% 15.79% | 18 9.47% 25.26% | 25 13.16% 38.42% | 23 12.11% 50.53% | 26 13.68% 64.21% | 22 11.58% 75.79% | 22 11.58% 87.37% | 24 12.63% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 190 +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 37195 12.53% 12.53% | 36903 12.43% 24.96% | 37291 12.56% 37.52% | 37035 12.48% 50.00% | 36796 12.39% 62.39% | 37446 12.61% 75.00% | 36996 12.46% 87.47% | 37211 12.53% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 296873 +system.ruby.L2Cache_Controller.L1_GETS 401738 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 224009 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 22269 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 301959 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 8861 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 4613091 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 616121 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 616114 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 213442 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 189443 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 3694 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 194003 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 1177 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 615339 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 396229 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 219899 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_PUTX_old 281116 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 8 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX 480 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L1_PUTX_old 3 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 1068 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2629 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 7166 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 12926 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 1167 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 1703 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 20107 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX_old 755 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 6 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 579381 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETS 220 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETX 138 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 13507 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 603168 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETS 68 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETX 70 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 5372 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 204712 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 188889 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 185778 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 2639 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 2629 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 1072 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 1068 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETS 2541 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETX 1297 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 249 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2131813 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 388746 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETS 10 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETX 4 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 13821 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 2541 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETS 1307 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETX 792 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_PUTX_old 303 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1159948 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 211892 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 10 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 11 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 1094 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2586 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 4 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 7542 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 12867 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 1177 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 1709 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 20422 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX_old 744 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 9 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 592022 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETS 235 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETX 156 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 13986 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 616114 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETS 59 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETX 87 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 5561 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 212344 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 189361 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 190317 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 2594 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 2586 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 1100 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 1094 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETS 2511 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETX 1295 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 278 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2138971 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 393714 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETS 8 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETX 5 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 13802 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 2511 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETS 1354 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETX 755 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_PUTX_old 265 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1192970 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 219896 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 11 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 8 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_GETS 144 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 83 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 815 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 657343 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 602353 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 490 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 91 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 840 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 656961 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 615331 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 525 0.00% 0.00% system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 3 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2686 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 763 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 60 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2875 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 778 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 55 0.00% 0.00% system.ruby.L2Cache_Controller.MT_IIB.Unblock 344 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 12 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 306 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 38 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 164 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 823 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 603181 0.00% 0.00% -system.ruby.Directory_Controller.Data 212951 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 603180 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 212946 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 390222 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 603181 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 212951 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 390222 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 603180 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 212946 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 26 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 317 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 27 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 210 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 833 0.00% 0.00% +system.ruby.Directory_Controller.Fetch 616128 0.00% 0.00% +system.ruby.Directory_Controller.Data 220989 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 616122 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 220986 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 395129 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 616128 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 220989 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 395129 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 616122 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 220986 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 9ceb39be3..9c9c7aca3 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,1171 +1,1155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007481 # Number of seconds simulated -sim_ticks 7481441 # Number of ticks simulated -final_tick 7481441 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007646 # Number of seconds simulated +sim_ticks 7645897 # Number of ticks simulated +final_tick 7645897 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 57492 # Simulator tick rate (ticks/s) -host_mem_usage 261156 # Number of bytes of host memory used -host_seconds 130.13 # Real time elapsed on the host +host_tick_rate 53519 # Simulator tick rate (ticks/s) +host_mem_usage 294536 # Number of bytes of host memory used +host_seconds 142.86 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 619788 -system.ruby.outstanding_req_hist::mean 15.998438 -system.ruby.outstanding_req_hist::gmean 15.997160 -system.ruby.outstanding_req_hist::stdev 0.126554 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 24 0.00% 0.02% | 619660 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 619788 +system.ruby.outstanding_req_hist::samples 632255 +system.ruby.outstanding_req_hist::mean 15.998472 +system.ruby.outstanding_req_hist::gmean 15.997219 +system.ruby.outstanding_req_hist::stdev 0.125288 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 22 0.00% 0.02% | 632129 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 632255 system.ruby.latency_hist::bucket_size 2048 system.ruby.latency_hist::max_bucket 20479 -system.ruby.latency_hist::samples 619660 -system.ruby.latency_hist::mean 1545.012692 -system.ruby.latency_hist::gmean 1029.214657 -system.ruby.latency_hist::stdev 1540.360700 -system.ruby.latency_hist | 466947 75.36% 75.36% | 106679 17.22% 92.57% | 32906 5.31% 97.88% | 9679 1.56% 99.44% | 2729 0.44% 99.88% | 577 0.09% 99.98% | 129 0.02% 100.00% | 11 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 619660 +system.ruby.latency_hist::samples 632127 +system.ruby.latency_hist::mean 1547.883220 +system.ruby.latency_hist::gmean 1029.918853 +system.ruby.latency_hist::stdev 1546.131099 +system.ruby.latency_hist | 476382 75.36% 75.36% | 108333 17.14% 92.50% | 33808 5.35% 97.85% | 10098 1.60% 99.45% | 2721 0.43% 99.88% | 625 0.10% 99.97% | 124 0.02% 99.99% | 33 0.01% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 632127 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 192 +system.ruby.hit_latency_hist::samples 166 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 192 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 192 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 166 system.ruby.miss_latency_hist::bucket_size 2048 system.ruby.miss_latency_hist::max_bucket 20479 -system.ruby.miss_latency_hist::samples 619468 -system.ruby.miss_latency_hist::mean 1545.490629 -system.ruby.miss_latency_hist::gmean 1031.078635 -system.ruby.miss_latency_hist::stdev 1540.360114 -system.ruby.miss_latency_hist | 466755 75.35% 75.35% | 106679 17.22% 92.57% | 32906 5.31% 97.88% | 9679 1.56% 99.44% | 2729 0.44% 99.88% | 577 0.09% 99.98% | 129 0.02% 100.00% | 11 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 619468 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 21 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 77428 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77449 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 631961 +system.ruby.miss_latency_hist::mean 1548.289021 +system.ruby.miss_latency_hist::gmean 1031.499608 +system.ruby.miss_latency_hist::stdev 1546.131374 +system.ruby.miss_latency_hist | 476216 75.36% 75.36% | 108333 17.14% 92.50% | 33808 5.35% 97.85% | 10098 1.60% 99.45% | 2721 0.43% 99.88% | 625 0.10% 99.97% | 124 0.02% 99.99% | 33 0.01% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 631961 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 27 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 79125 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 79152 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Dcache.demand_hits 25 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 77511 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77536 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 27 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78996 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 79023 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 21 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 77666 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77687 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 14 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 79210 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 79224 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 23 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 77528 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77551 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78757 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78774 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 27 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 77272 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 77299 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 22 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 79077 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 79099 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 30 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 77679 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77709 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78940 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78949 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 77082 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77096 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 26 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 79113 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 79139 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 31 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 77329 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 77360 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 24 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78765 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78789 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l2_cntrl0.L2cache.demand_hits 5922 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 613572 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 619494 # Number of cache demand accesses -system.ruby.network.routers00.percent_links_utilized 5.689262 -system.ruby.network.routers00.msg_count.Request_Control::0 77272 -system.ruby.network.routers00.msg_count.Response_Data::2 75499 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 705 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 2146 -system.ruby.network.routers00.msg_count.Response_Control::2 382 -system.ruby.network.routers00.msg_count.Writeback_Data::2 76215 -system.ruby.network.routers00.msg_count.Writeback_Control::0 154485 -system.ruby.network.routers00.msg_count.Forwarded_Control::0 1082 -system.ruby.network.routers00.msg_count.Invalidate_Control::0 6 -system.ruby.network.routers00.msg_count.Unblock_Control::2 78243 -system.ruby.network.routers00.msg_bytes.Request_Control::0 618176 -system.ruby.network.routers00.msg_bytes.Response_Data::2 5435928 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2 50760 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2 154512 -system.ruby.network.routers00.msg_bytes.Response_Control::2 3056 -system.ruby.network.routers00.msg_bytes.Writeback_Data::2 5487480 -system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1235880 -system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 8656 -system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 48 -system.ruby.network.routers00.msg_bytes.Unblock_Control::2 625944 -system.ruby.network.routers01.percent_links_utilized 5.720198 -system.ruby.network.routers01.msg_count.Request_Control::0 77679 -system.ruby.network.routers01.msg_count.Response_Data::2 75857 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 752 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 2136 -system.ruby.network.routers01.msg_count.Response_Control::2 379 -system.ruby.network.routers01.msg_count.Writeback_Data::2 76673 -system.ruby.network.routers01.msg_count.Writeback_Control::0 155314 -system.ruby.network.routers01.msg_count.Forwarded_Control::0 1069 -system.ruby.network.routers01.msg_count.Invalidate_Control::0 3 -system.ruby.network.routers01.msg_count.Unblock_Control::2 78607 -system.ruby.network.routers01.msg_bytes.Request_Control::0 621432 -system.ruby.network.routers01.msg_bytes.Response_Data::2 5461704 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 54144 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 153792 -system.ruby.network.routers01.msg_bytes.Response_Control::2 3032 -system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5520456 -system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1242512 -system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 8552 -system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 24 -system.ruby.network.routers01.msg_bytes.Unblock_Control::2 628856 -system.ruby.network.routers02.percent_links_utilized 5.676229 -system.ruby.network.routers02.msg_count.Request_Control::0 77082 -system.ruby.network.routers02.msg_count.Response_Data::2 75271 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 752 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 2100 -system.ruby.network.routers02.msg_count.Response_Control::2 382 -system.ruby.network.routers02.msg_count.Writeback_Data::2 76103 -system.ruby.network.routers02.msg_count.Writeback_Control::0 154124 -system.ruby.network.routers02.msg_count.Forwarded_Control::0 1045 -system.ruby.network.routers02.msg_count.Unblock_Control::2 77988 -system.ruby.network.routers02.msg_bytes.Request_Control::0 616656 -system.ruby.network.routers02.msg_bytes.Response_Data::2 5419512 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 54144 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 151200 -system.ruby.network.routers02.msg_bytes.Response_Control::2 3056 -system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5479416 -system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1232992 -system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 8360 -system.ruby.network.routers02.msg_bytes.Unblock_Control::2 623904 -system.ruby.network.routers03.percent_links_utilized 5.695076 -system.ruby.network.routers03.msg_count.Request_Control::0 77329 -system.ruby.network.routers03.msg_count.Response_Data::2 75554 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2 792 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::2 2076 -system.ruby.network.routers03.msg_count.Response_Control::2 354 -system.ruby.network.routers03.msg_count.Writeback_Data::2 76314 -system.ruby.network.routers03.msg_count.Writeback_Control::0 154618 -system.ruby.network.routers03.msg_count.Forwarded_Control::0 1099 -system.ruby.network.routers03.msg_count.Invalidate_Control::0 3 -system.ruby.network.routers03.msg_count.Unblock_Control::2 78268 -system.ruby.network.routers03.msg_bytes.Request_Control::0 618632 -system.ruby.network.routers03.msg_bytes.Response_Data::2 5439888 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2 57024 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2 149472 -system.ruby.network.routers03.msg_bytes.Response_Control::2 2832 -system.ruby.network.routers03.msg_bytes.Writeback_Data::2 5494608 -system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1236944 -system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 8792 -system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 24 -system.ruby.network.routers03.msg_bytes.Unblock_Control::2 626144 -system.ruby.network.routers04.percent_links_utilized 5.699310 -system.ruby.network.routers04.msg_count.Request_Control::0 77428 -system.ruby.network.routers04.msg_count.Response_Data::2 75631 -system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2 720 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 2101 -system.ruby.network.routers04.msg_count.Response_Control::2 374 -system.ruby.network.routers04.msg_count.Writeback_Data::2 76387 -system.ruby.network.routers04.msg_count.Writeback_Control::0 154786 -system.ruby.network.routers04.msg_count.Forwarded_Control::0 1028 -system.ruby.network.routers04.msg_count.Invalidate_Control::0 2 -system.ruby.network.routers04.msg_count.Unblock_Control::2 78393 -system.ruby.network.routers04.msg_bytes.Request_Control::0 619424 -system.ruby.network.routers04.msg_bytes.Response_Data::2 5445432 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 51840 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 151272 -system.ruby.network.routers04.msg_bytes.Response_Control::2 2992 -system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5499864 -system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1238288 -system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 8224 -system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 16 -system.ruby.network.routers04.msg_bytes.Unblock_Control::2 627144 -system.ruby.network.routers05.percent_links_utilized 5.706217 -system.ruby.network.routers05.msg_count.Request_Control::0 77511 -system.ruby.network.routers05.msg_count.Response_Data::2 75743 -system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2 737 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::2 2056 -system.ruby.network.routers05.msg_count.Response_Control::2 351 -system.ruby.network.routers05.msg_count.Writeback_Data::2 76496 -system.ruby.network.routers05.msg_count.Writeback_Control::0 154988 -system.ruby.network.routers05.msg_count.Forwarded_Control::0 1028 +system.ruby.l2_cntrl0.L2cache.demand_hits 6149 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 625832 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 631981 # Number of cache demand accesses +system.ruby.network.routers00.percent_links_utilized 5.698442 +system.ruby.network.routers00.msg_count.Request_Control::0 79077 +system.ruby.network.routers00.msg_count.Response_Data::2 77245 +system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 780 +system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 2140 +system.ruby.network.routers00.msg_count.Response_Control::2 385 +system.ruby.network.routers00.msg_count.Writeback_Data::2 78067 +system.ruby.network.routers00.msg_count.Writeback_Control::0 158122 +system.ruby.network.routers00.msg_count.Forwarded_Control::0 1092 +system.ruby.network.routers00.msg_count.Invalidate_Control::0 3 +system.ruby.network.routers00.msg_count.Unblock_Control::2 80021 +system.ruby.network.routers00.msg_bytes.Request_Control::0 632616 +system.ruby.network.routers00.msg_bytes.Response_Data::2 5561640 +system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2 56160 +system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2 154080 +system.ruby.network.routers00.msg_bytes.Response_Control::2 3080 +system.ruby.network.routers00.msg_bytes.Writeback_Data::2 5620824 +system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1264976 +system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 8736 +system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 24 +system.ruby.network.routers00.msg_bytes.Unblock_Control::2 640168 +system.ruby.network.routers01.percent_links_utilized 5.685628 +system.ruby.network.routers01.msg_count.Request_Control::0 78939 +system.ruby.network.routers01.msg_count.Response_Data::2 77083 +system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 799 +system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 2117 +system.ruby.network.routers01.msg_count.Response_Control::2 369 +system.ruby.network.routers01.msg_count.Writeback_Data::2 77862 +system.ruby.network.routers01.msg_count.Writeback_Control::0 157816 +system.ruby.network.routers01.msg_count.Forwarded_Control::0 1062 +system.ruby.network.routers01.msg_count.Invalidate_Control::0 1 +system.ruby.network.routers01.msg_count.Unblock_Control::2 79933 +system.ruby.network.routers01.msg_bytes.Request_Control::0 631512 +system.ruby.network.routers01.msg_bytes.Response_Data::2 5549976 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 57528 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 152424 +system.ruby.network.routers01.msg_bytes.Response_Control::2 2952 +system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5606064 +system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1262528 +system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 8496 +system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 8 +system.ruby.network.routers01.msg_bytes.Unblock_Control::2 639464 +system.ruby.network.routers02.percent_links_utilized 5.700427 +system.ruby.network.routers02.msg_count.Request_Control::0 79113 +system.ruby.network.routers02.msg_count.Response_Data::2 77289 +system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 789 +system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 2124 +system.ruby.network.routers02.msg_count.Response_Control::2 368 +system.ruby.network.routers02.msg_count.Writeback_Data::2 78085 +system.ruby.network.routers02.msg_count.Writeback_Control::0 158176 +system.ruby.network.routers02.msg_count.Forwarded_Control::0 1090 +system.ruby.network.routers02.msg_count.Invalidate_Control::0 1 +system.ruby.network.routers02.msg_count.Unblock_Control::2 80064 +system.ruby.network.routers02.msg_bytes.Request_Control::0 632904 +system.ruby.network.routers02.msg_bytes.Response_Data::2 5564808 +system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 56808 +system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 152928 +system.ruby.network.routers02.msg_bytes.Response_Control::2 2944 +system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5622120 +system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1265408 +system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 8720 +system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 8 +system.ruby.network.routers02.msg_bytes.Unblock_Control::2 640512 +system.ruby.network.routers03.percent_links_utilized 5.674514 +system.ruby.network.routers03.msg_count.Request_Control::0 78765 +system.ruby.network.routers03.msg_count.Response_Data::2 76945 +system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2 741 +system.ruby.network.routers03.msg_count.ResponseLocal_Data::2 2155 +system.ruby.network.routers03.msg_count.Response_Control::2 398 +system.ruby.network.routers03.msg_count.Writeback_Data::2 77719 +system.ruby.network.routers03.msg_count.Writeback_Control::0 157450 +system.ruby.network.routers03.msg_count.Forwarded_Control::0 1079 +system.ruby.network.routers03.msg_count.Invalidate_Control::0 2 +system.ruby.network.routers03.msg_count.Unblock_Control::2 79736 +system.ruby.network.routers03.msg_bytes.Request_Control::0 630120 +system.ruby.network.routers03.msg_bytes.Response_Data::2 5540040 +system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2 53352 +system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2 155160 +system.ruby.network.routers03.msg_bytes.Response_Control::2 3184 +system.ruby.network.routers03.msg_bytes.Writeback_Data::2 5595768 +system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1259600 +system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 8632 +system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 16 +system.ruby.network.routers03.msg_bytes.Unblock_Control::2 637888 +system.ruby.network.routers04.percent_links_utilized 5.699724 +system.ruby.network.routers04.msg_count.Request_Control::0 79125 +system.ruby.network.routers04.msg_count.Response_Data::2 77230 +system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2 793 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 2159 +system.ruby.network.routers04.msg_count.Response_Control::2 414 +system.ruby.network.routers04.msg_count.Writeback_Data::2 78072 +system.ruby.network.routers04.msg_count.Writeback_Control::0 158198 +system.ruby.network.routers04.msg_count.Forwarded_Control::0 1060 +system.ruby.network.routers04.msg_count.Invalidate_Control::0 1 +system.ruby.network.routers04.msg_count.Unblock_Control::2 80096 +system.ruby.network.routers04.msg_bytes.Request_Control::0 633000 +system.ruby.network.routers04.msg_bytes.Response_Data::2 5560560 +system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 57096 +system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 155448 +system.ruby.network.routers04.msg_bytes.Response_Control::2 3312 +system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5621184 +system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1265584 +system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 8480 +system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 8 +system.ruby.network.routers04.msg_bytes.Unblock_Control::2 640768 +system.ruby.network.routers05.percent_links_utilized 5.689251 +system.ruby.network.routers05.msg_count.Request_Control::0 78996 +system.ruby.network.routers05.msg_count.Response_Data::2 77132 +system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2 770 +system.ruby.network.routers05.msg_count.ResponseLocal_Data::2 2086 +system.ruby.network.routers05.msg_count.Response_Control::2 391 +system.ruby.network.routers05.msg_count.Writeback_Data::2 77981 +system.ruby.network.routers05.msg_count.Writeback_Control::0 157934 +system.ruby.network.routers05.msg_count.Forwarded_Control::0 994 system.ruby.network.routers05.msg_count.Invalidate_Control::0 1 -system.ruby.network.routers05.msg_count.Unblock_Control::2 78462 -system.ruby.network.routers05.msg_bytes.Request_Control::0 620088 -system.ruby.network.routers05.msg_bytes.Response_Data::2 5453496 -system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2 53064 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2 148032 -system.ruby.network.routers05.msg_bytes.Response_Control::2 2808 -system.ruby.network.routers05.msg_bytes.Writeback_Data::2 5507712 -system.ruby.network.routers05.msg_bytes.Writeback_Control::0 1239904 -system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 8224 +system.ruby.network.routers05.msg_count.Unblock_Control::2 79943 +system.ruby.network.routers05.msg_bytes.Request_Control::0 631968 +system.ruby.network.routers05.msg_bytes.Response_Data::2 5553504 +system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2 55440 +system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2 150192 +system.ruby.network.routers05.msg_bytes.Response_Control::2 3128 +system.ruby.network.routers05.msg_bytes.Writeback_Data::2 5614632 +system.ruby.network.routers05.msg_bytes.Writeback_Control::0 1263472 +system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 7952 system.ruby.network.routers05.msg_bytes.Invalidate_Control::0 8 -system.ruby.network.routers05.msg_bytes.Unblock_Control::2 627696 -system.ruby.network.routers06.percent_links_utilized 5.716967 -system.ruby.network.routers06.msg_count.Request_Control::0 77666 -system.ruby.network.routers06.msg_count.Response_Data::2 75840 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2 736 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::2 2109 -system.ruby.network.routers06.msg_count.Response_Control::2 420 -system.ruby.network.routers06.msg_count.Writeback_Data::2 76630 -system.ruby.network.routers06.msg_count.Writeback_Control::0 155272 -system.ruby.network.routers06.msg_count.Forwarded_Control::0 1022 -system.ruby.network.routers06.msg_count.Invalidate_Control::0 3 -system.ruby.network.routers06.msg_count.Unblock_Control::2 78631 -system.ruby.network.routers06.msg_bytes.Request_Control::0 621328 -system.ruby.network.routers06.msg_bytes.Response_Data::2 5460480 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2 52992 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2 151848 -system.ruby.network.routers06.msg_bytes.Response_Control::2 3360 -system.ruby.network.routers06.msg_bytes.Writeback_Data::2 5517360 -system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1242176 -system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 8176 -system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 24 -system.ruby.network.routers06.msg_bytes.Unblock_Control::2 629048 -system.ruby.network.routers07.percent_links_utilized 5.706304 -system.ruby.network.routers07.msg_count.Request_Control::0 77528 -system.ruby.network.routers07.msg_count.Response_Data::2 75730 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2 728 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::2 2116 -system.ruby.network.routers07.msg_count.Response_Control::2 381 -system.ruby.network.routers07.msg_count.Writeback_Data::2 76441 -system.ruby.network.routers07.msg_count.Writeback_Control::0 155010 -system.ruby.network.routers07.msg_count.Forwarded_Control::0 1048 -system.ruby.network.routers07.msg_count.Invalidate_Control::0 1 -system.ruby.network.routers07.msg_count.Unblock_Control::2 78552 -system.ruby.network.routers07.msg_bytes.Request_Control::0 620224 -system.ruby.network.routers07.msg_bytes.Response_Data::2 5452560 -system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2 52416 -system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2 152352 -system.ruby.network.routers07.msg_bytes.Response_Control::2 3048 -system.ruby.network.routers07.msg_bytes.Writeback_Data::2 5503752 -system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1240080 -system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 8384 -system.ruby.network.routers07.msg_bytes.Invalidate_Control::0 8 -system.ruby.network.routers07.msg_bytes.Unblock_Control::2 628416 -system.ruby.network.routers08.percent_links_utilized 79.161635 -system.ruby.network.routers08.msg_count.Request_Control::0 619494 -system.ruby.network.routers08.msg_count.Request_Control::1 605151 -system.ruby.network.routers08.msg_count.Response_Data::2 1210253 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2 5922 -system.ruby.network.routers08.msg_count.Response_Control::2 2985 -system.ruby.network.routers08.msg_count.Writeback_Data::2 826501 -system.ruby.network.routers08.msg_count.Writeback_Control::0 1238596 -system.ruby.network.routers08.msg_count.Writeback_Control::1 1209317 -system.ruby.network.routers08.msg_count.Writeback_Control::2 389402 -system.ruby.network.routers08.msg_count.Forwarded_Control::0 8421 -system.ruby.network.routers08.msg_count.Invalidate_Control::0 19 -system.ruby.network.routers08.msg_count.Unblock_Control::2 1232268 -system.ruby.network.routers08.msg_bytes.Request_Control::0 4955952 -system.ruby.network.routers08.msg_bytes.Request_Control::1 4841208 -system.ruby.network.routers08.msg_bytes.Response_Data::2 87138216 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 426384 -system.ruby.network.routers08.msg_bytes.Response_Control::2 23880 -system.ruby.network.routers08.msg_bytes.Writeback_Data::2 59508072 -system.ruby.network.routers08.msg_bytes.Writeback_Control::0 9908768 -system.ruby.network.routers08.msg_bytes.Writeback_Control::1 9674536 -system.ruby.network.routers08.msg_bytes.Writeback_Control::2 3115216 -system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 67368 -system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 152 -system.ruby.network.routers08.msg_bytes.Unblock_Control::2 9858144 +system.ruby.network.routers05.msg_bytes.Unblock_Control::2 639544 +system.ruby.network.routers06.percent_links_utilized 5.706584 +system.ruby.network.routers06.msg_count.Request_Control::0 79210 +system.ruby.network.routers06.msg_count.Response_Data::2 77396 +system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2 741 +system.ruby.network.routers06.msg_count.ResponseLocal_Data::2 2181 +system.ruby.network.routers06.msg_count.Response_Control::2 373 +system.ruby.network.routers06.msg_count.Writeback_Data::2 78123 +system.ruby.network.routers06.msg_count.Writeback_Control::0 158387 +system.ruby.network.routers06.msg_count.Forwarded_Control::0 1111 +system.ruby.network.routers06.msg_count.Invalidate_Control::0 2 +system.ruby.network.routers06.msg_count.Unblock_Control::2 80226 +system.ruby.network.routers06.msg_bytes.Request_Control::0 633680 +system.ruby.network.routers06.msg_bytes.Response_Data::2 5572512 +system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2 53352 +system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2 157032 +system.ruby.network.routers06.msg_bytes.Response_Control::2 2984 +system.ruby.network.routers06.msg_bytes.Writeback_Data::2 5624856 +system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1267096 +system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 8888 +system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 16 +system.ruby.network.routers06.msg_bytes.Unblock_Control::2 641808 +system.ruby.network.routers07.percent_links_utilized 5.672683 +system.ruby.network.routers07.msg_count.Request_Control::0 78757 +system.ruby.network.routers07.msg_count.Response_Data::2 76940 +system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2 736 +system.ruby.network.routers07.msg_count.ResponseLocal_Data::2 2142 +system.ruby.network.routers07.msg_count.Response_Control::2 362 +system.ruby.network.routers07.msg_count.Writeback_Data::2 77687 +system.ruby.network.routers07.msg_count.Writeback_Control::0 157436 +system.ruby.network.routers07.msg_count.Forwarded_Control::0 1064 +system.ruby.network.routers07.msg_count.Unblock_Control::2 79746 +system.ruby.network.routers07.msg_bytes.Request_Control::0 630056 +system.ruby.network.routers07.msg_bytes.Response_Data::2 5539680 +system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2 52992 +system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2 154224 +system.ruby.network.routers07.msg_bytes.Response_Control::2 2896 +system.ruby.network.routers07.msg_bytes.Writeback_Data::2 5593464 +system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1259488 +system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 8512 +system.ruby.network.routers07.msg_bytes.Unblock_Control::2 637968 +system.ruby.network.routers08.percent_links_utilized 79.115289 +system.ruby.network.routers08.msg_count.Request_Control::0 631981 +system.ruby.network.routers08.msg_count.Request_Control::1 617280 +system.ruby.network.routers08.msg_count.Response_Data::2 1234524 +system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2 6149 +system.ruby.network.routers08.msg_count.Response_Control::2 3038 +system.ruby.network.routers08.msg_count.Writeback_Data::2 846848 +system.ruby.network.routers08.msg_count.Writeback_Control::0 1263518 +system.ruby.network.routers08.msg_count.Writeback_Control::1 1233658 +system.ruby.network.routers08.msg_count.Writeback_Control::2 393565 +system.ruby.network.routers08.msg_count.Forwarded_Control::0 8552 +system.ruby.network.routers08.msg_count.Invalidate_Control::0 11 +system.ruby.network.routers08.msg_count.Unblock_Control::2 1257012 +system.ruby.network.routers08.msg_bytes.Request_Control::0 5055848 +system.ruby.network.routers08.msg_bytes.Request_Control::1 4938240 +system.ruby.network.routers08.msg_bytes.Response_Data::2 88885728 +system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 442728 +system.ruby.network.routers08.msg_bytes.Response_Control::2 24304 +system.ruby.network.routers08.msg_bytes.Writeback_Data::2 60973056 +system.ruby.network.routers08.msg_bytes.Writeback_Control::0 10108144 +system.ruby.network.routers08.msg_bytes.Writeback_Control::1 9869264 +system.ruby.network.routers08.msg_bytes.Writeback_Control::2 3148520 +system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 68416 +system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 88 +system.ruby.network.routers08.msg_bytes.Unblock_Control::2 10056096 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 820394 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 605143 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 215243 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 51955 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 11786270 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 6968030 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 3665383 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 22419683 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 27.327946 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 2079686 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 3902603 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 208436 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1319186 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 2932982 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memNotOld 1343377 # memory stalls due to anti starvation -system.ruby.dir_cntrl0.memBuffer.memBankCount | 25992 3.17% 3.17% | 25482 3.11% 6.27% | 25735 3.14% 9.41% | 25728 3.14% 12.55% | 25931 3.16% 15.71% | 25829 3.15% 18.86% | 25430 3.10% 21.96% | 25686 3.13% 25.09% | 25772 3.14% 28.23% | 25394 3.10% 31.32% | 25765 3.14% 34.46% | 25528 3.11% 37.58% | 25775 3.14% 40.72% | 25820 3.15% 43.87% | 25548 3.11% 46.98% | 25750 3.14% 50.12% | 25378 3.09% 53.21% | 25625 3.12% 56.33% | 25783 3.14% 59.48% | 25254 3.08% 62.56% | 25786 3.14% 65.70% | 25466 3.10% 68.80% | 25638 3.13% 71.93% | 25430 3.10% 75.03% | 25799 3.14% 78.17% | 25685 3.13% 81.30% | 25362 3.09% 84.39% | 25641 3.13% 87.52% | 25676 3.13% 90.65% | 25658 3.13% 93.78% | 25720 3.14% 96.91% | 25328 3.09% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 820394 # Number of accesses per bank -system.ruby.network.routers09.percent_links_utilized 34.059110 -system.ruby.network.routers09.msg_count.Request_Control::1 605151 -system.ruby.network.routers09.msg_count.Response_Data::2 605138 -system.ruby.network.routers09.msg_count.Writeback_Data::2 215243 -system.ruby.network.routers09.msg_count.Writeback_Control::1 1209343 -system.ruby.network.routers09.msg_count.Writeback_Control::2 389402 -system.ruby.network.routers09.msg_count.Unblock_Control::2 605124 -system.ruby.network.routers09.msg_bytes.Request_Control::1 4841208 -system.ruby.network.routers09.msg_bytes.Response_Data::2 43569936 -system.ruby.network.routers09.msg_bytes.Writeback_Data::2 15497496 -system.ruby.network.routers09.msg_bytes.Writeback_Control::1 9674744 -system.ruby.network.routers09.msg_bytes.Writeback_Control::2 3115216 -system.ruby.network.routers09.msg_bytes.Unblock_Control::2 4840992 -system.ruby.network.routers10.percent_links_utilized 15.882986 -system.ruby.network.routers10.msg_count.Request_Control::0 619494 -system.ruby.network.routers10.msg_count.Request_Control::1 605151 -system.ruby.network.routers10.msg_count.Response_Data::2 1210252 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2 5922 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::2 8420 -system.ruby.network.routers10.msg_count.Response_Control::2 3004 -system.ruby.network.routers10.msg_count.Writeback_Data::2 826501 -system.ruby.network.routers10.msg_count.Writeback_Control::0 1238596 -system.ruby.network.routers10.msg_count.Writeback_Control::1 1209317 -system.ruby.network.routers10.msg_count.Writeback_Control::2 389402 -system.ruby.network.routers10.msg_count.Forwarded_Control::0 8421 -system.ruby.network.routers10.msg_count.Invalidate_Control::0 19 -system.ruby.network.routers10.msg_count.Unblock_Control::2 1232268 -system.ruby.network.routers10.msg_bytes.Request_Control::0 4955952 -system.ruby.network.routers10.msg_bytes.Request_Control::1 4841208 -system.ruby.network.routers10.msg_bytes.Response_Data::2 87138144 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2 426384 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2 606240 -system.ruby.network.routers10.msg_bytes.Response_Control::2 24032 -system.ruby.network.routers10.msg_bytes.Writeback_Data::2 59508072 -system.ruby.network.routers10.msg_bytes.Writeback_Control::0 9908768 -system.ruby.network.routers10.msg_bytes.Writeback_Control::1 9674536 -system.ruby.network.routers10.msg_bytes.Writeback_Control::2 3115216 -system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 67368 -system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 152 -system.ruby.network.routers10.msg_bytes.Unblock_Control::2 9858144 -system.ruby.network.msg_count.Request_Control 3673936 -system.ruby.network.msg_count.Response_Data 3630768 -system.ruby.network.msg_count.ResponseL2hit_Data 17766 -system.ruby.network.msg_count.ResponseLocal_Data 25260 -system.ruby.network.msg_count.Response_Control 9012 -system.ruby.network.msg_count.Writeback_Data 2479504 -system.ruby.network.msg_count.Writeback_Control 8511972 -system.ruby.network.msg_count.Forwarded_Control 25263 -system.ruby.network.msg_count.Invalidate_Control 57 -system.ruby.network.msg_count.Unblock_Control 3696804 -system.ruby.network.msg_byte.Request_Control 29391488 -system.ruby.network.msg_byte.Response_Data 261415296 -system.ruby.network.msg_byte.ResponseL2hit_Data 1279152 -system.ruby.network.msg_byte.ResponseLocal_Data 1818720 -system.ruby.network.msg_byte.Response_Control 72096 -system.ruby.network.msg_byte.Writeback_Data 178524288 -system.ruby.network.msg_byte.Writeback_Control 68095776 -system.ruby.network.msg_byte.Forwarded_Control 202104 -system.ruby.network.msg_byte.Invalidate_Control 456 -system.ruby.network.msg_byte.Unblock_Control 29574432 +system.ruby.dir_cntrl0.memBuffer.memReq 840532 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 617276 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 223251 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 53097 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 12084618 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 7109815 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 3756357 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 22950790 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 27.305076 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 2125863 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 3998707 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 215811 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1338863 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 3014396 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memNotOld 1390978 # memory stalls due to anti starvation +system.ruby.dir_cntrl0.memBuffer.memBankCount | 26168 3.11% 3.11% | 26574 3.16% 6.27% | 26455 3.15% 9.42% | 26511 3.15% 12.58% | 26226 3.12% 15.70% | 26782 3.19% 18.88% | 26319 3.13% 22.01% | 26430 3.14% 25.16% | 26348 3.13% 28.29% | 26005 3.09% 31.39% | 26264 3.12% 34.51% | 26345 3.13% 37.65% | 26533 3.16% 40.80% | 26231 3.12% 43.92% | 26065 3.10% 47.02% | 26208 3.12% 50.14% | 26194 3.12% 53.26% | 26013 3.09% 56.35% | 26137 3.11% 59.46% | 26424 3.14% 62.61% | 25919 3.08% 65.69% | 26330 3.13% 68.82% | 26181 3.11% 71.94% | 26372 3.14% 75.08% | 26420 3.14% 78.22% | 26347 3.13% 81.35% | 26285 3.13% 84.48% | 25978 3.09% 87.57% | 26022 3.10% 90.67% | 25911 3.08% 93.75% | 26364 3.14% 96.89% | 26171 3.11% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 840532 # Number of accesses per bank +system.ruby.network.routers09.percent_links_utilized 34.091732 +system.ruby.network.routers09.msg_count.Request_Control::1 617280 +system.ruby.network.routers09.msg_count.Response_Data::2 617270 +system.ruby.network.routers09.msg_count.Writeback_Data::2 223252 +system.ruby.network.routers09.msg_count.Writeback_Control::1 1233682 +system.ruby.network.routers09.msg_count.Writeback_Control::2 393565 +system.ruby.network.routers09.msg_count.Unblock_Control::2 617253 +system.ruby.network.routers09.msg_bytes.Request_Control::1 4938240 +system.ruby.network.routers09.msg_bytes.Response_Data::2 44443440 +system.ruby.network.routers09.msg_bytes.Writeback_Data::2 16074144 +system.ruby.network.routers09.msg_bytes.Writeback_Control::1 9869456 +system.ruby.network.routers09.msg_bytes.Writeback_Control::2 3148520 +system.ruby.network.routers09.msg_bytes.Unblock_Control::2 4938024 +system.ruby.network.routers10.percent_links_utilized 15.873398 +system.ruby.network.routers10.msg_count.Request_Control::0 631981 +system.ruby.network.routers10.msg_count.Request_Control::1 617280 +system.ruby.network.routers10.msg_count.Response_Data::2 1234523 +system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2 6149 +system.ruby.network.routers10.msg_count.ResponseLocal_Data::2 8552 +system.ruby.network.routers10.msg_count.Response_Control::2 3049 +system.ruby.network.routers10.msg_count.Writeback_Data::2 846848 +system.ruby.network.routers10.msg_count.Writeback_Control::0 1263518 +system.ruby.network.routers10.msg_count.Writeback_Control::1 1233658 +system.ruby.network.routers10.msg_count.Writeback_Control::2 393565 +system.ruby.network.routers10.msg_count.Forwarded_Control::0 8552 +system.ruby.network.routers10.msg_count.Invalidate_Control::0 11 +system.ruby.network.routers10.msg_count.Unblock_Control::2 1257012 +system.ruby.network.routers10.msg_bytes.Request_Control::0 5055848 +system.ruby.network.routers10.msg_bytes.Request_Control::1 4938240 +system.ruby.network.routers10.msg_bytes.Response_Data::2 88885656 +system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2 442728 +system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2 615744 +system.ruby.network.routers10.msg_bytes.Response_Control::2 24392 +system.ruby.network.routers10.msg_bytes.Writeback_Data::2 60973056 +system.ruby.network.routers10.msg_bytes.Writeback_Control::0 10108144 +system.ruby.network.routers10.msg_bytes.Writeback_Control::1 9869264 +system.ruby.network.routers10.msg_bytes.Writeback_Control::2 3148520 +system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 68416 +system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 88 +system.ruby.network.routers10.msg_bytes.Unblock_Control::2 10056096 +system.ruby.network.msg_count.Request_Control 3747784 +system.ruby.network.msg_count.Response_Data 3703577 +system.ruby.network.msg_count.ResponseL2hit_Data 18447 +system.ruby.network.msg_count.ResponseLocal_Data 25656 +system.ruby.network.msg_count.Response_Control 9147 +system.ruby.network.msg_count.Writeback_Data 2540544 +system.ruby.network.msg_count.Writeback_Control 8672248 +system.ruby.network.msg_count.Forwarded_Control 25656 +system.ruby.network.msg_count.Invalidate_Control 33 +system.ruby.network.msg_count.Unblock_Control 3771042 +system.ruby.network.msg_byte.Request_Control 29982272 +system.ruby.network.msg_byte.Response_Data 266657544 +system.ruby.network.msg_byte.ResponseL2hit_Data 1328184 +system.ruby.network.msg_byte.ResponseLocal_Data 1847232 +system.ruby.network.msg_byte.Response_Control 73176 +system.ruby.network.msg_byte.Writeback_Data 182919168 +system.ruby.network.msg_byte.Writeback_Control 69377984 +system.ruby.network.msg_byte.Forwarded_Control 205248 +system.ruby.network.msg_byte.Invalidate_Control 264 +system.ruby.network.msg_byte.Unblock_Control 30168336 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 99553 # number of read accesses completed -system.cpu0.num_writes 54274 # number of write accesses completed +system.cpu0.num_reads 99316 # number of read accesses completed +system.cpu0.num_writes 55500 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99453 # number of read accesses completed -system.cpu1.num_writes 54478 # number of write accesses completed +system.cpu1.num_reads 99690 # number of read accesses completed +system.cpu1.num_writes 55732 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98747 # number of read accesses completed -system.cpu2.num_writes 53976 # number of write accesses completed +system.cpu2.num_reads 99856 # number of read accesses completed +system.cpu2.num_writes 55785 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99232 # number of read accesses completed -system.cpu3.num_writes 54121 # number of write accesses completed +system.cpu3.num_reads 99241 # number of read accesses completed +system.cpu3.num_writes 55367 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99563 # number of read accesses completed -system.cpu4.num_writes 53960 # number of write accesses completed +system.cpu4.num_reads 99899 # number of read accesses completed +system.cpu4.num_writes 55499 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99501 # number of read accesses completed -system.cpu5.num_writes 54015 # number of write accesses completed +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 55860 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 54332 # number of write accesses completed +system.cpu6.num_reads 99699 # number of read accesses completed +system.cpu6.num_writes 55767 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99277 # number of read accesses completed -system.cpu7.num_writes 53851 # number of write accesses completed +system.cpu7.num_reads 99546 # number of read accesses completed +system.cpu7.num_writes 55623 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers00.throttle0.link_utilization 5.173589 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 75499 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 705 -system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::2 1064 -system.ruby.network.routers00.throttle0.msg_count.Response_Control::2 376 -system.ruby.network.routers00.throttle0.msg_count.Writeback_Control::0 77242 -system.ruby.network.routers00.throttle0.msg_count.Forwarded_Control::0 1082 -system.ruby.network.routers00.throttle0.msg_count.Invalidate_Control::0 6 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::2 5435928 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::2 50760 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::2 76608 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::2 3008 -system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Control::0 617936 -system.ruby.network.routers00.throttle0.msg_bytes.Forwarded_Control::0 8656 -system.ruby.network.routers00.throttle0.msg_bytes.Invalidate_Control::0 48 -system.ruby.network.routers00.throttle1.link_utilization 6.204934 -system.ruby.network.routers00.throttle1.msg_count.Request_Control::0 77272 -system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::2 1082 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::2 6 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::2 76215 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Control::0 77243 -system.ruby.network.routers00.throttle1.msg_count.Unblock_Control::2 78243 -system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::0 618176 -system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::2 77904 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::2 48 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::2 5487480 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Control::0 617944 -system.ruby.network.routers00.throttle1.msg_bytes.Unblock_Control::2 625944 -system.ruby.network.routers01.throttle0.link_utilization 5.200796 -system.ruby.network.routers01.throttle0.msg_count.Response_Data::2 75857 -system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::2 752 -system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::2 1067 -system.ruby.network.routers01.throttle0.msg_count.Response_Control::2 376 -system.ruby.network.routers01.throttle0.msg_count.Writeback_Control::0 77657 -system.ruby.network.routers01.throttle0.msg_count.Forwarded_Control::0 1069 -system.ruby.network.routers01.throttle0.msg_count.Invalidate_Control::0 3 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::2 5461704 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::2 54144 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::2 76824 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::2 3008 -system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Control::0 621256 -system.ruby.network.routers01.throttle0.msg_bytes.Forwarded_Control::0 8552 -system.ruby.network.routers01.throttle0.msg_bytes.Invalidate_Control::0 24 -system.ruby.network.routers01.throttle1.link_utilization 6.239600 -system.ruby.network.routers01.throttle1.msg_count.Request_Control::0 77679 -system.ruby.network.routers01.throttle1.msg_count.ResponseLocal_Data::2 1069 -system.ruby.network.routers01.throttle1.msg_count.Response_Control::2 3 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::2 76673 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Control::0 77657 -system.ruby.network.routers01.throttle1.msg_count.Unblock_Control::2 78607 -system.ruby.network.routers01.throttle1.msg_bytes.Request_Control::0 621432 -system.ruby.network.routers01.throttle1.msg_bytes.ResponseLocal_Data::2 76968 -system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::2 24 -system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::2 5520456 -system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Control::0 621256 -system.ruby.network.routers01.throttle1.msg_bytes.Unblock_Control::2 628856 -system.ruby.network.routers02.throttle0.link_utilization 5.160710 -system.ruby.network.routers02.throttle0.msg_count.Response_Data::2 75271 -system.ruby.network.routers02.throttle0.msg_count.ResponseL2hit_Data::2 752 -system.ruby.network.routers02.throttle0.msg_count.ResponseLocal_Data::2 1055 -system.ruby.network.routers02.throttle0.msg_count.Response_Control::2 382 -system.ruby.network.routers02.throttle0.msg_count.Writeback_Control::0 77062 -system.ruby.network.routers02.throttle0.msg_count.Forwarded_Control::0 1045 -system.ruby.network.routers02.throttle0.msg_bytes.Response_Data::2 5419512 -system.ruby.network.routers02.throttle0.msg_bytes.ResponseL2hit_Data::2 54144 -system.ruby.network.routers02.throttle0.msg_bytes.ResponseLocal_Data::2 75960 -system.ruby.network.routers02.throttle0.msg_bytes.Response_Control::2 3056 -system.ruby.network.routers02.throttle0.msg_bytes.Writeback_Control::0 616496 -system.ruby.network.routers02.throttle0.msg_bytes.Forwarded_Control::0 8360 -system.ruby.network.routers02.throttle1.link_utilization 6.191748 -system.ruby.network.routers02.throttle1.msg_count.Request_Control::0 77082 -system.ruby.network.routers02.throttle1.msg_count.ResponseLocal_Data::2 1045 -system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::2 76103 -system.ruby.network.routers02.throttle1.msg_count.Writeback_Control::0 77062 -system.ruby.network.routers02.throttle1.msg_count.Unblock_Control::2 77988 -system.ruby.network.routers02.throttle1.msg_bytes.Request_Control::0 616656 -system.ruby.network.routers02.throttle1.msg_bytes.ResponseLocal_Data::2 75240 -system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::2 5479416 -system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Control::0 616496 -system.ruby.network.routers02.throttle1.msg_bytes.Unblock_Control::2 623904 -system.ruby.network.routers03.throttle0.link_utilization 5.177331 -system.ruby.network.routers03.throttle0.msg_count.Response_Data::2 75554 -system.ruby.network.routers03.throttle0.msg_count.ResponseL2hit_Data::2 792 -system.ruby.network.routers03.throttle0.msg_count.ResponseLocal_Data::2 978 -system.ruby.network.routers03.throttle0.msg_count.Response_Control::2 351 -system.ruby.network.routers03.throttle0.msg_count.Writeback_Control::0 77309 -system.ruby.network.routers03.throttle0.msg_count.Forwarded_Control::0 1099 -system.ruby.network.routers03.throttle0.msg_count.Invalidate_Control::0 3 -system.ruby.network.routers03.throttle0.msg_bytes.Response_Data::2 5439888 -system.ruby.network.routers03.throttle0.msg_bytes.ResponseL2hit_Data::2 57024 -system.ruby.network.routers03.throttle0.msg_bytes.ResponseLocal_Data::2 70416 -system.ruby.network.routers03.throttle0.msg_bytes.Response_Control::2 2808 -system.ruby.network.routers03.throttle0.msg_bytes.Writeback_Control::0 618472 -system.ruby.network.routers03.throttle0.msg_bytes.Forwarded_Control::0 8792 -system.ruby.network.routers03.throttle0.msg_bytes.Invalidate_Control::0 24 -system.ruby.network.routers03.throttle1.link_utilization 6.212820 -system.ruby.network.routers03.throttle1.msg_count.Request_Control::0 77329 -system.ruby.network.routers03.throttle1.msg_count.ResponseLocal_Data::2 1098 -system.ruby.network.routers03.throttle1.msg_count.Response_Control::2 3 -system.ruby.network.routers03.throttle1.msg_count.Writeback_Data::2 76314 -system.ruby.network.routers03.throttle1.msg_count.Writeback_Control::0 77309 -system.ruby.network.routers03.throttle1.msg_count.Unblock_Control::2 78268 -system.ruby.network.routers03.throttle1.msg_bytes.Request_Control::0 618632 -system.ruby.network.routers03.throttle1.msg_bytes.ResponseLocal_Data::2 79056 -system.ruby.network.routers03.throttle1.msg_bytes.Response_Control::2 24 -system.ruby.network.routers03.throttle1.msg_bytes.Writeback_Data::2 5494608 -system.ruby.network.routers03.throttle1.msg_bytes.Writeback_Control::0 618472 -system.ruby.network.routers03.throttle1.msg_bytes.Unblock_Control::2 626144 -system.ruby.network.routers04.throttle0.link_utilization 5.183567 -system.ruby.network.routers04.throttle0.msg_count.Response_Data::2 75631 -system.ruby.network.routers04.throttle0.msg_count.ResponseL2hit_Data::2 720 -system.ruby.network.routers04.throttle0.msg_count.ResponseLocal_Data::2 1073 -system.ruby.network.routers04.throttle0.msg_count.Response_Control::2 372 -system.ruby.network.routers04.throttle0.msg_count.Writeback_Control::0 77393 -system.ruby.network.routers04.throttle0.msg_count.Forwarded_Control::0 1028 -system.ruby.network.routers04.throttle0.msg_count.Invalidate_Control::0 2 -system.ruby.network.routers04.throttle0.msg_bytes.Response_Data::2 5445432 -system.ruby.network.routers04.throttle0.msg_bytes.ResponseL2hit_Data::2 51840 -system.ruby.network.routers04.throttle0.msg_bytes.ResponseLocal_Data::2 77256 -system.ruby.network.routers04.throttle0.msg_bytes.Response_Control::2 2976 -system.ruby.network.routers04.throttle0.msg_bytes.Writeback_Control::0 619144 -system.ruby.network.routers04.throttle0.msg_bytes.Forwarded_Control::0 8224 -system.ruby.network.routers04.throttle0.msg_bytes.Invalidate_Control::0 16 -system.ruby.network.routers04.throttle1.link_utilization 6.215053 -system.ruby.network.routers04.throttle1.msg_count.Request_Control::0 77428 -system.ruby.network.routers04.throttle1.msg_count.ResponseLocal_Data::2 1028 -system.ruby.network.routers04.throttle1.msg_count.Response_Control::2 2 -system.ruby.network.routers04.throttle1.msg_count.Writeback_Data::2 76387 -system.ruby.network.routers04.throttle1.msg_count.Writeback_Control::0 77393 -system.ruby.network.routers04.throttle1.msg_count.Unblock_Control::2 78393 -system.ruby.network.routers04.throttle1.msg_bytes.Request_Control::0 619424 -system.ruby.network.routers04.throttle1.msg_bytes.ResponseLocal_Data::2 74016 -system.ruby.network.routers04.throttle1.msg_bytes.Response_Control::2 16 -system.ruby.network.routers04.throttle1.msg_bytes.Writeback_Data::2 5499864 -system.ruby.network.routers04.throttle1.msg_bytes.Writeback_Control::0 619144 -system.ruby.network.routers04.throttle1.msg_bytes.Unblock_Control::2 627144 -system.ruby.network.routers05.throttle0.link_utilization 5.189141 -system.ruby.network.routers05.throttle0.msg_count.Response_Data::2 75743 -system.ruby.network.routers05.throttle0.msg_count.ResponseL2hit_Data::2 737 -system.ruby.network.routers05.throttle0.msg_count.ResponseLocal_Data::2 1028 -system.ruby.network.routers05.throttle0.msg_count.Response_Control::2 350 -system.ruby.network.routers05.throttle0.msg_count.Writeback_Control::0 77494 -system.ruby.network.routers05.throttle0.msg_count.Forwarded_Control::0 1028 +system.ruby.network.routers00.throttle0.link_utilization 5.180524 +system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 77245 +system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 780 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16074144 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::1 4934728 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::2 3148520 +system.ruby.network.routers10.throttle9.msg_bytes.Unblock_Control::2 4938024 system.ruby.LD.latency_hist::bucket_size 2048 system.ruby.LD.latency_hist::max_bucket 20479 -system.ruby.LD.latency_hist::samples 402593 -system.ruby.LD.latency_hist::mean 1545.043245 -system.ruby.LD.latency_hist::gmean 1028.893138 -system.ruby.LD.latency_hist::stdev 1540.768510 -system.ruby.LD.latency_hist | 303266 75.33% 75.33% | 69452 17.25% 92.58% | 21307 5.29% 97.87% | 6321 1.57% 99.44% | 1780 0.44% 99.88% | 373 0.09% 99.98% | 85 0.02% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 402593 +system.ruby.LD.latency_hist::samples 406981 +system.ruby.LD.latency_hist::mean 1548.085817 +system.ruby.LD.latency_hist::gmean 1028.850116 +system.ruby.LD.latency_hist::stdev 1547.317259 +system.ruby.LD.latency_hist | 306593 75.33% 75.33% | 69760 17.14% 92.47% | 21891 5.38% 97.85% | 6472 1.59% 99.44% | 1757 0.43% 99.88% | 406 0.10% 99.97% | 83 0.02% 100.00% | 18 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 406981 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 125 +system.ruby.LD.hit_latency_hist::samples 113 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 125 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 113 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 113 system.ruby.LD.miss_latency_hist::bucket_size 2048 system.ruby.LD.miss_latency_hist::max_bucket 20479 -system.ruby.LD.miss_latency_hist::samples 402468 -system.ruby.LD.miss_latency_hist::mean 1545.522178 -system.ruby.LD.miss_latency_hist::gmean 1030.760288 -system.ruby.LD.miss_latency_hist::stdev 1540.768039 -system.ruby.LD.miss_latency_hist | 303141 75.32% 75.32% | 69452 17.26% 92.58% | 21307 5.29% 97.87% | 6321 1.57% 99.44% | 1780 0.44% 99.88% | 373 0.09% 99.98% | 85 0.02% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 402468 +system.ruby.LD.miss_latency_hist::samples 406868 +system.ruby.LD.miss_latency_hist::mean 1548.514936 +system.ruby.LD.miss_latency_hist::gmean 1030.519523 +system.ruby.LD.miss_latency_hist::stdev 1547.317818 +system.ruby.LD.miss_latency_hist | 306480 75.33% 75.33% | 69760 17.15% 92.47% | 21891 5.38% 97.85% | 6472 1.59% 99.44% | 1757 0.43% 99.88% | 406 0.10% 99.97% | 83 0.02% 100.00% | 18 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 406868 system.ruby.ST.latency_hist::bucket_size 2048 system.ruby.ST.latency_hist::max_bucket 20479 -system.ruby.ST.latency_hist::samples 217067 -system.ruby.ST.latency_hist::mean 1544.956027 -system.ruby.ST.latency_hist::gmean 1029.811241 -system.ruby.ST.latency_hist::stdev 1539.607599 -system.ruby.ST.latency_hist | 163681 75.41% 75.41% | 37227 17.15% 92.56% | 11599 5.34% 97.90% | 3358 1.55% 99.45% | 949 0.44% 99.88% | 204 0.09% 99.98% | 44 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 217067 +system.ruby.ST.latency_hist::samples 225146 +system.ruby.ST.latency_hist::mean 1547.516998 +system.ruby.ST.latency_hist::gmean 1031.853555 +system.ruby.ST.latency_hist::stdev 1543.988015 +system.ruby.ST.latency_hist | 169789 75.41% 75.41% | 38573 17.13% 92.55% | 11917 5.29% 97.84% | 3626 1.61% 99.45% | 964 0.43% 99.88% | 219 0.10% 99.97% | 41 0.02% 99.99% | 15 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 225146 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 67 +system.ruby.ST.hit_latency_hist::samples 53 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 67 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 67 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 53 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 53 system.ruby.ST.miss_latency_hist::bucket_size 2048 system.ruby.ST.miss_latency_hist::max_bucket 20479 -system.ruby.ST.miss_latency_hist::samples 217000 -system.ruby.ST.miss_latency_hist::mean 1545.432115 -system.ruby.ST.miss_latency_hist::gmean 1031.669331 -system.ruby.ST.miss_latency_hist::stdev 1539.606800 -system.ruby.ST.miss_latency_hist | 163614 75.40% 75.40% | 37227 17.16% 92.55% | 11599 5.35% 97.90% | 3358 1.55% 99.45% | 949 0.44% 99.88% | 204 0.09% 99.98% | 44 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 217000 -system.ruby.L1Cache_Controller.Load | 50249 12.48% 12.48% | 50370 12.51% 24.99% | 49923 12.40% 37.38% | 50235 12.47% 49.86% | 50375 12.51% 62.37% | 50577 12.56% 74.93% | 50611 12.57% 87.49% | 50361 12.51% 100.00% -system.ruby.L1Cache_Controller.Load::total 402701 -system.ruby.L1Cache_Controller.Store | 27052 12.46% 12.46% | 27339 12.59% 25.05% | 27175 12.52% 37.57% | 27153 12.51% 50.08% | 27079 12.47% 62.55% | 26983 12.43% 74.98% | 27113 12.49% 87.47% | 27205 12.53% 100.00% -system.ruby.L1Cache_Controller.Store::total 217099 -system.ruby.L1Cache_Controller.L1_Replacement | 9611009 12.51% 12.51% | 9602265 12.49% 25.00% | 9618315 12.51% 37.51% | 9608777 12.50% 50.02% | 9608029 12.50% 62.52% | 9605100 12.50% 75.02% | 9598595 12.49% 87.50% | 9603783 12.50% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 76855873 -system.ruby.L1Cache_Controller.Own_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Own_GETX::total 1 -system.ruby.L1Cache_Controller.Fwd_GETX | 395 12.44% 12.44% | 352 11.09% 23.53% | 364 11.47% 35.00% | 433 13.64% 48.65% | 393 12.38% 61.03% | 374 11.78% 72.81% | 406 12.79% 85.60% | 457 14.40% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 3174 -system.ruby.L1Cache_Controller.Fwd_GETS | 764 13.27% 13.27% | 770 13.37% 26.64% | 739 12.83% 39.48% | 739 12.83% 52.31% | 692 12.02% 64.33% | 715 12.42% 76.75% | 690 11.98% 88.73% | 649 11.27% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 5758 -system.ruby.L1Cache_Controller.Inv | 6 31.58% 31.58% | 3 15.79% 47.37% | 0 0.00% 47.37% | 3 15.79% 63.16% | 2 10.53% 73.68% | 1 5.26% 78.95% | 3 15.79% 94.74% | 1 5.26% 100.00% -system.ruby.L1Cache_Controller.Inv::total 19 -system.ruby.L1Cache_Controller.Ack | 376 12.52% 12.52% | 376 12.52% 25.03% | 382 12.72% 37.75% | 351 11.68% 49.43% | 372 12.38% 61.82% | 350 11.65% 73.47% | 417 13.88% 87.35% | 380 12.65% 100.00% -system.ruby.L1Cache_Controller.Ack::total 3004 -system.ruby.L1Cache_Controller.Data | 720 12.65% 12.65% | 712 12.51% 25.17% | 716 12.58% 37.75% | 661 11.62% 49.37% | 738 12.97% 62.34% | 721 12.67% 75.01% | 703 12.36% 87.36% | 719 12.64% 100.00% -system.ruby.L1Cache_Controller.Data::total 5690 -system.ruby.L1Cache_Controller.Exclusive_Data | 76548 12.47% 12.47% | 76964 12.54% 25.01% | 76362 12.44% 37.45% | 76663 12.49% 49.94% | 76686 12.49% 62.44% | 76787 12.51% 74.95% | 76960 12.54% 87.49% | 76807 12.51% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 613777 -system.ruby.L1Cache_Controller.Writeback_Ack | 637 12.77% 12.77% | 632 12.67% 25.44% | 612 12.27% 37.70% | 579 11.61% 49.31% | 639 12.81% 62.12% | 632 12.67% 74.78% | 619 12.41% 87.19% | 639 12.81% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 4989 -system.ruby.L1Cache_Controller.Writeback_Ack_Data | 76553 12.47% 12.47% | 76972 12.54% 25.01% | 76401 12.44% 37.45% | 76678 12.49% 49.94% | 76717 12.50% 62.44% | 76818 12.51% 74.95% | 76980 12.54% 87.49% | 76828 12.51% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 613947 -system.ruby.L1Cache_Controller.Writeback_Nack | 52 14.36% 14.36% | 53 14.64% 29.01% | 49 13.54% 42.54% | 52 14.36% 56.91% | 37 10.22% 67.13% | 44 12.15% 79.28% | 37 10.22% 89.50% | 38 10.50% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 362 -system.ruby.L1Cache_Controller.All_acks | 27041 12.46% 12.46% | 27326 12.59% 25.05% | 27165 12.52% 37.57% | 27136 12.51% 50.08% | 27069 12.47% 62.55% | 26960 12.42% 74.98% | 27107 12.49% 87.47% | 27196 12.53% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 217000 -system.ruby.L1Cache_Controller.Use_Timeout | 76548 12.47% 12.47% | 76964 12.54% 25.01% | 76362 12.44% 37.45% | 76664 12.49% 49.94% | 76686 12.49% 62.44% | 76787 12.51% 74.95% | 76959 12.54% 87.49% | 76807 12.51% 100.00% -system.ruby.L1Cache_Controller.Use_Timeout::total 613777 -system.ruby.L1Cache_Controller.I.Load | 50230 12.48% 12.48% | 50351 12.51% 24.99% | 49916 12.40% 37.39% | 50192 12.47% 49.86% | 50358 12.51% 62.37% | 50550 12.56% 74.93% | 50559 12.56% 87.49% | 50332 12.51% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 402488 -system.ruby.L1Cache_Controller.I.Store | 27042 12.46% 12.46% | 27328 12.59% 25.05% | 27166 12.52% 37.57% | 27136 12.50% 50.08% | 27070 12.47% 62.55% | 26961 12.42% 74.98% | 27107 12.49% 87.47% | 27196 12.53% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 217006 -system.ruby.L1Cache_Controller.I.L1_Replacement | 70 13.78% 13.78% | 67 13.19% 26.97% | 65 12.80% 39.76% | 64 12.60% 52.36% | 67 13.19% 65.55% | 57 11.22% 76.77% | 62 12.20% 88.98% | 56 11.02% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 508 -system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1 -system.ruby.L1Cache_Controller.S.L1_Replacement | 719 12.65% 12.65% | 712 12.53% 25.18% | 716 12.60% 37.78% | 660 11.61% 49.39% | 736 12.95% 62.34% | 720 12.67% 75.01% | 701 12.34% 87.35% | 719 12.65% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 5683 -system.ruby.L1Cache_Controller.S.Inv | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 7 -system.ruby.L1Cache_Controller.O.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Store::total 1 -system.ruby.L1Cache_Controller.O.L1_Replacement | 50 14.75% 14.75% | 43 12.68% 27.43% | 42 12.39% 39.82% | 40 11.80% 51.62% | 37 10.91% 62.54% | 50 14.75% 77.29% | 34 10.03% 87.32% | 43 12.68% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 339 -system.ruby.L1Cache_Controller.O.Fwd_GETS | 0 0.00% 0.00% | 2 33.33% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.O.Fwd_GETS::total 6 -system.ruby.L1Cache_Controller.M.Load | 2 8.70% 8.70% | 3 13.04% 21.74% | 2 8.70% 30.43% | 5 21.74% 52.17% | 2 8.70% 60.87% | 5 21.74% 82.61% | 2 8.70% 91.30% | 2 8.70% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 23 -system.ruby.L1Cache_Controller.M.Store | 3 20.00% 20.00% | 0 0.00% 20.00% | 2 13.33% 33.33% | 2 13.33% 46.67% | 3 20.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 5 33.33% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 15 -system.ruby.L1Cache_Controller.M.L1_Replacement | 49426 12.48% 12.48% | 49555 12.51% 24.98% | 49122 12.40% 37.38% | 49457 12.48% 49.87% | 49545 12.51% 62.37% | 49751 12.56% 74.93% | 49794 12.57% 87.50% | 49535 12.50% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 396185 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 24 11.88% 11.88% | 29 14.36% 26.24% | 29 14.36% 40.59% | 27 13.37% 53.96% | 27 13.37% 67.33% | 19 9.41% 76.73% | 22 10.89% 87.62% | 25 12.38% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 202 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 50 14.71% 14.71% | 43 12.65% 27.35% | 42 12.35% 39.71% | 41 12.06% 51.76% | 37 10.88% 62.65% | 50 14.71% 77.35% | 34 10.00% 87.35% | 43 12.65% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 340 -system.ruby.L1Cache_Controller.M_W.Load | 9 15.79% 15.79% | 8 14.04% 29.82% | 3 5.26% 35.09% | 9 15.79% 50.88% | 7 12.28% 63.16% | 7 12.28% 75.44% | 6 10.53% 85.96% | 8 14.04% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 57 -system.ruby.L1Cache_Controller.M_W.Store | 4 12.12% 12.12% | 10 30.30% 42.42% | 2 6.06% 48.48% | 1 3.03% 51.52% | 5 15.15% 66.67% | 7 21.21% 87.88% | 2 6.06% 93.94% | 2 6.06% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 33 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 888542 12.47% 12.47% | 887409 12.46% 24.93% | 886648 12.45% 37.38% | 890208 12.50% 49.88% | 893182 12.54% 62.42% | 893219 12.54% 74.96% | 892511 12.53% 87.49% | 891162 12.51% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 7122881 -system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 14 12.17% 12.17% | 10 8.70% 20.87% | 15 13.04% 33.91% | 16 13.91% 47.83% | 15 13.04% 60.87% | 9 7.83% 68.70% | 19 16.52% 85.22% | 17 14.78% 100.00% -system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 115 -system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 35 16.83% 16.83% | 22 10.58% 27.40% | 26 12.50% 39.90% | 25 12.02% 51.92% | 14 6.73% 58.65% | 29 13.94% 72.60% | 32 15.38% 87.98% | 25 12.02% 100.00% -system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 208 -system.ruby.L1Cache_Controller.M_W.Use_Timeout | 49503 12.48% 12.48% | 49628 12.51% 24.99% | 49195 12.40% 37.39% | 49527 12.48% 49.87% | 49612 12.50% 62.37% | 49820 12.56% 74.93% | 49850 12.56% 87.50% | 49609 12.50% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 396744 -system.ruby.L1Cache_Controller.MM.Load | 3 17.65% 17.65% | 3 17.65% 35.29% | 0 0.00% 35.29% | 4 23.53% 58.82% | 3 17.65% 76.47% | 0 0.00% 76.47% | 3 17.65% 94.12% | 1 5.88% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 17 -system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 3 42.86% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 1 14.29% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 7 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 27003 12.46% 12.46% | 27298 12.59% 25.05% | 27133 12.52% 37.57% | 27103 12.50% 50.08% | 27039 12.47% 62.55% | 26929 12.42% 74.97% | 27071 12.49% 87.46% | 27171 12.54% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 216747 -system.ruby.L1Cache_Controller.MM.Fwd_GETX | 9 10.11% 10.11% | 7 7.87% 17.98% | 14 15.73% 33.71% | 11 12.36% 46.07% | 11 12.36% 58.43% | 13 14.61% 73.03% | 10 11.24% 84.27% | 14 15.73% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 89 -system.ruby.L1Cache_Controller.MM.Fwd_GETS | 36 17.14% 17.14% | 31 14.76% 31.90% | 22 10.48% 42.38% | 25 11.90% 54.29% | 27 12.86% 67.14% | 24 11.43% 78.57% | 28 13.33% 91.90% | 17 8.10% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 210 -system.ruby.L1Cache_Controller.MM_W.Load | 4 14.81% 14.81% | 5 18.52% 33.33% | 2 7.41% 40.74% | 5 18.52% 59.26% | 1 3.70% 62.96% | 3 11.11% 74.07% | 4 14.81% 88.89% | 3 11.11% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 27 -system.ruby.L1Cache_Controller.MM_W.Store | 2 16.67% 16.67% | 1 8.33% 25.00% | 2 16.67% 41.67% | 1 8.33% 50.00% | 0 0.00% 50.00% | 2 16.67% 66.67% | 3 25.00% 91.67% | 1 8.33% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 12 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 503603 12.54% 12.54% | 505001 12.58% 25.12% | 504191 12.56% 37.68% | 503264 12.54% 50.22% | 498638 12.42% 62.64% | 499252 12.44% 75.08% | 498871 12.43% 87.50% | 501742 12.50% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4014562 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 8 10.67% 10.67% | 6 8.00% 18.67% | 8 10.67% 29.33% | 14 18.67% 48.00% | 9 12.00% 60.00% | 11 14.67% 74.67% | 5 6.67% 81.33% | 14 18.67% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 75 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 20 17.54% 17.54% | 15 13.16% 30.70% | 9 7.89% 38.60% | 19 16.67% 55.26% | 19 16.67% 71.93% | 12 10.53% 82.46% | 18 15.79% 98.25% | 2 1.75% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 114 -system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27045 12.46% 12.46% | 27336 12.60% 25.06% | 27167 12.52% 37.57% | 27137 12.50% 50.08% | 27074 12.47% 62.55% | 26967 12.43% 74.98% | 27109 12.49% 87.47% | 27198 12.53% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 217033 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 2854379 12.51% 12.51% | 2860141 12.54% 25.05% | 2888247 12.66% 37.71% | 2844877 12.47% 50.18% | 2844320 12.47% 62.65% | 2831082 12.41% 75.06% | 2837633 12.44% 87.49% | 2852830 12.51% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 22813509 -system.ruby.L1Cache_Controller.IM.Ack | 374 12.57% 12.57% | 373 12.54% 25.11% | 380 12.77% 37.88% | 346 11.63% 49.51% | 370 12.44% 61.95% | 346 11.63% 73.58% | 410 13.78% 87.36% | 376 12.64% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 2975 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27041 12.46% 12.46% | 27326 12.59% 25.05% | 27165 12.52% 37.57% | 27135 12.50% 50.08% | 27069 12.47% 62.55% | 26960 12.42% 74.98% | 27107 12.49% 87.47% | 27196 12.53% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 216999 -system.ruby.L1Cache_Controller.OM.L1_Replacement | 15977 12.61% 12.61% | 16015 12.64% 25.26% | 16094 12.71% 37.97% | 15787 12.46% 50.43% | 15663 12.37% 62.80% | 15820 12.49% 75.29% | 15975 12.61% 87.90% | 15323 12.10% 100.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement::total 126654 -system.ruby.L1Cache_Controller.OM.Own_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Own_GETX::total 1 -system.ruby.L1Cache_Controller.OM.Ack | 2 6.90% 6.90% | 3 10.34% 17.24% | 2 6.90% 24.14% | 5 17.24% 41.38% | 2 6.90% 48.28% | 4 13.79% 62.07% | 7 24.14% 86.21% | 4 13.79% 100.00% -system.ruby.L1Cache_Controller.OM.Ack::total 29 -system.ruby.L1Cache_Controller.OM.All_acks | 27041 12.46% 12.46% | 27326 12.59% 25.05% | 27165 12.52% 37.57% | 27136 12.51% 50.08% | 27069 12.47% 62.55% | 26960 12.42% 74.98% | 27107 12.49% 87.47% | 27196 12.53% 100.00% -system.ruby.L1Cache_Controller.OM.All_acks::total 217000 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 5271240 12.50% 12.50% | 5256024 12.47% 24.97% | 5246057 12.44% 37.41% | 5277317 12.52% 49.93% | 5278802 12.52% 62.45% | 5288220 12.54% 75.00% | 5275943 12.51% 87.51% | 5265202 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 42158805 -system.ruby.L1Cache_Controller.IS.Data | 720 12.65% 12.65% | 712 12.51% 25.17% | 716 12.58% 37.75% | 661 11.62% 49.37% | 738 12.97% 62.34% | 721 12.67% 75.01% | 703 12.36% 87.36% | 719 12.64% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 5690 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 49507 12.48% 12.48% | 49638 12.51% 24.99% | 49197 12.40% 37.39% | 49528 12.48% 49.87% | 49617 12.50% 62.37% | 49827 12.56% 74.93% | 49853 12.56% 87.50% | 49611 12.50% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 396778 -system.ruby.L1Cache_Controller.SI.Fwd_GETS | 2 25.00% 25.00% | 0 0.00% 25.00% | 3 37.50% 62.50% | 1 12.50% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 8 -system.ruby.L1Cache_Controller.SI.Inv | 5 41.67% 41.67% | 3 25.00% 66.67% | 0 0.00% 66.67% | 2 16.67% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 1 8.33% 91.67% | 1 8.33% 100.00% -system.ruby.L1Cache_Controller.SI.Inv::total 12 -system.ruby.L1Cache_Controller.SI.Writeback_Ack | 637 12.77% 12.77% | 632 12.67% 25.44% | 612 12.27% 37.70% | 579 11.61% 49.31% | 639 12.81% 62.12% | 632 12.67% 74.78% | 619 12.41% 87.19% | 639 12.81% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 4989 -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 77 11.29% 11.29% | 77 11.29% 22.58% | 104 15.25% 37.83% | 79 11.58% 49.41% | 97 14.22% 63.64% | 88 12.90% 76.54% | 81 11.88% 88.42% | 79 11.58% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 682 -system.ruby.L1Cache_Controller.OI.Fwd_GETX | 3 25.00% 25.00% | 1 8.33% 33.33% | 1 8.33% 41.67% | 0 0.00% 41.67% | 2 16.67% 58.33% | 1 8.33% 66.67% | 3 25.00% 91.67% | 1 8.33% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 12 -system.ruby.L1Cache_Controller.OI.Fwd_GETS | 1 5.00% 5.00% | 5 25.00% 30.00% | 2 10.00% 40.00% | 0 0.00% 40.00% | 4 20.00% 60.00% | 2 10.00% 70.00% | 5 25.00% 95.00% | 1 5.00% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 20 -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 667 12.88% 12.88% | 694 13.40% 26.28% | 675 13.03% 39.31% | 668 12.90% 52.21% | 624 12.05% 64.26% | 647 12.49% 76.75% | 602 11.62% 88.38% | 602 11.62% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 5179 -system.ruby.L1Cache_Controller.OI.Writeback_Nack | 45 13.04% 13.04% | 49 14.20% 27.25% | 49 14.20% 41.45% | 49 14.20% 55.65% | 36 10.43% 66.09% | 44 12.75% 78.84% | 36 10.43% 89.28% | 37 10.72% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 345 -system.ruby.L1Cache_Controller.MI.Load | 1 1.14% 1.14% | 0 0.00% 1.14% | 0 0.00% 1.14% | 19 21.59% 22.73% | 4 4.55% 27.27% | 12 13.64% 40.91% | 37 42.05% 82.95% | 15 17.05% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 88 -system.ruby.L1Cache_Controller.MI.Store | 1 4.00% 4.00% | 0 0.00% 4.00% | 2 8.00% 12.00% | 9 36.00% 48.00% | 1 4.00% 52.00% | 12 48.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MI.Store::total 25 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 337 12.57% 12.57% | 299 11.15% 23.72% | 297 11.08% 34.80% | 365 13.61% 48.41% | 329 12.27% 60.69% | 321 11.97% 72.66% | 347 12.94% 85.60% | 386 14.40% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 2681 -system.ruby.L1Cache_Controller.MI.Fwd_GETS | 620 12.78% 12.78% | 652 13.44% 26.22% | 634 13.07% 39.28% | 628 12.94% 52.23% | 589 12.14% 64.37% | 598 12.32% 76.69% | 571 11.77% 88.46% | 560 11.54% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 4852 -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 75471 12.47% 12.47% | 75902 12.54% 25.00% | 75324 12.44% 37.45% | 75567 12.48% 49.93% | 75666 12.50% 62.43% | 75761 12.51% 74.94% | 75947 12.54% 87.49% | 75760 12.51% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 605398 -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 338 12.57% 12.57% | 299 11.12% 23.70% | 298 11.09% 34.78% | 364 13.54% 48.33% | 330 12.28% 60.60% | 322 11.98% 72.58% | 350 13.02% 85.60% | 387 14.40% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 2688 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 7 41.18% 41.18% | 4 23.53% 64.71% | 0 0.00% 64.71% | 3 17.65% 82.35% | 1 5.88% 88.24% | 0 0.00% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 17 -system.ruby.L2Cache_Controller.L1_GETS 504389 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 272648 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTO 1593 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 699797 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 21673 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS 495 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 211934 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 212372 0.00% 0.00% -system.ruby.L2Cache_Controller.Data_Exclusive 392755 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 393957 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 217301 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 604645 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 13367 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 613777 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 690149 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 393211 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 211938 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETS 8 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 666 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS 16 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETS 5402 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETX 2972 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTO 2 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 608084 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTS 12 0.00% 0.00% +system.ruby.ST.miss_latency_hist::samples 225093 +system.ruby.ST.miss_latency_hist::mean 1547.880667 +system.ruby.ST.miss_latency_hist::gmean 1033.273530 +system.ruby.ST.miss_latency_hist::stdev 1543.987848 +system.ruby.ST.miss_latency_hist | 169736 75.41% 75.41% | 38573 17.14% 92.54% | 11917 5.29% 97.84% | 3626 1.61% 99.45% | 964 0.43% 99.88% | 219 0.10% 99.97% | 41 0.02% 99.99% | 15 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 225093 +system.ruby.L1Cache_Controller.Load | 50872 12.50% 12.50% | 50771 12.47% 24.97% | 50915 12.51% 37.48% | 50811 12.48% 49.96% | 51089 12.55% 62.51% | 50942 12.51% 75.02% | 50938 12.51% 87.53% | 50752 12.47% 100.00% +system.ruby.L1Cache_Controller.Load::total 407090 +system.ruby.L1Cache_Controller.Store | 28229 12.54% 12.54% | 28181 12.52% 25.05% | 28245 12.54% 37.60% | 27993 12.43% 50.03% | 28086 12.47% 62.50% | 28102 12.48% 74.98% | 28291 12.56% 87.54% | 28047 12.46% 100.00% +system.ruby.L1Cache_Controller.Store::total 225174 +system.ruby.L1Cache_Controller.L1_Replacement | 9814873 12.50% 12.50% | 9819645 12.50% 25.00% | 9815706 12.50% 37.50% | 9824325 12.51% 50.01% | 9814920 12.50% 62.50% | 9818100 12.50% 75.00% | 9808821 12.49% 87.49% | 9823009 12.51% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 78539399 +system.ruby.L1Cache_Controller.Fwd_GETX | 372 11.56% 11.56% | 430 13.37% 24.93% | 403 12.53% 37.46% | 422 13.12% 50.58% | 400 12.43% 63.01% | 387 12.03% 75.04% | 436 13.55% 88.59% | 367 11.41% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 3217 +system.ruby.L1Cache_Controller.Fwd_GETS | 784 13.34% 13.34% | 703 11.96% 25.30% | 761 12.95% 38.24% | 724 12.32% 50.56% | 723 12.30% 62.86% | 690 11.74% 74.60% | 733 12.47% 87.07% | 760 12.93% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 5878 +system.ruby.L1Cache_Controller.Inv | 3 27.27% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 2 18.18% 63.64% | 1 9.09% 72.73% | 1 9.09% 81.82% | 2 18.18% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Inv::total 11 +system.ruby.L1Cache_Controller.Ack | 382 12.53% 12.53% | 368 12.07% 24.60% | 367 12.04% 36.63% | 396 12.99% 49.62% | 413 13.55% 63.17% | 390 12.79% 75.96% | 371 12.17% 88.13% | 362 11.87% 100.00% +system.ruby.L1Cache_Controller.Ack::total 3049 +system.ruby.L1Cache_Controller.Data | 694 12.16% 12.16% | 704 12.34% 24.50% | 697 12.21% 36.71% | 700 12.27% 48.97% | 718 12.58% 61.56% | 729 12.77% 74.33% | 707 12.39% 86.72% | 758 13.28% 100.00% +system.ruby.L1Cache_Controller.Data::total 5707 +system.ruby.L1Cache_Controller.Exclusive_Data | 78379 12.52% 12.52% | 78233 12.49% 25.01% | 78415 12.52% 37.53% | 78062 12.46% 49.99% | 78404 12.52% 62.51% | 78265 12.50% 75.01% | 78500 12.53% 87.55% | 77996 12.45% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 626254 +system.ruby.L1Cache_Controller.Writeback_Ack | 625 12.30% 12.30% | 638 12.55% 24.85% | 619 12.18% 37.03% | 619 12.18% 49.20% | 632 12.43% 61.64% | 635 12.49% 74.13% | 642 12.63% 86.76% | 673 13.24% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 5083 +system.ruby.L1Cache_Controller.Writeback_Ack_Data | 78390 12.52% 12.52% | 78220 12.49% 25.00% | 78418 12.52% 37.53% | 78074 12.47% 49.99% | 78414 12.52% 62.51% | 78296 12.50% 75.01% | 78500 12.53% 87.55% | 78006 12.45% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 626318 +system.ruby.L1Cache_Controller.Writeback_Nack | 46 12.85% 12.85% | 50 13.97% 26.82% | 51 14.25% 41.06% | 32 8.94% 50.00% | 53 14.80% 64.80% | 36 10.06% 74.86% | 51 14.25% 89.11% | 39 10.89% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 358 +system.ruby.L1Cache_Controller.All_acks | 28217 12.54% 12.54% | 28176 12.52% 25.05% | 28229 12.54% 37.59% | 27981 12.43% 50.03% | 28079 12.47% 62.50% | 28094 12.48% 74.98% | 28283 12.57% 87.55% | 28034 12.45% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 225093 +system.ruby.L1Cache_Controller.Use_Timeout | 78379 12.52% 12.52% | 78232 12.49% 25.01% | 78413 12.52% 37.53% | 78061 12.46% 49.99% | 78404 12.52% 62.51% | 78263 12.50% 75.01% | 78499 12.53% 87.55% | 77996 12.45% 100.00% +system.ruby.L1Cache_Controller.Use_Timeout::total 626247 +system.ruby.L1Cache_Controller.I.Load | 50857 12.50% 12.50% | 50764 12.48% 24.98% | 50884 12.51% 37.48% | 50783 12.48% 49.96% | 51044 12.55% 62.51% | 50901 12.51% 75.02% | 50925 12.52% 87.53% | 50722 12.47% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 406880 +system.ruby.L1Cache_Controller.I.Store | 28220 12.54% 12.54% | 28176 12.52% 25.05% | 28229 12.54% 37.59% | 27982 12.43% 50.02% | 28081 12.47% 62.50% | 28095 12.48% 74.98% | 28285 12.57% 87.55% | 28035 12.45% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 225103 +system.ruby.L1Cache_Controller.I.L1_Replacement | 56 10.51% 10.51% | 76 14.26% 24.77% | 71 13.32% 38.09% | 65 12.20% 50.28% | 72 13.51% 63.79% | 59 11.07% 74.86% | 61 11.44% 86.30% | 73 13.70% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 533 +system.ruby.L1Cache_Controller.S.L1_Replacement | 693 12.15% 12.15% | 703 12.32% 24.47% | 696 12.20% 36.68% | 700 12.27% 48.95% | 718 12.59% 61.54% | 729 12.78% 74.32% | 707 12.39% 86.71% | 758 13.29% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 5704 +system.ruby.L1Cache_Controller.S.Inv | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 3 +system.ruby.L1Cache_Controller.O.L1_Replacement | 54 14.21% 14.21% | 48 12.63% 26.84% | 36 9.47% 36.32% | 47 12.37% 48.68% | 53 13.95% 62.63% | 49 12.89% 75.53% | 55 14.47% 90.00% | 38 10.00% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 380 +system.ruby.L1Cache_Controller.O.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Fwd_GETX::total 1 +system.ruby.L1Cache_Controller.M.Load | 3 21.43% 21.43% | 1 7.14% 28.57% | 2 14.29% 42.86% | 3 21.43% 64.29% | 0 0.00% 64.29% | 1 7.14% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 14 +system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 22.22% 22.22% | 3 33.33% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 9 +system.ruby.L1Cache_Controller.M.L1_Replacement | 50081 12.50% 12.50% | 49976 12.48% 24.98% | 50119 12.51% 37.49% | 50002 12.48% 49.98% | 50246 12.54% 62.52% | 50092 12.51% 75.03% | 50133 12.52% 87.54% | 49901 12.46% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 400550 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 21 10.94% 10.94% | 31 16.15% 27.08% | 25 13.02% 40.10% | 25 13.02% 53.13% | 21 10.94% 64.06% | 25 13.02% 77.08% | 25 13.02% 90.10% | 19 9.90% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 192 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 54 14.17% 14.17% | 48 12.60% 26.77% | 36 9.45% 36.22% | 47 12.34% 48.56% | 53 13.91% 62.47% | 49 12.86% 75.33% | 56 14.70% 90.03% | 38 9.97% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 381 +system.ruby.L1Cache_Controller.M_W.Load | 8 14.81% 14.81% | 3 5.56% 20.37% | 9 16.67% 37.04% | 5 9.26% 46.30% | 10 18.52% 64.81% | 11 20.37% 85.19% | 3 5.56% 90.74% | 5 9.26% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 54 +system.ruby.L1Cache_Controller.M_W.Store | 6 26.09% 26.09% | 2 8.70% 34.78% | 2 8.70% 43.48% | 4 17.39% 60.87% | 4 17.39% 78.26% | 1 4.35% 82.61% | 3 13.04% 95.65% | 1 4.35% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 23 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 902830 12.52% 12.52% | 899421 12.48% 25.00% | 898295 12.46% 37.46% | 905887 12.57% 50.02% | 901263 12.50% 62.53% | 899087 12.47% 75.00% | 900514 12.49% 87.49% | 901987 12.51% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 7209284 +system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 14 11.76% 11.76% | 15 12.61% 24.37% | 15 12.61% 36.97% | 14 11.76% 48.74% | 14 11.76% 60.50% | 27 22.69% 83.19% | 14 11.76% 94.96% | 6 5.04% 100.00% +system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 119 +system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 32 13.45% 13.45% | 36 15.13% 28.57% | 23 9.66% 38.24% | 24 10.08% 48.32% | 36 15.13% 63.45% | 37 15.55% 78.99% | 24 10.08% 89.08% | 26 10.92% 100.00% +system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 238 +system.ruby.L1Cache_Controller.M_W.Use_Timeout | 50156 12.50% 12.50% | 50055 12.48% 24.98% | 50183 12.51% 37.49% | 50077 12.48% 49.98% | 50321 12.54% 62.52% | 50168 12.51% 75.03% | 50214 12.52% 87.55% | 49961 12.45% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 401135 +system.ruby.L1Cache_Controller.MM.Load | 1 6.67% 6.67% | 1 6.67% 13.33% | 3 20.00% 33.33% | 2 13.33% 46.67% | 3 20.00% 66.67% | 3 20.00% 86.67% | 1 6.67% 93.33% | 1 6.67% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 15 +system.ruby.L1Cache_Controller.MM.Store | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 4 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 28189 12.54% 12.54% | 28133 12.52% 25.06% | 28187 12.54% 37.60% | 27946 12.43% 50.03% | 28032 12.47% 62.50% | 28063 12.48% 74.98% | 28250 12.57% 87.55% | 27983 12.45% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 224783 +system.ruby.L1Cache_Controller.MM.Fwd_GETX | 10 8.55% 8.55% | 14 11.97% 20.51% | 17 14.53% 35.04% | 18 15.38% 50.43% | 15 12.82% 63.25% | 13 11.11% 74.36% | 13 11.11% 85.47% | 17 14.53% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 117 +system.ruby.L1Cache_Controller.MM.Fwd_GETS | 24 10.86% 10.86% | 30 13.57% 24.43% | 28 12.67% 37.10% | 23 10.41% 47.51% | 36 16.29% 63.80% | 21 9.50% 73.30% | 22 9.95% 83.26% | 37 16.74% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 221 +system.ruby.L1Cache_Controller.MM_W.Load | 1 3.33% 3.33% | 0 0.00% 3.33% | 6 20.00% 23.33% | 3 10.00% 33.33% | 9 30.00% 63.33% | 6 20.00% 83.33% | 4 13.33% 96.67% | 1 3.33% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 30 +system.ruby.L1Cache_Controller.MM_W.Store | 2 11.76% 11.76% | 2 11.76% 23.53% | 2 11.76% 35.29% | 4 23.53% 58.82% | 1 5.88% 64.71% | 2 11.76% 76.47% | 1 5.88% 82.35% | 3 17.65% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 17 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 518661 12.49% 12.49% | 521491 12.56% 25.06% | 520698 12.54% 37.60% | 514785 12.40% 50.00% | 518151 12.48% 62.48% | 520112 12.53% 75.01% | 520576 12.54% 87.55% | 516624 12.45% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4151098 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 4 6.67% 6.67% | 11 18.33% 25.00% | 12 20.00% 45.00% | 10 16.67% 61.67% | 6 10.00% 71.67% | 6 10.00% 81.67% | 6 10.00% 91.67% | 5 8.33% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 60 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 14 11.11% 11.11% | 9 7.14% 18.25% | 24 19.05% 37.30% | 19 15.08% 52.38% | 7 5.56% 57.94% | 13 10.32% 68.25% | 14 11.11% 79.37% | 26 20.63% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 126 +system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 28223 12.54% 12.54% | 28177 12.52% 25.05% | 28230 12.54% 37.59% | 27984 12.43% 50.03% | 28083 12.48% 62.50% | 28095 12.48% 74.98% | 28285 12.56% 87.55% | 28035 12.45% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 225112 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 2966552 12.54% 12.54% | 2968528 12.55% 25.10% | 2951843 12.48% 37.58% | 2970169 12.56% 50.14% | 2931613 12.40% 62.54% | 2956351 12.50% 75.04% | 2958165 12.51% 87.55% | 2944845 12.45% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 23648066 +system.ruby.L1Cache_Controller.IM.Ack | 380 12.62% 12.62% | 361 11.99% 24.61% | 364 12.09% 36.70% | 391 12.99% 49.68% | 409 13.58% 63.27% | 381 12.65% 75.92% | 365 12.12% 88.04% | 360 11.96% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 3011 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 28217 12.54% 12.54% | 28176 12.52% 25.05% | 28229 12.54% 37.59% | 27981 12.43% 50.03% | 28079 12.47% 62.50% | 28094 12.48% 74.98% | 28283 12.57% 87.55% | 28034 12.45% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 225093 +system.ruby.L1Cache_Controller.OM.L1_Replacement | 16577 12.58% 12.58% | 16710 12.68% 25.26% | 16598 12.59% 37.85% | 16673 12.65% 50.50% | 16150 12.25% 62.75% | 16566 12.57% 75.32% | 16599 12.59% 87.92% | 15925 12.08% 100.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement::total 131798 +system.ruby.L1Cache_Controller.OM.Ack | 2 5.26% 5.26% | 7 18.42% 23.68% | 3 7.89% 31.58% | 5 13.16% 44.74% | 4 10.53% 55.26% | 9 23.68% 78.95% | 6 15.79% 94.74% | 2 5.26% 100.00% +system.ruby.L1Cache_Controller.OM.Ack::total 38 +system.ruby.L1Cache_Controller.OM.All_acks | 28217 12.54% 12.54% | 28176 12.52% 25.05% | 28229 12.54% 37.59% | 27981 12.43% 50.03% | 28079 12.47% 62.50% | 28094 12.48% 74.98% | 28283 12.57% 87.55% | 28034 12.45% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks::total 225093 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 5331180 12.47% 12.47% | 5334559 12.47% 24.94% | 5349163 12.51% 37.45% | 5338051 12.48% 49.93% | 5368622 12.55% 62.48% | 5346992 12.50% 74.98% | 5333761 12.47% 87.46% | 5364875 12.54% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 42767203 +system.ruby.L1Cache_Controller.IS.Data | 694 12.16% 12.16% | 704 12.34% 24.50% | 697 12.21% 36.71% | 700 12.27% 48.97% | 718 12.58% 61.56% | 729 12.77% 74.33% | 707 12.39% 86.72% | 758 13.28% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 5707 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 50162 12.50% 12.50% | 50057 12.48% 24.98% | 50186 12.51% 37.49% | 50081 12.48% 49.98% | 50325 12.54% 62.52% | 50171 12.51% 75.03% | 50217 12.52% 87.55% | 49962 12.45% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 401161 +system.ruby.L1Cache_Controller.SI.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SI.Load::total 1 +system.ruby.L1Cache_Controller.SI.Inv | 2 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 2 25.00% 50.00% | 1 12.50% 62.50% | 1 12.50% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SI.Inv::total 8 +system.ruby.L1Cache_Controller.SI.Writeback_Ack | 625 12.30% 12.30% | 638 12.55% 24.85% | 619 12.18% 37.03% | 619 12.18% 49.20% | 632 12.43% 61.64% | 635 12.49% 74.13% | 642 12.63% 86.76% | 673 13.24% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5083 +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 66 10.77% 10.77% | 65 10.60% 21.37% | 77 12.56% 33.93% | 79 12.89% 46.82% | 85 13.87% 60.69% | 93 15.17% 75.86% | 63 10.28% 86.13% | 85 13.87% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 613 +system.ruby.L1Cache_Controller.OI.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 50.00% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 6 +system.ruby.L1Cache_Controller.OI.Fwd_GETS | 3 10.71% 10.71% | 2 7.14% 17.86% | 3 10.71% 28.57% | 5 17.86% 46.43% | 6 21.43% 67.86% | 3 10.71% 78.57% | 2 7.14% 85.71% | 4 14.29% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 28 +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 711 13.52% 13.52% | 626 11.91% 25.43% | 680 12.93% 38.36% | 653 12.42% 50.78% | 637 12.11% 62.89% | 616 11.72% 74.61% | 670 12.74% 87.35% | 665 12.65% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 5258 +system.ruby.L1Cache_Controller.OI.Writeback_Nack | 44 12.79% 12.79% | 49 14.24% 27.03% | 50 14.53% 41.57% | 30 8.72% 50.29% | 50 14.53% 64.83% | 34 9.88% 74.71% | 49 14.24% 88.95% | 38 11.05% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 344 +system.ruby.L1Cache_Controller.MI.Load | 2 2.08% 2.08% | 2 2.08% 4.17% | 11 11.46% 15.62% | 15 15.62% 31.25% | 23 23.96% 55.21% | 19 19.79% 75.00% | 4 4.17% 79.17% | 20 20.83% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 96 +system.ruby.L1Cache_Controller.MI.Store | 0 0.00% 0.00% | 1 5.56% 5.56% | 10 55.56% 61.11% | 0 0.00% 61.11% | 0 0.00% 61.11% | 1 5.56% 66.67% | 1 5.56% 72.22% | 5 27.78% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 18 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 323 11.87% 11.87% | 359 13.19% 25.06% | 331 12.16% 37.22% | 355 13.04% 50.26% | 343 12.60% 62.86% | 316 11.61% 74.47% | 377 13.85% 88.32% | 318 11.68% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 2722 +system.ruby.L1Cache_Controller.MI.Fwd_GETS | 657 13.45% 13.45% | 578 11.83% 25.29% | 647 13.25% 38.53% | 606 12.41% 50.94% | 585 11.98% 62.92% | 567 11.61% 74.53% | 615 12.59% 87.12% | 629 12.88% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 4884 +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 77290 12.51% 12.51% | 77171 12.49% 25.00% | 77328 12.52% 37.52% | 76987 12.46% 49.99% | 77350 12.52% 62.51% | 77272 12.51% 75.02% | 77390 12.53% 87.55% | 76937 12.45% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 617725 +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 323 11.87% 11.87% | 358 13.15% 25.02% | 333 12.23% 37.25% | 355 13.04% 50.29% | 342 12.56% 62.86% | 315 11.57% 74.43% | 377 13.85% 88.28% | 319 11.72% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 2722 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 2 14.29% 14.29% | 1 7.14% 21.43% | 1 7.14% 28.57% | 2 14.29% 42.86% | 3 21.43% 64.29% | 2 14.29% 78.57% | 2 14.29% 92.86% | 1 7.14% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 14 +system.ruby.L2Cache_Controller.L1_GETS 510526 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 279973 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTO 1729 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 714197 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS_only 22269 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS 380 0.00% 0.00% +system.ruby.L2Cache_Controller.All_Acks 219823 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 220223 0.00% 0.00% +system.ruby.L2Cache_Controller.Data_Exclusive 397040 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 398133 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 225463 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Ack 616817 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 13512 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 626247 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 705892 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 397447 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 219833 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 612 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS 1 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETS 5486 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETX 3031 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTO 1 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTX 620443 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTS 8 0.00% 0.00% system.ruby.L2Cache_Controller.ILOX.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTO 498 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTO 511 0.00% 0.00% system.ruby.L2Cache_Controller.ILOX.L1_PUTX 345 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETS 22 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETX 11 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 184 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 4499 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 504 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 11 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 675 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_GETS 20 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETS 24 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETX 4 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 212 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 4539 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 518 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS 2 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 611 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_GETS 13 0.00% 0.00% system.ruby.L2Cache_Controller.OLSX.L1_GETX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 4435 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS 23 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L2_Replacement 239 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 16 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L2_Replacement 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 3814 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 2075 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 4528 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS 30 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L2_Replacement 212 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L2_Replacement 2 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 3902 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 2225 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_PUTX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 604433 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_GETS 53 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_GETX 42 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 826 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 4960 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_WBCLEANDATA 389 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 109 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.Unblock 504 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 138 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 87 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTO 8 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 63 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 14625 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 56 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_WBCLEANDATA 3112 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1569 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.Unblock 13 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_PUTS 78 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 16 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETS 53 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETX 14 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 666 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.Unblock 16 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L2_Replacement 297 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETS 163 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETX 69 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.Unblock 4435 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L2_Replacement 33711 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 119 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.Unblock 23 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 225 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETS 23787 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETX 12537 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTX 5410 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTS 21 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA 389774 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 215623 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.Unblock 2686 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 50 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.Unblock 8 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 15 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 35 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 616629 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETS 86 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETX 44 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 929 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 5022 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_WBCLEANDATA 377 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 134 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.Unblock 518 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 84 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 73 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 83 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 15289 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 91 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_WBCLEANDATA 3142 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1605 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.Unblock 10 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_PUTS 9 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 1 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETS 11 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 612 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.Unblock 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L2_Replacement 25 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETS 121 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETX 86 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.Unblock 4528 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L2_Replacement 34549 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 165 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.Unblock 30 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 246 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETS 24257 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETX 13813 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTX 5282 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTS 17 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA 394001 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 223724 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.Unblock 2718 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTO 5 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 7 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 45 0.00% 0.00% system.ruby.L2Cache_Controller.IFLOX.Unblock 4 0.00% 0.00% system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 7 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 550 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 221 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO 75 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 75456 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 40 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Unblock 5192 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 3184 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 175 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 115 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.Unblock 22 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 134 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only 81 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 11 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETS 49660 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETX 26581 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_PUTX 426 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_PUTS 11 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 438 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data_Exclusive 392755 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 438 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock 392753 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETS 19915 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETX 11908 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 211933 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 23 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.Data 1 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETS 4990 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETX 3032 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTX 215 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 5 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 211934 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 211933 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_GETS 41 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_GETX 46 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_PUTX 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 2075 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.Unblock 6 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 127 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETS 101 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETX 49 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_PUTX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 3814 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L2_Replacement 50262 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 107 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.Unblock 20 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.L2_Replacement 174 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETS 2451 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETX 1055 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 604406 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 1011 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.L1_PUTS 108 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 239 0.00% 0.00% -system.ruby.Directory_Controller.GETX 211949 0.00% 0.00% -system.ruby.Directory_Controller.GETS 393220 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 604433 0.00% 0.00% -system.ruby.Directory_Controller.PUTO_SHARERS 239 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 438 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 604686 0.00% 0.00% -system.ruby.Directory_Controller.Clean_Writeback 389402 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 215243 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 605138 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 215243 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 211704 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 392773 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 213458 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 236 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 438 0.00% 0.00% -system.ruby.Directory_Controller.S.Memory_Ack 82 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 604433 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTO_SHARERS 239 0.00% 0.00% -system.ruby.Directory_Controller.IS.Exclusive_Unblock 392753 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 392763 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Ack 1125 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 438 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 438 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 211933 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 211937 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 578 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 9 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETS 9 0.00% 0.00% -system.ruby.Directory_Controller.MI.Clean_Writeback 389245 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 215161 0.00% 0.00% -system.ruby.Directory_Controller.MIS.Clean_Writeback 157 0.00% 0.00% -system.ruby.Directory_Controller.MIS.Dirty_Writeback 82 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 513 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 128 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO 71 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 77511 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 34 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Unblock 5265 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 3255 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 264 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 138 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.Unblock 24 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 50 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only 29 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 4 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETS 48444 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETX 25465 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_PUTX 427 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_PUTS 4 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data 399 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data_Exclusive 397040 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Unblock 399 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock 397035 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETS 21845 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETX 11064 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.Data 219824 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETS 5622 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETX 2829 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTX 209 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.All_Acks 219823 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 219819 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_GETS 61 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_GETX 48 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_PUTX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 2225 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.Unblock 2 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 21 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_GETS 100 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_GETX 62 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_PUTX 8 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 3902 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L2_Replacement 53526 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 50 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.Unblock 13 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.L2_Replacement 71 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETS 2504 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETX 1258 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.Writeback_Ack 616605 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 1059 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.L1_PUTS 15 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 212 0.00% 0.00% +system.ruby.Directory_Controller.GETX 219834 0.00% 0.00% +system.ruby.Directory_Controller.GETS 397454 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 616629 0.00% 0.00% +system.ruby.Directory_Controller.PUTO_SHARERS 212 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 399 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 616854 0.00% 0.00% +system.ruby.Directory_Controller.Clean_Writeback 393565 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 223252 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 617270 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 223251 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 219624 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 397048 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 221545 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 209 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 399 0.00% 0.00% +system.ruby.Directory_Controller.S.Memory_Ack 75 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 616629 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTO_SHARERS 212 0.00% 0.00% +system.ruby.Directory_Controller.IS.Exclusive_Unblock 397035 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 397043 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Ack 1058 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 399 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 399 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 219819 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 219828 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 573 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETX 1 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETS 7 0.00% 0.00% +system.ruby.Directory_Controller.MI.Clean_Writeback 393428 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 223177 0.00% 0.00% +system.ruby.Directory_Controller.MIS.Clean_Writeback 137 0.00% 0.00% +system.ruby.Directory_Controller.MIS.Dirty_Writeback 75 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 7d7ea198b..607213fd3 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,1351 +1,1360 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.006151 # Number of seconds simulated -sim_ticks 6151475 # Number of ticks simulated -final_tick 6151475 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.006285 # Number of seconds simulated +sim_ticks 6284915 # Number of ticks simulated +final_tick 6284915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 74061 # Simulator tick rate (ticks/s) -host_mem_usage 259044 # Number of bytes of host memory used -host_seconds 83.06 # Real time elapsed on the host +host_tick_rate 64396 # Simulator tick rate (ticks/s) +host_mem_usage 293488 # Number of bytes of host memory used +host_seconds 97.60 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 617095 -system.ruby.outstanding_req_hist::mean 15.998444 -system.ruby.outstanding_req_hist::gmean 15.997161 -system.ruby.outstanding_req_hist::stdev 0.126779 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 16 0.00% 0.02% | 616975 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 617095 -system.ruby.latency_hist::bucket_size 1024 -system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 616967 -system.ruby.latency_hist::mean 1276.004801 -system.ruby.latency_hist::gmean 906.102654 -system.ruby.latency_hist::stdev 879.924073 -system.ruby.latency_hist | 283362 45.93% 45.93% | 188407 30.54% 76.47% | 133926 21.71% 98.17% | 11074 1.79% 99.97% | 197 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 616967 +system.ruby.outstanding_req_hist::samples 628367 +system.ruby.outstanding_req_hist::mean 15.998471 +system.ruby.outstanding_req_hist::gmean 15.997210 +system.ruby.outstanding_req_hist::stdev 0.125643 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 17 0.00% 0.02% | 628246 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 628367 +system.ruby.latency_hist::bucket_size 512 +system.ruby.latency_hist::max_bucket 5119 +system.ruby.latency_hist::samples 628239 +system.ruby.latency_hist::mean 1280.340022 +system.ruby.latency_hist::gmean 910.453414 +system.ruby.latency_hist::stdev 881.906997 +system.ruby.latency_hist | 178239 28.37% 28.37% | 109504 17.43% 45.80% | 92912 14.79% 60.59% | 97614 15.54% 76.13% | 93350 14.86% 90.99% | 44633 7.10% 98.09% | 10565 1.68% 99.77% | 1287 0.20% 99.98% | 121 0.02% 100.00% | 14 0.00% 100.00% +system.ruby.latency_hist::total 628239 system.ruby.hit_latency_hist::bucket_size 512 system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 3585 -system.ruby.hit_latency_hist::mean 1200.185216 -system.ruby.hit_latency_hist::gmean 616.910494 -system.ruby.hit_latency_hist::stdev 912.592872 -system.ruby.hit_latency_hist | 1173 32.72% 32.72% | 570 15.90% 48.62% | 519 14.48% 63.10% | 546 15.23% 78.33% | 453 12.64% 90.96% | 259 7.22% 98.19% | 56 1.56% 99.75% | 8 0.22% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 3585 -system.ruby.miss_latency_hist::bucket_size 1024 -system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 613382 -system.ruby.miss_latency_hist::mean 1276.447939 -system.ruby.miss_latency_hist::gmean 908.140819 -system.ruby.miss_latency_hist::stdev 879.711134 -system.ruby.miss_latency_hist | 281619 45.91% 45.91% | 187342 30.54% 76.45% | 133214 21.72% 98.17% | 11010 1.79% 99.97% | 196 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 613382 -system.ruby.L1Cache.incomplete_times 2563 -system.ruby.Directory.incomplete_times 610812 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 20 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 76947 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76967 # Number of cache demand accesses +system.ruby.hit_latency_hist::samples 3487 +system.ruby.hit_latency_hist::mean 1186.728993 +system.ruby.hit_latency_hist::gmean 569.952123 +system.ruby.hit_latency_hist::stdev 923.761130 +system.ruby.hit_latency_hist | 1143 32.78% 32.78% | 594 17.03% 49.81% | 495 14.20% 64.01% | 467 13.39% 77.40% | 486 13.94% 91.34% | 230 6.60% 97.94% | 60 1.72% 99.66% | 11 0.32% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 3487 +system.ruby.miss_latency_hist::bucket_size 512 +system.ruby.miss_latency_hist::max_bucket 5119 +system.ruby.miss_latency_hist::samples 624752 +system.ruby.miss_latency_hist::mean 1280.862504 +system.ruby.miss_latency_hist::gmean 912.836708 +system.ruby.miss_latency_hist::stdev 881.640698 +system.ruby.miss_latency_hist | 177096 28.35% 28.35% | 108910 17.43% 45.78% | 92417 14.79% 60.57% | 97147 15.55% 76.12% | 92864 14.86% 90.99% | 44403 7.11% 98.09% | 10505 1.68% 99.77% | 1276 0.20% 99.98% | 120 0.02% 100.00% | 14 0.00% 100.00% +system.ruby.miss_latency_hist::total 624752 +system.ruby.L1Cache.incomplete_times 2524 +system.ruby.Directory.incomplete_times 622224 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 34 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78735 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78769 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Dcache.demand_hits 25 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 77241 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77266 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 26 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78593 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78619 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 19 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 77320 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77339 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 25 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78361 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78386 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 21 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 76925 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 76946 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 26 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78366 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78392 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.demand_hits 24 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 77267 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 77291 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78372 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78396 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 77262 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77279 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 27 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78895 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78922 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 77078 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77095 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 23 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78341 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78364 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Dcache.demand_hits 22 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 76783 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 76805 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78389 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78411 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l2_cntrl0.L2cache.demand_hits 1681 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 615142 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 616823 # Number of cache demand accesses -system.ruby.network.routers00.percent_links_utilized 9.956291 -system.ruby.network.routers00.msg_count.Request_Control::1 77267 -system.ruby.network.routers00.msg_count.Response_Data::4 76923 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 231 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 399 -system.ruby.network.routers00.msg_count.Response_Control::4 188 -system.ruby.network.routers00.msg_count.Writeback_Data::4 85053 -system.ruby.network.routers00.msg_count.Broadcast_Control::1 616823 -system.ruby.network.routers00.msg_count.Persistent_Control::3 292106 -system.ruby.network.routers00.msg_bytes.Request_Control::1 618136 -system.ruby.network.routers00.msg_bytes.Response_Data::4 5538456 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 16632 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 28728 -system.ruby.network.routers00.msg_bytes.Response_Control::4 1504 -system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6123816 -system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 4934584 -system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2336848 -system.ruby.network.routers01.percent_links_utilized 9.941095 -system.ruby.network.routers01.msg_count.Request_Control::1 77262 -system.ruby.network.routers01.msg_count.Response_Data::4 76930 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 196 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 372 -system.ruby.network.routers01.msg_count.Response_Control::4 173 -system.ruby.network.routers01.msg_count.Writeback_Data::4 84683 -system.ruby.network.routers01.msg_count.Broadcast_Control::1 616823 -system.ruby.network.routers01.msg_count.Persistent_Control::3 292209 -system.ruby.network.routers01.msg_bytes.Request_Control::1 618096 -system.ruby.network.routers01.msg_bytes.Response_Data::4 5538960 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 14112 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 26784 -system.ruby.network.routers01.msg_bytes.Response_Control::4 1384 -system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6097176 -system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 4934584 -system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2337672 -system.ruby.network.routers02.percent_links_utilized 9.933215 -system.ruby.network.routers02.msg_count.Request_Control::1 77078 -system.ruby.network.routers02.msg_count.Response_Data::4 76729 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 197 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 401 -system.ruby.network.routers02.msg_count.Response_Control::4 179 -system.ruby.network.routers02.msg_count.Writeback_Data::4 84627 -system.ruby.network.routers02.msg_count.Broadcast_Control::1 616823 -system.ruby.network.routers02.msg_count.Persistent_Control::3 292491 -system.ruby.network.routers02.msg_bytes.Request_Control::1 616624 -system.ruby.network.routers02.msg_bytes.Response_Data::4 5524488 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 14184 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 28872 -system.ruby.network.routers02.msg_bytes.Response_Control::4 1432 -system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6093144 -system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 4934584 -system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2339928 -system.ruby.network.routers03.percent_links_utilized 9.903320 -system.ruby.network.routers03.msg_count.Request_Control::1 76783 -system.ruby.network.routers03.msg_count.Response_Data::4 76429 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 214 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 379 -system.ruby.network.routers03.msg_count.Response_Control::4 182 -system.ruby.network.routers03.msg_count.Writeback_Data::4 84224 -system.ruby.network.routers03.msg_count.Broadcast_Control::1 616823 -system.ruby.network.routers03.msg_count.Persistent_Control::3 291799 -system.ruby.network.routers03.msg_bytes.Request_Control::1 614264 -system.ruby.network.routers03.msg_bytes.Response_Data::4 5502888 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 15408 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 27288 -system.ruby.network.routers03.msg_bytes.Response_Control::4 1456 -system.ruby.network.routers03.msg_bytes.Writeback_Data::4 6064128 -system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 4934584 -system.ruby.network.routers03.msg_bytes.Persistent_Control::3 2334392 -system.ruby.network.routers04.percent_links_utilized 9.916236 -system.ruby.network.routers04.msg_count.Request_Control::1 76947 -system.ruby.network.routers04.msg_count.Response_Data::4 76520 -system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 224 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 401 -system.ruby.network.routers04.msg_count.Response_Control::4 179 -system.ruby.network.routers04.msg_count.Writeback_Data::4 84404 -system.ruby.network.routers04.msg_count.Broadcast_Control::1 616823 -system.ruby.network.routers04.msg_count.Persistent_Control::3 292089 -system.ruby.network.routers04.msg_bytes.Request_Control::1 615576 -system.ruby.network.routers04.msg_bytes.Response_Data::4 5509440 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 16128 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 28872 -system.ruby.network.routers04.msg_bytes.Response_Control::4 1432 -system.ruby.network.routers04.msg_bytes.Writeback_Data::4 6077088 -system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 4934584 -system.ruby.network.routers04.msg_bytes.Persistent_Control::3 2336712 -system.ruby.network.routers05.percent_links_utilized 9.943201 -system.ruby.network.routers05.msg_count.Request_Control::1 77241 -system.ruby.network.routers05.msg_count.Response_Data::4 76822 -system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 228 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 398 -system.ruby.network.routers05.msg_count.Response_Control::4 168 -system.ruby.network.routers05.msg_count.Writeback_Data::4 84787 -system.ruby.network.routers05.msg_count.Broadcast_Control::1 616823 -system.ruby.network.routers05.msg_count.Persistent_Control::3 292267 -system.ruby.network.routers05.msg_bytes.Request_Control::1 617928 -system.ruby.network.routers05.msg_bytes.Response_Data::4 5531184 -system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 16416 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 28656 -system.ruby.network.routers05.msg_bytes.Response_Control::4 1344 -system.ruby.network.routers05.msg_bytes.Writeback_Data::4 6104664 -system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 4934584 -system.ruby.network.routers05.msg_bytes.Persistent_Control::3 2338136 -system.ruby.network.routers06.percent_links_utilized 9.948553 -system.ruby.network.routers06.msg_count.Request_Control::1 77320 -system.ruby.network.routers06.msg_count.Response_Data::4 76935 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 187 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 362 -system.ruby.network.routers06.msg_count.Response_Control::4 166 -system.ruby.network.routers06.msg_count.Writeback_Data::4 84904 -system.ruby.network.routers06.msg_count.Broadcast_Control::1 616823 -system.ruby.network.routers06.msg_count.Persistent_Control::3 292130 -system.ruby.network.routers06.msg_bytes.Request_Control::1 618560 -system.ruby.network.routers06.msg_bytes.Response_Data::4 5539320 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 13464 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 26064 -system.ruby.network.routers06.msg_bytes.Response_Control::4 1328 -system.ruby.network.routers06.msg_bytes.Writeback_Data::4 6113088 -system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 4934584 -system.ruby.network.routers06.msg_bytes.Persistent_Control::3 2337040 -system.ruby.network.routers07.percent_links_utilized 9.919076 -system.ruby.network.routers07.msg_count.Request_Control::1 76925 -system.ruby.network.routers07.msg_count.Response_Data::4 76452 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 214 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 420 -system.ruby.network.routers07.msg_count.Response_Control::4 195 -system.ruby.network.routers07.msg_count.Writeback_Data::4 84536 -system.ruby.network.routers07.msg_count.Broadcast_Control::1 616823 -system.ruby.network.routers07.msg_count.Persistent_Control::3 292137 -system.ruby.network.routers07.msg_bytes.Request_Control::1 615400 -system.ruby.network.routers07.msg_bytes.Response_Data::4 5504544 -system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 15408 -system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 30240 -system.ruby.network.routers07.msg_bytes.Response_Control::4 1560 -system.ruby.network.routers07.msg_bytes.Writeback_Data::4 6086592 -system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 4934584 -system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2337096 -system.ruby.network.routers08.percent_links_utilized 38.819523 -system.ruby.network.routers08.msg_count.Request_Control::1 616823 -system.ruby.network.routers08.msg_count.Request_Control::2 615142 -system.ruby.network.routers08.msg_count.Response_Data::4 1316 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1684 -system.ruby.network.routers08.msg_count.Response_Control::4 1398 -system.ruby.network.routers08.msg_count.Writeback_Data::4 850473 -system.ruby.network.routers08.msg_count.Writeback_Control::4 377581 -system.ruby.network.routers08.msg_count.Persistent_Control::3 259692 -system.ruby.network.routers08.msg_bytes.Request_Control::1 4934584 -system.ruby.network.routers08.msg_bytes.Request_Control::2 4921136 -system.ruby.network.routers08.msg_bytes.Response_Data::4 94752 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 121248 -system.ruby.network.routers08.msg_bytes.Response_Control::4 11184 -system.ruby.network.routers08.msg_bytes.Writeback_Data::4 61234056 -system.ruby.network.routers08.msg_bytes.Writeback_Control::4 3020648 -system.ruby.network.routers08.msg_bytes.Persistent_Control::3 2077536 +system.ruby.l2_cntrl0.L2cache.demand_hits 1540 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 626511 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 628051 # Number of cache demand accesses +system.ruby.network.routers00.percent_links_utilized 9.881597 +system.ruby.network.routers00.msg_count.Request_Control::1 78371 +system.ruby.network.routers00.msg_count.Response_Data::4 78092 +system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 187 +system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 360 +system.ruby.network.routers00.msg_count.Response_Control::4 159 +system.ruby.network.routers00.msg_count.Writeback_Data::4 85878 +system.ruby.network.routers00.msg_count.Broadcast_Control::1 628051 +system.ruby.network.routers00.msg_count.Persistent_Control::3 296969 +system.ruby.network.routers00.msg_bytes.Request_Control::1 626968 +system.ruby.network.routers00.msg_bytes.Response_Data::4 5622624 +system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 13464 +system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 25920 +system.ruby.network.routers00.msg_bytes.Response_Control::4 1272 +system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6183216 +system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5024408 +system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2375752 +system.ruby.network.routers01.percent_links_utilized 9.921833 +system.ruby.network.routers01.msg_count.Request_Control::1 78895 +system.ruby.network.routers01.msg_count.Response_Data::4 78610 +system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 189 +system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 337 +system.ruby.network.routers01.msg_count.Response_Control::4 156 +system.ruby.network.routers01.msg_count.Writeback_Data::4 86402 +system.ruby.network.routers01.msg_count.Writeback_Control::4 2 +system.ruby.network.routers01.msg_count.Broadcast_Control::1 628051 +system.ruby.network.routers01.msg_count.Persistent_Control::3 297369 +system.ruby.network.routers01.msg_bytes.Request_Control::1 631160 +system.ruby.network.routers01.msg_bytes.Response_Data::4 5659920 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 13608 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 24264 +system.ruby.network.routers01.msg_bytes.Response_Control::4 1248 +system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6220944 +system.ruby.network.routers01.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5024408 +system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2378952 +system.ruby.network.routers02.percent_links_utilized 9.878833 +system.ruby.network.routers02.msg_count.Request_Control::1 78341 +system.ruby.network.routers02.msg_count.Response_Data::4 77980 +system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 204 +system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 408 +system.ruby.network.routers02.msg_count.Response_Control::4 170 +system.ruby.network.routers02.msg_count.Writeback_Data::4 85810 +system.ruby.network.routers02.msg_count.Broadcast_Control::1 628051 +system.ruby.network.routers02.msg_count.Persistent_Control::3 297325 +system.ruby.network.routers02.msg_bytes.Request_Control::1 626728 +system.ruby.network.routers02.msg_bytes.Response_Data::4 5614560 +system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 14688 +system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 29376 +system.ruby.network.routers02.msg_bytes.Response_Control::4 1360 +system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6178320 +system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5024408 +system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2378600 +system.ruby.network.routers03.percent_links_utilized 9.881140 +system.ruby.network.routers03.msg_count.Request_Control::1 78389 +system.ruby.network.routers03.msg_count.Response_Data::4 78013 +system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 216 +system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 388 +system.ruby.network.routers03.msg_count.Response_Control::4 177 +system.ruby.network.routers03.msg_count.Writeback_Data::4 85850 +system.ruby.network.routers03.msg_count.Writeback_Control::4 1 +system.ruby.network.routers03.msg_count.Broadcast_Control::1 628051 +system.ruby.network.routers03.msg_count.Persistent_Control::3 297264 +system.ruby.network.routers03.msg_bytes.Request_Control::1 627112 +system.ruby.network.routers03.msg_bytes.Response_Data::4 5616936 +system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 15552 +system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 27936 +system.ruby.network.routers03.msg_bytes.Response_Control::4 1416 +system.ruby.network.routers03.msg_bytes.Writeback_Data::4 6181200 +system.ruby.network.routers03.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5024408 +system.ruby.network.routers03.msg_bytes.Persistent_Control::3 2378112 +system.ruby.network.routers04.percent_links_utilized 9.912946 +system.ruby.network.routers04.msg_count.Request_Control::1 78735 +system.ruby.network.routers04.msg_count.Response_Data::4 78378 +system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 176 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 410 +system.ruby.network.routers04.msg_count.Response_Control::4 192 +system.ruby.network.routers04.msg_count.Writeback_Data::4 86320 +system.ruby.network.routers04.msg_count.Writeback_Control::4 2 +system.ruby.network.routers04.msg_count.Broadcast_Control::1 628051 +system.ruby.network.routers04.msg_count.Persistent_Control::3 297545 +system.ruby.network.routers04.msg_bytes.Request_Control::1 629880 +system.ruby.network.routers04.msg_bytes.Response_Data::4 5643216 +system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 12672 +system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 29520 +system.ruby.network.routers04.msg_bytes.Response_Control::4 1536 +system.ruby.network.routers04.msg_bytes.Writeback_Data::4 6215040 +system.ruby.network.routers04.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5024408 +system.ruby.network.routers04.msg_bytes.Persistent_Control::3 2380360 +system.ruby.network.routers05.percent_links_utilized 9.904116 +system.ruby.network.routers05.msg_count.Request_Control::1 78593 +system.ruby.network.routers05.msg_count.Response_Data::4 78170 +system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 203 +system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 374 +system.ruby.network.routers05.msg_count.Response_Control::4 171 +system.ruby.network.routers05.msg_count.Writeback_Data::4 86349 +system.ruby.network.routers05.msg_count.Broadcast_Control::1 628051 +system.ruby.network.routers05.msg_count.Persistent_Control::3 297182 +system.ruby.network.routers05.msg_bytes.Request_Control::1 628744 +system.ruby.network.routers05.msg_bytes.Response_Data::4 5628240 +system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 14616 +system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 26928 +system.ruby.network.routers05.msg_bytes.Response_Control::4 1368 +system.ruby.network.routers05.msg_bytes.Writeback_Data::4 6217128 +system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5024408 +system.ruby.network.routers05.msg_bytes.Persistent_Control::3 2377456 +system.ruby.network.routers06.percent_links_utilized 9.877453 +system.ruby.network.routers06.msg_count.Request_Control::1 78361 +system.ruby.network.routers06.msg_count.Response_Data::4 77958 +system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 176 +system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 389 +system.ruby.network.routers06.msg_count.Response_Control::4 176 +system.ruby.network.routers06.msg_count.Writeback_Data::4 85870 +system.ruby.network.routers06.msg_count.Broadcast_Control::1 628051 +system.ruby.network.routers06.msg_count.Persistent_Control::3 297033 +system.ruby.network.routers06.msg_bytes.Request_Control::1 626888 +system.ruby.network.routers06.msg_bytes.Response_Data::4 5612976 +system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 12672 +system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 28008 +system.ruby.network.routers06.msg_bytes.Response_Control::4 1408 +system.ruby.network.routers06.msg_bytes.Writeback_Data::4 6182640 +system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5024408 +system.ruby.network.routers06.msg_bytes.Persistent_Control::3 2376264 +system.ruby.network.routers07.percent_links_utilized 9.879175 +system.ruby.network.routers07.msg_count.Request_Control::1 78366 +system.ruby.network.routers07.msg_count.Response_Data::4 77966 +system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 194 +system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 394 +system.ruby.network.routers07.msg_count.Response_Control::4 200 +system.ruby.network.routers07.msg_count.Writeback_Data::4 85877 +system.ruby.network.routers07.msg_count.Broadcast_Control::1 628051 +system.ruby.network.routers07.msg_count.Persistent_Control::3 297095 +system.ruby.network.routers07.msg_bytes.Request_Control::1 626928 +system.ruby.network.routers07.msg_bytes.Response_Data::4 5613552 +system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 13968 +system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 28368 +system.ruby.network.routers07.msg_bytes.Response_Control::4 1600 +system.ruby.network.routers07.msg_bytes.Writeback_Data::4 6183144 +system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5024408 +system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2376760 +system.ruby.network.routers08.percent_links_utilized 38.794550 +system.ruby.network.routers08.msg_count.Request_Control::1 628051 +system.ruby.network.routers08.msg_count.Request_Control::2 626511 +system.ruby.network.routers08.msg_count.Response_Data::4 1307 +system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1542 +system.ruby.network.routers08.msg_count.Response_Control::4 1381 +system.ruby.network.routers08.msg_count.Writeback_Data::4 869556 +system.ruby.network.routers08.msg_count.Writeback_Control::4 381032 +system.ruby.network.routers08.msg_count.Persistent_Control::3 264198 +system.ruby.network.routers08.msg_bytes.Request_Control::1 5024408 +system.ruby.network.routers08.msg_bytes.Request_Control::2 5012088 +system.ruby.network.routers08.msg_bytes.Response_Data::4 94104 +system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 111024 +system.ruby.network.routers08.msg_bytes.Response_Control::4 11048 +system.ruby.network.routers08.msg_bytes.Writeback_Data::4 62608032 +system.ruby.network.routers08.msg_bytes.Writeback_Control::4 3048256 +system.ruby.network.routers08.msg_bytes.Persistent_Control::3 2113584 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 844944 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 610587 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 234338 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 42719 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 26579508 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 577720 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 15763537 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 42920765 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 50.797171 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 4097613 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 7372232 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2122830 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1320142 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 5356376 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memNotOld 6310315 # memory stalls due to anti starvation -system.ruby.dir_cntrl0.memBuffer.memBankCount | 26606 3.15% 3.15% | 25663 3.04% 6.19% | 25635 3.03% 9.22% | 25980 3.07% 12.29% | 25947 3.07% 15.37% | 25870 3.06% 18.43% | 25993 3.08% 21.50% | 25627 3.03% 24.54% | 26268 3.11% 27.65% | 26143 3.09% 30.74% | 25936 3.07% 33.81% | 26178 3.10% 36.91% | 26391 3.12% 40.03% | 26459 3.13% 43.16% | 26079 3.09% 46.25% | 26348 3.12% 49.37% | 26234 3.10% 52.47% | 26478 3.13% 55.61% | 26175 3.10% 58.70% | 26431 3.13% 61.83% | 26351 3.12% 64.95% | 26505 3.14% 68.09% | 26354 3.12% 71.21% | 26626 3.15% 74.36% | 26636 3.15% 77.51% | 26614 3.15% 80.66% | 27037 3.20% 83.86% | 26934 3.19% 87.05% | 26972 3.19% 90.24% | 27613 3.27% 93.51% | 27729 3.28% 96.79% | 27132 3.21% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 844944 # Number of accesses per bank -system.ruby.network.routers09.percent_links_utilized 36.009872 -system.ruby.network.routers09.msg_count.Request_Control::2 615142 -system.ruby.network.routers09.msg_count.Response_Data::4 610757 -system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 7 +system.ruby.dir_cntrl0.memBuffer.memReq 864242 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 622033 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 242193 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 43645 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 27461495 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 578673 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 16277009 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 44317177 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 51.278666 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 4218454 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 7606216 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2196938 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1343216 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 5525484 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memNotOld 6571187 # memory stalls due to anti starvation +system.ruby.dir_cntrl0.memBuffer.memBankCount | 26896 3.11% 3.11% | 26818 3.10% 6.22% | 26669 3.09% 9.30% | 26464 3.06% 12.36% | 26562 3.07% 15.44% | 26747 3.09% 18.53% | 26938 3.12% 21.65% | 26620 3.08% 24.73% | 26486 3.06% 27.79% | 26669 3.09% 30.88% | 26845 3.11% 33.99% | 26587 3.08% 37.06% | 26997 3.12% 40.19% | 27036 3.13% 43.31% | 27094 3.14% 46.45% | 27338 3.16% 49.61% | 26976 3.12% 52.73% | 26825 3.10% 55.84% | 26849 3.11% 58.94% | 27229 3.15% 62.09% | 26807 3.10% 65.20% | 26957 3.12% 68.32% | 26908 3.11% 71.43% | 26873 3.11% 74.54% | 27042 3.13% 77.67% | 27208 3.15% 80.82% | 26897 3.11% 83.93% | 27258 3.15% 87.08% | 27597 3.19% 90.27% | 27873 3.23% 93.50% | 27778 3.21% 96.71% | 28399 3.29% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 864242 # Number of accesses per bank +system.ruby.network.routers09.percent_links_utilized 36.011036 +system.ruby.network.routers09.msg_count.Request_Control::2 626510 +system.ruby.network.routers09.msg_count.Response_Data::4 622169 +system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 3 system.ruby.network.routers09.msg_count.Response_Control::4 4 -system.ruby.network.routers09.msg_count.Writeback_Data::4 234585 -system.ruby.network.routers09.msg_count.Writeback_Control::4 377581 -system.ruby.network.routers09.msg_count.Persistent_Control::3 259692 -system.ruby.network.routers09.msg_bytes.Request_Control::2 4921136 -system.ruby.network.routers09.msg_bytes.Response_Data::4 43974504 -system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 504 +system.ruby.network.routers09.msg_count.Writeback_Data::4 242418 +system.ruby.network.routers09.msg_count.Writeback_Control::4 381037 +system.ruby.network.routers09.msg_count.Persistent_Control::3 264198 +system.ruby.network.routers09.msg_bytes.Request_Control::2 5012080 +system.ruby.network.routers09.msg_bytes.Response_Data::4 44796168 +system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 216 system.ruby.network.routers09.msg_bytes.Response_Control::4 32 -system.ruby.network.routers09.msg_bytes.Writeback_Data::4 16890120 -system.ruby.network.routers09.msg_bytes.Writeback_Control::4 3020648 -system.ruby.network.routers09.msg_bytes.Persistent_Control::3 2077536 -system.ruby.network.routers10.percent_links_utilized 17.671908 -system.ruby.network.routers10.msg_count.Request_Control::1 616823 -system.ruby.network.routers10.msg_count.Request_Control::2 615142 -system.ruby.network.routers10.msg_count.Response_Data::4 612906 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1691 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 1566 -system.ruby.network.routers10.msg_count.Response_Control::4 1416 -system.ruby.network.routers10.msg_count.Writeback_Data::4 881138 -system.ruby.network.routers10.msg_count.Writeback_Control::4 377581 -system.ruby.network.routers10.msg_count.Broadcast_Control::1 4317761 -system.ruby.network.routers10.msg_count.Persistent_Control::3 2337228 -system.ruby.network.routers10.msg_bytes.Request_Control::1 4934584 -system.ruby.network.routers10.msg_bytes.Request_Control::2 4921136 -system.ruby.network.routers10.msg_bytes.Response_Data::4 44129232 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 121752 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 112752 -system.ruby.network.routers10.msg_bytes.Response_Control::4 11328 -system.ruby.network.routers10.msg_bytes.Writeback_Data::4 63441936 -system.ruby.network.routers10.msg_bytes.Writeback_Control::4 3020648 -system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 34542088 -system.ruby.network.routers10.msg_bytes.Persistent_Control::3 18697824 -system.ruby.network.msg_count.Request_Control 3695895 -system.ruby.network.msg_count.Response_Data 1838719 -system.ruby.network.msg_count.ResponseL2hit_Data 5073 -system.ruby.network.msg_count.ResponseLocal_Data 4698 -system.ruby.network.msg_count.Response_Control 4248 -system.ruby.network.msg_count.Writeback_Data 2643414 -system.ruby.network.msg_count.Writeback_Control 1132743 -system.ruby.network.msg_count.Broadcast_Control 9252345 -system.ruby.network.msg_count.Persistent_Control 5193840 -system.ruby.network.msg_byte.Request_Control 29567160 -system.ruby.network.msg_byte.Response_Data 132387768 -system.ruby.network.msg_byte.ResponseL2hit_Data 365256 -system.ruby.network.msg_byte.ResponseLocal_Data 338256 -system.ruby.network.msg_byte.Response_Control 33984 -system.ruby.network.msg_byte.Writeback_Data 190325808 -system.ruby.network.msg_byte.Writeback_Control 9061944 -system.ruby.network.msg_byte.Broadcast_Control 74018760 -system.ruby.network.msg_byte.Persistent_Control 41550720 +system.ruby.network.routers09.msg_bytes.Writeback_Data::4 17454096 +system.ruby.network.routers09.msg_bytes.Writeback_Control::4 3048296 +system.ruby.network.routers09.msg_bytes.Persistent_Control::3 2113584 +system.ruby.network.routers10.percent_links_utilized 17.628861 +system.ruby.network.routers10.msg_count.Request_Control::1 628051 +system.ruby.network.routers10.msg_count.Request_Control::2 626510 +system.ruby.network.routers10.msg_count.Response_Data::4 624321 +system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1545 +system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 1530 +system.ruby.network.routers10.msg_count.Response_Control::4 1393 +system.ruby.network.routers10.msg_count.Writeback_Data::4 900165 +system.ruby.network.routers10.msg_count.Writeback_Control::4 381037 +system.ruby.network.routers10.msg_count.Broadcast_Control::1 4396357 +system.ruby.network.routers10.msg_count.Persistent_Control::3 2377782 +system.ruby.network.routers10.msg_bytes.Request_Control::1 5024408 +system.ruby.network.routers10.msg_bytes.Request_Control::2 5012080 +system.ruby.network.routers10.msg_bytes.Response_Data::4 44951112 +system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 111240 +system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 110160 +system.ruby.network.routers10.msg_bytes.Response_Control::4 11144 +system.ruby.network.routers10.msg_bytes.Writeback_Data::4 64811880 +system.ruby.network.routers10.msg_bytes.Writeback_Control::4 3048296 +system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35170856 +system.ruby.network.routers10.msg_bytes.Persistent_Control::3 19022256 +system.ruby.network.msg_count.Request_Control 3763684 +system.ruby.network.msg_count.Response_Data 1872964 +system.ruby.network.msg_count.ResponseL2hit_Data 4635 +system.ruby.network.msg_count.ResponseLocal_Data 4590 +system.ruby.network.msg_count.Response_Control 4179 +system.ruby.network.msg_count.Writeback_Data 2700495 +system.ruby.network.msg_count.Writeback_Control 1143111 +system.ruby.network.msg_count.Broadcast_Control 9420765 +system.ruby.network.msg_count.Persistent_Control 5283960 +system.ruby.network.msg_byte.Request_Control 30109472 +system.ruby.network.msg_byte.Response_Data 134853408 +system.ruby.network.msg_byte.ResponseL2hit_Data 333720 +system.ruby.network.msg_byte.ResponseLocal_Data 330480 +system.ruby.network.msg_byte.Response_Control 33432 +system.ruby.network.msg_byte.Writeback_Data 194435640 +system.ruby.network.msg_byte.Writeback_Control 9144888 +system.ruby.network.msg_byte.Broadcast_Control 75366120 +system.ruby.network.msg_byte.Persistent_Control 42271680 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu_clk_domain.clock 1 # Clock period in ticks system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 54250 # number of write accesses completed +system.cpu0.num_writes 55570 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99858 # number of read accesses completed -system.cpu1.num_writes 54337 # number of write accesses completed +system.cpu1.num_reads 99982 # number of read accesses completed +system.cpu1.num_writes 55877 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99660 # number of read accesses completed -system.cpu2.num_writes 53758 # number of write accesses completed +system.cpu2.num_reads 99439 # number of read accesses completed +system.cpu2.num_writes 55577 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99997 # number of read accesses completed -system.cpu3.num_writes 53569 # number of write accesses completed +system.cpu3.num_reads 99038 # number of read accesses completed +system.cpu3.num_writes 55261 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99232 # number of read accesses completed -system.cpu4.num_writes 53727 # number of write accesses completed +system.cpu4.num_reads 99740 # number of read accesses completed +system.cpu4.num_writes 55487 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99852 # number of read accesses completed -system.cpu5.num_writes 54401 # number of write accesses completed +system.cpu5.num_reads 99865 # number of read accesses completed +system.cpu5.num_writes 55475 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99007 # number of read accesses completed -system.cpu6.num_writes 53961 # number of write accesses completed +system.cpu6.num_reads 99179 # number of read accesses completed +system.cpu6.num_writes 55288 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99727 # number of read accesses completed -system.cpu7.num_writes 53437 # number of write accesses completed +system.cpu7.num_reads 99432 # number of read accesses completed +system.cpu7.num_writes 55258 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers00.throttle0.link_utilization 12.440008 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 76833 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 229 -system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4 190 -system.ruby.network.routers00.throttle0.msg_count.Response_Control::4 2 -system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4 3997 -system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1 539556 -system.ruby.network.routers00.throttle0.msg_count.Persistent_Control::3 259692 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::4 5531976 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::4 16488 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::4 13680 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::4 16 -system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Data::4 287784 -system.ruby.network.routers00.throttle0.msg_bytes.Broadcast_Control::1 4316448 -system.ruby.network.routers00.throttle0.msg_bytes.Persistent_Control::3 2077536 -system.ruby.network.routers00.throttle1.link_utilization 7.472574 -system.ruby.network.routers00.throttle1.msg_count.Request_Control::1 77267 -system.ruby.network.routers00.throttle1.msg_count.Response_Data::4 90 -system.ruby.network.routers00.throttle1.msg_count.ResponseL2hit_Data::4 2 -system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::4 209 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::4 186 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::4 81056 -system.ruby.network.routers00.throttle1.msg_count.Broadcast_Control::1 77267 -system.ruby.network.routers00.throttle1.msg_count.Persistent_Control::3 32414 -system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::1 618136 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::4 6480 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-system.ruby.network.routers03.throttle0.msg_count.Writeback_Data::4 3852 -system.ruby.network.routers03.throttle0.msg_count.Broadcast_Control::1 540040 -system.ruby.network.routers03.throttle0.msg_count.Persistent_Control::3 259692 -system.ruby.network.routers03.throttle0.msg_bytes.Response_Data::4 5494824 -system.ruby.network.routers03.throttle0.msg_bytes.ResponseL2hit_Data::4 15408 -system.ruby.network.routers03.throttle0.msg_bytes.ResponseLocal_Data::4 12528 +system.ruby.network.routers03.throttle0.msg_count.Writeback_Data::4 3854 +system.ruby.network.routers03.throttle0.msg_count.Writeback_Control::4 1 +system.ruby.network.routers03.throttle0.msg_count.Broadcast_Control::1 549662 +system.ruby.network.routers03.throttle0.msg_count.Persistent_Control::3 264198 +system.ruby.network.routers03.throttle0.msg_bytes.Response_Data::4 5609232 +system.ruby.network.routers03.throttle0.msg_bytes.ResponseL2hit_Data::4 15552 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-system.ruby.network.routers03.throttle1.msg_bytes.Request_Control::1 614264 -system.ruby.network.routers03.throttle1.msg_bytes.Response_Data::4 8064 -system.ruby.network.routers03.throttle1.msg_bytes.ResponseLocal_Data::4 14760 -system.ruby.network.routers03.throttle1.msg_bytes.Response_Control::4 1448 -system.ruby.network.routers03.throttle1.msg_bytes.Writeback_Data::4 5786784 -system.ruby.network.routers03.throttle1.msg_bytes.Broadcast_Control::1 614264 -system.ruby.network.routers03.throttle1.msg_bytes.Persistent_Control::3 256856 -system.ruby.network.routers04.throttle0.link_utilization 12.403513 -system.ruby.network.routers04.throttle0.msg_count.Response_Data::4 76414 -system.ruby.network.routers04.throttle0.msg_count.ResponseL2hit_Data::4 223 -system.ruby.network.routers04.throttle0.msg_count.ResponseLocal_Data::4 208 -system.ruby.network.routers04.throttle0.msg_count.Response_Control::4 4 -system.ruby.network.routers04.throttle0.msg_count.Writeback_Data::4 3869 -system.ruby.network.routers04.throttle0.msg_count.Broadcast_Control::1 539876 -system.ruby.network.routers04.throttle0.msg_count.Persistent_Control::3 259692 -system.ruby.network.routers04.throttle0.msg_bytes.Response_Data::4 5501808 -system.ruby.network.routers04.throttle0.msg_bytes.ResponseL2hit_Data::4 16056 -system.ruby.network.routers04.throttle0.msg_bytes.ResponseLocal_Data::4 14976 -system.ruby.network.routers04.throttle0.msg_bytes.Response_Control::4 32 -system.ruby.network.routers04.throttle0.msg_bytes.Writeback_Data::4 278568 -system.ruby.network.routers04.throttle0.msg_bytes.Broadcast_Control::1 4319008 -system.ruby.network.routers04.throttle0.msg_bytes.Persistent_Control::3 2077536 -system.ruby.network.routers04.throttle1.link_utilization 7.428958 -system.ruby.network.routers04.throttle1.msg_count.Request_Control::1 76947 -system.ruby.network.routers04.throttle1.msg_count.Response_Data::4 106 +system.ruby.network.routers03.throttle0.msg_bytes.Writeback_Data::4 277488 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-system.ruby.network.routers10.throttle0.msg_count.Response_Data::4 76833 -system.ruby.network.routers10.throttle0.msg_count.ResponseL2hit_Data::4 229 -system.ruby.network.routers10.throttle0.msg_count.ResponseLocal_Data::4 190 -system.ruby.network.routers10.throttle0.msg_count.Response_Control::4 2 -system.ruby.network.routers10.throttle0.msg_count.Writeback_Data::4 3997 -system.ruby.network.routers10.throttle0.msg_count.Broadcast_Control::1 539556 -system.ruby.network.routers10.throttle0.msg_count.Persistent_Control::3 227278 -system.ruby.network.routers10.throttle0.msg_bytes.Response_Data::4 5531976 -system.ruby.network.routers10.throttle0.msg_bytes.ResponseL2hit_Data::4 16488 -system.ruby.network.routers10.throttle0.msg_bytes.ResponseLocal_Data::4 13680 -system.ruby.network.routers10.throttle0.msg_bytes.Response_Control::4 16 -system.ruby.network.routers10.throttle0.msg_bytes.Writeback_Data::4 287784 -system.ruby.network.routers10.throttle0.msg_bytes.Broadcast_Control::1 4316448 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+system.ruby.network.routers07.throttle1.msg_count.Writeback_Data::4 81952 +system.ruby.network.routers07.throttle1.msg_count.Broadcast_Control::1 78366 +system.ruby.network.routers07.throttle1.msg_count.Persistent_Control::3 32897 +system.ruby.network.routers07.throttle1.msg_bytes.Request_Control::1 626928 +system.ruby.network.routers07.throttle1.msg_bytes.Response_Data::4 8784 +system.ruby.network.routers07.throttle1.msg_bytes.ResponseLocal_Data::4 14760 +system.ruby.network.routers07.throttle1.msg_bytes.Response_Control::4 1584 +system.ruby.network.routers07.throttle1.msg_bytes.Writeback_Data::4 5900544 +system.ruby.network.routers07.throttle1.msg_bytes.Broadcast_Control::1 626928 +system.ruby.network.routers07.throttle1.msg_bytes.Persistent_Control::3 263176 +system.ruby.network.routers08.throttle0.link_utilization 51.976741 +system.ruby.network.routers08.throttle0.msg_count.Request_Control::1 628051 +system.ruby.network.routers08.throttle0.msg_count.Response_Control::4 1379 +system.ruby.network.routers08.throttle0.msg_count.Writeback_Data::4 626640 +system.ruby.network.routers08.throttle0.msg_count.Persistent_Control::3 264198 +system.ruby.network.routers08.throttle0.msg_bytes.Request_Control::1 5024408 +system.ruby.network.routers08.throttle0.msg_bytes.Response_Control::4 11032 +system.ruby.network.routers08.throttle0.msg_bytes.Writeback_Data::4 45118080 +system.ruby.network.routers08.throttle0.msg_bytes.Persistent_Control::3 2113584 +system.ruby.network.routers08.throttle1.link_utilization 25.612359 +system.ruby.network.routers08.throttle1.msg_count.Request_Control::2 626511 +system.ruby.network.routers08.throttle1.msg_count.Response_Data::4 1307 +system.ruby.network.routers08.throttle1.msg_count.ResponseL2hit_Data::4 1542 +system.ruby.network.routers08.throttle1.msg_count.Response_Control::4 2 +system.ruby.network.routers08.throttle1.msg_count.Writeback_Data::4 242916 +system.ruby.network.routers08.throttle1.msg_count.Writeback_Control::4 381032 +system.ruby.network.routers08.throttle1.msg_bytes.Request_Control::2 5012088 +system.ruby.network.routers08.throttle1.msg_bytes.Response_Data::4 94104 +system.ruby.network.routers08.throttle1.msg_bytes.ResponseL2hit_Data::4 111024 +system.ruby.network.routers08.throttle1.msg_bytes.Response_Control::4 16 +system.ruby.network.routers08.throttle1.msg_bytes.Writeback_Data::4 17489952 +system.ruby.network.routers08.throttle1.msg_bytes.Writeback_Control::4 3048256 +system.ruby.network.routers09.throttle0.link_utilization 27.469345 +system.ruby.network.routers09.throttle0.msg_count.Request_Control::2 626510 +system.ruby.network.routers09.throttle0.msg_count.Response_Data::4 17 +system.ruby.network.routers09.throttle0.msg_count.ResponseL2hit_Data::4 3 +system.ruby.network.routers09.throttle0.msg_count.Response_Control::4 3 +system.ruby.network.routers09.throttle0.msg_count.Writeback_Data::4 242325 +system.ruby.network.routers09.throttle0.msg_count.Writeback_Control::4 381034 +system.ruby.network.routers09.throttle0.msg_count.Persistent_Control::3 264198 +system.ruby.network.routers09.throttle0.msg_bytes.Request_Control::2 5012080 +system.ruby.network.routers09.throttle0.msg_bytes.Response_Data::4 1224 +system.ruby.network.routers09.throttle0.msg_bytes.ResponseL2hit_Data::4 216 +system.ruby.network.routers09.throttle0.msg_bytes.Response_Control::4 24 +system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Data::4 17447400 +system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Control::4 3048272 +system.ruby.network.routers09.throttle0.msg_bytes.Persistent_Control::3 2113584 +system.ruby.network.routers09.throttle1.link_utilization 44.552727 +system.ruby.network.routers09.throttle1.msg_count.Response_Data::4 622152 +system.ruby.network.routers09.throttle1.msg_count.Response_Control::4 1 +system.ruby.network.routers09.throttle1.msg_count.Writeback_Data::4 93 +system.ruby.network.routers09.throttle1.msg_count.Writeback_Control::4 3 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::4 44794944 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Control::4 8 +system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Data::4 6696 +system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Control::4 24 +system.ruby.network.routers10.throttle0.link_utilization 12.099527 +system.ruby.network.routers10.throttle0.msg_count.Response_Data::4 77998 +system.ruby.network.routers10.throttle0.msg_count.ResponseL2hit_Data::4 187 +system.ruby.network.routers10.throttle0.msg_count.ResponseLocal_Data::4 169 +system.ruby.network.routers10.throttle0.msg_count.Response_Control::4 1 +system.ruby.network.routers10.throttle0.msg_count.Writeback_Data::4 3844 +system.ruby.network.routers10.throttle0.msg_count.Broadcast_Control::1 549680 +system.ruby.network.routers10.throttle0.msg_count.Persistent_Control::3 231427 +system.ruby.network.routers10.throttle0.msg_bytes.Response_Data::4 5615856 +system.ruby.network.routers10.throttle0.msg_bytes.ResponseL2hit_Data::4 13464 +system.ruby.network.routers10.throttle0.msg_bytes.ResponseLocal_Data::4 12168 +system.ruby.network.routers10.throttle0.msg_bytes.Response_Control::4 8 +system.ruby.network.routers10.throttle0.msg_bytes.Writeback_Data::4 276768 +system.ruby.network.routers10.throttle0.msg_bytes.Broadcast_Control::1 4397440 +system.ruby.network.routers10.throttle0.msg_bytes.Persistent_Control::3 1851416 +system.ruby.network.routers10.throttle1.link_utilization 12.128772 +system.ruby.network.routers10.throttle1.msg_count.Response_Data::4 78508 +system.ruby.network.routers10.throttle1.msg_count.ResponseL2hit_Data::4 188 +system.ruby.network.routers10.throttle1.msg_count.ResponseLocal_Data::4 163 system.ruby.network.routers10.throttle1.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle1.msg_count.Writeback_Data::4 3823 -system.ruby.network.routers10.throttle1.msg_count.Broadcast_Control::1 539561 -system.ruby.network.routers10.throttle1.msg_count.Persistent_Control::3 227175 -system.ruby.network.routers10.throttle1.msg_bytes.Response_Data::4 5531184 -system.ruby.network.routers10.throttle1.msg_bytes.ResponseL2hit_Data::4 14112 -system.ruby.network.routers10.throttle1.msg_bytes.ResponseLocal_Data::4 14040 +system.ruby.network.routers10.throttle1.msg_count.Writeback_Data::4 3850 +system.ruby.network.routers10.throttle1.msg_count.Writeback_Control::4 1 +system.ruby.network.routers10.throttle1.msg_count.Broadcast_Control::1 549156 +system.ruby.network.routers10.throttle1.msg_count.Persistent_Control::3 231027 +system.ruby.network.routers10.throttle1.msg_bytes.Response_Data::4 5652576 +system.ruby.network.routers10.throttle1.msg_bytes.ResponseL2hit_Data::4 13536 +system.ruby.network.routers10.throttle1.msg_bytes.ResponseLocal_Data::4 11736 system.ruby.network.routers10.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Data::4 275256 -system.ruby.network.routers10.throttle1.msg_bytes.Broadcast_Control::1 4316488 -system.ruby.network.routers10.throttle1.msg_bytes.Persistent_Control::3 1817400 -system.ruby.network.routers10.throttle2.link_utilization 12.150842 -system.ruby.network.routers10.throttle2.msg_count.Response_Data::4 76622 -system.ruby.network.routers10.throttle2.msg_count.ResponseL2hit_Data::4 196 -system.ruby.network.routers10.throttle2.msg_count.ResponseLocal_Data::4 209 +system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Data::4 277200 +system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers10.throttle1.msg_bytes.Broadcast_Control::1 4393248 +system.ruby.network.routers10.throttle1.msg_bytes.Persistent_Control::3 1848216 +system.ruby.network.routers10.throttle2.link_utilization 12.092439 +system.ruby.network.routers10.throttle2.msg_count.Response_Data::4 77883 +system.ruby.network.routers10.throttle2.msg_count.ResponseL2hit_Data::4 203 +system.ruby.network.routers10.throttle2.msg_count.ResponseLocal_Data::4 204 system.ruby.network.routers10.throttle2.msg_count.Response_Control::4 3 -system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 3892 -system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 539745 -system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 226893 -system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5516784 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 14112 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 15048 +system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 3845 +system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 549710 +system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 231071 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5607576 +system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 14616 +system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 14688 system.ruby.network.routers10.throttle2.msg_bytes.Response_Control::4 24 -system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 280224 -system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4317960 -system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 1815144 -system.ruby.network.routers10.throttle3.link_utilization 12.132367 -system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 76317 -system.ruby.network.routers10.throttle3.msg_count.ResponseL2hit_Data::4 214 -system.ruby.network.routers10.throttle3.msg_count.ResponseLocal_Data::4 174 +system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 276840 +system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4397680 +system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 1848568 +system.ruby.network.routers10.throttle3.link_utilization 12.095470 +system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 77906 +system.ruby.network.routers10.throttle3.msg_count.ResponseL2hit_Data::4 216 +system.ruby.network.routers10.throttle3.msg_count.ResponseLocal_Data::4 200 system.ruby.network.routers10.throttle3.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle3.msg_count.Writeback_Data::4 3852 -system.ruby.network.routers10.throttle3.msg_count.Broadcast_Control::1 540040 -system.ruby.network.routers10.throttle3.msg_count.Persistent_Control::3 227585 -system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::4 5494824 -system.ruby.network.routers10.throttle3.msg_bytes.ResponseL2hit_Data::4 15408 -system.ruby.network.routers10.throttle3.msg_bytes.ResponseLocal_Data::4 12528 +system.ruby.network.routers10.throttle3.msg_count.Writeback_Data::4 3854 +system.ruby.network.routers10.throttle3.msg_count.Writeback_Control::4 1 +system.ruby.network.routers10.throttle3.msg_count.Broadcast_Control::1 549662 +system.ruby.network.routers10.throttle3.msg_count.Persistent_Control::3 231132 +system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::4 5609232 +system.ruby.network.routers10.throttle3.msg_bytes.ResponseL2hit_Data::4 15552 +system.ruby.network.routers10.throttle3.msg_bytes.ResponseLocal_Data::4 14400 system.ruby.network.routers10.throttle3.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle3.msg_bytes.Writeback_Data::4 277344 -system.ruby.network.routers10.throttle3.msg_bytes.Broadcast_Control::1 4320320 -system.ruby.network.routers10.throttle3.msg_bytes.Persistent_Control::3 1820680 -system.ruby.network.routers10.throttle4.link_utilization 12.140186 -system.ruby.network.routers10.throttle4.msg_count.Response_Data::4 76414 -system.ruby.network.routers10.throttle4.msg_count.ResponseL2hit_Data::4 223 -system.ruby.network.routers10.throttle4.msg_count.ResponseLocal_Data::4 208 -system.ruby.network.routers10.throttle4.msg_count.Response_Control::4 4 -system.ruby.network.routers10.throttle4.msg_count.Writeback_Data::4 3869 -system.ruby.network.routers10.throttle4.msg_count.Broadcast_Control::1 539876 -system.ruby.network.routers10.throttle4.msg_count.Persistent_Control::3 227295 -system.ruby.network.routers10.throttle4.msg_bytes.Response_Data::4 5501808 -system.ruby.network.routers10.throttle4.msg_bytes.ResponseL2hit_Data::4 16056 -system.ruby.network.routers10.throttle4.msg_bytes.ResponseLocal_Data::4 14976 -system.ruby.network.routers10.throttle4.msg_bytes.Response_Control::4 32 -system.ruby.network.routers10.throttle4.msg_bytes.Writeback_Data::4 278568 -system.ruby.network.routers10.throttle4.msg_bytes.Broadcast_Control::1 4319008 -system.ruby.network.routers10.throttle4.msg_bytes.Persistent_Control::3 1818360 -system.ruby.network.routers10.throttle5.link_utilization 12.160401 -system.ruby.network.routers10.throttle5.msg_count.Response_Data::4 76710 -system.ruby.network.routers10.throttle5.msg_count.ResponseL2hit_Data::4 226 -system.ruby.network.routers10.throttle5.msg_count.ResponseLocal_Data::4 192 -system.ruby.network.routers10.throttle5.msg_count.Response_Control::4 2 -system.ruby.network.routers10.throttle5.msg_count.Writeback_Data::4 3915 -system.ruby.network.routers10.throttle5.msg_count.Broadcast_Control::1 539582 -system.ruby.network.routers10.throttle5.msg_count.Persistent_Control::3 227117 -system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::4 5523120 -system.ruby.network.routers10.throttle5.msg_bytes.ResponseL2hit_Data::4 16272 -system.ruby.network.routers10.throttle5.msg_bytes.ResponseLocal_Data::4 13824 -system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::4 16 -system.ruby.network.routers10.throttle5.msg_bytes.Writeback_Data::4 281880 -system.ruby.network.routers10.throttle5.msg_bytes.Broadcast_Control::1 4316656 -system.ruby.network.routers10.throttle5.msg_bytes.Persistent_Control::3 1816936 -system.ruby.network.routers10.throttle6.link_utilization 12.167326 -system.ruby.network.routers10.throttle6.msg_count.Response_Data::4 76822 -system.ruby.network.routers10.throttle6.msg_count.ResponseL2hit_Data::4 186 -system.ruby.network.routers10.throttle6.msg_count.ResponseLocal_Data::4 187 -system.ruby.network.routers10.throttle6.msg_count.Response_Control::4 4 -system.ruby.network.routers10.throttle6.msg_count.Writeback_Data::4 3936 -system.ruby.network.routers10.throttle6.msg_count.Broadcast_Control::1 539503 -system.ruby.network.routers10.throttle6.msg_count.Persistent_Control::3 227254 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::4 5531184 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseL2hit_Data::4 13392 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseLocal_Data::4 13464 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::4 32 -system.ruby.network.routers10.throttle6.msg_bytes.Writeback_Data::4 283392 -system.ruby.network.routers10.throttle6.msg_bytes.Broadcast_Control::1 4316024 -system.ruby.network.routers10.throttle6.msg_bytes.Persistent_Control::3 1818032 -system.ruby.network.routers10.throttle7.link_utilization 12.142519 -system.ruby.network.routers10.throttle7.msg_count.Response_Data::4 76342 -system.ruby.network.routers10.throttle7.msg_count.ResponseL2hit_Data::4 214 -system.ruby.network.routers10.throttle7.msg_count.ResponseLocal_Data::4 211 +system.ruby.network.routers10.throttle3.msg_bytes.Writeback_Data::4 277488 +system.ruby.network.routers10.throttle3.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers10.throttle3.msg_bytes.Broadcast_Control::1 4397296 +system.ruby.network.routers10.throttle3.msg_bytes.Persistent_Control::3 1849056 +system.ruby.network.routers10.throttle4.link_utilization 12.119201 +system.ruby.network.routers10.throttle4.msg_count.Response_Data::4 78259 +system.ruby.network.routers10.throttle4.msg_count.ResponseL2hit_Data::4 175 +system.ruby.network.routers10.throttle4.msg_count.ResponseLocal_Data::4 207 +system.ruby.network.routers10.throttle4.msg_count.Response_Control::4 2 +system.ruby.network.routers10.throttle4.msg_count.Writeback_Data::4 3936 +system.ruby.network.routers10.throttle4.msg_count.Writeback_Control::4 1 +system.ruby.network.routers10.throttle4.msg_count.Broadcast_Control::1 549316 +system.ruby.network.routers10.throttle4.msg_count.Persistent_Control::3 230851 +system.ruby.network.routers10.throttle4.msg_bytes.Response_Data::4 5634648 +system.ruby.network.routers10.throttle4.msg_bytes.ResponseL2hit_Data::4 12600 +system.ruby.network.routers10.throttle4.msg_bytes.ResponseLocal_Data::4 14904 +system.ruby.network.routers10.throttle4.msg_bytes.Response_Control::4 16 +system.ruby.network.routers10.throttle4.msg_bytes.Writeback_Data::4 283392 +system.ruby.network.routers10.throttle4.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers10.throttle4.msg_bytes.Broadcast_Control::1 4394528 +system.ruby.network.routers10.throttle4.msg_bytes.Persistent_Control::3 1846808 +system.ruby.network.routers10.throttle5.link_utilization 12.117610 +system.ruby.network.routers10.throttle5.msg_count.Response_Data::4 78073 +system.ruby.network.routers10.throttle5.msg_count.ResponseL2hit_Data::4 203 +system.ruby.network.routers10.throttle5.msg_count.ResponseLocal_Data::4 197 +system.ruby.network.routers10.throttle5.msg_count.Writeback_Data::4 4026 +system.ruby.network.routers10.throttle5.msg_count.Broadcast_Control::1 549458 +system.ruby.network.routers10.throttle5.msg_count.Persistent_Control::3 231214 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::4 5621256 +system.ruby.network.routers10.throttle5.msg_bytes.ResponseL2hit_Data::4 14616 +system.ruby.network.routers10.throttle5.msg_bytes.ResponseLocal_Data::4 14184 +system.ruby.network.routers10.throttle5.msg_bytes.Writeback_Data::4 289872 +system.ruby.network.routers10.throttle5.msg_bytes.Broadcast_Control::1 4395664 +system.ruby.network.routers10.throttle5.msg_bytes.Persistent_Control::3 1849712 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+system.ruby.network.routers10.throttle6.msg_bytes.Broadcast_Control::1 4397520 +system.ruby.network.routers10.throttle6.msg_bytes.Persistent_Control::3 1850904 +system.ruby.network.routers10.throttle7.link_utilization 12.095279 +system.ruby.network.routers10.throttle7.msg_count.Response_Data::4 77844 +system.ruby.network.routers10.throttle7.msg_count.ResponseL2hit_Data::4 194 +system.ruby.network.routers10.throttle7.msg_count.ResponseLocal_Data::4 189 system.ruby.network.routers10.throttle7.msg_count.Response_Control::4 2 -system.ruby.network.routers10.throttle7.msg_count.Writeback_Data::4 3982 -system.ruby.network.routers10.throttle7.msg_count.Broadcast_Control::1 539898 -system.ruby.network.routers10.throttle7.msg_count.Persistent_Control::3 227247 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::4 5496624 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseL2hit_Data::4 15408 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseLocal_Data::4 15192 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-system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::4 615396 -system.ruby.network.routers10.throttle8.msg_count.Persistent_Control::3 259692 -system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::1 4934584 -system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::4 11160 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::4 44308512 -system.ruby.network.routers10.throttle8.msg_bytes.Persistent_Control::3 2077536 -system.ruby.network.routers10.throttle9.link_utilization 27.334745 -system.ruby.network.routers10.throttle9.msg_count.Request_Control::2 615142 -system.ruby.network.routers10.throttle9.msg_count.Response_Data::4 24 -system.ruby.network.routers10.throttle9.msg_count.ResponseL2hit_Data::4 7 -system.ruby.network.routers10.throttle9.msg_count.Response_Control::4 2 -system.ruby.network.routers10.throttle9.msg_count.Writeback_Data::4 234476 -system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::4 377581 -system.ruby.network.routers10.throttle9.msg_count.Persistent_Control::3 259692 -system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::2 4921136 -system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::4 1728 -system.ruby.network.routers10.throttle9.msg_bytes.ResponseL2hit_Data::4 504 -system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::4 16 -system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::4 16882272 -system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::4 3020648 -system.ruby.network.routers10.throttle9.msg_bytes.Persistent_Control::3 2077536 +system.ruby.network.routers10.throttle7.msg_bytes.Writeback_Data::4 282600 +system.ruby.network.routers10.throttle7.msg_bytes.Broadcast_Control::1 4397480 +system.ruby.network.routers10.throttle7.msg_bytes.Persistent_Control::3 1850408 +system.ruby.network.routers10.throttle8.link_utilization 51.976741 +system.ruby.network.routers10.throttle8.msg_count.Request_Control::1 628051 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::4 1379 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::4 626640 +system.ruby.network.routers10.throttle8.msg_count.Persistent_Control::3 264198 +system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::1 5024408 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::4 11032 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::4 45118080 +system.ruby.network.routers10.throttle8.msg_bytes.Persistent_Control::3 2113584 +system.ruby.network.routers10.throttle9.link_utilization 27.469345 +system.ruby.network.routers10.throttle9.msg_count.Request_Control::2 626510 +system.ruby.network.routers10.throttle9.msg_count.Response_Data::4 17 +system.ruby.network.routers10.throttle9.msg_count.ResponseL2hit_Data::4 3 +system.ruby.network.routers10.throttle9.msg_count.Response_Control::4 3 +system.ruby.network.routers10.throttle9.msg_count.Writeback_Data::4 242325 +system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::4 381034 +system.ruby.network.routers10.throttle9.msg_count.Persistent_Control::3 264198 +system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::2 5012080 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::4 1224 +system.ruby.network.routers10.throttle9.msg_bytes.ResponseL2hit_Data::4 216 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::4 24 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::4 17447400 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::4 3048272 +system.ruby.network.routers10.throttle9.msg_bytes.Persistent_Control::3 2113584 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 401150 -system.ruby.LD.latency_hist::mean 1276.530639 -system.ruby.LD.latency_hist::gmean 906.015371 -system.ruby.LD.latency_hist::stdev 880.306835 -system.ruby.LD.latency_hist | 114447 28.53% 28.53% | 69647 17.36% 45.89% | 58610 14.61% 60.50% | 63948 15.94% 76.44% | 59270 14.78% 91.22% | 27867 6.95% 98.17% | 6198 1.55% 99.71% | 1034 0.26% 99.97% | 109 0.03% 100.00% | 20 0.00% 100.00% -system.ruby.LD.latency_hist::total 401150 +system.ruby.LD.latency_hist::samples 404587 +system.ruby.LD.latency_hist::mean 1281.489712 +system.ruby.LD.latency_hist::gmean 911.698103 +system.ruby.LD.latency_hist::stdev 881.845423 +system.ruby.LD.latency_hist | 114672 28.34% 28.34% | 70346 17.39% 45.73% | 59895 14.80% 60.53% | 62905 15.55% 76.08% | 60348 14.92% 91.00% | 28706 7.10% 98.09% | 6783 1.68% 99.77% | 841 0.21% 99.98% | 80 0.02% 100.00% | 11 0.00% 100.00% +system.ruby.LD.latency_hist::total 404587 system.ruby.LD.hit_latency_hist::bucket_size 512 system.ruby.LD.hit_latency_hist::max_bucket 5119 -system.ruby.LD.hit_latency_hist::samples 2325 -system.ruby.LD.hit_latency_hist::mean 1206.759140 -system.ruby.LD.hit_latency_hist::gmean 607.027231 -system.ruby.LD.hit_latency_hist::stdev 920.547274 -system.ruby.LD.hit_latency_hist | 761 32.73% 32.73% | 367 15.78% 48.52% | 331 14.24% 62.75% | 343 14.75% 77.51% | 308 13.25% 90.75% | 177 7.61% 98.37% | 31 1.33% 99.70% | 6 0.26% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 2325 +system.ruby.LD.hit_latency_hist::samples 2258 +system.ruby.LD.hit_latency_hist::mean 1187.532329 +system.ruby.LD.hit_latency_hist::gmean 564.429261 +system.ruby.LD.hit_latency_hist::stdev 929.035810 +system.ruby.LD.hit_latency_hist | 747 33.08% 33.08% | 381 16.87% 49.96% | 319 14.13% 64.08% | 286 12.67% 76.75% | 325 14.39% 91.14% | 151 6.69% 97.83% | 42 1.86% 99.69% | 6 0.27% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 2258 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 398825 -system.ruby.LD.miss_latency_hist::mean 1276.937381 -system.ruby.LD.miss_latency_hist::gmean 908.133083 -system.ruby.LD.miss_latency_hist::stdev 880.051843 -system.ruby.LD.miss_latency_hist | 113686 28.51% 28.51% | 69280 17.37% 45.88% | 58279 14.61% 60.49% | 63605 15.95% 76.44% | 58962 14.78% 91.22% | 27690 6.94% 98.16% | 6167 1.55% 99.71% | 1028 0.26% 99.97% | 108 0.03% 99.99% | 20 0.01% 100.00% -system.ruby.LD.miss_latency_hist::total 398825 -system.ruby.ST.latency_hist::bucket_size 1024 -system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 215817 -system.ruby.ST.latency_hist::mean 1275.027398 -system.ruby.ST.latency_hist::gmean 906.264914 -system.ruby.ST.latency_hist::stdev 879.213376 -system.ruby.ST.latency_hist | 99268 46.00% 46.00% | 65849 30.51% 76.51% | 46789 21.68% 98.19% | 3842 1.78% 99.97% | 68 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 215817 +system.ruby.LD.miss_latency_hist::samples 402329 +system.ruby.LD.miss_latency_hist::mean 1282.017031 +system.ruby.LD.miss_latency_hist::gmean 914.154854 +system.ruby.LD.miss_latency_hist::stdev 881.546404 +system.ruby.LD.miss_latency_hist | 113925 28.32% 28.32% | 69965 17.39% 45.71% | 59576 14.81% 60.51% | 62619 15.56% 76.08% | 60023 14.92% 91.00% | 28555 7.10% 98.09% | 6741 1.68% 99.77% | 835 0.21% 99.98% | 79 0.02% 100.00% | 11 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 402329 +system.ruby.ST.latency_hist::bucket_size 512 +system.ruby.ST.latency_hist::max_bucket 5119 +system.ruby.ST.latency_hist::samples 223652 +system.ruby.ST.latency_hist::mean 1278.260230 +system.ruby.ST.latency_hist::gmean 908.206083 +system.ruby.ST.latency_hist::stdev 882.016539 +system.ruby.ST.latency_hist | 63567 28.42% 28.42% | 39158 17.51% 45.93% | 33017 14.76% 60.69% | 34709 15.52% 76.21% | 33002 14.76% 90.97% | 15927 7.12% 98.09% | 3782 1.69% 99.78% | 446 0.20% 99.98% | 41 0.02% 100.00% | 3 0.00% 100.00% +system.ruby.ST.latency_hist::total 223652 system.ruby.ST.hit_latency_hist::bucket_size 512 system.ruby.ST.hit_latency_hist::max_bucket 5119 -system.ruby.ST.hit_latency_hist::samples 1260 -system.ruby.ST.hit_latency_hist::mean 1188.054762 -system.ruby.ST.hit_latency_hist::gmean 635.571815 -system.ruby.ST.hit_latency_hist::stdev 897.966582 -system.ruby.ST.hit_latency_hist | 412 32.70% 32.70% | 203 16.11% 48.81% | 188 14.92% 63.73% | 203 16.11% 79.84% | 145 11.51% 91.35% | 82 6.51% 97.86% | 25 1.98% 99.84% | 2 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 1260 -system.ruby.ST.miss_latency_hist::bucket_size 1024 -system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 214557 -system.ruby.ST.miss_latency_hist::mean 1275.538151 -system.ruby.ST.miss_latency_hist::gmean 908.155198 -system.ruby.ST.miss_latency_hist::stdev 879.078788 -system.ruby.ST.miss_latency_hist | 98653 45.98% 45.98% | 65458 30.51% 76.49% | 46562 21.70% 98.19% | 3815 1.78% 99.97% | 68 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 214557 +system.ruby.ST.hit_latency_hist::samples 1229 +system.ruby.ST.hit_latency_hist::mean 1185.253051 +system.ruby.ST.hit_latency_hist::gmean 580.240327 +system.ruby.ST.hit_latency_hist::stdev 914.365384 +system.ruby.ST.hit_latency_hist | 396 32.22% 32.22% | 213 17.33% 49.55% | 176 14.32% 63.87% | 181 14.73% 78.60% | 161 13.10% 91.70% | 79 6.43% 98.13% | 18 1.46% 99.59% | 5 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 1229 +system.ruby.ST.miss_latency_hist::bucket_size 512 +system.ruby.ST.miss_latency_hist::max_bucket 5119 +system.ruby.ST.miss_latency_hist::samples 222423 +system.ruby.ST.miss_latency_hist::mean 1278.774142 +system.ruby.ST.miss_latency_hist::gmean 910.457212 +system.ruby.ST.miss_latency_hist::stdev 881.809378 +system.ruby.ST.miss_latency_hist | 63171 28.40% 28.40% | 38945 17.51% 45.91% | 32841 14.77% 60.68% | 34528 15.52% 76.20% | 32841 14.77% 90.96% | 15848 7.13% 98.09% | 3764 1.69% 99.78% | 441 0.20% 99.98% | 41 0.02% 100.00% | 3 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 222423 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 165 +system.ruby.L1Cache.hit_mach_latency_hist::samples 207 system.ruby.L1Cache.hit_mach_latency_hist::mean 2 system.ruby.L1Cache.hit_mach_latency_hist::gmean 2.000000 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 165 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 165 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 207 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 207 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 2563 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1189.708545 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 741.796098 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 871.261468 -system.ruby.L1Cache.miss_mach_latency_hist | 782 30.51% 30.51% | 487 19.00% 49.51% | 387 15.10% 64.61% | 376 14.67% 79.28% | 340 13.27% 92.55% | 158 6.16% 98.71% | 29 1.13% 99.84% | 3 0.12% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 2563 +system.ruby.L1Cache.miss_mach_latency_hist::samples 2524 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1216.203645 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 763.649631 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 879.591941 +system.ruby.L1Cache.miss_mach_latency_hist | 755 29.91% 29.91% | 443 17.55% 47.46% | 398 15.77% 63.23% | 388 15.37% 78.61% | 337 13.35% 91.96% | 163 6.46% 98.42% | 35 1.39% 99.80% | 5 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 2524 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 512 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L2Cache.hit_mach_latency_hist::samples 3420 -system.ruby.L2Cache.hit_mach_latency_hist::mean 1257.992398 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 813.419843 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 894.645782 -system.ruby.L2Cache.hit_mach_latency_hist | 1008 29.47% 29.47% | 570 16.67% 46.14% | 519 15.18% 61.32% | 546 15.96% 77.28% | 453 13.25% 90.53% | 259 7.57% 98.10% | 56 1.64% 99.74% | 8 0.23% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 3420 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 1024 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 10239 -system.ruby.Directory.miss_mach_latency_hist::samples 610819 -system.ruby.Directory.miss_mach_latency_hist::mean 1276.811898 -system.ruby.Directory.miss_mach_latency_hist::gmean 908.912119 -system.ruby.Directory.miss_mach_latency_hist::stdev 879.729106 -system.ruby.Directory.miss_mach_latency_hist | 280350 45.90% 45.90% | 186579 30.55% 76.44% | 132716 21.73% 98.17% | 10978 1.80% 99.97% | 195 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 610819 +system.ruby.L2Cache.hit_mach_latency_hist::samples 3280 +system.ruby.L2Cache.hit_mach_latency_hist::mean 1261.496951 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 814.255562 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 901.668484 +system.ruby.L2Cache.hit_mach_latency_hist | 936 28.54% 28.54% | 594 18.11% 46.65% | 495 15.09% 61.74% | 467 14.24% 75.98% | 486 14.82% 90.79% | 230 7.01% 97.80% | 60 1.83% 99.63% | 11 0.34% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 3280 +system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 +system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 +system.ruby.Directory.miss_mach_latency_hist::samples 622228 +system.ruby.Directory.miss_mach_latency_hist::mean 1281.124785 +system.ruby.Directory.miss_mach_latency_hist::gmean 913.497709 +system.ruby.Directory.miss_mach_latency_hist::stdev 881.640047 +system.ruby.Directory.miss_mach_latency_hist | 176341 28.34% 28.34% | 108467 17.43% 45.77% | 92019 14.79% 60.56% | 96759 15.55% 76.11% | 92527 14.87% 90.98% | 44240 7.11% 98.09% | 10470 1.68% 99.77% | 1271 0.20% 99.98% | 120 0.02% 100.00% | 14 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 622228 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 7 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 7 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 4 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 4 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 7 -system.ruby.Directory.miss_latency_hist.initial_to_forward | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 7 +system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 4 +system.ruby.Directory.miss_latency_hist.initial_to_forward | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.initial_to_forward::total 4 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 7 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 7 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 32 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 319 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 7 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 122.714286 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 113.915443 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 50.582323 -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 57.14% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 3 42.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 7 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 4 +system.ruby.Directory.miss_latency_hist.forward_to_first_response | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 4 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 4 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 84.250000 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 83.040125 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 17.211914 +system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 4 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 112 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 139 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 112 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 112 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 139 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 139 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 1608 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1188.308458 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 741.622065 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 867.195204 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 500 31.09% 31.09% | 292 18.16% 49.25% | 245 15.24% 64.49% | 245 15.24% 79.73% | 206 12.81% 92.54% | 98 6.09% 98.63% | 20 1.24% 99.88% | 2 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 1608 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 1645 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1213.688754 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 768.636375 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 877.770074 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 498 30.27% 30.27% | 276 16.78% 47.05% | 273 16.60% 63.65% | 252 15.32% 78.97% | 220 13.37% 92.34% | 99 6.02% 98.36% | 23 1.40% 99.76% | 4 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 1645 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 2213 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1267.732038 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 810.646085 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 901.722652 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 649 29.33% 29.33% | 367 16.58% 45.91% | 331 14.96% 60.87% | 343 15.50% 76.37% | 308 13.92% 90.28% | 177 8.00% 98.28% | 31 1.40% 99.68% | 6 0.27% 99.95% | 1 0.05% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 2213 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 2119 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1265.299670 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 817.259797 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 906.345230 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 608 28.69% 28.69% | 381 17.98% 46.67% | 319 15.05% 61.73% | 286 13.50% 75.22% | 325 15.34% 90.56% | 151 7.13% 97.69% | 42 1.98% 99.67% | 6 0.28% 99.95% | 1 0.05% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 2119 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 397217 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1277.296166 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 908.878022 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 880.086444 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 113186 28.49% 28.49% | 68988 17.37% 45.86% | 58034 14.61% 60.47% | 63360 15.95% 76.42% | 58756 14.79% 91.22% | 27592 6.95% 98.16% | 6147 1.55% 99.71% | 1026 0.26% 99.97% | 108 0.03% 99.99% | 20 0.01% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 397217 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 400684 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1282.297551 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 914.805796 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 881.552049 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 113427 28.31% 28.31% | 69689 17.39% 45.70% | 59303 14.80% 60.50% | 62367 15.57% 76.07% | 59803 14.93% 90.99% | 28456 7.10% 98.09% | 6718 1.68% 99.77% | 831 0.21% 99.98% | 79 0.02% 100.00% | 11 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 400684 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 53 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 68 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 53 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 53 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2.000000 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 68 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 955 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1192.065969 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 742.089221 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 878.516392 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 282 29.53% 29.53% | 195 20.42% 49.95% | 142 14.87% 64.82% | 131 13.72% 78.53% | 134 14.03% 92.57% | 60 6.28% 98.85% | 9 0.94% 99.79% | 1 0.10% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 955 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 879 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1220.910125 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 754.403979 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 883.472744 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 257 29.24% 29.24% | 167 19.00% 48.24% | 125 14.22% 62.46% | 136 15.47% 77.93% | 117 13.31% 91.24% | 64 7.28% 98.52% | 12 1.37% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 879 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 1207 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1240.135046 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 818.530124 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 881.614674 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 359 29.74% 29.74% | 203 16.82% 46.56% | 188 15.58% 62.14% | 203 16.82% 78.96% | 145 12.01% 90.97% | 82 6.79% 97.76% | 25 2.07% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 1207 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 1024 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 10239 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213602 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1275.911349 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 908.975529 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 879.065559 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 98176 45.96% 45.96% | 65185 30.52% 76.48% | 46368 21.71% 98.19% | 3805 1.78% 99.97% | 67 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213602 -system.ruby.L1Cache_Controller.Load | 50331 12.55% 12.55% | 49967 12.46% 25.00% | 50254 12.53% 37.53% | 50183 12.51% 50.04% | 50017 12.47% 62.51% | 50259 12.53% 75.03% | 50136 12.50% 87.53% | 50016 12.47% 100.00% -system.ruby.L1Cache_Controller.Load::total 401163 -system.ruby.L1Cache_Controller.Store | 26960 12.49% 12.49% | 27312 12.65% 25.15% | 26841 12.44% 37.58% | 26622 12.33% 49.92% | 26950 12.49% 62.40% | 27007 12.51% 74.92% | 27203 12.60% 87.52% | 26930 12.48% 100.00% -system.ruby.L1Cache_Controller.Store::total 215825 -system.ruby.L1Cache_Controller.L1_Replacement | 1368057 12.53% 12.53% | 1367643 12.53% 25.06% | 1363908 12.49% 37.56% | 1358410 12.44% 50.00% | 1362554 12.48% 62.48% | 1365525 12.51% 74.99% | 1369124 12.54% 87.53% | 1360777 12.47% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 10915998 -system.ruby.L1Cache_Controller.Data_Shared | 236 13.02% 13.02% | 219 12.09% 25.11% | 237 13.08% 38.19% | 210 11.59% 49.78% | 242 13.36% 63.13% | 233 12.86% 75.99% | 202 11.15% 87.14% | 233 12.86% 100.00% -system.ruby.L1Cache_Controller.Data_Shared::total 1812 -system.ruby.L1Cache_Controller.Data_Owner | 73 15.24% 15.24% | 74 15.45% 30.69% | 52 10.86% 41.54% | 50 10.44% 51.98% | 71 14.82% 66.81% | 66 13.78% 80.58% | 41 8.56% 89.14% | 52 10.86% 100.00% -system.ruby.L1Cache_Controller.Data_Owner::total 479 -system.ruby.L1Cache_Controller.Data_All_Tokens | 80940 12.55% 12.55% | 80743 12.52% 25.06% | 80630 12.50% 37.56% | 80297 12.45% 50.01% | 80401 12.46% 62.47% | 80744 12.52% 74.99% | 80888 12.54% 87.53% | 80464 12.47% 100.00% -system.ruby.L1Cache_Controller.Data_All_Tokens::total 645107 -system.ruby.L1Cache_Controller.Ack | 1 7.14% 7.14% | 0 0.00% 7.14% | 3 21.43% 28.57% | 0 0.00% 28.57% | 3 21.43% 50.00% | 2 14.29% 64.29% | 4 28.57% 92.86% | 1 7.14% 100.00% -system.ruby.L1Cache_Controller.Ack::total 14 -system.ruby.L1Cache_Controller.Ack_All_Tokens | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.Ack_All_Tokens::total 5 -system.ruby.L1Cache_Controller.Transient_Local_GETX | 188823 12.50% 12.50% | 188465 12.48% 24.98% | 188937 12.51% 37.49% | 189155 12.52% 50.01% | 188828 12.50% 62.51% | 188776 12.50% 75.01% | 188573 12.48% 87.50% | 188847 12.50% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1510404 -system.ruby.L1Cache_Controller.Transient_Local_GETS | 350731 12.49% 12.49% | 351096 12.51% 25.00% | 350807 12.50% 37.50% | 350881 12.50% 49.99% | 351048 12.50% 62.50% | 350805 12.50% 74.99% | 350930 12.50% 87.50% | 351050 12.50% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2807348 -system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 2 22.22% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 4 44.44% 77.78% | 0 0.00% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 9 -system.ruby.L1Cache_Controller.Persistent_GETX | 40243 12.48% 12.48% | 40235 12.48% 24.97% | 40237 12.48% 37.45% | 40452 12.55% 50.00% | 40236 12.48% 62.48% | 40319 12.51% 74.99% | 40323 12.51% 87.50% | 40294 12.50% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETX::total 322339 -system.ruby.L1Cache_Controller.Persistent_GETS | 74022 12.51% 12.51% | 73973 12.50% 25.00% | 73853 12.48% 37.48% | 73992 12.50% 49.98% | 74071 12.51% 62.50% | 73914 12.49% 74.99% | 74014 12.51% 87.49% | 74024 12.51% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETS::total 591863 -system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 3 -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 145427 12.50% 12.50% | 145484 12.51% 25.01% | 145601 12.52% 37.52% | 145247 12.49% 50.01% | 145384 12.50% 62.51% | 145459 12.50% 75.01% | 145355 12.49% 87.50% | 145374 12.50% 100.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 1163331 -system.ruby.L1Cache_Controller.Request_Timeout | 60159 12.52% 12.52% | 59656 12.41% 24.93% | 60277 12.54% 37.47% | 60879 12.67% 50.14% | 60010 12.49% 62.63% | 60642 12.62% 75.24% | 60033 12.49% 87.74% | 58941 12.26% 100.00% -system.ruby.L1Cache_Controller.Request_Timeout::total 480597 -system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 5 5.62% 5.62% | 4 4.49% 10.11% | 12 13.48% 23.60% | 11 12.36% 35.96% | 13 14.61% 50.56% | 10 11.24% 61.80% | 18 20.22% 82.02% | 16 17.98% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 89 -system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 6 4.35% 4.35% | 15 10.87% 15.22% | 16 11.59% 26.81% | 13 9.42% 36.23% | 14 10.14% 46.38% | 25 18.12% 64.49% | 24 17.39% 81.88% | 25 18.12% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 138 -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 76982 12.53% 12.53% | 76971 12.53% 25.05% | 76777 12.49% 37.55% | 76512 12.45% 50.00% | 76634 12.47% 62.47% | 76926 12.52% 74.99% | 77048 12.54% 87.53% | 76616 12.47% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 614466 -system.ruby.L1Cache_Controller.NP.Load | 50234 12.54% 12.54% | 49878 12.46% 25.00% | 50162 12.53% 37.53% | 50102 12.51% 50.04% | 49920 12.47% 62.51% | 50179 12.53% 75.04% | 50054 12.50% 87.54% | 49912 12.46% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 400441 -system.ruby.L1Cache_Controller.NP.Store | 26908 12.49% 12.49% | 27274 12.66% 25.15% | 26779 12.43% 37.57% | 26582 12.34% 49.91% | 26907 12.49% 62.40% | 26962 12.51% 74.91% | 27158 12.60% 87.52% | 26896 12.48% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 215466 -system.ruby.L1Cache_Controller.NP.Data_Shared | 15 25.42% 25.42% | 7 11.86% 37.29% | 5 8.47% 45.76% | 4 6.78% 52.54% | 11 18.64% 71.19% | 6 10.17% 81.36% | 6 10.17% 91.53% | 5 8.47% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Shared::total 59 -system.ruby.L1Cache_Controller.NP.Data_Owner | 21 18.26% 18.26% | 15 13.04% 31.30% | 12 10.43% 41.74% | 10 8.70% 50.43% | 18 15.65% 66.09% | 16 13.91% 80.00% | 11 9.57% 89.57% | 12 10.43% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Owner::total 115 -system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 3905 12.91% 12.91% | 3708 12.26% 25.17% | 3801 12.57% 37.73% | 3744 12.38% 50.11% | 3722 12.30% 62.42% | 3775 12.48% 74.90% | 3791 12.53% 87.43% | 3803 12.57% 100.00% -system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 30249 -system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.NP.Ack::total 2 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 188213 12.50% 12.50% | 187862 12.48% 24.98% | 188356 12.51% 37.49% | 188542 12.52% 50.01% | 188229 12.50% 62.52% | 188157 12.50% 75.01% | 187989 12.49% 87.50% | 188206 12.50% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1505554 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 349628 12.49% 12.49% | 349983 12.51% 25.00% | 349669 12.50% 37.50% | 349728 12.50% 49.99% | 349922 12.50% 62.50% | 349655 12.50% 74.99% | 349776 12.50% 87.49% | 349964 12.51% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2798325 -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 126885 12.50% 12.50% | 126871 12.50% 25.00% | 126751 12.49% 37.48% | 126905 12.50% 49.99% | 126881 12.50% 62.49% | 126869 12.50% 74.98% | 126992 12.51% 87.49% | 126955 12.51% 100.00% -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 1015109 -system.ruby.L1Cache_Controller.I.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 1161 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1254.556417 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 808.800824 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 893.416755 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 328 28.25% 28.25% | 213 18.35% 46.60% | 176 15.16% 61.76% | 181 15.59% 77.35% | 161 13.87% 91.21% | 79 6.80% 98.02% | 18 1.55% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 1161 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221544 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1279.003724 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 911.136653 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 881.797207 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 62914 28.40% 28.40% | 38778 17.50% 45.90% | 32716 14.77% 60.67% | 34392 15.52% 76.19% | 32724 14.77% 90.96% | 15784 7.12% 98.09% | 3752 1.69% 99.78% | 440 0.20% 99.98% | 41 0.02% 100.00% | 3 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221544 +system.ruby.L1Cache_Controller.Load | 50657 12.52% 12.52% | 50729 12.54% 25.06% | 50452 12.47% 37.53% | 50277 12.43% 49.95% | 50756 12.54% 62.50% | 50740 12.54% 75.04% | 50491 12.48% 87.52% | 50498 12.48% 100.00% +system.ruby.L1Cache_Controller.Load::total 404600 +system.ruby.L1Cache_Controller.Store | 27739 12.40% 12.40% | 28193 12.61% 25.01% | 27912 12.48% 37.49% | 28134 12.58% 50.07% | 28013 12.52% 62.59% | 27879 12.46% 75.06% | 27895 12.47% 87.53% | 27894 12.47% 100.00% +system.ruby.L1Cache_Controller.Store::total 223659 +system.ruby.L1Cache_Controller.L1_Replacement | 1387935 12.49% 12.49% | 1393411 12.54% 25.03% | 1386651 12.48% 37.51% | 1386696 12.48% 49.99% | 1393529 12.54% 62.54% | 1389740 12.51% 75.04% | 1385760 12.47% 87.52% | 1387026 12.48% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 11110748 +system.ruby.L1Cache_Controller.Data_Shared | 207 12.27% 12.27% | 196 11.62% 23.89% | 225 13.34% 37.23% | 230 13.63% 50.86% | 203 12.03% 62.89% | 226 13.40% 76.29% | 199 11.80% 88.09% | 201 11.91% 100.00% +system.ruby.L1Cache_Controller.Data_Shared::total 1687 +system.ruby.L1Cache_Controller.Data_Owner | 58 12.24% 12.24% | 57 12.03% 24.26% | 63 13.29% 37.55% | 59 12.45% 50.00% | 55 11.60% 61.60% | 73 15.40% 77.00% | 70 14.77% 91.77% | 39 8.23% 100.00% +system.ruby.L1Cache_Controller.Data_Owner::total 474 +system.ruby.L1Cache_Controller.Data_All_Tokens | 81933 12.48% 12.48% | 82456 12.56% 25.04% | 81847 12.47% 37.51% | 81887 12.47% 49.99% | 82319 12.54% 62.53% | 82200 12.52% 75.05% | 81861 12.47% 87.52% | 81912 12.48% 100.00% +system.ruby.L1Cache_Controller.Data_All_Tokens::total 656415 +system.ruby.L1Cache_Controller.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 3 27.27% 54.55% | 0 0.00% 54.55% | 3 27.27% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% +system.ruby.L1Cache_Controller.Ack::total 11 +system.ruby.L1Cache_Controller.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.Ack_All_Tokens::total 3 +system.ruby.L1Cache_Controller.Transient_Local_GETX | 195856 12.51% 12.51% | 195405 12.48% 25.00% | 195686 12.50% 37.50% | 195464 12.49% 49.99% | 195589 12.50% 62.49% | 195721 12.51% 74.99% | 195705 12.50% 87.50% | 195711 12.50% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1565137 +system.ruby.L1Cache_Controller.Transient_Local_GETS | 353824 12.50% 12.50% | 353751 12.49% 24.99% | 354024 12.50% 37.50% | 354198 12.51% 50.01% | 353727 12.49% 62.50% | 353736 12.49% 74.99% | 353985 12.50% 87.50% | 353973 12.50% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2831218 +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 2 +system.ruby.L1Cache_Controller.Persistent_GETX | 41310 12.50% 12.50% | 41193 12.47% 24.97% | 41275 12.49% 37.46% | 41218 12.47% 49.93% | 41337 12.51% 62.44% | 41353 12.51% 74.95% | 41394 12.53% 87.48% | 41368 12.52% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETX::total 330448 +system.ruby.L1Cache_Controller.Persistent_GETS | 75041 12.51% 12.51% | 74960 12.50% 25.02% | 74914 12.49% 37.51% | 75011 12.51% 50.02% | 74765 12.47% 62.49% | 74943 12.50% 74.99% | 74980 12.50% 87.49% | 74997 12.51% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETS::total 599611 +system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 1 +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 147847 12.49% 12.49% | 148045 12.51% 25.00% | 148009 12.51% 37.51% | 147969 12.50% 50.01% | 148096 12.51% 62.52% | 147902 12.50% 75.02% | 147823 12.49% 87.51% | 147833 12.49% 100.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 1183524 +system.ruby.L1Cache_Controller.Request_Timeout | 60198 12.41% 12.41% | 61718 12.72% 25.13% | 61562 12.69% 37.81% | 60908 12.55% 50.36% | 60726 12.51% 62.88% | 60057 12.38% 75.26% | 59803 12.32% 87.58% | 60259 12.42% 100.00% +system.ruby.L1Cache_Controller.Request_Timeout::total 485231 +system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 5 5.38% 5.38% | 4 4.30% 9.68% | 3 3.23% 12.90% | 14 15.05% 27.96% | 17 18.28% 46.24% | 11 11.83% 58.06% | 19 20.43% 78.49% | 20 21.51% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 93 +system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 5 3.27% 3.27% | 6 3.92% 7.19% | 12 7.84% 15.03% | 17 11.11% 26.14% | 23 15.03% 41.18% | 24 15.69% 56.86% | 34 22.22% 79.08% | 32 20.92% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 153 +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78118 12.48% 12.48% | 78650 12.57% 25.05% | 78056 12.47% 37.52% | 78094 12.48% 50.00% | 78456 12.54% 62.54% | 78284 12.51% 75.05% | 78056 12.47% 87.52% | 78078 12.48% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 625792 +system.ruby.L1Cache_Controller.NP.Load | 50564 12.52% 12.52% | 50644 12.54% 25.06% | 50367 12.47% 37.53% | 50194 12.43% 49.96% | 50652 12.54% 62.50% | 50646 12.54% 75.04% | 50410 12.48% 87.52% | 50414 12.48% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 403891 +system.ruby.L1Cache_Controller.NP.Store | 27691 12.40% 12.40% | 28155 12.61% 25.01% | 27877 12.48% 37.50% | 28080 12.58% 50.07% | 27961 12.52% 62.59% | 27826 12.46% 75.06% | 27849 12.47% 87.53% | 27846 12.47% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 223285 +system.ruby.L1Cache_Controller.NP.Data_Shared | 8 14.55% 14.55% | 8 14.55% 29.09% | 9 16.36% 45.45% | 10 18.18% 63.64% | 8 14.55% 78.18% | 8 14.55% 92.73% | 3 5.45% 98.18% | 1 1.82% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Shared::total 55 +system.ruby.L1Cache_Controller.NP.Data_Owner | 15 13.39% 13.39% | 13 11.61% 25.00% | 11 9.82% 34.82% | 17 15.18% 50.00% | 14 12.50% 62.50% | 19 16.96% 79.46% | 17 15.18% 94.64% | 6 5.36% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Owner::total 112 +system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 3770 12.48% 12.48% | 3762 12.45% 24.92% | 3754 12.42% 37.35% | 3737 12.37% 49.71% | 3801 12.58% 62.29% | 3871 12.81% 75.10% | 3746 12.40% 87.50% | 3778 12.50% 100.00% +system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 30219 +system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 2 40.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.NP.Ack::total 5 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 195270 12.52% 12.52% | 194792 12.48% 25.00% | 195065 12.50% 37.50% | 194859 12.49% 49.99% | 194966 12.50% 62.49% | 195149 12.51% 74.99% | 195088 12.50% 87.50% | 195074 12.50% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1560263 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 352736 12.50% 12.50% | 352665 12.50% 24.99% | 352880 12.50% 37.50% | 353067 12.51% 50.01% | 352630 12.49% 62.50% | 352652 12.50% 75.00% | 352848 12.50% 87.50% | 352851 12.50% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2822329 +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 129129 12.50% 12.50% | 129222 12.51% 25.01% | 129019 12.49% 37.50% | 129118 12.50% 50.00% | 129094 12.50% 62.50% | 129148 12.50% 75.00% | 129162 12.50% 87.51% | 129056 12.49% 100.00% +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 1032948 +system.ruby.L1Cache_Controller.I.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.I.Load::total 1 -system.ruby.L1Cache_Controller.I.L1_Replacement | 183 13.13% 13.13% | 170 12.20% 25.32% | 174 12.48% 37.80% | 180 12.91% 50.72% | 173 12.41% 63.13% | 164 11.76% 74.89% | 159 11.41% 86.30% | 191 13.70% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 1394 -system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 3 -system.ruby.L1Cache_Controller.I.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement | 158 11.47% 11.47% | 153 11.10% 22.57% | 166 12.05% 34.62% | 174 12.63% 47.24% | 189 13.72% 60.96% | 170 12.34% 73.29% | 173 12.55% 85.85% | 195 14.15% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 1378 +system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 4 +system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 1 +system.ruby.L1Cache_Controller.I.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.I.Persistent_GETX::total 1 -system.ruby.L1Cache_Controller.I.Persistent_GETS | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Persistent_GETS::total 3 -system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock::total 2 -system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1 -system.ruby.L1Cache_Controller.S.L1_Replacement | 249 11.95% 11.95% | 252 12.09% 24.04% | 274 13.15% 37.19% | 244 11.71% 48.90% | 272 13.05% 61.95% | 281 13.48% 75.43% | 241 11.56% 87.00% | 271 13.00% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 2084 -system.ruby.L1Cache_Controller.S.Data_Shared | 1 20.00% 20.00% | 0 0.00% 20.00% | 2 40.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.I.Persistent_GETS | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Persistent_GETS::total 1 +system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 2 40.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock::total 5 +system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 2 +system.ruby.L1Cache_Controller.S.L1_Replacement | 239 12.11% 12.11% | 233 11.80% 23.91% | 265 13.42% 37.34% | 258 13.07% 50.41% | 244 12.36% 62.77% | 250 12.66% 75.43% | 244 12.36% 87.79% | 241 12.21% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1974 +system.ruby.L1Cache_Controller.S.Data_Shared | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Data_Shared::total 5 -system.ruby.L1Cache_Controller.S.Data_All_Tokens | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 1 -system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 1 12.50% 12.50% | 2 25.00% 37.50% | 1 12.50% 50.00% | 1 12.50% 62.50% | 2 25.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 8 -system.ruby.L1Cache_Controller.S.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 2 50.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 4 +system.ruby.L1Cache_Controller.S.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Transient_Local_GETS::total 1 -system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 2 22.22% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 4 44.44% 77.78% | 0 0.00% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 9 -system.ruby.L1Cache_Controller.S.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETX::total 1 -system.ruby.L1Cache_Controller.S.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETS::total 2 -system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 3 -system.ruby.L1Cache_Controller.O.L1_Replacement | 133 13.05% 13.05% | 127 12.46% 25.52% | 116 11.38% 36.90% | 134 13.15% 50.05% | 132 12.95% 63.00% | 145 14.23% 77.23% | 111 10.89% 88.13% | 121 11.87% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 1019 -system.ruby.L1Cache_Controller.O.Data_All_Tokens | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 2 +system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 1 +system.ruby.L1Cache_Controller.O.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Load::total 1 +system.ruby.L1Cache_Controller.O.L1_Replacement | 124 12.44% 12.44% | 120 12.04% 24.47% | 135 13.54% 38.01% | 119 11.94% 49.95% | 122 12.24% 62.19% | 121 12.14% 74.32% | 138 13.84% 88.16% | 118 11.84% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 997 +system.ruby.L1Cache_Controller.O.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 2 -system.ruby.L1Cache_Controller.O.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Ack_All_Tokens::total 1 -system.ruby.L1Cache_Controller.O.Transient_Local_GETX | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Transient_Local_GETX::total 2 -system.ruby.L1Cache_Controller.O.Persistent_GETS | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Persistent_GETS::total 2 -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 12 12.24% 12.24% | 15 15.31% 27.55% | 17 17.35% 44.90% | 13 13.27% 58.16% | 12 12.24% 70.41% | 13 13.27% 83.67% | 10 10.20% 93.88% | 6 6.12% 100.00% -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 98 -system.ruby.L1Cache_Controller.M.Load | 5 12.20% 12.20% | 2 4.88% 17.07% | 3 7.32% 24.39% | 5 12.20% 36.59% | 5 12.20% 48.78% | 3 7.32% 56.10% | 8 19.51% 75.61% | 10 24.39% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 41 -system.ruby.L1Cache_Controller.M.Store | 3 14.29% 14.29% | 2 9.52% 23.81% | 5 23.81% 47.62% | 4 19.05% 66.67% | 3 14.29% 80.95% | 4 19.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 21 -system.ruby.L1Cache_Controller.M.L1_Replacement | 49847 12.55% 12.55% | 49500 12.46% 25.00% | 49774 12.53% 37.53% | 49713 12.51% 50.04% | 49519 12.46% 62.51% | 49733 12.52% 75.03% | 49702 12.51% 87.53% | 49527 12.47% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 397315 -system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 50 13.62% 13.62% | 36 9.81% 23.43% | 52 14.17% 37.60% | 40 10.90% 48.50% | 46 12.53% 61.04% | 55 14.99% 76.02% | 33 8.99% 85.01% | 55 14.99% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 367 -system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 83 12.44% 12.44% | 71 10.64% 23.09% | 76 11.39% 34.48% | 96 14.39% 48.88% | 80 11.99% 60.87% | 96 14.39% 75.26% | 81 12.14% 87.41% | 84 12.59% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 667 -system.ruby.L1Cache_Controller.M.Persistent_GETX | 25 16.78% 16.78% | 26 17.45% 34.23% | 14 9.40% 43.62% | 21 14.09% 57.72% | 21 14.09% 71.81% | 13 8.72% 80.54% | 18 12.08% 92.62% | 11 7.38% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETX::total 149 -system.ruby.L1Cache_Controller.M.Persistent_GETS | 27 10.63% 10.63% | 31 12.20% 22.83% | 33 12.99% 35.83% | 32 12.60% 48.43% | 36 14.17% 62.60% | 38 14.96% 77.56% | 28 11.02% 88.58% | 29 11.42% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETS::total 254 -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 1187 12.24% 12.24% | 1229 12.68% 24.92% | 1293 13.34% 38.25% | 1200 12.38% 50.63% | 1221 12.59% 63.22% | 1249 12.88% 76.10% | 1131 11.66% 87.77% | 1186 12.23% 100.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 9696 -system.ruby.L1Cache_Controller.MM.Load | 1 4.17% 4.17% | 5 20.83% 25.00% | 2 8.33% 33.33% | 7 29.17% 62.50% | 3 12.50% 75.00% | 2 8.33% 83.33% | 3 12.50% 95.83% | 1 4.17% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 24 -system.ruby.L1Cache_Controller.MM.Store | 5 33.33% 33.33% | 1 6.67% 40.00% | 1 6.67% 46.67% | 1 6.67% 53.33% | 0 0.00% 53.33% | 3 20.00% 73.33% | 1 6.67% 80.00% | 3 20.00% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 15 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 26851 12.49% 12.49% | 27209 12.66% 25.15% | 26736 12.44% 37.58% | 26508 12.33% 49.91% | 26847 12.49% 62.40% | 26914 12.52% 74.92% | 27102 12.61% 87.53% | 26811 12.47% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 214978 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 31 14.76% 14.76% | 33 15.71% 30.48% | 27 12.86% 43.33% | 28 13.33% 56.67% | 17 8.10% 64.76% | 21 10.00% 74.76% | 25 11.90% 86.67% | 28 13.33% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 210 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 45 14.11% 14.11% | 36 11.29% 25.39% | 37 11.60% 36.99% | 41 12.85% 49.84% | 49 15.36% 65.20% | 33 10.34% 75.55% | 36 11.29% 86.83% | 42 13.17% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 319 -system.ruby.L1Cache_Controller.MM.Persistent_GETX | 11 13.10% 13.10% | 11 13.10% 26.19% | 10 11.90% 38.10% | 17 20.24% 58.33% | 10 11.90% 70.24% | 10 11.90% 82.14% | 8 9.52% 91.67% | 7 8.33% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 84 -system.ruby.L1Cache_Controller.MM.Persistent_GETS | 12 10.17% 10.17% | 17 14.41% 24.58% | 17 14.41% 38.98% | 14 11.86% 50.85% | 9 7.63% 58.47% | 12 10.17% 68.64% | 15 12.71% 81.36% | 22 18.64% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 118 -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 712 13.37% 13.37% | 667 12.52% 25.89% | 685 12.86% 38.75% | 670 12.58% 51.32% | 668 12.54% 63.86% | 648 12.16% 76.03% | 636 11.94% 87.97% | 641 12.03% 100.00% -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 5327 -system.ruby.L1Cache_Controller.M_W.Load | 2 7.14% 7.14% | 4 14.29% 21.43% | 5 17.86% 39.29% | 3 10.71% 50.00% | 3 10.71% 60.71% | 4 14.29% 75.00% | 3 10.71% 85.71% | 4 14.29% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 28 -system.ruby.L1Cache_Controller.M_W.Store | 1 11.11% 11.11% | 2 22.22% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 11.11% 44.44% | 2 22.22% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 9 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 291266 12.59% 12.59% | 289622 12.52% 25.11% | 289644 12.52% 37.63% | 290259 12.55% 50.18% | 288045 12.45% 62.63% | 288216 12.46% 75.09% | 288197 12.46% 87.55% | 287895 12.45% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2313144 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 42 14.38% 14.38% | 27 9.25% 23.63% | 30 10.27% 33.90% | 37 12.67% 46.58% | 39 13.36% 59.93% | 45 15.41% 75.34% | 33 11.30% 86.64% | 39 13.36% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 292 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 66 11.60% 11.60% | 79 13.88% 25.48% | 75 13.18% 38.66% | 88 15.47% 54.13% | 63 11.07% 65.20% | 60 10.54% 75.75% | 78 13.71% 89.46% | 60 10.54% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 569 -system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 3 7.14% 7.14% | 4 9.52% 16.67% | 4 9.52% 26.19% | 5 11.90% 38.10% | 4 9.52% 47.62% | 6 14.29% 61.90% | 8 19.05% 80.95% | 8 19.05% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 42 -system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 5 5.88% 5.88% | 11 12.94% 18.82% | 11 12.94% 31.76% | 4 4.71% 36.47% | 7 8.24% 44.71% | 15 17.65% 62.35% | 15 17.65% 80.00% | 17 20.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 85 -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 469 12.17% 12.17% | 479 12.43% 24.60% | 514 13.34% 37.94% | 489 12.69% 50.64% | 496 12.87% 63.51% | 466 12.09% 75.60% | 481 12.48% 88.09% | 459 11.91% 100.00% -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3853 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 4 7.69% 7.69% | 4 7.69% 15.38% | 5 9.62% 25.00% | 6 11.54% 36.54% | 5 9.62% 46.15% | 7 13.46% 59.62% | 11 21.15% 80.77% | 10 19.23% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 52 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 5 5.38% 5.38% | 11 11.83% 17.20% | 12 12.90% 30.11% | 6 6.45% 36.56% | 8 8.60% 45.16% | 17 18.28% 63.44% | 17 18.28% 81.72% | 17 18.28% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 93 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50035 12.55% 12.55% | 49666 12.45% 25.00% | 49954 12.53% 37.53% | 49907 12.52% 50.04% | 49705 12.46% 62.51% | 49940 12.52% 75.03% | 49862 12.50% 87.54% | 49706 12.46% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 398775 -system.ruby.L1Cache_Controller.MM_W.Load | 5 27.78% 27.78% | 1 5.56% 33.33% | 0 0.00% 33.33% | 2 11.11% 44.44% | 3 16.67% 61.11% | 5 27.78% 88.89% | 1 5.56% 94.44% | 1 5.56% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 18 -system.ruby.L1Cache_Controller.MM_W.Store | 2 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 8 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 155942 12.48% 12.48% | 158074 12.65% 25.12% | 153918 12.31% 37.44% | 152634 12.21% 49.65% | 158304 12.67% 62.32% | 157087 12.57% 74.89% | 158031 12.64% 87.53% | 155857 12.47% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1249847 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 23 13.07% 13.07% | 18 10.23% 23.30% | 18 10.23% 33.52% | 26 14.77% 48.30% | 23 13.07% 61.36% | 21 11.93% 73.30% | 20 11.36% 84.66% | 27 15.34% 100.00% +system.ruby.L1Cache_Controller.O.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Ack::total 1 +system.ruby.L1Cache_Controller.O.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETX::total 1 +system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 2 +system.ruby.L1Cache_Controller.O.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Persistent_GETX::total 1 +system.ruby.L1Cache_Controller.O.Persistent_GETS | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Persistent_GETS::total 4 +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 15 17.44% 17.44% | 11 12.79% 30.23% | 13 15.12% 45.35% | 9 10.47% 55.81% | 10 11.63% 67.44% | 9 10.47% 77.91% | 12 13.95% 91.86% | 7 8.14% 100.00% +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 86 +system.ruby.L1Cache_Controller.M.Load | 6 12.00% 12.00% | 9 18.00% 30.00% | 5 10.00% 40.00% | 4 8.00% 48.00% | 8 16.00% 64.00% | 8 16.00% 80.00% | 4 8.00% 88.00% | 6 12.00% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 50 +system.ruby.L1Cache_Controller.M.Store | 2 8.00% 8.00% | 4 16.00% 24.00% | 2 8.00% 32.00% | 3 12.00% 44.00% | 5 20.00% 64.00% | 4 16.00% 80.00% | 3 12.00% 92.00% | 2 8.00% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 25 +system.ruby.L1Cache_Controller.M.L1_Replacement | 50210 12.52% 12.52% | 50284 12.54% 25.07% | 49968 12.46% 37.53% | 49814 12.43% 49.96% | 50283 12.54% 62.50% | 50284 12.54% 75.04% | 50007 12.47% 87.52% | 50037 12.48% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 400887 +system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 39 11.82% 11.82% | 40 12.12% 23.94% | 47 14.24% 38.18% | 39 11.82% 50.00% | 45 13.64% 63.64% | 36 10.91% 74.55% | 38 11.52% 86.06% | 46 13.94% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 330 +system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 83 12.85% 12.85% | 77 11.92% 24.77% | 83 12.85% 37.62% | 79 12.23% 49.85% | 84 13.00% 62.85% | 67 10.37% 73.22% | 86 13.31% 86.53% | 87 13.47% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 646 +system.ruby.L1Cache_Controller.M.Persistent_GETX | 15 11.03% 11.03% | 18 13.24% 24.26% | 14 10.29% 34.56% | 16 11.76% 46.32% | 19 13.97% 60.29% | 16 11.76% 72.06% | 22 16.18% 88.24% | 16 11.76% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETX::total 136 +system.ruby.L1Cache_Controller.M.Persistent_GETS | 38 15.08% 15.08% | 40 15.87% 30.95% | 41 16.27% 47.22% | 32 12.70% 59.92% | 32 12.70% 72.62% | 20 7.94% 80.56% | 26 10.32% 90.87% | 23 9.13% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETS::total 252 +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 1217 12.47% 12.47% | 1156 11.84% 24.31% | 1266 12.97% 37.28% | 1220 12.50% 49.77% | 1200 12.29% 62.07% | 1226 12.56% 74.63% | 1208 12.37% 87.00% | 1269 13.00% 100.00% +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 9762 +system.ruby.L1Cache_Controller.MM.Load | 5 19.23% 19.23% | 2 7.69% 26.92% | 2 7.69% 34.62% | 1 3.85% 38.46% | 10 38.46% 76.92% | 1 3.85% 80.77% | 2 7.69% 88.46% | 3 11.54% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 26 +system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 21.43% 21.43% | 3 21.43% 42.86% | 1 7.14% 50.00% | 2 14.29% 64.29% | 2 14.29% 78.57% | 3 21.43% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 14 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 27637 12.41% 12.41% | 28101 12.61% 25.02% | 27803 12.48% 37.50% | 28019 12.58% 50.08% | 27893 12.52% 62.60% | 27764 12.46% 75.06% | 27795 12.48% 87.53% | 27771 12.47% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222783 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 21 11.41% 11.41% | 15 8.15% 19.57% | 28 15.22% 34.78% | 22 11.96% 46.74% | 31 16.85% 63.59% | 26 14.13% 77.72% | 23 12.50% 90.22% | 18 9.78% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 184 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 48 13.11% 13.11% | 42 11.48% 24.59% | 44 12.02% 36.61% | 47 12.84% 49.45% | 43 11.75% 61.20% | 48 13.11% 74.32% | 41 11.20% 85.52% | 53 14.48% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 366 +system.ruby.L1Cache_Controller.MM.Persistent_GETX | 10 13.89% 13.89% | 10 13.89% 27.78% | 9 12.50% 40.28% | 8 11.11% 51.39% | 10 13.89% 65.28% | 7 9.72% 75.00% | 6 8.33% 83.33% | 12 16.67% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 72 +system.ruby.L1Cache_Controller.MM.Persistent_GETS | 17 12.59% 12.59% | 22 16.30% 28.89% | 17 12.59% 41.48% | 19 14.07% 55.56% | 16 11.85% 67.41% | 16 11.85% 79.26% | 13 9.63% 88.89% | 15 11.11% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 135 +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 653 12.24% 12.24% | 657 12.31% 24.55% | 734 13.75% 38.30% | 664 12.44% 50.74% | 685 12.83% 63.58% | 640 11.99% 75.57% | 621 11.64% 87.20% | 683 12.80% 100.00% +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 5337 +system.ruby.L1Cache_Controller.M_W.Load | 6 17.14% 17.14% | 4 11.43% 28.57% | 4 11.43% 40.00% | 6 17.14% 57.14% | 3 8.57% 65.71% | 6 17.14% 82.86% | 4 11.43% 94.29% | 2 5.71% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 35 +system.ruby.L1Cache_Controller.M_W.Store | 1 5.26% 5.26% | 2 10.53% 15.79% | 2 10.53% 26.32% | 1 5.26% 31.58% | 3 15.79% 47.37% | 2 10.53% 57.89% | 2 10.53% 68.42% | 6 31.58% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 19 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 292424 12.54% 12.54% | 289923 12.43% 24.97% | 291806 12.51% 37.49% | 287812 12.34% 49.83% | 293129 12.57% 62.40% | 292944 12.56% 74.96% | 290472 12.46% 87.41% | 293489 12.59% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2331999 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 53 17.04% 17.04% | 43 13.83% 30.87% | 36 11.58% 42.44% | 43 13.83% 56.27% | 38 12.22% 68.49% | 29 9.32% 77.81% | 25 8.04% 85.85% | 44 14.15% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 311 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 63 12.07% 12.07% | 49 9.39% 21.46% | 78 14.94% 36.40% | 71 13.60% 50.00% | 59 11.30% 61.30% | 70 13.41% 74.71% | 71 13.60% 88.31% | 61 11.69% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 522 +system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 3 5.36% 5.36% | 3 5.36% 10.71% | 1 1.79% 12.50% | 8 14.29% 26.79% | 7 12.50% 39.29% | 4 7.14% 46.43% | 16 28.57% 75.00% | 14 25.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 56 +system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 3 3.45% 3.45% | 5 5.75% 9.20% | 6 6.90% 16.09% | 7 8.05% 24.14% | 14 16.09% 40.23% | 13 14.94% 55.17% | 21 24.14% 79.31% | 18 20.69% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 87 +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 494 12.81% 12.81% | 485 12.58% 25.39% | 490 12.71% 38.10% | 468 12.14% 50.23% | 495 12.84% 63.07% | 487 12.63% 75.70% | 488 12.66% 88.36% | 449 11.64% 100.00% +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3856 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 3 4.92% 4.92% | 3 4.92% 9.84% | 1 1.64% 11.48% | 9 14.75% 26.23% | 8 13.11% 39.34% | 6 9.84% 49.18% | 17 27.87% 77.05% | 14 22.95% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 61 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 3 3.00% 3.00% | 5 5.00% 8.00% | 8 8.00% 16.00% | 8 8.00% 24.00% | 16 16.00% 40.00% | 15 15.00% 55.00% | 24 24.00% 79.00% | 21 21.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 100 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50387 12.53% 12.53% | 50464 12.54% 25.07% | 50156 12.47% 37.54% | 49982 12.42% 49.96% | 50468 12.55% 62.51% | 50427 12.54% 75.04% | 50181 12.47% 87.52% | 50211 12.48% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 402276 +system.ruby.L1Cache_Controller.MM_W.Load | 3 12.00% 12.00% | 4 16.00% 28.00% | 4 16.00% 44.00% | 4 16.00% 60.00% | 1 4.00% 64.00% | 2 8.00% 72.00% | 6 24.00% 96.00% | 1 4.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 25 +system.ruby.L1Cache_Controller.MM_W.Store | 1 10.00% 10.00% | 1 10.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 2 20.00% 40.00% | 1 10.00% 50.00% | 2 20.00% 70.00% | 3 30.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 10 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 161716 12.53% 12.53% | 161272 12.49% 25.02% | 160842 12.46% 37.48% | 163936 12.70% 50.18% | 160722 12.45% 62.63% | 161511 12.51% 75.15% | 160578 12.44% 87.59% | 160236 12.41% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1290813 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 24 13.64% 13.64% | 26 14.77% 28.41% | 25 14.20% 42.61% | 16 9.09% 51.70% | 22 12.50% 64.20% | 17 9.66% 73.86% | 13 7.39% 81.25% | 33 18.75% 100.00% system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 176 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 30 9.71% 9.71% | 45 14.56% 24.27% | 31 10.03% 34.30% | 43 13.92% 48.22% | 33 10.68% 58.90% | 40 12.94% 71.84% | 44 14.24% 86.08% | 43 13.92% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 309 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 1 3.03% 3.03% | 0 0.00% 3.03% | 6 18.18% 21.21% | 4 12.12% 33.33% | 7 21.21% 54.55% | 2 6.06% 60.61% | 7 21.21% 81.82% | 6 18.18% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 33 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 1 2.38% 2.38% | 3 7.14% 9.52% | 3 7.14% 16.67% | 7 16.67% 33.33% | 6 14.29% 47.62% | 7 16.67% 64.29% | 7 16.67% 80.95% | 8 19.05% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 42 -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 292 13.90% 13.90% | 270 12.85% 26.75% | 253 12.04% 38.79% | 231 10.99% 49.79% | 270 12.85% 62.64% | 272 12.95% 75.58% | 278 13.23% 88.81% | 235 11.19% 100.00% -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 2101 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 1 2.70% 2.70% | 0 0.00% 2.70% | 7 18.92% 21.62% | 5 13.51% 35.14% | 8 21.62% 56.76% | 3 8.11% 64.86% | 7 18.92% 83.78% | 6 16.22% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 37 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 1 2.22% 2.22% | 4 8.89% 11.11% | 4 8.89% 20.00% | 7 15.56% 35.56% | 6 13.33% 48.89% | 8 17.78% 66.67% | 7 15.56% 82.22% | 8 17.78% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 45 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 26947 12.49% 12.49% | 27305 12.66% 25.15% | 26823 12.44% 37.59% | 26605 12.33% 49.92% | 26929 12.48% 62.41% | 26986 12.51% 74.92% | 27186 12.60% 87.52% | 26910 12.48% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 215691 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 293340 12.49% 12.49% | 295809 12.59% 25.08% | 291989 12.43% 37.52% | 287885 12.26% 49.77% | 295320 12.57% 62.35% | 295503 12.58% 74.93% | 296204 12.61% 87.54% | 292704 12.46% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2348754 -system.ruby.L1Cache_Controller.IM.Data_Owner | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00% -system.ruby.L1Cache_Controller.IM.Data_Owner::total 5 -system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 26946 12.49% 12.49% | 27305 12.66% 25.15% | 26829 12.44% 37.58% | 26615 12.34% 49.92% | 26941 12.49% 62.40% | 26992 12.51% 74.92% | 27198 12.61% 87.52% | 26921 12.48% 100.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 215747 -system.ruby.L1Cache_Controller.IM.Ack | 1 10.00% 10.00% | 0 0.00% 10.00% | 1 10.00% 20.00% | 0 0.00% 20.00% | 2 20.00% 40.00% | 2 20.00% 60.00% | 3 30.00% 90.00% | 1 10.00% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 10 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 90 12.45% 12.45% | 84 11.62% 24.07% | 90 12.45% 36.51% | 94 13.00% 49.52% | 93 12.86% 62.38% | 87 12.03% 74.41% | 89 12.31% 86.72% | 96 13.28% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 723 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 147 11.89% 11.89% | 144 11.65% 23.54% | 177 14.32% 37.86% | 153 12.38% 50.24% | 146 11.81% 62.06% | 154 12.46% 74.51% | 150 12.14% 86.65% | 165 13.35% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1236 -system.ruby.L1Cache_Controller.IM.Persistent_GETX | 29 14.15% 14.15% | 27 13.17% 27.32% | 22 10.73% 38.05% | 27 13.17% 51.22% | 26 12.68% 63.90% | 33 16.10% 80.00% | 22 10.73% 90.73% | 19 9.27% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 205 -system.ruby.L1Cache_Controller.IM.Persistent_GETS | 36 9.28% 9.28% | 39 10.05% 19.33% | 50 12.89% 32.22% | 42 10.82% 43.04% | 48 12.37% 55.41% | 53 13.66% 69.07% | 57 14.69% 83.76% | 63 16.24% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 388 -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 5483 12.57% 12.57% | 5506 12.62% 25.19% | 5529 12.68% 37.87% | 5327 12.21% 50.08% | 5492 12.59% 62.67% | 5408 12.40% 75.07% | 5402 12.38% 87.46% | 5471 12.54% 100.00% -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 43618 -system.ruby.L1Cache_Controller.IM.Request_Timeout | 20923 12.52% 12.52% | 21057 12.60% 25.13% | 21290 12.74% 37.87% | 20719 12.40% 50.27% | 21245 12.72% 62.99% | 21018 12.58% 75.57% | 20732 12.41% 87.98% | 20087 12.02% 100.00% -system.ruby.L1Cache_Controller.IM.Request_Timeout::total 167071 -system.ruby.L1Cache_Controller.OM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement::total 1 -system.ruby.L1Cache_Controller.OM.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.OM.Data_All_Tokens::total 1 -system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% -system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total 4 -system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock::total 1 -system.ruby.L1Cache_Controller.OM.Request_Timeout | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Request_Timeout::total 1 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 548020 12.55% 12.55% | 544678 12.47% 25.02% | 548767 12.57% 37.58% | 548504 12.56% 50.14% | 541488 12.40% 62.54% | 544959 12.48% 75.02% | 546694 12.52% 87.54% | 544234 12.46% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4367344 -system.ruby.L1Cache_Controller.IS.Data_Shared | 219 12.55% 12.55% | 212 12.15% 24.70% | 230 13.18% 37.88% | 206 11.81% 49.68% | 230 13.18% 62.87% | 226 12.95% 75.82% | 196 11.23% 87.05% | 226 12.95% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Shared::total 1745 -system.ruby.L1Cache_Controller.IS.Data_Owner | 51 14.21% 14.21% | 58 16.16% 30.36% | 40 11.14% 41.50% | 39 10.86% 52.37% | 53 14.76% 67.13% | 50 13.93% 81.06% | 30 8.36% 89.42% | 38 10.58% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 30 10.53% 10.53% | 33 11.58% 22.11% | 43 15.09% 37.19% | 30 10.53% 47.72% | 32 11.23% 58.95% | 41 14.39% 73.33% | 38 13.33% 86.67% | 38 13.33% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 285 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 2 6.67% 6.67% | 1 3.33% 10.00% | 1 3.33% 13.33% | 4 13.33% 26.67% | 9 30.00% 56.67% | 5 16.67% 73.33% | 2 6.67% 80.00% | 6 20.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 30 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 2 4.17% 4.17% | 1 2.08% 6.25% | 4 8.33% 14.58% | 9 18.75% 33.33% | 6 12.50% 45.83% | 9 18.75% 64.58% | 8 16.67% 81.25% | 9 18.75% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 48 +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 275 12.91% 12.91% | 284 13.33% 26.24% | 284 13.33% 39.58% | 295 13.85% 53.43% | 247 11.60% 65.02% | 261 12.25% 77.28% | 232 10.89% 88.17% | 252 11.83% 100.00% +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 2130 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 2 6.25% 6.25% | 1 3.12% 9.38% | 2 6.25% 15.62% | 5 15.62% 31.25% | 9 28.12% 59.38% | 5 15.62% 75.00% | 2 6.25% 81.25% | 6 18.75% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 32 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 2 3.77% 3.77% | 1 1.89% 5.66% | 4 7.55% 13.21% | 9 16.98% 30.19% | 7 13.21% 43.40% | 9 16.98% 60.38% | 10 18.87% 79.25% | 11 20.75% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 53 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 27731 12.41% 12.41% | 28186 12.61% 25.02% | 27900 12.48% 37.50% | 28112 12.58% 50.08% | 27988 12.52% 62.60% | 27857 12.46% 75.06% | 27875 12.47% 87.53% | 27867 12.47% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223516 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 300828 12.38% 12.38% | 309296 12.73% 25.11% | 302781 12.46% 37.57% | 307942 12.67% 50.24% | 302491 12.45% 62.69% | 302723 12.46% 75.15% | 301437 12.41% 87.55% | 302449 12.45% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2429947 +system.ruby.L1Cache_Controller.IM.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.IM.Data_Owner::total 3 +system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 27732 12.40% 12.40% | 28185 12.61% 25.01% | 27903 12.48% 37.49% | 28123 12.58% 50.07% | 28000 12.52% 62.59% | 27869 12.47% 75.06% | 27883 12.47% 87.53% | 27875 12.47% 100.00% +system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223570 +system.ruby.L1Cache_Controller.IM.Ack | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 5 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 72 10.26% 10.26% | 91 12.96% 23.22% | 90 12.82% 36.04% | 89 12.68% 48.72% | 97 13.82% 62.54% | 87 12.39% 74.93% | 93 13.25% 88.18% | 83 11.82% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 702 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 151 11.48% 11.48% | 171 13.00% 24.49% | 164 12.47% 36.96% | 175 13.31% 50.27% | 155 11.79% 62.05% | 156 11.86% 73.92% | 166 12.62% 86.54% | 177 13.46% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1315 +system.ruby.L1Cache_Controller.IM.Persistent_GETX | 27 10.47% 10.47% | 29 11.24% 21.71% | 37 14.34% 36.05% | 28 10.85% 46.90% | 40 15.50% 62.40% | 29 11.24% 73.64% | 34 13.18% 86.82% | 34 13.18% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 258 +system.ruby.L1Cache_Controller.IM.Persistent_GETS | 49 11.75% 11.75% | 35 8.39% 20.14% | 45 10.79% 30.94% | 52 12.47% 43.41% | 51 12.23% 55.64% | 70 16.79% 72.42% | 58 13.91% 86.33% | 57 13.67% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 417 +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 5586 12.50% 12.50% | 5689 12.73% 25.22% | 5604 12.54% 37.76% | 5653 12.65% 50.40% | 5575 12.47% 62.87% | 5536 12.38% 75.26% | 5523 12.35% 87.61% | 5538 12.39% 100.00% +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 44704 +system.ruby.L1Cache_Controller.IM.Request_Timeout | 20724 12.08% 12.08% | 21868 12.75% 24.83% | 21815 12.72% 37.55% | 21448 12.50% 50.05% | 21768 12.69% 62.74% | 21311 12.42% 75.16% | 21334 12.44% 87.60% | 21268 12.40% 100.00% +system.ruby.L1Cache_Controller.IM.Request_Timeout::total 171536 +system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total 3 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 552820 12.53% 12.53% | 551947 12.51% 25.05% | 550867 12.49% 37.54% | 546383 12.39% 49.92% | 555966 12.60% 62.53% | 551042 12.49% 75.02% | 551994 12.51% 87.54% | 549743 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4410762 +system.ruby.L1Cache_Controller.IS.Data_Shared | 197 12.14% 12.14% | 187 11.52% 23.66% | 216 13.31% 36.97% | 219 13.49% 50.46% | 195 12.01% 62.48% | 215 13.25% 75.72% | 195 12.01% 87.74% | 199 12.26% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Shared::total 1623 +system.ruby.L1Cache_Controller.IS.Data_Owner | 43 11.98% 11.98% | 44 12.26% 24.23% | 52 14.48% 38.72% | 40 11.14% 49.86% | 41 11.42% 61.28% | 54 15.04% 76.32% | 53 14.76% 91.09% | 32 8.91% 100.00% system.ruby.L1Cache_Controller.IS.Data_Owner::total 359 -system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50045 12.55% 12.55% | 49683 12.45% 25.00% | 49970 12.53% 37.53% | 49916 12.51% 50.04% | 49717 12.46% 62.50% | 49963 12.52% 75.03% | 49887 12.51% 87.53% | 49732 12.47% 100.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 398913 -system.ruby.L1Cache_Controller.IS.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS.Ack::total 2 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 152 12.13% 12.13% | 168 13.41% 25.54% | 140 11.17% 36.71% | 160 12.77% 49.48% | 153 12.21% 61.69% | 161 12.85% 74.54% | 153 12.21% 86.75% | 166 13.25% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1253 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 287 12.04% 12.04% | 298 12.50% 24.54% | 300 12.58% 37.12% | 291 12.21% 49.33% | 322 13.51% 62.84% | 311 13.05% 75.88% | 302 12.67% 88.55% | 273 11.45% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2384 -system.ruby.L1Cache_Controller.IS.Persistent_GETX | 36 9.07% 9.07% | 37 9.32% 18.39% | 47 11.84% 30.23% | 56 14.11% 44.33% | 49 12.34% 56.68% | 57 14.36% 71.03% | 59 14.86% 85.89% | 56 14.11% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 397 -system.ruby.L1Cache_Controller.IS.Persistent_GETS | 86 10.87% 10.87% | 112 14.16% 25.03% | 92 11.63% 36.66% | 95 12.01% 48.67% | 105 13.27% 61.95% | 100 12.64% 74.59% | 104 13.15% 87.74% | 97 12.26% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 791 -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 9989 12.48% 12.48% | 10016 12.52% 25.00% | 10115 12.64% 37.64% | 9985 12.48% 50.12% | 9893 12.36% 62.49% | 10088 12.61% 75.09% | 9969 12.46% 87.55% | 9961 12.45% 100.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 80016 -system.ruby.L1Cache_Controller.IS.Request_Timeout | 38867 12.52% 12.52% | 38204 12.31% 24.83% | 38667 12.46% 37.29% | 39766 12.81% 50.11% | 38271 12.33% 62.44% | 39197 12.63% 75.07% | 38932 12.54% 87.61% | 38452 12.39% 100.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout::total 310356 -system.ruby.L1Cache_Controller.I_L.Load | 84 13.79% 13.79% | 77 12.64% 26.44% | 81 13.30% 39.74% | 64 10.51% 50.25% | 83 13.63% 63.88% | 66 10.84% 74.71% | 66 10.84% 85.55% | 88 14.45% 100.00% -system.ruby.L1Cache_Controller.I_L.Load::total 609 -system.ruby.L1Cache_Controller.I_L.Store | 41 13.40% 13.40% | 33 10.78% 24.18% | 56 18.30% 42.48% | 35 11.44% 53.92% | 37 12.09% 66.01% | 34 11.11% 77.12% | 41 13.40% 90.52% | 29 9.48% 100.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50394 12.52% 12.52% | 50475 12.54% 25.06% | 50165 12.47% 37.53% | 50000 12.42% 49.95% | 50492 12.55% 62.50% | 50447 12.54% 75.04% | 50219 12.48% 87.51% | 50250 12.49% 100.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 402442 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 157 11.91% 11.91% | 160 12.14% 24.05% | 142 10.77% 34.83% | 172 13.05% 47.88% | 154 11.68% 59.56% | 148 11.23% 70.79% | 192 14.57% 85.36% | 193 14.64% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1318 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 293 12.49% 12.49% | 280 11.94% 24.42% | 287 12.23% 36.66% | 306 13.04% 49.70% | 299 12.75% 62.45% | 285 12.15% 74.60% | 314 13.38% 87.98% | 282 12.02% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2346 +system.ruby.L1Cache_Controller.IS.Persistent_GETX | 46 10.60% 10.60% | 54 12.44% 23.04% | 61 14.06% 37.10% | 49 11.29% 48.39% | 46 10.60% 58.99% | 58 13.36% 72.35% | 62 14.29% 86.64% | 58 13.36% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 434 +system.ruby.L1Cache_Controller.IS.Persistent_GETS | 83 11.11% 11.11% | 92 12.32% 23.43% | 98 13.12% 36.55% | 87 11.65% 48.19% | 94 12.58% 60.78% | 86 11.51% 72.29% | 115 15.39% 87.68% | 92 12.32% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 747 +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 10066 12.40% 12.40% | 10135 12.49% 24.89% | 10168 12.53% 37.42% | 10107 12.46% 49.88% | 10323 12.72% 62.60% | 10139 12.49% 75.10% | 10091 12.44% 87.53% | 10118 12.47% 100.00% +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 81147 +system.ruby.L1Cache_Controller.IS.Request_Timeout | 39132 12.61% 12.61% | 39345 12.68% 25.28% | 39222 12.64% 37.92% | 39039 12.58% 50.50% | 38571 12.43% 62.92% | 38411 12.37% 75.30% | 38124 12.28% 87.58% | 38551 12.42% 100.00% +system.ruby.L1Cache_Controller.IS.Request_Timeout::total 310395 +system.ruby.L1Cache_Controller.I_L.Load | 73 12.83% 12.83% | 65 11.42% 24.25% | 69 12.13% 36.38% | 67 11.78% 48.15% | 81 14.24% 62.39% | 77 13.53% 75.92% | 65 11.42% 87.35% | 72 12.65% 100.00% +system.ruby.L1Cache_Controller.I_L.Load::total 569 +system.ruby.L1Cache_Controller.I_L.Store | 44 14.38% 14.38% | 31 10.13% 24.51% | 28 9.15% 33.66% | 47 15.36% 49.02% | 41 13.40% 62.42% | 44 14.38% 76.80% | 37 12.09% 88.89% | 34 11.11% 100.00% system.ruby.L1Cache_Controller.I_L.Store::total 306 -system.ruby.L1Cache_Controller.I_L.L1_Replacement | 206 10.60% 10.60% | 148 7.61% 18.21% | 234 12.04% 30.25% | 329 16.92% 47.17% | 249 12.81% 59.98% | 203 10.44% 70.42% | 258 13.27% 83.69% | 317 16.31% 100.00% -system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1944 -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 41 25.00% 25.00% | 45 27.44% 52.44% | 23 14.02% 66.46% | 18 10.98% 77.44% | 18 10.98% 88.41% | 8 4.88% 93.29% | 7 4.27% 97.56% | 4 2.44% 100.00% -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 164 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 221 12.20% 12.20% | 233 12.87% 25.07% | 222 12.26% 37.33% | 225 12.42% 49.75% | 225 12.42% 62.18% | 228 12.59% 74.77% | 230 12.70% 87.47% | 227 12.53% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 1811 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 445 12.62% 12.62% | 439 12.45% 25.07% | 441 12.51% 37.58% | 435 12.34% 49.91% | 432 12.25% 62.17% | 455 12.90% 75.07% | 463 13.13% 88.20% | 416 11.80% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 3526 -system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 40137 12.49% 12.49% | 40125 12.49% 24.98% | 40121 12.49% 37.47% | 40304 12.54% 50.01% | 40099 12.48% 62.49% | 40175 12.50% 75.00% | 40167 12.50% 87.50% | 40156 12.50% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 321284 -system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 73854 12.52% 12.52% | 73741 12.50% 25.02% | 73628 12.48% 37.50% | 73761 12.50% 50.01% | 73818 12.51% 62.52% | 73632 12.48% 75.01% | 73718 12.50% 87.50% | 73704 12.50% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 589856 -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 57 11.56% 11.56% | 63 12.78% 24.34% | 57 11.56% 35.90% | 71 14.40% 50.30% | 60 12.17% 62.47% | 54 10.95% 73.43% | 66 13.39% 86.82% | 65 13.18% 100.00% -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 493 -system.ruby.L1Cache_Controller.S_L.L1_Replacement | 42 10.42% 10.42% | 35 8.68% 19.11% | 64 15.88% 34.99% | 55 13.65% 48.64% | 24 5.96% 54.59% | 80 19.85% 74.44% | 47 11.66% 86.10% | 56 13.90% 100.00% -system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 403 -system.ruby.L1Cache_Controller.S_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S_L.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 4 6.35% 6.35% | 7 11.11% 17.46% | 6 9.52% 26.98% | 5 7.94% 34.92% | 17 26.98% 61.90% | 10 15.87% 77.78% | 14 22.22% 100.00% -system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 63 -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 32 9.04% 9.04% | 43 12.15% 21.19% | 46 12.99% 34.18% | 40 11.30% 45.48% | 45 12.71% 58.19% | 56 15.82% 74.01% | 46 12.99% 87.01% | 46 12.99% 100.00% -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 354 -system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 616 10.64% 10.64% | 650 11.23% 21.87% | 788 13.61% 35.49% | 576 9.95% 45.44% | 691 11.94% 57.38% | 852 14.72% 72.10% | 843 14.56% 86.66% | 772 13.34% 100.00% -system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 5788 -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 1 8.33% 8.33% | 1 8.33% 16.67% | 5 41.67% 58.33% | 1 8.33% 66.67% | 1 8.33% 75.00% | 3 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 12 -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.I_L.L1_Replacement | 129 6.65% 6.65% | 284 14.64% 21.29% | 163 8.40% 29.69% | 208 10.72% 40.41% | 294 15.15% 55.57% | 224 11.55% 67.11% | 336 17.32% 84.43% | 302 15.57% 100.00% +system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1940 +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 34 22.67% 22.67% | 33 22.00% 44.67% | 22 14.67% 59.33% | 23 15.33% 74.67% | 20 13.33% 88.00% | 9 6.00% 94.00% | 5 3.33% 97.33% | 4 2.67% 100.00% +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 150 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 218 11.86% 11.86% | 235 12.79% 24.65% | 253 13.76% 38.41% | 223 12.13% 50.54% | 234 12.73% 63.28% | 227 12.35% 75.63% | 231 12.57% 88.19% | 217 11.81% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 1838 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 417 12.29% 12.29% | 432 12.74% 25.03% | 441 13.00% 38.03% | 421 12.41% 50.44% | 424 12.50% 62.94% | 414 12.21% 75.15% | 419 12.35% 87.50% | 424 12.50% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 3392 +system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 41206 12.51% 12.51% | 41068 12.47% 24.99% | 41138 12.49% 37.48% | 41087 12.48% 49.96% | 41184 12.51% 62.46% | 41199 12.51% 74.98% | 41210 12.52% 87.49% | 41190 12.51% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 329282 +system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 74847 12.52% 12.52% | 74756 12.51% 25.03% | 74686 12.50% 37.53% | 74789 12.51% 50.04% | 74514 12.47% 62.51% | 74673 12.49% 75.01% | 74669 12.49% 87.50% | 74707 12.50% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 597641 +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 51 10.28% 10.28% | 56 11.29% 21.57% | 47 9.48% 31.05% | 68 13.71% 44.76% | 69 13.91% 58.67% | 60 12.10% 70.77% | 70 14.11% 84.88% | 75 15.12% 100.00% +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 496 +system.ruby.L1Cache_Controller.S_L.L1_Replacement | 5 1.51% 1.51% | 83 25.00% 26.51% | 34 10.24% 36.75% | 12 3.61% 40.36% | 56 16.87% 57.23% | 41 12.35% 69.58% | 41 12.35% 81.93% | 60 18.07% 100.00% +system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 332 +system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 3 4.84% 4.84% | 2 3.23% 8.06% | 0 0.00% 8.06% | 9 14.52% 22.58% | 11 17.74% 40.32% | 18 29.03% 69.35% | 19 30.65% 100.00% +system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 62 +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 42 11.76% 11.76% | 46 12.89% 24.65% | 49 13.73% 38.38% | 40 11.20% 49.58% | 50 14.01% 63.59% | 35 9.80% 73.39% | 51 14.29% 87.68% | 44 12.32% 100.00% +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 357 +system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 710 11.66% 11.66% | 553 9.08% 20.74% | 675 11.08% 31.82% | 757 12.43% 44.25% | 762 12.51% 56.76% | 889 14.60% 71.35% | 956 15.70% 87.05% | 789 12.95% 100.00% +system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 6091 +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 2 18.18% 18.18% | 1 9.09% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 2 18.18% 63.64% | 0 0.00% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 11 +system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX::total 3 -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total 5 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 3 6.67% 6.67% | 2 4.44% 11.11% | 4 8.89% 20.00% | 10 22.22% 42.22% | 10 22.22% 64.44% | 10 22.22% 86.67% | 6 13.33% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 45 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 2 2.00% 2.00% | 7 7.00% 9.00% | 11 11.00% 20.00% | 13 13.00% 33.00% | 15 15.00% 48.00% | 23 23.00% 71.00% | 29 29.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 100 -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 105 11.84% 11.84% | 98 11.05% 22.89% | 123 13.87% 36.75% | 103 11.61% 48.37% | 110 12.40% 60.77% | 117 13.19% 73.96% | 120 13.53% 87.49% | 111 12.51% 100.00% -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 887 -system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 92 8.01% 8.01% | 153 13.33% 21.34% | 130 11.32% 32.67% | 128 11.15% 43.82% | 153 13.33% 57.14% | 194 16.90% 74.04% | 147 12.80% 86.85% | 151 13.15% 100.00% -system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 1148 -system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 1362 11.37% 11.37% | 1369 11.42% 22.79% | 1430 11.93% 34.72% | 1388 11.58% 46.31% | 1490 12.43% 58.74% | 1388 11.58% 70.32% | 1535 12.81% 83.13% | 2021 16.87% 100.00% -system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 11983 -system.ruby.L1Cache_Controller.IS_L.Data_Shared | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 3 -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 1 5.56% 5.56% | 0 0.00% 5.56% | 2 11.11% 16.67% | 3 16.67% 33.33% | 2 11.11% 44.44% | 3 16.67% 61.11% | 5 27.78% 88.89% | 2 11.11% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 18 -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS | 2 33.33% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total 6 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 3 4.55% 4.55% | 2 3.03% 7.58% | 7 10.61% 18.18% | 11 16.67% 34.85% | 14 21.21% 56.06% | 16 24.24% 80.30% | 13 19.70% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 66 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 4.88% 4.88% | 9 10.98% 15.85% | 14 17.07% 32.93% | 23 28.05% 60.98% | 11 13.41% 74.39% | 21 25.61% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 82 +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 118 12.16% 12.16% | 94 9.69% 21.86% | 109 11.24% 33.09% | 126 12.99% 46.08% | 130 13.40% 59.48% | 143 14.74% 74.23% | 127 13.09% 87.32% | 123 12.68% 100.00% +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 970 +system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 114 9.64% 9.64% | 186 15.72% 25.36% | 156 13.19% 38.55% | 163 13.78% 52.32% | 190 16.06% 68.39% | 134 11.33% 79.71% | 73 6.17% 85.88% | 167 14.12% 100.00% +system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 1183 +system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 935 8.62% 8.62% | 1162 10.71% 19.34% | 1146 10.57% 29.90% | 1262 11.64% 41.54% | 1378 12.71% 54.25% | 1777 16.39% 70.63% | 1589 14.65% 85.28% | 1596 14.72% 100.00% +system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 10845 +system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 4 +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 1 5.00% 5.00% | 0 0.00% 5.00% | 2 10.00% 15.00% | 2 10.00% 25.00% | 3 15.00% 40.00% | 4 20.00% 60.00% | 5 25.00% 85.00% | 3 15.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 20 +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total 3 -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 4 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 2 2.04% 2.04% | 11 11.22% 13.27% | 14 14.29% 27.55% | 9 9.18% 36.73% | 13 13.27% 50.00% | 24 24.49% 74.49% | 25 25.51% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 98 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 11 6.92% 6.92% | 5 3.14% 10.06% | 18 11.32% 21.38% | 24 15.09% 36.48% | 24 15.09% 51.57% | 36 22.64% 74.21% | 41 25.79% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 159 -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 204 11.49% 11.49% | 226 12.73% 24.21% | 218 12.27% 36.49% | 212 11.94% 48.42% | 235 13.23% 61.66% | 219 12.33% 73.99% | 224 12.61% 86.60% | 238 13.40% 100.00% -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 1776 -system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 277 13.71% 13.71% | 242 11.97% 25.68% | 190 9.40% 35.08% | 265 13.11% 48.19% | 341 16.87% 65.07% | 233 11.53% 76.60% | 222 10.98% 87.58% | 251 12.42% 100.00% -system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 2021 -system.ruby.L2Cache_Controller.L1_GETS 401048 0.00% 0.00% +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 1 14.29% 14.29% | 1 14.29% 28.57% | 1 14.29% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 7 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 7 6.25% 6.25% | 12 10.71% 16.96% | 10 8.93% 25.89% | 11 9.82% 35.71% | 21 18.75% 54.46% | 26 23.21% 77.68% | 25 22.32% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 112 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 5 3.70% 3.70% | 11 8.15% 11.85% | 7 5.19% 17.04% | 13 9.63% 26.67% | 22 16.30% 42.96% | 41 30.37% 73.33% | 36 26.67% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 135 +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 201 11.65% 11.65% | 210 12.17% 23.81% | 226 13.09% 36.91% | 200 11.59% 48.49% | 218 12.63% 61.12% | 216 12.51% 73.64% | 237 13.73% 87.37% | 218 12.63% 100.00% +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 1726 +system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 228 10.77% 10.77% | 319 15.07% 25.84% | 369 17.43% 43.27% | 258 12.19% 55.46% | 197 9.31% 64.76% | 201 9.49% 74.26% | 272 12.85% 87.10% | 273 12.90% 100.00% +system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 2117 +system.ruby.L2Cache_Controller.L1_GETS 404457 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETS_Last_Token 3 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 215772 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_INV 1395 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 583206 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Shared_Data 1451 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 613102 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Owned 843 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETX 46049 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 84554 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 129089 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 399363 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 214874 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_INV 909 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 1386 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 581094 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Owned 734 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 128754 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETS 2 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_INV 2 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 559 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 366 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Owned 2 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 223591 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_INV 1379 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 594493 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Shared_Data 1349 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_All_Tokens 624482 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Owned 809 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETX 47208 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS 85660 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 131330 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 402910 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 222716 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_INV 890 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 1290 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 592515 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Owned 696 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 130991 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_INV 1 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L2_Replacement 531 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 360 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_Owned 3 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETS 1 0.00% 0.00% system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 3 0.00% 0.00% system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 1209 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 5 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 176 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETS 13 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 1168 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 7 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 633 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1075 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 590 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 579287 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETX 460 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETS 849 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETS 595 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETX 304 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_INV 484 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L2_Replacement 982 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 53 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 30833 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Owned 107 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 45586 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 83699 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 330 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.L2_Replacement 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 5 0.00% 0.00% -system.ruby.Directory_Controller.GETX 255487 0.00% 0.00% -system.ruby.Directory_Controller.GETS 476933 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 130603 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 129089 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 344 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 235610 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 694 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 375677 0.00% 0.00% -system.ruby.Directory_Controller.Tokens 456 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 3709 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 610582 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 234338 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 212118 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 394360 0.00% 0.00% -system.ruby.Directory_Controller.O.Lockdown 2461 0.00% 0.00% -system.ruby.Directory_Controller.O.Data_All_Tokens 49 0.00% 0.00% -system.ruby.Directory_Controller.O.Tokens 4 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 967 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 2212 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 3891 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 20370 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 344 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 233998 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 694 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 375526 0.00% 0.00% -system.ruby.Directory_Controller.NO.Tokens 248 0.00% 0.00% -system.ruby.Directory_Controller.L.GETX 852 0.00% 0.00% -system.ruby.Directory_Controller.L.GETS 1708 0.00% 0.00% -system.ruby.Directory_Controller.L.Lockdown 1080 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 129089 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_All_Tokens 106 0.00% 0.00% -system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 151 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 1099 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 3 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 188 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Owned 2 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Persistent_GETS 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETS 4 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L2_Replacement 1049 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 625 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Persistent_GETS 3 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 978 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 555 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 590843 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETX 445 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETS 859 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETS 565 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETX 317 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_INV 487 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L2_Replacement 971 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 55 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 30794 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Owned 108 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETX 46762 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETS 84796 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 335 0.00% 0.00% +system.ruby.L2Cache_Controller.S_L.L1_INV 1 0.00% 0.00% +system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 4 0.00% 0.00% +system.ruby.Directory_Controller.GETX 263101 0.00% 0.00% +system.ruby.Directory_Controller.GETS 477895 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 132868 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 131330 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 346 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 243507 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 579 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 379354 0.00% 0.00% +system.ruby.Directory_Controller.Tokens 299 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 3429 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 622028 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 242193 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 219976 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 397919 0.00% 0.00% +system.ruby.Directory_Controller.O.Lockdown 2510 0.00% 0.00% +system.ruby.Directory_Controller.O.Data_All_Tokens 52 0.00% 0.00% +system.ruby.Directory_Controller.O.Tokens 2 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 864 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 2155 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 3924 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 20743 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 346 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 241851 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 579 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 379230 0.00% 0.00% +system.ruby.Directory_Controller.NO.Tokens 238 0.00% 0.00% +system.ruby.Directory_Controller.L.GETX 905 0.00% 0.00% +system.ruby.Directory_Controller.L.GETS 1631 0.00% 0.00% +system.ruby.Directory_Controller.L.Lockdown 1114 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 131330 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_All_Tokens 93 0.00% 0.00% +system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 124 0.00% 0.00% system.ruby.Directory_Controller.L.Tokens 3 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 13301 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 26689 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Lockdown 1663 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Data_All_Tokens 1388 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Tokens 201 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Ack_All_Tokens 2722 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 232675 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETX 6131 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETS 13880 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Lockdown 30 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Data_All_Tokens 69 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Data 4123 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Ack 1663 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETX 5886 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETS 10623 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Lockdown 398 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 104596 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETX 14987 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETS 25782 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 104601 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 20 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 501863 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 13508 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 25780 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Lockdown 1640 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Data_All_Tokens 1511 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Tokens 54 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Ack_All_Tokens 2445 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 240553 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETX 5952 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETS 11594 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Lockdown 34 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Ack_All_Tokens 45 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Data 4150 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Ack 1640 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETX 5644 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETS 9783 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Lockdown 384 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Ack_All_Tokens 33 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 106440 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETX 14961 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETS 27264 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 106443 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Tokens 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 42 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 511438 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index c7c9aeb58..2a34715b3 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,1242 +1,1247 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.005796 # Number of seconds simulated -sim_ticks 5795833 # Number of ticks simulated -final_tick 5795833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.005921 # Number of seconds simulated +sim_ticks 5920895 # Number of ticks simulated +final_tick 5920895 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 66984 # Simulator tick rate (ticks/s) -host_mem_usage 260008 # Number of bytes of host memory used -host_seconds 86.53 # Real time elapsed on the host +host_tick_rate 58624 # Simulator tick rate (ticks/s) +host_mem_usage 293400 # Number of bytes of host memory used +host_seconds 101.00 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 618244 -system.ruby.outstanding_req_hist::mean 15.998447 -system.ruby.outstanding_req_hist::gmean 15.997166 -system.ruby.outstanding_req_hist::stdev 0.126661 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 16 0.00% 0.02% | 618124 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 618244 +system.ruby.outstanding_req_hist::samples 629183 +system.ruby.outstanding_req_hist::mean 15.998474 +system.ruby.outstanding_req_hist::gmean 15.997215 +system.ruby.outstanding_req_hist::stdev 0.125555 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 16 0.00% 0.02% | 629063 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 629183 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 618116 -system.ruby.latency_hist::mean 1200.021813 -system.ruby.latency_hist::gmean 820.629025 -system.ruby.latency_hist::stdev 895.776411 -system.ruby.latency_hist | 317693 51.40% 51.40% | 164349 26.59% 77.99% | 123580 19.99% 97.98% | 12269 1.98% 99.96% | 224 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 618116 +system.ruby.latency_hist::samples 629055 +system.ruby.latency_hist::mean 1204.590594 +system.ruby.latency_hist::gmean 823.731643 +system.ruby.latency_hist::stdev 899.026148 +system.ruby.latency_hist | 322549 51.28% 51.28% | 166734 26.51% 77.78% | 126612 20.13% 97.91% | 12813 2.04% 99.94% | 340 0.05% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 629055 system.ruby.hit_latency_hist::bucket_size 256 system.ruby.hit_latency_hist::max_bucket 2559 -system.ruby.hit_latency_hist::samples 737 -system.ruby.hit_latency_hist::mean 133.263229 -system.ruby.hit_latency_hist::gmean 41.298079 -system.ruby.hit_latency_hist::stdev 176.676430 -system.ruby.hit_latency_hist | 600 81.41% 81.41% | 109 14.79% 96.20% | 20 2.71% 98.91% | 6 0.81% 99.73% | 1 0.14% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 737 +system.ruby.hit_latency_hist::samples 752 +system.ruby.hit_latency_hist::mean 140.220745 +system.ruby.hit_latency_hist::gmean 42.859600 +system.ruby.hit_latency_hist::stdev 185.954397 +system.ruby.hit_latency_hist | 612 81.38% 81.38% | 110 14.63% 96.01% | 20 2.66% 98.67% | 7 0.93% 99.60% | 1 0.13% 99.73% | 1 0.13% 99.87% | 1 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 752 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 617379 -system.ruby.miss_latency_hist::mean 1201.295263 -system.ruby.miss_latency_hist::gmean 823.562623 -system.ruby.miss_latency_hist::stdev 895.531111 -system.ruby.miss_latency_hist | 316958 51.34% 51.34% | 164347 26.62% 77.96% | 123580 20.02% 97.98% | 12269 1.99% 99.96% | 224 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 617379 -system.ruby.L1Cache.incomplete_times 439 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 77212 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77226 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 628303 +system.ruby.miss_latency_hist::mean 1205.864511 +system.ruby.miss_latency_hist::gmean 826.651052 +system.ruby.miss_latency_hist::stdev 898.786133 +system.ruby.miss_latency_hist | 321800 51.22% 51.22% | 166731 26.54% 77.75% | 126612 20.15% 97.91% | 12813 2.04% 99.94% | 340 0.05% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 628303 +system.ruby.L1Cache.incomplete_times 423 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78646 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78665 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.L2cache.demand_hits 66 # Number of cache demand hits -system.ruby.l1_cntrl4.L2cache.demand_misses 77146 # Number of cache demand misses -system.ruby.l1_cntrl4.L2cache.demand_accesses 77212 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Dcache.demand_hits 28 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 77076 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77104 # Number of cache demand accesses +system.ruby.l1_cntrl4.L2cache.demand_hits 77 # Number of cache demand hits +system.ruby.l1_cntrl4.L2cache.demand_misses 78569 # Number of cache demand misses +system.ruby.l1_cntrl4.L2cache.demand_accesses 78646 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78666 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78685 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L2cache.demand_hits 84 # Number of cache demand hits -system.ruby.l1_cntrl5.L2cache.demand_misses 76992 # Number of cache demand misses -system.ruby.l1_cntrl5.L2cache.demand_accesses 77076 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 77608 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77620 # Number of cache demand accesses +system.ruby.l1_cntrl5.L2cache.demand_hits 76 # Number of cache demand hits +system.ruby.l1_cntrl5.L2cache.demand_misses 78590 # Number of cache demand misses +system.ruby.l1_cntrl5.L2cache.demand_accesses 78666 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 16 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78670 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78686 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L2cache.demand_hits 66 # Number of cache demand hits -system.ruby.l1_cntrl6.L2cache.demand_misses 77542 # Number of cache demand misses -system.ruby.l1_cntrl6.L2cache.demand_accesses 77608 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 76959 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 76973 # Number of cache demand accesses +system.ruby.l1_cntrl6.L2cache.demand_hits 70 # Number of cache demand hits +system.ruby.l1_cntrl6.L2cache.demand_misses 78600 # Number of cache demand misses +system.ruby.l1_cntrl6.L2cache.demand_accesses 78670 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 24 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78321 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78345 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L2cache.demand_hits 67 # Number of cache demand hits -system.ruby.l1_cntrl7.L2cache.demand_misses 76892 # Number of cache demand misses -system.ruby.l1_cntrl7.L2cache.demand_accesses 76959 # Number of cache demand accesses +system.ruby.l1_cntrl7.L2cache.demand_hits 78 # Number of cache demand hits +system.ruby.l1_cntrl7.L2cache.demand_misses 78243 # Number of cache demand misses +system.ruby.l1_cntrl7.L2cache.demand_accesses 78321 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 76963 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 76980 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78395 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78412 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 72 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 76891 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 76963 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 22 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 77461 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77483 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 78315 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 78395 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 15 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78908 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78923 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L2cache.demand_hits 69 # Number of cache demand hits -system.ruby.l1_cntrl1.L2cache.demand_misses 77392 # Number of cache demand misses -system.ruby.l1_cntrl1.L2cache.demand_accesses 77461 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 77314 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77326 # Number of cache demand accesses +system.ruby.l1_cntrl1.L2cache.demand_hits 80 # Number of cache demand hits +system.ruby.l1_cntrl1.L2cache.demand_misses 78828 # Number of cache demand misses +system.ruby.l1_cntrl1.L2cache.demand_accesses 78908 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 15 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78622 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78637 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L2cache.demand_hits 98 # Number of cache demand hits -system.ruby.l1_cntrl2.L2cache.demand_misses 77216 # Number of cache demand misses -system.ruby.l1_cntrl2.L2cache.demand_accesses 77314 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 19 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 77408 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 77427 # Number of cache demand accesses +system.ruby.l1_cntrl2.L2cache.demand_hits 77 # Number of cache demand hits +system.ruby.l1_cntrl2.L2cache.demand_misses 78545 # Number of cache demand misses +system.ruby.l1_cntrl2.L2cache.demand_accesses 78622 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78711 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78728 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L2cache.demand_hits 77 # Number of cache demand hits -system.ruby.l1_cntrl3.L2cache.demand_misses 77331 # Number of cache demand misses -system.ruby.l1_cntrl3.L2cache.demand_accesses 77408 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 12.556021 -system.ruby.network.routers0.msg_count.Request_Control::2 76891 -system.ruby.network.routers0.msg_count.Request_Control::3 67 -system.ruby.network.routers0.msg_count.Response_Data::4 79331 -system.ruby.network.routers0.msg_count.Response_Control::4 1073182 -system.ruby.network.routers0.msg_count.Writeback_Data::5 26490 -system.ruby.network.routers0.msg_count.Writeback_Control::2 72619 -system.ruby.network.routers0.msg_count.Writeback_Control::3 72619 -system.ruby.network.routers0.msg_count.Writeback_Control::5 46104 -system.ruby.network.routers0.msg_count.Broadcast_Control::3 540121 -system.ruby.network.routers0.msg_count.Unblock_Control::5 76912 -system.ruby.network.routers0.msg_bytes.Request_Control::2 615128 -system.ruby.network.routers0.msg_bytes.Request_Control::3 536 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5711832 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8585456 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 1907280 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 580952 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 580952 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 368832 -system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4320968 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 615296 -system.ruby.network.routers1.percent_links_utilized 12.611060 -system.ruby.network.routers1.msg_count.Request_Control::2 77392 -system.ruby.network.routers1.msg_count.Request_Control::3 47 -system.ruby.network.routers1.msg_count.Response_Data::4 79893 -system.ruby.network.routers1.msg_count.Response_Control::4 1076151 -system.ruby.network.routers1.msg_count.Writeback_Data::5 26871 -system.ruby.network.routers1.msg_count.Writeback_Control::2 73022 -system.ruby.network.routers1.msg_count.Writeback_Control::3 73022 -system.ruby.network.routers1.msg_count.Writeback_Control::5 46119 -system.ruby.network.routers1.msg_count.Broadcast_Control::3 539613 -system.ruby.network.routers1.msg_count.Unblock_Control::5 77422 -system.ruby.network.routers1.msg_bytes.Request_Control::2 619136 -system.ruby.network.routers1.msg_bytes.Request_Control::3 376 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5752296 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8609208 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 1934712 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 584176 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 584176 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 368952 -system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4316904 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 619376 -system.ruby.network.routers2.percent_links_utilized 12.591042 -system.ruby.network.routers2.msg_count.Request_Control::2 77216 -system.ruby.network.routers2.msg_count.Request_Control::3 56 -system.ruby.network.routers2.msg_count.Response_Data::4 79706 -system.ruby.network.routers2.msg_count.Response_Control::4 1075089 -system.ruby.network.routers2.msg_count.Writeback_Data::5 26730 -system.ruby.network.routers2.msg_count.Writeback_Control::2 72821 -system.ruby.network.routers2.msg_count.Writeback_Control::3 72821 -system.ruby.network.routers2.msg_count.Writeback_Control::5 46059 -system.ruby.network.routers2.msg_count.Broadcast_Control::3 539797 -system.ruby.network.routers2.msg_count.Unblock_Control::5 77245 -system.ruby.network.routers2.msg_bytes.Request_Control::2 617728 -system.ruby.network.routers2.msg_bytes.Request_Control::3 448 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5738832 -system.ruby.network.routers2.msg_bytes.Response_Control::4 8600712 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 1924560 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 582568 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 582568 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 368472 -system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4318376 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 617960 -system.ruby.network.routers3.percent_links_utilized 12.606475 -system.ruby.network.routers3.msg_count.Request_Control::2 77331 -system.ruby.network.routers3.msg_count.Request_Control::3 60 -system.ruby.network.routers3.msg_count.Response_Data::4 79797 -system.ruby.network.routers3.msg_count.Response_Control::4 1075802 -system.ruby.network.routers3.msg_count.Writeback_Data::5 26915 -system.ruby.network.routers3.msg_count.Writeback_Control::2 72965 -system.ruby.network.routers3.msg_count.Writeback_Control::3 72965 -system.ruby.network.routers3.msg_count.Writeback_Control::5 46025 -system.ruby.network.routers3.msg_count.Broadcast_Control::3 539692 -system.ruby.network.routers3.msg_count.Unblock_Control::5 77353 -system.ruby.network.routers3.msg_bytes.Request_Control::2 618648 -system.ruby.network.routers3.msg_bytes.Request_Control::3 480 -system.ruby.network.routers3.msg_bytes.Response_Data::4 5745384 -system.ruby.network.routers3.msg_bytes.Response_Control::4 8606416 -system.ruby.network.routers3.msg_bytes.Writeback_Data::5 1937880 -system.ruby.network.routers3.msg_bytes.Writeback_Control::2 583720 -system.ruby.network.routers3.msg_bytes.Writeback_Control::3 583720 -system.ruby.network.routers3.msg_bytes.Writeback_Control::5 368200 -system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4317536 -system.ruby.network.routers3.msg_bytes.Unblock_Control::5 618824 -system.ruby.network.routers4.percent_links_utilized 12.582311 -system.ruby.network.routers4.msg_count.Request_Control::2 77146 -system.ruby.network.routers4.msg_count.Request_Control::3 48 -system.ruby.network.routers4.msg_count.Response_Data::4 79619 -system.ruby.network.routers4.msg_count.Response_Control::4 1074623 -system.ruby.network.routers4.msg_count.Writeback_Data::5 26652 -system.ruby.network.routers4.msg_count.Writeback_Control::2 72792 -system.ruby.network.routers4.msg_count.Writeback_Control::3 72792 -system.ruby.network.routers4.msg_count.Writeback_Control::5 46109 -system.ruby.network.routers4.msg_count.Broadcast_Control::3 539876 -system.ruby.network.routers4.msg_count.Unblock_Control::5 77174 -system.ruby.network.routers4.msg_bytes.Request_Control::2 617168 -system.ruby.network.routers4.msg_bytes.Request_Control::3 384 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5732568 -system.ruby.network.routers4.msg_bytes.Response_Control::4 8596984 -system.ruby.network.routers4.msg_bytes.Writeback_Data::5 1918944 -system.ruby.network.routers4.msg_bytes.Writeback_Control::2 582336 -system.ruby.network.routers4.msg_bytes.Writeback_Control::3 582336 -system.ruby.network.routers4.msg_bytes.Writeback_Control::5 368872 -system.ruby.network.routers4.msg_bytes.Broadcast_Control::3 4319008 -system.ruby.network.routers4.msg_bytes.Unblock_Control::5 617392 -system.ruby.network.routers5.percent_links_utilized 12.572088 -system.ruby.network.routers5.msg_count.Request_Control::2 76992 -system.ruby.network.routers5.msg_count.Request_Control::3 51 -system.ruby.network.routers5.msg_count.Response_Data::4 79504 -system.ruby.network.routers5.msg_count.Response_Control::4 1073637 -system.ruby.network.routers5.msg_count.Writeback_Data::5 26712 -system.ruby.network.routers5.msg_count.Writeback_Control::2 72564 -system.ruby.network.routers5.msg_count.Writeback_Control::3 72564 -system.ruby.network.routers5.msg_count.Writeback_Control::5 45823 -system.ruby.network.routers5.msg_count.Broadcast_Control::3 540035 -system.ruby.network.routers5.msg_count.Unblock_Control::5 77019 -system.ruby.network.routers5.msg_bytes.Request_Control::2 615936 -system.ruby.network.routers5.msg_bytes.Request_Control::3 408 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5724288 -system.ruby.network.routers5.msg_bytes.Response_Control::4 8589096 -system.ruby.network.routers5.msg_bytes.Writeback_Data::5 1923264 -system.ruby.network.routers5.msg_bytes.Writeback_Control::2 580512 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 580512 -system.ruby.network.routers5.msg_bytes.Writeback_Control::5 366584 -system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4320280 -system.ruby.network.routers5.msg_bytes.Unblock_Control::5 616152 -system.ruby.network.routers6.percent_links_utilized 12.626714 -system.ruby.network.routers6.msg_count.Request_Control::2 77542 -system.ruby.network.routers6.msg_count.Request_Control::3 52 -system.ruby.network.routers6.msg_count.Response_Data::4 80017 -system.ruby.network.routers6.msg_count.Response_Control::4 1077041 -system.ruby.network.routers6.msg_count.Writeback_Data::5 26999 -system.ruby.network.routers6.msg_count.Writeback_Control::2 73171 -system.ruby.network.routers6.msg_count.Writeback_Control::3 73169 -system.ruby.network.routers6.msg_count.Writeback_Control::5 46140 -system.ruby.network.routers6.msg_count.Broadcast_Control::3 539467 -system.ruby.network.routers6.msg_count.Unblock_Control::5 77567 -system.ruby.network.routers6.msg_bytes.Request_Control::2 620336 -system.ruby.network.routers6.msg_bytes.Request_Control::3 416 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5761224 -system.ruby.network.routers6.msg_bytes.Response_Control::4 8616328 -system.ruby.network.routers6.msg_bytes.Writeback_Data::5 1943928 -system.ruby.network.routers6.msg_bytes.Writeback_Control::2 585368 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 585352 -system.ruby.network.routers6.msg_bytes.Writeback_Control::5 369120 -system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4315736 -system.ruby.network.routers6.msg_bytes.Unblock_Control::5 620536 -system.ruby.network.routers7.percent_links_utilized 12.559398 -system.ruby.network.routers7.msg_count.Request_Control::2 76892 -system.ruby.network.routers7.msg_count.Request_Control::3 58 -system.ruby.network.routers7.msg_count.Response_Data::4 79385 -system.ruby.network.routers7.msg_count.Response_Control::4 1073007 -system.ruby.network.routers7.msg_count.Writeback_Data::5 26654 -system.ruby.network.routers7.msg_count.Writeback_Control::2 72340 -system.ruby.network.routers7.msg_count.Writeback_Control::3 72340 -system.ruby.network.routers7.msg_count.Writeback_Control::5 45668 -system.ruby.network.routers7.msg_count.Broadcast_Control::3 540126 -system.ruby.network.routers7.msg_count.Unblock_Control::5 76905 -system.ruby.network.routers7.msg_bytes.Request_Control::2 615136 -system.ruby.network.routers7.msg_bytes.Request_Control::3 464 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5715720 -system.ruby.network.routers7.msg_bytes.Response_Control::4 8584056 -system.ruby.network.routers7.msg_bytes.Writeback_Data::5 1919088 -system.ruby.network.routers7.msg_bytes.Writeback_Control::2 578720 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 578720 -system.ruby.network.routers7.msg_bytes.Writeback_Control::5 365344 -system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4321008 -system.ruby.network.routers7.msg_bytes.Unblock_Control::5 615240 +system.ruby.l1_cntrl3.L2cache.demand_hits 72 # Number of cache demand hits +system.ruby.l1_cntrl3.L2cache.demand_misses 78639 # Number of cache demand misses +system.ruby.l1_cntrl3.L2cache.demand_accesses 78711 # Number of cache demand accesses +system.ruby.network.routers0.percent_links_utilized 12.539882 +system.ruby.network.routers0.msg_count.Request_Control::2 78315 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+system.ruby.network.routers0.msg_bytes.Writeback_Control::3 591720 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 370520 +system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4397184 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 626624 +system.ruby.network.routers1.percent_links_utilized 12.590850 +system.ruby.network.routers1.msg_count.Request_Control::2 78828 +system.ruby.network.routers1.msg_count.Request_Control::3 53 +system.ruby.network.routers1.msg_count.Response_Data::4 81413 +system.ruby.network.routers1.msg_count.Response_Control::4 1095506 +system.ruby.network.routers1.msg_count.Writeback_Data::5 27983 +system.ruby.network.routers1.msg_count.Writeback_Control::2 74350 +system.ruby.network.routers1.msg_count.Writeback_Control::3 74350 +system.ruby.network.routers1.msg_count.Writeback_Control::5 46341 +system.ruby.network.routers1.msg_count.Broadcast_Control::3 549124 +system.ruby.network.routers1.msg_count.Unblock_Control::5 78851 +system.ruby.network.routers1.msg_bytes.Request_Control::2 630624 +system.ruby.network.routers1.msg_bytes.Request_Control::3 424 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5861736 +system.ruby.network.routers1.msg_bytes.Response_Control::4 8764048 +system.ruby.network.routers1.msg_bytes.Writeback_Data::5 2014776 +system.ruby.network.routers1.msg_bytes.Writeback_Control::2 594800 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 594800 +system.ruby.network.routers1.msg_bytes.Writeback_Control::5 370728 +system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4392992 +system.ruby.network.routers1.msg_bytes.Unblock_Control::5 630808 +system.ruby.network.routers2.percent_links_utilized 12.557548 +system.ruby.network.routers2.msg_count.Request_Control::2 78545 +system.ruby.network.routers2.msg_count.Request_Control::3 51 +system.ruby.network.routers2.msg_count.Response_Data::4 81046 +system.ruby.network.routers2.msg_count.Response_Control::4 1093927 +system.ruby.network.routers2.msg_count.Writeback_Data::5 27726 +system.ruby.network.routers2.msg_count.Writeback_Control::2 74128 +system.ruby.network.routers2.msg_count.Writeback_Control::3 74128 +system.ruby.network.routers2.msg_count.Writeback_Control::5 46381 +system.ruby.network.routers2.msg_count.Broadcast_Control::3 549406 +system.ruby.network.routers2.msg_count.Unblock_Control::5 78563 +system.ruby.network.routers2.msg_bytes.Request_Control::2 628360 +system.ruby.network.routers2.msg_bytes.Request_Control::3 408 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5835312 +system.ruby.network.routers2.msg_bytes.Response_Control::4 8751416 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 1996272 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 593024 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 593024 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 371048 +system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4395248 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 628504 +system.ruby.network.routers3.percent_links_utilized 12.569726 +system.ruby.network.routers3.msg_count.Request_Control::2 78639 +system.ruby.network.routers3.msg_count.Request_Control::3 54 +system.ruby.network.routers3.msg_count.Response_Data::4 81256 +system.ruby.network.routers3.msg_count.Response_Control::4 1094314 +system.ruby.network.routers3.msg_count.Writeback_Data::5 27761 +system.ruby.network.routers3.msg_count.Writeback_Control::2 74201 +system.ruby.network.routers3.msg_count.Writeback_Control::3 74201 +system.ruby.network.routers3.msg_count.Writeback_Control::5 46424 +system.ruby.network.routers3.msg_count.Broadcast_Control::3 549323 +system.ruby.network.routers3.msg_count.Unblock_Control::5 78652 +system.ruby.network.routers3.msg_bytes.Request_Control::2 629112 +system.ruby.network.routers3.msg_bytes.Request_Control::3 432 +system.ruby.network.routers3.msg_bytes.Response_Data::4 5850432 +system.ruby.network.routers3.msg_bytes.Response_Control::4 8754512 +system.ruby.network.routers3.msg_bytes.Writeback_Data::5 1998792 +system.ruby.network.routers3.msg_bytes.Writeback_Control::2 593608 +system.ruby.network.routers3.msg_bytes.Writeback_Control::3 593608 +system.ruby.network.routers3.msg_bytes.Writeback_Control::5 371392 +system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4394584 +system.ruby.network.routers3.msg_bytes.Unblock_Control::5 629216 +system.ruby.network.routers4.percent_links_utilized 12.558849 +system.ruby.network.routers4.msg_count.Request_Control::2 78569 +system.ruby.network.routers4.msg_count.Request_Control::3 57 +system.ruby.network.routers4.msg_count.Response_Data::4 81144 +system.ruby.network.routers4.msg_count.Response_Control::4 1093886 +system.ruby.network.routers4.msg_count.Writeback_Data::5 27693 +system.ruby.network.routers4.msg_count.Writeback_Control::2 74027 +system.ruby.network.routers4.msg_count.Writeback_Control::3 74027 +system.ruby.network.routers4.msg_count.Writeback_Control::5 46298 +system.ruby.network.routers4.msg_count.Broadcast_Control::3 549387 +system.ruby.network.routers4.msg_count.Unblock_Control::5 78601 +system.ruby.network.routers4.msg_bytes.Request_Control::2 628552 +system.ruby.network.routers4.msg_bytes.Request_Control::3 456 +system.ruby.network.routers4.msg_bytes.Response_Data::4 5842368 +system.ruby.network.routers4.msg_bytes.Response_Control::4 8751088 +system.ruby.network.routers4.msg_bytes.Writeback_Data::5 1993896 +system.ruby.network.routers4.msg_bytes.Writeback_Control::2 592216 +system.ruby.network.routers4.msg_bytes.Writeback_Control::3 592216 +system.ruby.network.routers4.msg_bytes.Writeback_Control::5 370384 +system.ruby.network.routers4.msg_bytes.Broadcast_Control::3 4395096 +system.ruby.network.routers4.msg_bytes.Unblock_Control::5 628808 +system.ruby.network.routers5.percent_links_utilized 12.551928 +system.ruby.network.routers5.msg_count.Request_Control::2 78590 +system.ruby.network.routers5.msg_count.Request_Control::3 45 +system.ruby.network.routers5.msg_count.Response_Data::4 81153 +system.ruby.network.routers5.msg_count.Response_Control::4 1094141 +system.ruby.network.routers5.msg_count.Writeback_Data::5 27387 +system.ruby.network.routers5.msg_count.Writeback_Control::2 74179 +system.ruby.network.routers5.msg_count.Writeback_Control::3 74179 +system.ruby.network.routers5.msg_count.Writeback_Control::5 46760 +system.ruby.network.routers5.msg_count.Broadcast_Control::3 549374 +system.ruby.network.routers5.msg_count.Unblock_Control::5 78618 +system.ruby.network.routers5.msg_bytes.Request_Control::2 628720 +system.ruby.network.routers5.msg_bytes.Request_Control::3 360 +system.ruby.network.routers5.msg_bytes.Response_Data::4 5843016 +system.ruby.network.routers5.msg_bytes.Response_Control::4 8753128 +system.ruby.network.routers5.msg_bytes.Writeback_Data::5 1971864 +system.ruby.network.routers5.msg_bytes.Writeback_Control::2 593432 +system.ruby.network.routers5.msg_bytes.Writeback_Control::3 593432 +system.ruby.network.routers5.msg_bytes.Writeback_Control::5 374080 +system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4394992 +system.ruby.network.routers5.msg_bytes.Unblock_Control::5 628944 +system.ruby.network.routers6.percent_links_utilized 12.555969 +system.ruby.network.routers6.msg_count.Request_Control::2 78600 +system.ruby.network.routers6.msg_count.Request_Control::3 62 +system.ruby.network.routers6.msg_count.Response_Data::4 81186 +system.ruby.network.routers6.msg_count.Response_Control::4 1094124 +system.ruby.network.routers6.msg_count.Writeback_Data::5 27482 +system.ruby.network.routers6.msg_count.Writeback_Control::2 74144 +system.ruby.network.routers6.msg_count.Writeback_Control::3 74144 +system.ruby.network.routers6.msg_count.Writeback_Control::5 46633 +system.ruby.network.routers6.msg_count.Broadcast_Control::3 549359 +system.ruby.network.routers6.msg_count.Unblock_Control::5 78625 +system.ruby.network.routers6.msg_bytes.Request_Control::2 628800 +system.ruby.network.routers6.msg_bytes.Request_Control::3 496 +system.ruby.network.routers6.msg_bytes.Response_Data::4 5845392 +system.ruby.network.routers6.msg_bytes.Response_Control::4 8752992 +system.ruby.network.routers6.msg_bytes.Writeback_Data::5 1978704 +system.ruby.network.routers6.msg_bytes.Writeback_Control::2 593152 +system.ruby.network.routers6.msg_bytes.Writeback_Control::3 593152 +system.ruby.network.routers6.msg_bytes.Writeback_Control::5 373064 +system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4394872 +system.ruby.network.routers6.msg_bytes.Unblock_Control::5 629000 +system.ruby.network.routers7.percent_links_utilized 12.542424 +system.ruby.network.routers7.msg_count.Request_Control::2 78243 +system.ruby.network.routers7.msg_count.Request_Control::3 42 +system.ruby.network.routers7.msg_count.Response_Data::4 80772 +system.ruby.network.routers7.msg_count.Response_Control::4 1092029 +system.ruby.network.routers7.msg_count.Writeback_Data::5 27935 +system.ruby.network.routers7.msg_count.Writeback_Control::2 73931 +system.ruby.network.routers7.msg_count.Writeback_Control::3 73931 +system.ruby.network.routers7.msg_count.Writeback_Control::5 45971 +system.ruby.network.routers7.msg_count.Broadcast_Control::3 549721 +system.ruby.network.routers7.msg_count.Unblock_Control::5 78264 +system.ruby.network.routers7.msg_bytes.Request_Control::2 625944 +system.ruby.network.routers7.msg_bytes.Request_Control::3 336 +system.ruby.network.routers7.msg_bytes.Response_Data::4 5815584 +system.ruby.network.routers7.msg_bytes.Response_Control::4 8736232 +system.ruby.network.routers7.msg_bytes.Writeback_Data::5 2011320 +system.ruby.network.routers7.msg_bytes.Writeback_Control::2 591448 +system.ruby.network.routers7.msg_bytes.Writeback_Control::3 591448 +system.ruby.network.routers7.msg_bytes.Writeback_Control::5 367768 +system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4397768 +system.ruby.network.routers7.msg_bytes.Unblock_Control::5 626112 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 811546 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 597507 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 214013 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 40249 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 29190456 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 408038 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 19549348 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 49147842 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 60.560759 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 4395939 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 8156080 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2068734 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1377698 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 6011646 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memNotOld 7180359 # memory stalls due to anti starvation -system.ruby.dir_cntrl0.memBuffer.memBankCount | 25525 3.15% 3.15% | 25047 3.09% 6.23% | 25485 3.14% 9.37% | 25568 3.15% 12.52% | 25590 3.15% 15.68% | 25517 3.14% 18.82% | 25716 3.17% 21.99% | 25410 3.13% 25.12% | 25335 3.12% 28.24% | 25484 3.14% 31.38% | 25540 3.15% 34.53% | 25414 3.13% 37.66% | 25457 3.14% 40.80% | 25303 3.12% 43.92% | 25416 3.13% 47.05% | 25361 3.13% 50.17% | 25622 3.16% 53.33% | 25433 3.13% 56.46% | 25171 3.10% 59.56% | 25194 3.10% 62.67% | 25397 3.13% 65.80% | 25498 3.14% 68.94% | 25175 3.10% 72.04% | 25106 3.09% 75.14% | 25081 3.09% 78.23% | 25088 3.09% 81.32% | 24820 3.06% 84.38% | 25599 3.15% 87.53% | 25387 3.13% 90.66% | 25331 3.12% 93.78% | 25290 3.12% 96.90% | 25186 3.10% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 811546 # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memReq 829348 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 607726 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 221589 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 41118 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 29891924 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 415495 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 20161616 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 50469035 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 60.853870 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 4511761 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 8350172 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2127555 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1394322 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 6158676 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memNotOld 7349438 # memory stalls due to anti starvation +system.ruby.dir_cntrl0.memBuffer.memBankCount | 26193 3.16% 3.16% | 26128 3.15% 6.31% | 26105 3.15% 9.46% | 25961 3.13% 12.59% | 26151 3.15% 15.74% | 26370 3.18% 18.92% | 25970 3.13% 22.05% | 26083 3.15% 25.20% | 25945 3.13% 28.32% | 25763 3.11% 31.43% | 26082 3.14% 34.58% | 26004 3.14% 37.71% | 26080 3.14% 40.86% | 26077 3.14% 44.00% | 25922 3.13% 47.13% | 25819 3.11% 50.24% | 25968 3.13% 53.37% | 25870 3.12% 56.49% | 25867 3.12% 59.61% | 25796 3.11% 62.72% | 25881 3.12% 65.84% | 25705 3.10% 68.94% | 25499 3.07% 72.01% | 25623 3.09% 75.10% | 26078 3.14% 78.25% | 25821 3.11% 81.36% | 25430 3.07% 84.43% | 25795 3.11% 87.54% | 25934 3.13% 90.66% | 25506 3.08% 93.74% | 25828 3.11% 96.85% | 26094 3.15% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 829348 # Number of accesses per bank system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers8.percent_links_utilized 46.105327 -system.ruby.network.routers8.msg_count.Request_Control::2 617400 -system.ruby.network.routers8.msg_count.Request_Control::3 439 -system.ruby.network.routers8.msg_count.Response_Data::4 597502 -system.ruby.network.routers8.msg_count.Writeback_Data::5 214023 -system.ruby.network.routers8.msg_count.Writeback_Control::2 582292 -system.ruby.network.routers8.msg_count.Writeback_Control::3 582292 -system.ruby.network.routers8.msg_count.Writeback_Control::5 368046 -system.ruby.network.routers8.msg_count.Broadcast_Control::3 616961 -system.ruby.network.routers8.msg_count.Unblock_Control::5 617596 -system.ruby.network.routers8.msg_bytes.Request_Control::2 4939200 -system.ruby.network.routers8.msg_bytes.Request_Control::3 3512 -system.ruby.network.routers8.msg_bytes.Response_Data::4 43020144 -system.ruby.network.routers8.msg_bytes.Writeback_Data::5 15409656 -system.ruby.network.routers8.msg_bytes.Writeback_Control::2 4658336 -system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4658336 -system.ruby.network.routers8.msg_bytes.Writeback_Control::5 2944368 -system.ruby.network.routers8.msg_bytes.Broadcast_Control::3 4935688 -system.ruby.network.routers8.msg_bytes.Unblock_Control::5 4940768 -system.ruby.network.routers9.percent_links_utilized 18.086419 -system.ruby.network.routers9.msg_count.Request_Control::2 617401 -system.ruby.network.routers9.msg_count.Request_Control::3 439 -system.ruby.network.routers9.msg_count.Response_Data::4 617377 -system.ruby.network.routers9.msg_count.Response_Control::4 4299263 -system.ruby.network.routers9.msg_count.Writeback_Data::5 214023 -system.ruby.network.routers9.msg_count.Writeback_Control::2 582292 -system.ruby.network.routers9.msg_count.Writeback_Control::3 582292 -system.ruby.network.routers9.msg_count.Writeback_Control::5 368047 -system.ruby.network.routers9.msg_count.Broadcast_Control::3 4318727 -system.ruby.network.routers9.msg_count.Unblock_Control::5 617596 -system.ruby.network.routers9.msg_bytes.Request_Control::2 4939208 -system.ruby.network.routers9.msg_bytes.Request_Control::3 3512 -system.ruby.network.routers9.msg_bytes.Response_Data::4 44451144 -system.ruby.network.routers9.msg_bytes.Response_Control::4 34394104 -system.ruby.network.routers9.msg_bytes.Writeback_Data::5 15409656 -system.ruby.network.routers9.msg_bytes.Writeback_Control::2 4658336 -system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4658336 -system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2944376 -system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 34549816 -system.ruby.network.routers9.msg_bytes.Unblock_Control::5 4940768 -system.ruby.network.msg_count.Request_Control 1853520 -system.ruby.network.msg_count.Response_Data 1852131 -system.ruby.network.msg_count.Response_Control 12897795 -system.ruby.network.msg_count.Writeback_Data 642069 -system.ruby.network.msg_count.Writeback_Control 4597894 -system.ruby.network.msg_count.Broadcast_Control 9254415 -system.ruby.network.msg_count.Unblock_Control 1852789 -system.ruby.network.msg_byte.Request_Control 14828160 -system.ruby.network.msg_byte.Response_Data 133353432 -system.ruby.network.msg_byte.Response_Control 103182360 -system.ruby.network.msg_byte.Writeback_Data 46228968 -system.ruby.network.msg_byte.Writeback_Control 36783152 -system.ruby.network.msg_byte.Broadcast_Control 74035320 -system.ruby.network.msg_byte.Unblock_Control 14822312 +system.ruby.network.routers8.percent_links_utilized 46.048912 +system.ruby.network.routers8.msg_count.Request_Control::2 628329 +system.ruby.network.routers8.msg_count.Request_Control::3 423 +system.ruby.network.routers8.msg_count.Response_Data::4 607721 +system.ruby.network.routers8.msg_count.Writeback_Data::5 221601 +system.ruby.network.routers8.msg_count.Writeback_Control::2 592925 +system.ruby.network.routers8.msg_count.Writeback_Control::3 592925 +system.ruby.network.routers8.msg_count.Writeback_Control::5 371123 +system.ruby.network.routers8.msg_count.Broadcast_Control::3 627906 +system.ruby.network.routers8.msg_count.Unblock_Control::5 628502 +system.ruby.network.routers8.msg_bytes.Request_Control::2 5026632 +system.ruby.network.routers8.msg_bytes.Request_Control::3 3384 +system.ruby.network.routers8.msg_bytes.Response_Data::4 43755912 +system.ruby.network.routers8.msg_bytes.Writeback_Data::5 15955272 +system.ruby.network.routers8.msg_bytes.Writeback_Control::2 4743400 +system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4743400 +system.ruby.network.routers8.msg_bytes.Writeback_Control::5 2968984 +system.ruby.network.routers8.msg_bytes.Broadcast_Control::3 5023248 +system.ruby.network.routers8.msg_bytes.Unblock_Control::5 5028016 +system.ruby.network.routers9.percent_links_utilized 18.047053 +system.ruby.network.routers9.msg_count.Request_Control::2 628329 +system.ruby.network.routers9.msg_count.Request_Control::3 423 +system.ruby.network.routers9.msg_count.Response_Data::4 628298 +system.ruby.network.routers9.msg_count.Response_Control::4 4375187 +system.ruby.network.routers9.msg_count.Writeback_Data::5 221601 +system.ruby.network.routers9.msg_count.Writeback_Control::2 592925 +system.ruby.network.routers9.msg_count.Writeback_Control::3 592925 +system.ruby.network.routers9.msg_count.Writeback_Control::5 371123 +system.ruby.network.routers9.msg_count.Broadcast_Control::3 4395342 +system.ruby.network.routers9.msg_count.Unblock_Control::5 628502 +system.ruby.network.routers9.msg_bytes.Request_Control::2 5026632 +system.ruby.network.routers9.msg_bytes.Request_Control::3 3384 +system.ruby.network.routers9.msg_bytes.Response_Data::4 45237456 +system.ruby.network.routers9.msg_bytes.Response_Control::4 35001496 +system.ruby.network.routers9.msg_bytes.Writeback_Data::5 15955272 +system.ruby.network.routers9.msg_bytes.Writeback_Control::2 4743400 +system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4743400 +system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2968984 +system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 35162736 +system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5028016 +system.ruby.network.msg_count.Request_Control 1886256 +system.ruby.network.msg_count.Response_Data 1884894 +system.ruby.network.msg_count.Response_Control 13125561 +system.ruby.network.msg_count.Writeback_Data 664803 +system.ruby.network.msg_count.Writeback_Control 4670919 +system.ruby.network.msg_count.Broadcast_Control 9418590 +system.ruby.network.msg_count.Unblock_Control 1885506 +system.ruby.network.msg_byte.Request_Control 15090048 +system.ruby.network.msg_byte.Response_Data 135712368 +system.ruby.network.msg_byte.Response_Control 105004488 +system.ruby.network.msg_byte.Writeback_Data 47865816 +system.ruby.network.msg_byte.Writeback_Control 37367352 +system.ruby.network.msg_byte.Broadcast_Control 75348720 +system.ruby.network.msg_byte.Unblock_Control 15084048 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 99395 # number of read accesses completed -system.cpu0.num_writes 53721 # number of write accesses completed +system.cpu0.num_reads 99506 # number of read accesses completed +system.cpu0.num_writes 55459 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99652 # number of read accesses completed -system.cpu1.num_writes 54399 # number of write accesses completed +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 56034 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 54294 # number of write accesses completed +system.cpu2.num_reads 99774 # number of read accesses completed +system.cpu2.num_writes 55650 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99790 # number of read accesses completed -system.cpu3.num_writes 54193 # number of write accesses completed +system.cpu3.num_reads 99487 # number of read accesses completed +system.cpu3.num_writes 55471 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99482 # number of read accesses completed -system.cpu4.num_writes 53726 # number of write accesses completed +system.cpu4.num_reads 99515 # number of read accesses completed +system.cpu4.num_writes 55612 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99470 # number of read accesses completed -system.cpu5.num_writes 54029 # number of write accesses completed +system.cpu5.num_reads 99579 # number of read accesses completed +system.cpu5.num_writes 55211 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99753 # number of read accesses completed -system.cpu6.num_writes 54335 # number of write accesses completed +system.cpu6.num_reads 99679 # number of read accesses completed +system.cpu6.num_writes 55618 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99102 # number of read accesses completed -system.cpu7.num_writes 53848 # number of write accesses completed +system.cpu7.num_reads 98792 # number of read accesses completed +system.cpu7.num_writes 55627 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers0.throttle0.link_utilization 15.875388 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 67 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 76886 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 535441 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 72619 -system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3 540121 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3 536 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5535792 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 4283528 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 580952 -system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3 4320968 -system.ruby.network.routers0.throttle1.link_utilization 9.236653 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 76891 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 2445 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::4 537741 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 26490 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 72619 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 46104 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 76912 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 615128 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 176040 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::4 4301928 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 1907280 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 580952 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 368832 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 615296 -system.ruby.network.routers1.throttle0.link_utilization 15.944041 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::3 47 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 77389 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::4 538997 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 73022 -system.ruby.network.routers1.throttle0.msg_count.Broadcast_Control::3 539613 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::3 376 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5572008 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::4 4311976 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 584176 -system.ruby.network.routers1.throttle0.msg_bytes.Broadcast_Control::3 4316904 -system.ruby.network.routers1.throttle1.link_utilization 9.278080 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 77392 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 2504 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 537154 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::5 26871 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 73022 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::5 46119 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::5 77422 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 619136 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 180288 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 4297232 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::5 1934712 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 584176 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::5 368952 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::5 619376 -system.ruby.network.routers2.throttle0.link_utilization 15.919411 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::3 56 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 77214 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::4 537730 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 72821 -system.ruby.network.routers2.throttle0.msg_count.Broadcast_Control::3 539797 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::3 448 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5559408 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::4 4301840 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 582568 -system.ruby.network.routers2.throttle0.msg_bytes.Broadcast_Control::3 4318376 -system.ruby.network.routers2.throttle1.link_utilization 9.262672 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 77216 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 2492 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::4 537359 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 26730 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 72821 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 46059 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 77245 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 617728 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 179424 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4 4298872 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 1924560 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 582568 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 368472 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 617960 -system.ruby.network.routers3.throttle0.link_utilization 15.935501 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::3 60 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 77328 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 538521 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 72965 -system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3 539692 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3 480 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5567616 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 4308168 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 583720 -system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3 4317536 -system.ruby.network.routers3.throttle1.link_utilization 9.277450 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::2 77331 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 2469 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::4 537281 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5 26915 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2 72965 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5 46025 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5 77353 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2 618648 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 177768 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4 4298248 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5 1937880 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2 583720 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5 368200 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5 618824 -system.ruby.network.routers4.throttle0.link_utilization 15.909534 -system.ruby.network.routers4.throttle0.msg_count.Request_Control::3 48 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 77143 -system.ruby.network.routers4.throttle0.msg_count.Response_Control::4 537177 -system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 72792 -system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3 539876 -system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3 384 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5554296 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4 4297416 -system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 582336 -system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3 4319008 -system.ruby.network.routers4.throttle1.link_utilization 9.255089 -system.ruby.network.routers4.throttle1.msg_count.Request_Control::2 77146 -system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 2476 -system.ruby.network.routers4.throttle1.msg_count.Response_Control::4 537446 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5 26652 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2 72792 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5 46109 -system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5 77174 -system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2 617168 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 178272 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4 4299568 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5 1918944 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2 582336 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5 368872 -system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5 617392 -system.ruby.network.routers5.throttle0.link_utilization 15.887509 -system.ruby.network.routers5.throttle0.msg_count.Request_Control::3 51 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 76990 -system.ruby.network.routers5.throttle0.msg_count.Response_Control::4 536067 -system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 72564 -system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3 540035 -system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3 408 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5543280 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4 4288536 -system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 580512 -system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3 4320280 -system.ruby.network.routers5.throttle1.link_utilization 9.256668 -system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 76992 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 2514 -system.ruby.network.routers5.throttle1.msg_count.Response_Control::4 537570 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5 26712 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2 72564 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5 45823 -system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5 77019 -system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 615936 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 181008 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4 4300560 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5 1923264 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 580512 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 366584 -system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 616152 -system.ruby.network.routers6.throttle0.link_utilization 15.964409 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 52 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 77539 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 540002 -system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 73169 -system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 539467 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 416 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5582808 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4320016 -system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 585352 -system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4315736 -system.ruby.network.routers6.throttle1.link_utilization 9.289019 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 77542 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 2478 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::4 537039 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5 26999 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2 73171 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::5 46140 -system.ruby.network.routers6.throttle1.msg_count.Unblock_Control::5 77567 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 620336 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 178416 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::4 4296312 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Data::5 1943928 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::2 585368 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::5 369120 -system.ruby.network.routers6.throttle1.msg_bytes.Unblock_Control::5 620536 -system.ruby.network.routers7.throttle0.link_utilization 15.872058 -system.ruby.network.routers7.throttle0.msg_count.Request_Control::3 58 -system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 76888 -system.ruby.network.routers7.throttle0.msg_count.Response_Control::4 535320 -system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 72340 -system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 540126 -system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 464 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5535936 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4282560 -system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 578720 -system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4321008 -system.ruby.network.routers7.throttle1.link_utilization 9.246738 -system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 76892 -system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 2497 -system.ruby.network.routers7.throttle1.msg_count.Response_Control::4 537687 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5 26654 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2 72340 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::5 45668 -system.ruby.network.routers7.throttle1.msg_count.Unblock_Control::5 76905 -system.ruby.network.routers7.throttle1.msg_bytes.Request_Control::2 615136 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 179784 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Control::4 4301496 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Data::5 1919088 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::2 578720 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::5 365344 -system.ruby.network.routers7.throttle1.msg_bytes.Unblock_Control::5 615240 -system.ruby.network.routers8.throttle0.link_utilization 35.469802 -system.ruby.network.routers8.throttle0.msg_count.Request_Control::2 617400 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Data::5 214023 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2 582292 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5 368046 -system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5 617596 -system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2 4939200 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5 15409656 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2 4658336 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5 2944368 -system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5 4940768 -system.ruby.network.routers8.throttle1.link_utilization 56.740852 -system.ruby.network.routers8.throttle1.msg_count.Request_Control::3 439 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 597502 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 582292 -system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3 616961 -system.ruby.network.routers8.throttle1.msg_bytes.Request_Control::3 3512 -system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43020144 -system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4658336 -system.ruby.network.routers8.throttle1.msg_bytes.Broadcast_Control::3 4935688 -system.ruby.network.routers9.throttle0.link_utilization 15.875423 -system.ruby.network.routers9.throttle0.msg_count.Request_Control::3 67 -system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 76886 -system.ruby.network.routers9.throttle0.msg_count.Response_Control::4 535445 -system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 72619 -system.ruby.network.routers9.throttle0.msg_count.Broadcast_Control::3 540121 -system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3 536 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5535792 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4 4283560 -system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 580952 -system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4320968 -system.ruby.network.routers9.throttle1.link_utilization 15.944041 -system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 47 -system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 77389 -system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 538997 -system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 73022 -system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 539613 -system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 376 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5572008 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4 4311976 -system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 584176 -system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4316904 -system.ruby.network.routers9.throttle2.link_utilization 15.919446 -system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 56 -system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 77214 -system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 537730 -system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 72821 -system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 539797 -system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 448 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5559408 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4301840 -system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 582568 -system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4318376 -system.ruby.network.routers9.throttle3.link_utilization 15.935501 -system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 60 -system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 77328 -system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 538521 -system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 72965 -system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 539692 -system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 480 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5567616 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4308168 -system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 583720 -system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4317536 -system.ruby.network.routers9.throttle4.link_utilization 15.909568 -system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 48 -system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 77143 -system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 537181 -system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 72792 -system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 539876 -system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 384 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5554296 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4297448 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 582336 -system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4319008 -system.ruby.network.routers9.throttle5.link_utilization 15.887509 -system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 51 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 76990 -system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 536067 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 72564 -system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 540035 -system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 408 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5543280 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4288536 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 580512 -system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4320280 -system.ruby.network.routers9.throttle6.link_utilization 15.964409 -system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 52 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 77539 -system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 540002 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 73169 -system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 539467 -system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 416 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5582808 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4320016 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 585352 -system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4315736 -system.ruby.network.routers9.throttle7.link_utilization 15.872058 -system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 58 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 76888 -system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 535320 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 72340 -system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 540126 -system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 464 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5535936 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4282560 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 578720 -system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4321008 -system.ruby.network.routers9.throttle8.link_utilization 35.469819 -system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 617401 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 214023 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 582292 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 368047 -system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 617596 -system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 4939208 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15409656 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4658336 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2944376 -system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 4940768 +system.ruby.network.routers0.throttle0.link_utilization 15.823528 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 59 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78309 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 545336 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+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 46381 +system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 78563 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 628360 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 180288 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4 4375624 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 1996272 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 593024 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 371048 +system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 628504 +system.ruby.network.routers3.throttle0.link_utilization 15.866275 +system.ruby.network.routers3.throttle0.msg_count.Request_Control::3 54 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78635 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 547558 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 74201 +system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3 549323 +system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3 432 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5661720 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 4380464 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 593608 +system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3 4394584 +system.ruby.network.routers3.throttle1.link_utilization 9.273176 +system.ruby.network.routers3.throttle1.msg_count.Request_Control::2 78639 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 2621 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::4 546756 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5 27761 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2 74201 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5 46424 +system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5 78652 +system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2 629112 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 188712 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4 4374048 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5 1998792 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2 593608 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5 371392 +system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5 629216 +system.ruby.network.routers4.throttle0.link_utilization 15.855517 +system.ruby.network.routers4.throttle0.msg_count.Request_Control::3 57 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78565 +system.ruby.network.routers4.throttle0.msg_count.Response_Control::4 547021 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 74027 +system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3 549387 +system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3 456 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5656680 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4 4376168 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 592216 +system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3 4395096 +system.ruby.network.routers4.throttle1.link_utilization 9.262181 +system.ruby.network.routers4.throttle1.msg_count.Request_Control::2 78569 +system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 2579 +system.ruby.network.routers4.throttle1.msg_count.Response_Control::4 546865 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5 27693 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2 74027 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5 46298 +system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5 78601 +system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2 628552 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 185688 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4 4374920 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5 1993896 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2 592216 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5 370384 +system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5 628808 +system.ruby.network.routers5.throttle0.link_utilization 15.860457 +system.ruby.network.routers5.throttle0.msg_count.Request_Control::3 45 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78586 +system.ruby.network.routers5.throttle0.msg_count.Response_Control::4 547290 +system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 74179 +system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3 549374 +system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3 360 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5658192 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4 4378320 +system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 593432 +system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3 4394992 +system.ruby.network.routers5.throttle1.link_utilization 9.243400 +system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 78590 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 2567 +system.ruby.network.routers5.throttle1.msg_count.Response_Control::4 546851 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5 27387 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2 74179 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5 46760 +system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5 78618 +system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 628720 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 184824 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4 4374808 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5 1971864 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 593432 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 374080 +system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 628944 +system.ruby.network.routers6.throttle0.link_utilization 15.861031 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 62 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78597 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 547292 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 74144 +system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 549359 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 496 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5658984 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4378336 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 593152 +system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4394872 +system.ruby.network.routers6.throttle1.link_utilization 9.250907 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 78600 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 2589 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::4 546832 +system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5 27482 +system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2 74144 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+system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 73931 +system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 549721 +system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 336 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5633208 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4358392 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 591448 +system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4397768 +system.ruby.network.routers7.throttle1.link_utilization 9.270989 +system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 78243 +system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 2533 +system.ruby.network.routers7.throttle1.msg_count.Response_Control::4 547230 +system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5 27935 +system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2 73931 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+system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4397184 +system.ruby.network.routers9.throttle1.link_utilization 15.891761 +system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 53 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78825 +system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 548917 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 74350 +system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 549124 +system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 424 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5675400 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4 4391336 +system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 594800 +system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4392992 +system.ruby.network.routers9.throttle2.link_utilization 15.854335 +system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 51 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78542 +system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 546974 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 74128 +system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 549406 +system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 408 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5655024 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4375792 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 593024 +system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4395248 +system.ruby.network.routers9.throttle3.link_utilization 15.866275 +system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 54 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78635 +system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 547558 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 74201 +system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 549323 +system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 432 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5661720 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4380464 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 593608 +system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4394584 +system.ruby.network.routers9.throttle4.link_utilization 15.855517 +system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 57 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78565 +system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 547021 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 74027 +system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 549387 +system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 456 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5656680 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4376168 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 592216 +system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4395096 +system.ruby.network.routers9.throttle5.link_utilization 15.860457 +system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 45 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78586 +system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 547290 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 74179 +system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 549374 +system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 360 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5658192 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4378320 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 593432 +system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4394992 +system.ruby.network.routers9.throttle6.link_utilization 15.861031 +system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 62 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78597 +system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 547292 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 74144 +system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 549359 +system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 496 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5658984 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4378336 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 593152 +system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4394872 +system.ruby.network.routers9.throttle7.link_utilization 15.813859 +system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 42 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78239 +system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 544799 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 73931 +system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 549721 +system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 336 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5633208 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4358392 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 591448 +system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4397768 +system.ruby.network.routers9.throttle8.link_utilization 35.596713 +system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 628329 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 221601 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 592925 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 371123 +system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 628502 +system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5026632 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15955272 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4743400 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2968984 +system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5028016 system.ruby.LD.latency_hist::bucket_size 1024 system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 401404 -system.ruby.LD.latency_hist::mean 1200.205225 -system.ruby.LD.latency_hist::gmean 820.467518 -system.ruby.LD.latency_hist::stdev 896.107731 -system.ruby.LD.latency_hist | 206231 51.38% 51.38% | 106792 26.60% 77.98% | 80227 19.99% 97.97% | 8012 2.00% 99.96% | 141 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 401404 -system.ruby.LD.hit_latency_hist::bucket_size 256 -system.ruby.LD.hit_latency_hist::max_bucket 2559 -system.ruby.LD.hit_latency_hist::samples 496 -system.ruby.LD.hit_latency_hist::mean 129.788306 -system.ruby.LD.hit_latency_hist::gmean 40.678454 -system.ruby.LD.hit_latency_hist::stdev 179.340502 -system.ruby.LD.hit_latency_hist | 409 82.46% 82.46% | 72 14.52% 96.98% | 8 1.61% 98.59% | 5 1.01% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 496 +system.ruby.LD.latency_hist::samples 404548 +system.ruby.LD.latency_hist::mean 1203.834526 +system.ruby.LD.latency_hist::gmean 822.623780 +system.ruby.LD.latency_hist::stdev 899.503786 +system.ruby.LD.latency_hist | 207765 51.36% 51.36% | 106851 26.41% 77.77% | 81488 20.14% 97.91% | 8228 2.03% 99.95% | 210 0.05% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 404548 +system.ruby.LD.hit_latency_hist::bucket_size 128 +system.ruby.LD.hit_latency_hist::max_bucket 1279 +system.ruby.LD.hit_latency_hist::samples 490 +system.ruby.LD.hit_latency_hist::mean 139.479592 +system.ruby.LD.hit_latency_hist::gmean 44.536825 +system.ruby.LD.hit_latency_hist::stdev 171.671956 +system.ruby.LD.hit_latency_hist | 282 57.55% 57.55% | 119 24.29% 81.84% | 50 10.20% 92.04% | 20 4.08% 96.12% | 8 1.63% 97.76% | 6 1.22% 98.98% | 1 0.20% 99.18% | 3 0.61% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 490 system.ruby.LD.miss_latency_hist::bucket_size 1024 system.ruby.LD.miss_latency_hist::max_bucket 10239 -system.ruby.LD.miss_latency_hist::samples 400908 -system.ruby.LD.miss_latency_hist::mean 1201.529535 -system.ruby.LD.miss_latency_hist::gmean 823.522657 -system.ruby.LD.miss_latency_hist::stdev 895.847928 -system.ruby.LD.miss_latency_hist | 205737 51.32% 51.32% | 106790 26.64% 77.95% | 80227 20.01% 97.97% | 8012 2.00% 99.96% | 141 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 400908 -system.ruby.ST.latency_hist::bucket_size 512 -system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 216712 -system.ruby.ST.latency_hist::mean 1199.682090 -system.ruby.ST.latency_hist::gmean 820.928261 -system.ruby.ST.latency_hist::stdev 895.164370 -system.ruby.ST.latency_hist | 72217 33.32% 33.32% | 39245 18.11% 51.43% | 26157 12.07% 63.50% | 31400 14.49% 77.99% | 29405 13.57% 91.56% | 13948 6.44% 98.00% | 3617 1.67% 99.67% | 640 0.30% 99.96% | 77 0.04% 100.00% | 6 0.00% 100.00% -system.ruby.ST.latency_hist::total 216712 -system.ruby.ST.hit_latency_hist::bucket_size 128 -system.ruby.ST.hit_latency_hist::max_bucket 1279 -system.ruby.ST.hit_latency_hist::samples 241 -system.ruby.ST.hit_latency_hist::mean 140.414938 -system.ruby.ST.hit_latency_hist::gmean 42.603184 -system.ruby.ST.hit_latency_hist::stdev 171.207823 -system.ruby.ST.hit_latency_hist | 141 58.51% 58.51% | 50 20.75% 79.25% | 31 12.86% 92.12% | 6 2.49% 94.61% | 6 2.49% 97.10% | 6 2.49% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 241 -system.ruby.ST.miss_latency_hist::bucket_size 512 -system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 216471 -system.ruby.ST.miss_latency_hist::mean 1200.861386 -system.ruby.ST.miss_latency_hist::gmean 823.636647 -system.ruby.ST.miss_latency_hist::stdev 894.945970 -system.ruby.ST.miss_latency_hist | 71989 33.26% 33.26% | 39232 18.12% 51.38% | 26157 12.08% 63.46% | 31400 14.51% 77.97% | 29405 13.58% 91.55% | 13948 6.44% 98.00% | 3617 1.67% 99.67% | 640 0.30% 99.96% | 77 0.04% 100.00% | 6 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 216471 +system.ruby.LD.miss_latency_hist::samples 404058 +system.ruby.LD.miss_latency_hist::mean 1205.125267 +system.ruby.LD.miss_latency_hist::gmean 825.538095 +system.ruby.LD.miss_latency_hist::stdev 899.264768 +system.ruby.LD.miss_latency_hist | 207276 51.30% 51.30% | 106850 26.44% 77.74% | 81488 20.17% 97.91% | 8228 2.04% 99.95% | 210 0.05% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 404058 +system.ruby.ST.latency_hist::bucket_size 1024 +system.ruby.ST.latency_hist::max_bucket 10239 +system.ruby.ST.latency_hist::samples 224507 +system.ruby.ST.latency_hist::mean 1205.952981 +system.ruby.ST.latency_hist::gmean 825.731714 +system.ruby.ST.latency_hist::stdev 898.165229 +system.ruby.ST.latency_hist | 114784 51.13% 51.13% | 59883 26.67% 77.80% | 45124 20.10% 97.90% | 4585 2.04% 99.94% | 130 0.06% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 224507 +system.ruby.ST.hit_latency_hist::bucket_size 256 +system.ruby.ST.hit_latency_hist::max_bucket 2559 +system.ruby.ST.hit_latency_hist::samples 262 +system.ruby.ST.hit_latency_hist::mean 141.606870 +system.ruby.ST.hit_latency_hist::gmean 39.890479 +system.ruby.ST.hit_latency_hist::stdev 210.424116 +system.ruby.ST.hit_latency_hist | 211 80.53% 80.53% | 40 15.27% 95.80% | 6 2.29% 98.09% | 3 1.15% 99.24% | 0 0.00% 99.24% | 1 0.38% 99.62% | 1 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 262 +system.ruby.ST.miss_latency_hist::bucket_size 1024 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 138 +system.ruby.L1Cache.hit_mach_latency_hist::gmean 2 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 142 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 142 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 19877 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1068.632842 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 609.184476 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 891.446161 -system.ruby.L1Cache.miss_mach_latency_hist | 8066 40.58% 40.58% | 2780 13.99% 54.57% | 2446 12.31% 66.87% | 2998 15.08% 81.95% | 2398 12.06% 94.02% | 956 4.81% 98.83% | 195 0.98% 99.81% | 36 0.18% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 19877 +system.ruby.L1Cache.miss_mach_latency_hist::samples 20582 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1078.160286 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 614.806458 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 895.586319 +system.ruby.L1Cache.miss_mach_latency_hist | 8287 40.26% 40.26% | 2815 13.68% 53.94% | 2557 12.42% 66.36% | 3192 15.51% 81.87% | 2465 11.98% 93.85% | 962 4.67% 98.52% | 261 1.27% 99.79% | 37 0.18% 99.97% | 5 0.02% 100.00% | 1 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 20582 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 19438 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 985.051343 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 380.663652 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 886.076563 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 8575 44.11% 44.11% | 2388 12.29% 56.40% | 2456 12.64% 69.03% | 2961 15.23% 84.27% | 2158 11.10% 95.37% | 735 3.78% 99.15% | 140 0.72% 99.87% | 24 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 19438 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 20159 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 995.735453 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 387.436377 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 890.441418 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 8785 43.58% 43.58% | 2515 12.48% 56.05% | 2495 12.38% 68.43% | 3188 15.81% 84.25% | 2171 10.77% 95.01% | 809 4.01% 99.03% | 167 0.83% 99.86% | 27 0.13% 99.99% | 1 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 20159 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::bucket_size 128 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::max_bucket 1279 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 19438 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 56.696677 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 19.964374 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 97.360116 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 16154 83.11% 83.11% | 2126 10.94% 94.04% | 813 4.18% 98.23% | 254 1.31% 99.53% | 69 0.35% 99.89% | 19 0.10% 99.98% | 2 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 19438 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0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 20159 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::bucket_size 2 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::max_bucket 19 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 19438 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 1.883990 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 1.916605 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 9557 49.17% 49.17% | 7546 38.82% 87.99% | 1175 6.04% 94.03% | 733 3.77% 97.80% | 258 1.33% 99.13% | 122 0.63% 99.76% | 25 0.13% 99.89% | 17 0.09% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 19438 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 20159 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0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 599 +system.ruby.L2Cache.hit_mach_latency_hist::samples 610 +system.ruby.L2Cache.hit_mach_latency_hist::mean 172.396721 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 87.476555 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 192.743659 +system.ruby.L2Cache.hit_mach_latency_hist | 470 77.05% 77.05% | 110 18.03% 95.08% | 20 3.28% 98.36% | 7 1.15% 99.51% | 1 0.16% 99.67% | 1 0.16% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 610 system.ruby.Directory.miss_mach_latency_hist::bucket_size 1024 system.ruby.Directory.miss_mach_latency_hist::max_bucket 10239 -system.ruby.Directory.miss_mach_latency_hist::samples 597502 -system.ruby.Directory.miss_mach_latency_hist::mean 1205.708521 -system.ruby.Directory.miss_mach_latency_hist::gmean 831.864990 -system.ruby.Directory.miss_mach_latency_hist::stdev 895.329653 -system.ruby.Directory.miss_mach_latency_hist | 306112 51.23% 51.23% | 158903 26.59% 77.83% | 120226 20.12% 97.95% | 12038 2.01% 99.96% | 222 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 597502 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 512 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 597502 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 986.665291 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 384.184543 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 885.752609 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 262430 43.92% 43.92% | 74515 12.47% 56.39% | 75171 12.58% 68.97% | 92711 15.52% 84.49% | 64576 10.81% 95.30% | 22828 3.82% 99.12% | 4553 0.76% 99.88% | 651 0.11% 99.99% | 67 0.01% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 597502 +system.ruby.Directory.miss_mach_latency_hist::samples 607721 +system.ruby.Directory.miss_mach_latency_hist::mean 1210.189536 +system.ruby.Directory.miss_mach_latency_hist::gmean 834.981852 +system.ruby.Directory.miss_mach_latency_hist::stdev 898.577352 +system.ruby.Directory.miss_mach_latency_hist | 310698 51.13% 51.13% | 160982 26.49% 77.61% | 123185 20.27% 97.88% | 12515 2.06% 99.94% | 334 0.05% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 607721 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1024 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 10239 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0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.initial_to_forward::total 607721 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 8 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 79 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 597502 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 26.125536 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 26.035848 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 2.225599 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 583382 97.64% 97.64% | 14030 2.35% 99.98% | 90 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 597502 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34.10% 76.10% | 93561 15.40% 91.49% | 35437 5.83% 97.32% | 11568 1.90% 99.23% | 3450 0.57% 99.80% | 937 0.15% 99.95% | 242 0.04% 99.99% | 55 0.01% 100.00% | 6 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 607721 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 88 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 89 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 88 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 88 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 89 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 12936 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1063.318878 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 603.424470 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 892.034712 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 5286 40.86% 40.86% | 1815 14.03% 54.89% | 1582 12.23% 67.12% | 1934 14.95% 82.07% | 1539 11.90% 93.97% | 627 4.85% 98.82% | 128 0.99% 99.81% | 24 0.19% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 12936 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 256 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 2559 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 408 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 157.350490 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 77.903007 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 186.614207 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 321 78.68% 78.68% | 72 17.65% 96.32% | 8 1.96% 98.28% | 5 1.23% 99.51% | 1 0.25% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 408 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13181 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1077.888552 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 616.224244 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 894.841487 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 5304 40.24% 40.24% | 1827 13.86% 54.10% | 1624 12.32% 66.42% | 2023 15.35% 81.77% | 1594 12.09% 93.86% | 613 4.65% 98.51% | 170 1.29% 99.80% | 23 0.17% 99.98% | 2 0.02% 99.99% | 1 0.01% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13181 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 401 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 169.992519 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 88.681357 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 175.755106 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 193 48.13% 48.13% | 119 29.68% 77.81% | 50 12.47% 90.27% | 20 4.99% 95.26% | 8 2.00% 97.26% | 6 1.50% 98.75% | 1 0.25% 99.00% | 3 0.75% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 401 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 1024 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 10239 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 387972 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1206.137840 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 832.105820 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 895.608577 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 198636 51.20% 51.20% | 103274 26.62% 77.82% | 78061 20.12% 97.94% | 7860 2.03% 99.96% | 140 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 387972 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 390877 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1209.415893 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 833.719014 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 899.100909 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 200145 51.20% 51.20% | 103203 26.40% 77.61% | 79281 20.28% 97.89% | 8035 2.06% 99.95% | 207 0.05% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 390877 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 50 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 53 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 50 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 50 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 53 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 53 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 6941 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1078.536522 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 620.066573 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 890.327819 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 2780 40.05% 40.05% | 965 13.90% 53.95% | 864 12.45% 66.40% | 1064 15.33% 81.73% | 859 12.38% 94.11% | 329 4.74% 98.85% | 67 0.97% 99.81% | 12 0.17% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 6941 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 128 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 191 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 176.649215 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 94.884201 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 175.112077 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 91 47.64% 47.64% | 50 26.18% 73.82% | 31 16.23% 90.05% | 6 3.14% 93.19% | 6 3.14% 96.34% | 6 3.14% 99.48% | 1 0.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 191 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 209530 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1204.913583 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 831.419247 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 894.814552 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 69209 33.03% 33.03% | 38267 18.26% 51.29% | 25293 12.07% 63.37% | 30336 14.48% 77.84% | 28546 13.62% 91.47% | 13619 6.50% 97.97% | 3550 1.69% 99.66% | 628 0.30% 99.96% | 76 0.04% 100.00% | 6 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 209530 -system.ruby.L1Cache_Controller.Load | 50266 12.51% 12.51% | 50315 12.53% 25.04% | 50271 12.52% 37.56% | 50212 12.50% 50.06% | 50263 12.51% 62.57% | 50069 12.47% 75.04% | 50306 12.52% 87.56% | 49970 12.44% 100.00% -system.ruby.L1Cache_Controller.Load::total 401672 -system.ruby.L1Cache_Controller.Store | 26762 12.34% 12.34% | 27215 12.55% 24.89% | 27106 12.50% 37.39% | 27272 12.58% 49.96% | 27014 12.46% 62.42% | 27080 12.49% 74.91% | 27361 12.62% 87.52% | 27054 12.48% 100.00% -system.ruby.L1Cache_Controller.Store::total 216864 -system.ruby.L1Cache_Controller.L2_Replacement | 76877 12.45% 12.45% | 77378 12.53% 24.99% | 77204 12.51% 37.50% | 77319 12.53% 50.02% | 77135 12.50% 62.52% | 76978 12.47% 74.99% | 77528 12.56% 87.55% | 76877 12.45% 100.00% -system.ruby.L1Cache_Controller.L2_Replacement::total 617296 -system.ruby.L1Cache_Controller.L1_to_L2 | 839684 12.46% 12.46% | 843217 12.52% 24.98% | 843158 12.52% 37.50% | 840771 12.48% 49.98% | 842565 12.51% 62.49% | 841910 12.50% 74.98% | 845488 12.55% 87.54% | 839694 12.46% 100.00% -system.ruby.L1Cache_Controller.L1_to_L2::total 6736487 -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 75 12.08% 12.08% | 72 11.59% 23.67% | 99 15.94% 39.61% | 79 12.72% 52.33% | 66 10.63% 62.96% | 89 14.33% 77.29% | 69 11.11% 88.41% | 72 11.59% 100.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 621 -system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 75 12.08% 12.08% | 72 11.59% 23.67% | 99 15.94% 39.61% | 79 12.72% 52.33% | 66 10.63% 62.96% | 89 14.33% 77.29% | 69 11.11% 88.41% | 72 11.59% 100.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 621 -system.ruby.L1Cache_Controller.Other_GETX | 189761 12.52% 12.52% | 189309 12.49% 25.02% | 189417 12.50% 37.52% | 189262 12.49% 50.01% | 189522 12.51% 62.51% | 189457 12.50% 75.01% | 189156 12.48% 87.50% | 189455 12.50% 100.00% -system.ruby.L1Cache_Controller.Other_GETX::total 1515339 -system.ruby.L1Cache_Controller.Other_GETS | 350360 12.50% 12.50% | 350304 12.50% 24.99% | 350380 12.50% 37.49% | 350430 12.50% 49.99% | 350354 12.50% 62.49% | 350578 12.51% 75.00% | 350311 12.50% 87.49% | 350671 12.51% 100.00% -system.ruby.L1Cache_Controller.Other_GETS::total 2803388 -system.ruby.L1Cache_Controller.Merged_GETS | 67 15.26% 15.26% | 47 10.71% 25.97% | 56 12.76% 38.72% | 60 13.67% 52.39% | 48 10.93% 63.33% | 51 11.62% 74.94% | 52 11.85% 86.79% | 58 13.21% 100.00% -system.ruby.L1Cache_Controller.Merged_GETS::total 439 -system.ruby.L1Cache_Controller.Ack | 535380 12.45% 12.45% | 538939 12.54% 24.99% | 537669 12.51% 37.50% | 538458 12.53% 50.02% | 537124 12.49% 62.52% | 535993 12.47% 74.99% | 539952 12.56% 87.55% | 535252 12.45% 100.00% -system.ruby.L1Cache_Controller.Ack::total 4298767 -system.ruby.L1Cache_Controller.Shared_Ack | 61 12.55% 12.55% | 58 11.93% 24.49% | 61 12.55% 37.04% | 63 12.96% 50.00% | 51 10.49% 60.49% | 74 15.23% 75.72% | 50 10.29% 86.01% | 68 13.99% 100.00% -system.ruby.L1Cache_Controller.Shared_Ack::total 486 -system.ruby.L1Cache_Controller.Data | 2873 11.99% 11.99% | 3045 12.71% 24.69% | 2960 12.35% 37.04% | 3027 12.63% 49.67% | 2998 12.51% 62.18% | 3000 12.52% 74.70% | 2981 12.44% 87.14% | 3082 12.86% 100.00% -system.ruby.L1Cache_Controller.Data::total 23966 -system.ruby.L1Cache_Controller.Shared_Data | 1060 12.39% 12.39% | 1048 12.25% 24.63% | 1056 12.34% 36.98% | 1053 12.31% 49.28% | 1045 12.21% 61.49% | 1094 12.78% 74.28% | 1078 12.60% 86.88% | 1123 13.12% 100.00% -system.ruby.L1Cache_Controller.Shared_Data::total 8557 -system.ruby.L1Cache_Controller.Exclusive_Data | 72953 12.47% 12.47% | 73296 12.53% 25.01% | 73198 12.52% 37.52% | 73248 12.52% 50.05% | 73100 12.50% 62.54% | 72896 12.46% 75.01% | 73480 12.56% 87.57% | 72683 12.43% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 584854 -system.ruby.L1Cache_Controller.Writeback_Ack | 72619 12.47% 12.47% | 73022 12.54% 25.01% | 72821 12.51% 37.52% | 72965 12.53% 50.05% | 72792 12.50% 62.55% | 72564 12.46% 75.01% | 73169 12.57% 87.58% | 72340 12.42% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 582292 -system.ruby.L1Cache_Controller.All_acks | 1114 12.42% 12.42% | 1096 12.21% 24.63% | 1109 12.36% 36.99% | 1107 12.34% 49.33% | 1091 12.16% 61.48% | 1156 12.88% 74.37% | 1120 12.48% 86.85% | 1180 13.15% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 8973 -system.ruby.L1Cache_Controller.All_acks_no_sharers | 75773 12.45% 12.45% | 76294 12.54% 24.99% | 76104 12.51% 37.50% | 76221 12.53% 50.03% | 76052 12.50% 62.53% | 75834 12.46% 75.00% | 76419 12.56% 87.56% | 75708 12.44% 100.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers::total 608405 -system.ruby.L1Cache_Controller.I.Load | 50174 12.51% 12.51% | 50224 12.53% 25.04% | 50155 12.51% 37.55% | 50116 12.50% 50.05% | 50191 12.52% 62.57% | 49971 12.46% 75.04% | 50219 12.53% 87.56% | 49868 12.44% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 400918 -system.ruby.L1Cache_Controller.I.Store | 26713 12.34% 12.34% | 27165 12.55% 24.89% | 27060 12.50% 37.39% | 27213 12.57% 49.96% | 26955 12.45% 62.42% | 27016 12.48% 74.90% | 27320 12.62% 87.52% | 27019 12.48% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 216461 -system.ruby.L1Cache_Controller.I.L2_Replacement | 1339 11.82% 11.82% | 1403 12.39% 24.21% | 1446 12.76% 36.97% | 1410 12.45% 49.42% | 1437 12.69% 62.10% | 1441 12.72% 74.82% | 1373 12.12% 86.94% | 1479 13.06% 100.00% -system.ruby.L1Cache_Controller.I.L2_Replacement::total 11328 -system.ruby.L1Cache_Controller.I.L1_to_L2 | 263 12.00% 12.00% | 295 13.46% 25.47% | 253 11.55% 37.02% | 281 12.83% 49.84% | 292 13.33% 63.17% | 256 11.68% 74.85% | 261 11.91% 86.76% | 290 13.24% 100.00% -system.ruby.L1Cache_Controller.I.L1_to_L2::total 2191 -system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 3 20.00% 20.00% | 0 0.00% 20.00% | 1 6.67% 26.67% | 2 13.33% 40.00% | 0 0.00% 40.00% | 4 26.67% 66.67% | 2 13.33% 80.00% | 3 20.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 7401 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1078.644237 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 612.289487 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 896.971610 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 2983 40.31% 40.31% | 988 13.35% 53.65% | 933 12.61% 66.26% | 1169 15.80% 82.06% | 871 11.77% 93.83% | 349 4.72% 98.54% | 91 1.23% 99.77% | 14 0.19% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 7401 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 256 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 2559 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 209 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 177.009569 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 85.210589 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 222.115203 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 158 75.60% 75.60% | 40 19.14% 94.74% | 6 2.87% 97.61% | 3 1.44% 99.04% | 0 0.00% 99.04% | 1 0.48% 99.52% | 1 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 209 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 1024 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 10239 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 216844 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1211.584083 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 837.263042 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 897.633219 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 110553 50.98% 50.98% | 57779 26.65% 77.63% | 43904 20.25% 97.87% | 4480 2.07% 99.94% | 127 0.06% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 216844 +system.ruby.L1Cache_Controller.Load | 50433 12.46% 12.46% | 50616 12.50% 24.96% | 50620 12.50% 37.46% | 50648 12.51% 49.97% | 50636 12.51% 62.48% | 50962 12.59% 75.07% | 50842 12.56% 87.63% | 50083 12.37% 100.00% +system.ruby.L1Cache_Controller.Load::total 404840 +system.ruby.L1Cache_Controller.Store | 28039 12.48% 12.48% | 28372 12.63% 25.11% | 28070 12.49% 37.60% | 28136 12.52% 50.13% | 28079 12.50% 62.62% | 27776 12.36% 74.99% | 27886 12.41% 87.40% | 28307 12.60% 100.00% +system.ruby.L1Cache_Controller.Store::total 224665 +system.ruby.L1Cache_Controller.L2_Replacement | 78300 12.46% 12.46% | 78816 12.55% 25.01% | 78529 12.50% 37.51% | 78625 12.52% 50.03% | 78556 12.50% 62.53% | 78576 12.51% 75.04% | 78587 12.51% 87.55% | 78231 12.45% 100.00% +system.ruby.L1Cache_Controller.L2_Replacement::total 628220 +system.ruby.L1Cache_Controller.L1_to_L2 | 858524 12.53% 12.53% | 857879 12.52% 25.05% | 856223 12.49% 37.54% | 857953 12.52% 50.06% | 859985 12.55% 62.61% | 855111 12.48% 75.09% | 853105 12.45% 87.53% | 854232 12.47% 100.00% +system.ruby.L1Cache_Controller.L1_to_L2::total 6853012 +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 85 13.34% 13.34% | 83 13.03% 26.37% | 81 12.72% 39.09% | 75 11.77% 50.86% | 80 12.56% 63.42% | 80 12.56% 75.98% | 73 11.46% 87.44% | 80 12.56% 100.00% +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 637 +system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 85 13.34% 13.34% | 83 13.03% 26.37% | 81 12.72% 39.09% | 75 11.77% 50.86% | 80 12.56% 63.42% | 80 12.56% 75.98% | 73 11.46% 87.44% | 80 12.56% 100.00% +system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 637 +system.ruby.L1Cache_Controller.Other_GETX | 196274 12.50% 12.50% | 195945 12.48% 24.99% | 196230 12.50% 37.49% | 196167 12.50% 49.98% | 196227 12.50% 62.48% | 196523 12.52% 75.00% | 196414 12.51% 87.51% | 196005 12.49% 100.00% +system.ruby.L1Cache_Controller.Other_GETX::total 1569785 +system.ruby.L1Cache_Controller.Other_GETS | 353374 12.51% 12.51% | 353179 12.50% 25.01% | 353176 12.50% 37.51% | 353156 12.50% 50.00% | 353160 12.50% 62.50% | 352851 12.49% 74.99% | 352945 12.49% 87.48% | 353716 12.52% 100.00% +system.ruby.L1Cache_Controller.Other_GETS::total 2825557 +system.ruby.L1Cache_Controller.Merged_GETS | 59 13.95% 13.95% | 53 12.53% 26.48% | 51 12.06% 38.53% | 54 12.77% 51.30% | 57 13.48% 64.78% | 45 10.64% 75.41% | 62 14.66% 90.07% | 42 9.93% 100.00% +system.ruby.L1Cache_Controller.Merged_GETS::total 423 +system.ruby.L1Cache_Controller.Ack | 545290 12.46% 12.46% | 548865 12.55% 25.01% | 546914 12.50% 37.51% | 547510 12.52% 50.03% | 546983 12.50% 62.53% | 547231 12.51% 75.04% | 547243 12.51% 87.55% | 544739 12.45% 100.00% +system.ruby.L1Cache_Controller.Ack::total 4374775 +system.ruby.L1Cache_Controller.Shared_Ack | 46 11.17% 11.17% | 52 12.62% 23.79% | 60 14.56% 38.35% | 48 11.65% 50.00% | 38 9.22% 59.22% | 59 14.32% 73.54% | 49 11.89% 85.44% | 60 14.56% 100.00% +system.ruby.L1Cache_Controller.Shared_Ack::total 412 +system.ruby.L1Cache_Controller.Data | 2902 12.29% 12.29% | 2956 12.52% 24.81% | 2952 12.50% 37.31% | 2956 12.52% 49.83% | 3021 12.80% 62.63% | 2932 12.42% 75.05% | 2963 12.55% 87.60% | 2928 12.40% 100.00% +system.ruby.L1Cache_Controller.Data::total 23610 +system.ruby.L1Cache_Controller.Shared_Data | 1044 12.06% 12.06% | 1090 12.59% 24.65% | 1109 12.81% 37.47% | 1077 12.44% 49.91% | 1114 12.87% 62.78% | 1071 12.37% 75.15% | 1132 13.08% 88.23% | 1019 11.77% 100.00% +system.ruby.L1Cache_Controller.Shared_Data::total 8656 +system.ruby.L1Cache_Controller.Exclusive_Data | 74363 12.48% 12.48% | 74779 12.55% 25.02% | 74481 12.50% 37.52% | 74602 12.52% 50.04% | 74430 12.49% 62.52% | 74583 12.51% 75.04% | 74502 12.50% 87.54% | 74292 12.46% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 596032 +system.ruby.L1Cache_Controller.Writeback_Ack | 73965 12.47% 12.47% | 74350 12.54% 25.01% | 74128 12.50% 37.52% | 74201 12.51% 50.03% | 74027 12.49% 62.52% | 74179 12.51% 75.03% | 74144 12.50% 87.53% | 73931 12.47% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 592925 +system.ruby.L1Cache_Controller.All_acks | 1085 12.05% 12.05% | 1134 12.59% 24.64% | 1163 12.91% 37.55% | 1122 12.46% 50.01% | 1145 12.71% 62.72% | 1121 12.45% 75.16% | 1174 13.03% 88.20% | 1063 11.80% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 9007 +system.ruby.L1Cache_Controller.All_acks_no_sharers | 77227 12.47% 12.47% | 77692 12.55% 25.02% | 77379 12.49% 37.51% | 77514 12.52% 50.03% | 77420 12.50% 62.53% | 77465 12.51% 75.04% | 77423 12.50% 87.54% | 77176 12.46% 100.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers::total 619296 +system.ruby.L1Cache_Controller.I.Load | 50333 12.46% 12.46% | 50517 12.50% 24.96% | 50518 12.50% 37.46% | 50550 12.51% 49.97% | 50540 12.51% 62.48% | 50855 12.59% 75.07% | 50759 12.56% 87.63% | 49992 12.37% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 404064 +system.ruby.L1Cache_Controller.I.Store | 27977 12.48% 12.48% | 28308 12.62% 25.10% | 28022 12.50% 37.60% | 28085 12.52% 50.12% | 28026 12.50% 62.62% | 27731 12.37% 74.99% | 27838 12.41% 87.40% | 28249 12.60% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 224236 +system.ruby.L1Cache_Controller.I.L2_Replacement | 1529 12.80% 12.80% | 1508 12.62% 25.42% | 1449 12.13% 37.55% | 1525 12.77% 50.32% | 1515 12.68% 63.00% | 1499 12.55% 75.55% | 1468 12.29% 87.84% | 1453 12.16% 100.00% +system.ruby.L1Cache_Controller.I.L2_Replacement::total 11946 +system.ruby.L1Cache_Controller.I.L1_to_L2 | 278 12.20% 12.20% | 287 12.59% 24.79% | 266 11.67% 36.46% | 294 12.90% 49.36% | 308 13.51% 62.88% | 269 11.80% 74.68% | 277 12.15% 86.84% | 300 13.16% 100.00% +system.ruby.L1Cache_Controller.I.L1_to_L2::total 2279 +system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 2 13.33% 13.33% | 1 6.67% 20.00% | 3 20.00% 40.00% | 2 13.33% 53.33% | 2 13.33% 66.67% | 3 20.00% 86.67% | 0 0.00% 86.67% | 2 13.33% 100.00% system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total 15 -system.ruby.L1Cache_Controller.I.Other_GETX | 188850 12.52% 12.52% | 188385 12.49% 25.02% | 188473 12.50% 37.52% | 188307 12.49% 50.00% | 188572 12.51% 62.51% | 188504 12.50% 75.01% | 188287 12.49% 87.50% | 188527 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETX::total 1507905 -system.ruby.L1Cache_Controller.I.Other_GETS | 348728 12.50% 12.50% | 348598 12.49% 24.99% | 348711 12.50% 37.49% | 348779 12.50% 49.99% | 348712 12.50% 62.49% | 348887 12.50% 75.00% | 348575 12.49% 87.49% | 348998 12.51% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETS::total 2789988 -system.ruby.L1Cache_Controller.S.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 2 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 6 -system.ruby.L1Cache_Controller.S.L2_Replacement | 2919 12.33% 12.33% | 2953 12.47% 24.80% | 2937 12.41% 37.21% | 2944 12.44% 49.65% | 2906 12.28% 61.92% | 2973 12.56% 74.48% | 2984 12.60% 87.08% | 3058 12.92% 100.00% -system.ruby.L1Cache_Controller.S.L2_Replacement::total 23674 -system.ruby.L1Cache_Controller.S.L1_to_L2 | 2947 12.34% 12.34% | 2984 12.49% 24.83% | 2973 12.45% 37.27% | 2971 12.44% 49.71% | 2929 12.26% 61.97% | 2993 12.53% 74.50% | 3006 12.58% 87.08% | 3086 12.92% 100.00% -system.ruby.L1Cache_Controller.S.L1_to_L2::total 23889 -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 2 8.70% 8.70% | 5 21.74% 30.43% | 4 17.39% 47.83% | 1 4.35% 52.17% | 0 0.00% 52.17% | 2 8.70% 60.87% | 3 13.04% 73.91% | 6 26.09% 100.00% -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 23 -system.ruby.L1Cache_Controller.S.Other_GETX | 29 11.74% 11.74% | 31 12.55% 24.29% | 38 15.38% 39.68% | 33 13.36% 53.04% | 32 12.96% 65.99% | 28 11.34% 77.33% | 25 10.12% 87.45% | 31 12.55% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETX::total 247 -system.ruby.L1Cache_Controller.S.Other_GETS | 57 11.73% 11.73% | 56 11.52% 23.25% | 59 12.14% 35.39% | 72 14.81% 50.21% | 52 10.70% 60.91% | 62 12.76% 73.66% | 79 16.26% 89.92% | 49 10.08% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETS::total 486 -system.ruby.L1Cache_Controller.O.Store | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Store::total 1 -system.ruby.L1Cache_Controller.O.L2_Replacement | 1037 12.92% 12.92% | 1033 12.87% 25.79% | 990 12.33% 38.12% | 999 12.45% 50.57% | 972 12.11% 62.68% | 1001 12.47% 75.15% | 1015 12.64% 87.79% | 980 12.21% 100.00% -system.ruby.L1Cache_Controller.O.L2_Replacement::total 8027 -system.ruby.L1Cache_Controller.O.L1_to_L2 | 204 12.62% 12.62% | 188 11.63% 24.26% | 202 12.50% 36.76% | 199 12.31% 49.07% | 190 11.76% 60.83% | 218 13.49% 74.32% | 217 13.43% 87.75% | 198 12.25% 100.00% -system.ruby.L1Cache_Controller.O.L1_to_L2::total 1616 -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 6 -system.ruby.L1Cache_Controller.O.Other_GETX | 7 12.50% 12.50% | 8 14.29% 26.79% | 8 14.29% 41.07% | 5 8.93% 50.00% | 3 5.36% 55.36% | 11 19.64% 75.00% | 9 16.07% 91.07% | 5 8.93% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETX::total 56 -system.ruby.L1Cache_Controller.O.Other_GETS | 9 9.89% 9.89% | 14 15.38% 25.27% | 12 13.19% 38.46% | 12 13.19% 51.65% | 13 14.29% 65.93% | 9 9.89% 75.82% | 9 9.89% 85.71% | 13 14.29% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETS::total 91 -system.ruby.L1Cache_Controller.O.Merged_GETS | 4 19.05% 19.05% | 3 14.29% 33.33% | 2 9.52% 42.86% | 6 28.57% 71.43% | 3 14.29% 85.71% | 1 4.76% 90.48% | 1 4.76% 95.24% | 1 4.76% 100.00% -system.ruby.L1Cache_Controller.O.Merged_GETS::total 21 -system.ruby.L1Cache_Controller.M.Load | 7 16.67% 16.67% | 3 7.14% 23.81% | 5 11.90% 35.71% | 6 14.29% 50.00% | 2 4.76% 54.76% | 11 26.19% 80.95% | 6 14.29% 95.24% | 2 4.76% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 42 -system.ruby.L1Cache_Controller.M.Store | 5 16.13% 16.13% | 5 16.13% 32.26% | 2 6.45% 38.71% | 5 16.13% 54.84% | 2 6.45% 61.29% | 9 29.03% 90.32% | 1 3.23% 93.55% | 2 6.45% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 31 -system.ruby.L1Cache_Controller.M.L2_Replacement | 45647 12.52% 12.52% | 45669 12.52% 25.04% | 45641 12.52% 37.56% | 45593 12.50% 50.06% | 45746 12.55% 62.61% | 45407 12.45% 75.06% | 45688 12.53% 87.59% | 45251 12.41% 100.00% -system.ruby.L1Cache_Controller.M.L2_Replacement::total 364642 -system.ruby.L1Cache_Controller.M.L1_to_L2 | 46941 12.52% 12.52% | 46960 12.53% 25.05% | 46927 12.52% 37.57% | 46865 12.50% 50.08% | 46980 12.53% 62.61% | 46700 12.46% 75.07% | 46933 12.52% 87.59% | 46507 12.41% 100.00% -system.ruby.L1Cache_Controller.M.L1_to_L2::total 374813 -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 49 13.14% 13.14% | 40 10.72% 23.86% | 60 16.09% 39.95% | 51 13.67% 53.62% | 41 10.99% 64.61% | 55 14.75% 79.36% | 37 9.92% 89.28% | 40 10.72% 100.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 373 -system.ruby.L1Cache_Controller.M.Other_GETX | 529 12.54% 12.54% | 518 12.28% 24.82% | 538 12.75% 37.57% | 533 12.63% 50.20% | 520 12.33% 62.53% | 540 12.80% 75.33% | 502 11.90% 87.22% | 539 12.78% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETX::total 4219 -system.ruby.L1Cache_Controller.M.Other_GETS | 983 12.81% 12.81% | 999 13.02% 25.84% | 944 12.31% 38.14% | 950 12.38% 50.53% | 931 12.14% 62.66% | 962 12.54% 75.21% | 974 12.70% 87.90% | 928 12.10% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETS::total 7671 -system.ruby.L1Cache_Controller.M.Merged_GETS | 39 15.29% 15.29% | 27 10.59% 25.88% | 33 12.94% 38.82% | 31 12.16% 50.98% | 27 10.59% 61.57% | 27 10.59% 72.16% | 29 11.37% 83.53% | 42 16.47% 100.00% -system.ruby.L1Cache_Controller.M.Merged_GETS::total 255 -system.ruby.L1Cache_Controller.MM.Load | 4 10.00% 10.00% | 8 20.00% 30.00% | 2 5.00% 35.00% | 6 15.00% 50.00% | 6 15.00% 65.00% | 4 10.00% 75.00% | 3 7.50% 82.50% | 7 17.50% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 40 -system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 5 26.32% 26.32% | 1 5.26% 31.58% | 2 10.53% 42.11% | 4 21.05% 63.16% | 4 21.05% 84.21% | 1 5.26% 89.47% | 2 10.53% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETX | 195293 12.50% 12.50% | 194946 12.48% 24.98% | 195299 12.50% 37.49% | 195174 12.50% 49.98% | 195217 12.50% 62.48% | 195495 12.52% 75.00% | 195467 12.51% 87.51% | 195040 12.49% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETX::total 1561931 +system.ruby.L1Cache_Controller.I.Other_GETS | 351649 12.51% 12.51% | 351467 12.50% 25.00% | 351522 12.50% 37.51% | 351428 12.50% 50.00% | 351472 12.50% 62.50% | 351196 12.49% 74.99% | 351192 12.49% 87.48% | 352050 12.52% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETS::total 2811976 +system.ruby.L1Cache_Controller.S.Load | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 3 60.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 5 +system.ruby.L1Cache_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 2 +system.ruby.L1Cache_Controller.S.L2_Replacement | 2806 12.02% 12.02% | 2958 12.67% 24.69% | 2952 12.64% 37.33% | 2899 12.42% 49.75% | 3014 12.91% 62.65% | 2898 12.41% 75.07% | 2975 12.74% 87.81% | 2847 12.19% 100.00% +system.ruby.L1Cache_Controller.S.L2_Replacement::total 23349 +system.ruby.L1Cache_Controller.S.L1_to_L2 | 2835 12.03% 12.03% | 2983 12.66% 24.69% | 2980 12.65% 37.34% | 2927 12.42% 49.76% | 3041 12.91% 62.66% | 2923 12.40% 75.07% | 2999 12.73% 87.79% | 2876 12.21% 100.00% +system.ruby.L1Cache_Controller.S.L1_to_L2::total 23564 +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 0 0.00% 0.00% | 3 14.29% 14.29% | 4 19.05% 33.33% | 3 14.29% 47.62% | 3 14.29% 61.90% | 3 14.29% 76.19% | 3 14.29% 90.48% | 2 9.52% 100.00% +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 21 +system.ruby.L1Cache_Controller.S.Other_GETX | 33 13.64% 13.64% | 30 12.40% 26.03% | 29 11.98% 38.02% | 31 12.81% 50.83% | 35 14.46% 65.29% | 27 11.16% 76.45% | 26 10.74% 87.19% | 31 12.81% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETX::total 242 +system.ruby.L1Cache_Controller.S.Other_GETS | 57 13.83% 13.83% | 65 15.78% 29.61% | 41 9.95% 39.56% | 38 9.22% 48.79% | 58 14.08% 62.86% | 52 12.62% 75.49% | 53 12.86% 88.35% | 48 11.65% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETS::total 412 +system.ruby.L1Cache_Controller.O.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Load::total 1 +system.ruby.L1Cache_Controller.O.L2_Replacement | 1012 12.53% 12.53% | 1001 12.40% 24.93% | 990 12.26% 37.19% | 1022 12.66% 49.85% | 997 12.35% 62.20% | 995 12.32% 74.52% | 1049 12.99% 87.52% | 1008 12.48% 100.00% +system.ruby.L1Cache_Controller.O.L2_Replacement::total 8074 +system.ruby.L1Cache_Controller.O.L1_to_L2 | 169 10.51% 10.51% | 186 11.57% 22.08% | 201 12.50% 34.58% | 205 12.75% 47.33% | 202 12.56% 59.89% | 213 13.25% 73.13% | 222 13.81% 86.94% | 210 13.06% 100.00% +system.ruby.L1Cache_Controller.O.L1_to_L2::total 1608 +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 3 42.86% 42.86% | 2 28.57% 71.43% | 0 0.00% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 7 +system.ruby.L1Cache_Controller.O.Other_GETX | 10 16.67% 16.67% | 9 15.00% 31.67% | 8 13.33% 45.00% | 8 13.33% 58.33% | 6 10.00% 68.33% | 5 8.33% 76.67% | 7 11.67% 88.33% | 7 11.67% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETX::total 60 +system.ruby.L1Cache_Controller.O.Other_GETS | 11 13.10% 13.10% | 13 15.48% 28.57% | 15 17.86% 46.43% | 12 14.29% 60.71% | 7 8.33% 69.05% | 8 9.52% 78.57% | 8 9.52% 88.10% | 10 11.90% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETS::total 84 +system.ruby.L1Cache_Controller.O.Merged_GETS | 1 4.55% 4.55% | 3 13.64% 18.18% | 2 9.09% 27.27% | 4 18.18% 45.45% | 5 22.73% 68.18% | 3 13.64% 81.82% | 2 9.09% 90.91% | 2 9.09% 100.00% +system.ruby.L1Cache_Controller.O.Merged_GETS::total 22 +system.ruby.L1Cache_Controller.M.Load | 2 3.57% 3.57% | 8 14.29% 17.86% | 4 7.14% 25.00% | 6 10.71% 35.71% | 10 17.86% 53.57% | 8 14.29% 67.86% | 7 12.50% 80.36% | 11 19.64% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 56 +system.ruby.L1Cache_Controller.M.Store | 3 8.82% 8.82% | 3 8.82% 17.65% | 6 17.65% 35.29% | 5 14.71% 50.00% | 1 2.94% 52.94% | 3 8.82% 61.76% | 5 14.71% 76.47% | 8 23.53% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 34 +system.ruby.L1Cache_Controller.M.L2_Replacement | 45887 12.48% 12.48% | 45937 12.49% 24.97% | 46011 12.51% 37.47% | 46008 12.51% 49.98% | 45925 12.49% 62.47% | 46336 12.60% 75.07% | 46151 12.55% 87.61% | 45554 12.39% 100.00% +system.ruby.L1Cache_Controller.M.L2_Replacement::total 367809 +system.ruby.L1Cache_Controller.M.L1_to_L2 | 47252 12.49% 12.49% | 47281 12.50% 24.99% | 47263 12.49% 37.48% | 47324 12.51% 49.99% | 47202 12.48% 62.47% | 47652 12.60% 75.07% | 47474 12.55% 87.62% | 46832 12.38% 100.00% +system.ruby.L1Cache_Controller.M.L1_to_L2::total 378280 +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 52 13.27% 13.27% | 52 13.27% 26.53% | 42 10.71% 37.24% | 45 11.48% 48.72% | 46 11.73% 60.46% | 50 12.76% 73.21% | 49 12.50% 85.71% | 56 14.29% 100.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 392 +system.ruby.L1Cache_Controller.M.Other_GETX | 573 12.90% 12.90% | 565 12.72% 25.61% | 521 11.73% 37.34% | 575 12.94% 50.28% | 559 12.58% 62.86% | 587 13.21% 76.07% | 542 12.20% 88.27% | 521 11.73% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETX::total 4443 +system.ruby.L1Cache_Controller.M.Other_GETS | 968 12.50% 12.50% | 962 12.42% 24.92% | 950 12.26% 37.18% | 983 12.69% 49.87% | 952 12.29% 62.16% | 958 12.37% 74.53% | 998 12.88% 87.41% | 975 12.59% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETS::total 7746 +system.ruby.L1Cache_Controller.M.Merged_GETS | 34 13.65% 13.65% | 36 14.46% 28.11% | 26 10.44% 38.55% | 27 10.84% 49.40% | 30 12.05% 61.45% | 31 12.45% 73.90% | 37 14.86% 88.76% | 28 11.24% 100.00% +system.ruby.L1Cache_Controller.M.Merged_GETS::total 249 +system.ruby.L1Cache_Controller.MM.Load | 9 33.33% 33.33% | 2 7.41% 40.74% | 3 11.11% 51.85% | 5 18.52% 70.37% | 2 7.41% 77.78% | 1 3.70% 81.48% | 1 3.70% 85.19% | 4 14.81% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 27 +system.ruby.L1Cache_Controller.MM.Store | 2 10.53% 10.53% | 2 10.53% 21.05% | 1 5.26% 26.32% | 1 5.26% 31.58% | 3 15.79% 47.37% | 6 31.58% 78.95% | 3 15.79% 94.74% | 1 5.26% 100.00% system.ruby.L1Cache_Controller.MM.Store::total 19 -system.ruby.L1Cache_Controller.MM.L2_Replacement | 25935 12.37% 12.37% | 26320 12.56% 24.93% | 26190 12.49% 37.42% | 26373 12.58% 50.00% | 26074 12.44% 62.44% | 26156 12.48% 74.92% | 26468 12.63% 87.54% | 26109 12.46% 100.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement::total 209625 -system.ruby.L1Cache_Controller.MM.L1_to_L2 | 26603 12.35% 12.35% | 27029 12.54% 24.89% | 26955 12.51% 37.40% | 27088 12.57% 49.98% | 26817 12.45% 62.42% | 26905 12.49% 74.91% | 27186 12.62% 87.53% | 26874 12.47% 100.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2::total 215457 -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 21 10.29% 10.29% | 25 12.25% 22.55% | 34 16.67% 39.22% | 24 11.76% 50.98% | 25 12.25% 63.24% | 27 13.24% 76.47% | 27 13.24% 89.71% | 21 10.29% 100.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 204 -system.ruby.L1Cache_Controller.MM.Other_GETX | 296 12.11% 12.11% | 298 12.19% 24.30% | 301 12.32% 36.62% | 320 13.09% 49.71% | 334 13.67% 63.38% | 308 12.60% 75.98% | 279 11.42% 87.40% | 308 12.60% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETX::total 2444 -system.ruby.L1Cache_Controller.MM.Other_GETS | 481 10.98% 10.98% | 549 12.54% 23.52% | 562 12.83% 36.36% | 521 11.90% 48.25% | 548 12.51% 60.77% | 558 12.74% 73.51% | 561 12.81% 86.32% | 599 13.68% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETS::total 4379 -system.ruby.L1Cache_Controller.MM.Merged_GETS | 23 14.37% 14.37% | 16 10.00% 24.38% | 21 13.12% 37.50% | 23 14.37% 51.88% | 18 11.25% 63.13% | 23 14.37% 77.50% | 21 13.12% 90.63% | 15 9.38% 100.00% -system.ruby.L1Cache_Controller.MM.Merged_GETS::total 160 -system.ruby.L1Cache_Controller.IR.Load | 1 16.67% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00% -system.ruby.L1Cache_Controller.IR.Load::total 6 -system.ruby.L1Cache_Controller.IR.Store | 2 22.22% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 3 33.33% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.IR.Store::total 9 -system.ruby.L1Cache_Controller.IR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 84.62% 84.62% | 0 0.00% 84.62% | 2 15.38% 100.00% -system.ruby.L1Cache_Controller.IR.L1_to_L2::total 13 -system.ruby.L1Cache_Controller.SR.Load | 2 11.76% 11.76% | 3 17.65% 29.41% | 4 23.53% 52.94% | 1 5.88% 58.82% | 0 0.00% 58.82% | 1 5.88% 64.71% | 2 11.76% 76.47% | 4 23.53% 100.00% -system.ruby.L1Cache_Controller.SR.Load::total 17 -system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00% -system.ruby.L1Cache_Controller.SR.Store::total 6 -system.ruby.L1Cache_Controller.SR.L1_to_L2 | 0 0.00% 0.00% | 3 18.75% 18.75% | 0 0.00% 18.75% | 0 0.00% 18.75% | 0 0.00% 18.75% | 0 0.00% 18.75% | 0 0.00% 18.75% | 13 81.25% 100.00% -system.ruby.L1Cache_Controller.SR.L1_to_L2::total 16 -system.ruby.L1Cache_Controller.OR.Load | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00% -system.ruby.L1Cache_Controller.OR.Load::total 5 -system.ruby.L1Cache_Controller.OR.Store | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OR.Store::total 1 -system.ruby.L1Cache_Controller.MR.Load | 32 12.85% 12.85% | 27 10.84% 23.69% | 42 16.87% 40.56% | 33 13.25% 53.82% | 20 8.03% 61.85% | 37 14.86% 76.71% | 27 10.84% 87.55% | 31 12.45% 100.00% -system.ruby.L1Cache_Controller.MR.Load::total 249 -system.ruby.L1Cache_Controller.MR.Store | 17 13.71% 13.71% | 13 10.48% 24.19% | 18 14.52% 38.71% | 18 14.52% 53.23% | 21 16.94% 70.16% | 18 14.52% 84.68% | 10 8.06% 92.74% | 9 7.26% 100.00% -system.ruby.L1Cache_Controller.MR.Store::total 124 -system.ruby.L1Cache_Controller.MR.L1_to_L2 | 91 14.35% 14.35% | 56 8.83% 23.19% | 102 16.09% 39.27% | 86 13.56% 52.84% | 95 14.98% 67.82% | 89 14.04% 81.86% | 59 9.31% 91.17% | 56 8.83% 100.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2::total 634 -system.ruby.L1Cache_Controller.MMR.Load | 14 10.22% 10.22% | 17 12.41% 22.63% | 26 18.98% 41.61% | 16 11.68% 53.28% | 16 11.68% 64.96% | 16 11.68% 76.64% | 18 13.14% 89.78% | 14 10.22% 100.00% -system.ruby.L1Cache_Controller.MMR.Load::total 137 -system.ruby.L1Cache_Controller.MMR.Store | 7 10.45% 10.45% | 8 11.94% 22.39% | 8 11.94% 34.33% | 8 11.94% 46.27% | 9 13.43% 59.70% | 11 16.42% 76.12% | 9 13.43% 89.55% | 7 10.45% 100.00% -system.ruby.L1Cache_Controller.MMR.Store::total 67 -system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 59 15.28% 15.28% | 75 19.43% 34.72% | 46 11.92% 46.63% | 41 10.62% 57.25% | 49 12.69% 69.95% | 33 8.55% 78.50% | 49 12.69% 91.19% | 34 8.81% 100.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 386 -system.ruby.L1Cache_Controller.IM.L1_to_L2 | 264282 12.35% 12.35% | 266577 12.46% 24.81% | 267890 12.52% 37.33% | 269848 12.61% 49.94% | 268056 12.53% 62.46% | 268579 12.55% 75.02% | 269306 12.59% 87.60% | 265306 12.40% 100.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2139844 -system.ruby.L1Cache_Controller.IM.Other_GETX | 7 7.69% 7.69% | 12 13.19% 20.88% | 10 10.99% 31.87% | 15 16.48% 48.35% | 9 9.89% 58.24% | 15 16.48% 74.73% | 10 10.99% 85.71% | 13 14.29% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETX::total 91 -system.ruby.L1Cache_Controller.IM.Other_GETS | 21 14.00% 14.00% | 19 12.67% 26.67% | 20 13.33% 40.00% | 24 16.00% 56.00% | 14 9.33% 65.33% | 14 9.33% 74.67% | 22 14.67% 89.33% | 16 10.67% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETS::total 150 -system.ruby.L1Cache_Controller.IM.Ack | 183448 12.33% 12.33% | 186647 12.55% 24.88% | 185973 12.50% 37.38% | 187270 12.59% 49.97% | 185299 12.46% 62.42% | 185768 12.49% 74.91% | 187652 12.61% 87.52% | 185613 12.48% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1487670 -system.ruby.L1Cache_Controller.IM.Data | 985 11.47% 11.47% | 1103 12.85% 24.32% | 1041 12.12% 36.44% | 1101 12.82% 49.27% | 1105 12.87% 62.14% | 1091 12.71% 74.84% | 1048 12.21% 87.05% | 1112 12.95% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 8586 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 25729 12.38% 12.38% | 26061 12.54% 24.91% | 26018 12.52% 37.43% | 26114 12.56% 49.99% | 25848 12.43% 62.43% | 25928 12.47% 74.90% | 26272 12.64% 87.54% | 25907 12.46% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 207877 -system.ruby.L1Cache_Controller.SM.L1_to_L2 | 0 0.00% 0.00% | 11 57.89% 57.89% | 0 0.00% 57.89% | 0 0.00% 57.89% | 0 0.00% 57.89% | 1 5.26% 63.16% | 7 36.84% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.L1_to_L2::total 19 -system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 14 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 7 16.67% 50.00% | 7 16.67% 66.67% | 14 33.33% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 42 -system.ruby.L1Cache_Controller.SM.Data | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00% -system.ruby.L1Cache_Controller.SM.Data::total 6 -system.ruby.L1Cache_Controller.OM.Ack | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Ack::total 14 -system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 2 -system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 2 11.11% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 1 5.56% 16.67% | 0 0.00% 16.67% | 14 77.78% 94.44% | 1 5.56% 100.00% -system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 18 -system.ruby.L1Cache_Controller.ISM.Ack | 104 12.84% 12.84% | 73 9.01% 21.85% | 108 13.33% 35.19% | 117 14.44% 49.63% | 100 12.35% 61.98% | 106 13.09% 75.06% | 115 14.20% 89.26% | 87 10.74% 100.00% -system.ruby.L1Cache_Controller.ISM.Ack::total 810 -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 985 11.46% 11.46% | 1105 12.86% 24.32% | 1041 12.12% 36.44% | 1101 12.81% 49.26% | 1105 12.86% 62.12% | 1092 12.71% 74.83% | 1049 12.21% 87.03% | 1114 12.97% 100.00% -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 8592 -system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 539 13.66% 13.66% | 550 13.94% 27.60% | 404 10.24% 37.84% | 533 13.51% 51.34% | 478 12.11% 63.46% | 492 12.47% 75.92% | 525 13.30% 89.23% | 425 10.77% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 3946 -system.ruby.L1Cache_Controller.M_W.Ack | 1618 12.50% 12.50% | 1714 13.24% 25.73% | 1578 12.19% 37.92% | 1607 12.41% 50.33% | 1665 12.86% 63.19% | 1631 12.60% 75.78% | 1583 12.22% 88.01% | 1553 11.99% 100.00% -system.ruby.L1Cache_Controller.M_W.Ack::total 12949 -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47224 12.53% 12.53% | 47235 12.53% 25.06% | 47179 12.52% 37.57% | 47134 12.50% 50.08% | 47252 12.53% 62.61% | 46968 12.46% 75.07% | 47208 12.52% 87.59% | 46776 12.41% 100.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 376976 -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 1079 15.32% 15.32% | 875 12.43% 27.75% | 817 11.60% 39.36% | 808 11.48% 50.83% | 798 11.33% 62.16% | 840 11.93% 74.09% | 931 13.22% 87.32% | 893 12.68% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 7041 -system.ruby.L1Cache_Controller.MM_W.Ack | 2578 12.99% 12.99% | 2557 12.89% 25.88% | 2465 12.42% 38.30% | 2275 11.47% 49.77% | 2427 12.23% 62.00% | 2427 12.23% 74.23% | 2583 13.02% 87.24% | 2531 12.76% 100.00% -system.ruby.L1Cache_Controller.MM_W.Ack::total 19843 -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 25729 12.38% 12.38% | 26061 12.54% 24.91% | 26018 12.52% 37.43% | 26114 12.56% 49.99% | 25848 12.43% 62.43% | 25928 12.47% 74.90% | 26272 12.64% 87.54% | 25907 12.46% 100.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 207877 -system.ruby.L1Cache_Controller.IS.L1_to_L2 | 495283 12.52% 12.52% | 496463 12.55% 25.07% | 495139 12.51% 37.58% | 490703 12.40% 49.98% | 494908 12.51% 62.49% | 493655 12.48% 74.97% | 495921 12.53% 87.50% | 494562 12.50% 100.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2::total 3956634 -system.ruby.L1Cache_Controller.IS.Other_GETX | 18 11.46% 11.46% | 25 15.92% 27.39% | 17 10.83% 38.22% | 24 15.29% 53.50% | 21 13.38% 66.88% | 22 14.01% 80.89% | 15 9.55% 90.45% | 15 9.55% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETX::total 157 -system.ruby.L1Cache_Controller.IS.Other_GETS | 33 12.36% 12.36% | 30 11.24% 23.60% | 33 12.36% 35.96% | 29 10.86% 46.82% | 36 13.48% 60.30% | 40 14.98% 75.28% | 28 10.49% 85.77% | 38 14.23% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETS::total 267 -system.ruby.L1Cache_Controller.IS.Ack | 344673 12.52% 12.52% | 344866 12.53% 25.05% | 344538 12.51% 37.56% | 344199 12.50% 50.06% | 344619 12.52% 62.58% | 343059 12.46% 75.04% | 344891 12.53% 87.57% | 342300 12.43% 100.00% -system.ruby.L1Cache_Controller.IS.Ack::total 2753145 -system.ruby.L1Cache_Controller.IS.Shared_Ack | 57 12.61% 12.61% | 54 11.95% 24.56% | 57 12.61% 37.17% | 59 13.05% 50.22% | 48 10.62% 60.84% | 68 15.04% 75.88% | 45 9.96% 85.84% | 64 14.16% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Ack::total 452 -system.ruby.L1Cache_Controller.IS.Data | 1888 12.28% 12.28% | 1940 12.62% 24.90% | 1919 12.48% 37.38% | 1926 12.53% 49.91% | 1893 12.31% 62.22% | 1908 12.41% 74.63% | 1932 12.57% 87.20% | 1968 12.80% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 15374 -system.ruby.L1Cache_Controller.IS.Shared_Data | 1060 12.39% 12.39% | 1048 12.25% 24.63% | 1056 12.34% 36.98% | 1053 12.31% 49.28% | 1045 12.21% 61.49% | 1094 12.78% 74.28% | 1078 12.60% 86.88% | 1123 13.12% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Data::total 8557 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47224 12.53% 12.53% | 47235 12.53% 25.06% | 47180 12.52% 37.57% | 47134 12.50% 50.08% | 47252 12.53% 62.61% | 46968 12.46% 75.07% | 47208 12.52% 87.59% | 46776 12.41% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 376977 -system.ruby.L1Cache_Controller.SS.L1_to_L2 | 1116 14.02% 14.02% | 874 10.98% 25.01% | 1194 15.00% 40.01% | 1064 13.37% 53.38% | 767 9.64% 63.02% | 881 11.07% 74.09% | 901 11.32% 85.41% | 1161 14.59% 100.00% -system.ruby.L1Cache_Controller.SS.L1_to_L2::total 7958 -system.ruby.L1Cache_Controller.SS.Ack | 2952 12.15% 12.15% | 3061 12.60% 24.75% | 3007 12.38% 37.13% | 2990 12.31% 49.44% | 3014 12.41% 61.84% | 2995 12.33% 74.17% | 3121 12.85% 87.02% | 3154 12.98% 100.00% -system.ruby.L1Cache_Controller.SS.Ack::total 24294 -system.ruby.L1Cache_Controller.SS.Shared_Ack | 4 11.76% 11.76% | 4 11.76% 23.53% | 4 11.76% 35.29% | 4 11.76% 47.06% | 3 8.82% 55.88% | 6 17.65% 73.53% | 5 14.71% 88.24% | 4 11.76% 100.00% -system.ruby.L1Cache_Controller.SS.Shared_Ack::total 34 -system.ruby.L1Cache_Controller.SS.All_acks | 1114 12.42% 12.42% | 1096 12.21% 24.63% | 1109 12.36% 36.99% | 1107 12.34% 49.33% | 1091 12.16% 61.48% | 1156 12.88% 74.37% | 1120 12.48% 86.85% | 1180 13.15% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks::total 8973 -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 1834 12.26% 12.26% | 1892 12.65% 24.91% | 1866 12.47% 37.38% | 1872 12.52% 49.90% | 1847 12.35% 62.25% | 1846 12.34% 74.59% | 1890 12.64% 87.22% | 1911 12.78% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 14958 -system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement | 27066 12.47% 12.47% | 27412 12.63% 25.10% | 27127 12.50% 37.60% | 27171 12.52% 50.12% | 27105 12.49% 62.61% | 26848 12.37% 74.98% | 26944 12.41% 87.39% | 27369 12.61% 100.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement::total 217042 +system.ruby.L1Cache_Controller.MM.L1_to_L2 | 27857 12.48% 12.48% | 28167 12.62% 25.10% | 27907 12.50% 37.61% | 27956 12.53% 50.13% | 27889 12.50% 62.63% | 27605 12.37% 75.00% | 27694 12.41% 87.41% | 28099 12.59% 100.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2::total 223174 +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 28 13.86% 13.86% | 25 12.38% 26.24% | 32 15.84% 42.08% | 24 11.88% 53.96% | 29 14.36% 68.32% | 23 11.39% 79.70% | 21 10.40% 90.10% | 20 9.90% 100.00% +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 202 +system.ruby.L1Cache_Controller.MM.Other_GETX | 323 12.00% 12.00% | 349 12.96% 24.96% | 322 11.96% 36.92% | 331 12.30% 49.22% | 348 12.93% 62.15% | 351 13.04% 75.19% | 310 11.52% 86.70% | 358 13.30% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETX::total 2692 +system.ruby.L1Cache_Controller.MM.Other_GETS | 592 13.08% 13.08% | 556 12.29% 25.37% | 572 12.64% 38.01% | 582 12.86% 50.87% | 569 12.57% 63.45% | 533 11.78% 75.23% | 583 12.88% 88.11% | 538 11.89% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETS::total 4525 +system.ruby.L1Cache_Controller.MM.Merged_GETS | 23 15.86% 15.86% | 13 8.97% 24.83% | 22 15.17% 40.00% | 22 15.17% 55.17% | 21 14.48% 69.66% | 11 7.59% 77.24% | 21 14.48% 91.72% | 12 8.28% 100.00% +system.ruby.L1Cache_Controller.MM.Merged_GETS::total 145 +system.ruby.L1Cache_Controller.IR.Load | 1 10.00% 10.00% | 1 10.00% 20.00% | 2 20.00% 40.00% | 1 10.00% 50.00% | 1 10.00% 60.00% | 3 30.00% 90.00% | 0 0.00% 90.00% | 1 10.00% 100.00% +system.ruby.L1Cache_Controller.IR.Load::total 10 +system.ruby.L1Cache_Controller.IR.Store | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.IR.Store::total 5 +system.ruby.L1Cache_Controller.IR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 2 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IR.L1_to_L2::total 4 +system.ruby.L1Cache_Controller.SR.Load | 0 0.00% 0.00% | 2 14.29% 14.29% | 3 21.43% 35.71% | 3 21.43% 57.14% | 2 14.29% 71.43% | 2 14.29% 85.71% | 0 0.00% 85.71% | 2 14.29% 100.00% +system.ruby.L1Cache_Controller.SR.Load::total 14 +system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 1 14.29% 14.29% | 1 14.29% 28.57% | 0 0.00% 28.57% | 1 14.29% 42.86% | 1 14.29% 57.14% | 3 42.86% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SR.Store::total 7 +system.ruby.L1Cache_Controller.SR.L1_to_L2 | 0 0.00% 0.00% | 15 22.39% 22.39% | 0 0.00% 22.39% | 19 28.36% 50.75% | 1 1.49% 52.24% | 9 13.43% 65.67% | 11 16.42% 82.09% | 12 17.91% 100.00% +system.ruby.L1Cache_Controller.SR.L1_to_L2::total 67 +system.ruby.L1Cache_Controller.OR.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OR.Load::total 2 +system.ruby.L1Cache_Controller.OR.Store | 3 60.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OR.Store::total 5 +system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OR.L1_to_L2::total 3 +system.ruby.L1Cache_Controller.MR.Load | 31 12.16% 12.16% | 32 12.55% 24.71% | 28 10.98% 35.69% | 30 11.76% 47.45% | 29 11.37% 58.82% | 39 15.29% 74.12% | 31 12.16% 86.27% | 35 13.73% 100.00% +system.ruby.L1Cache_Controller.MR.Load::total 255 +system.ruby.L1Cache_Controller.MR.Store | 21 15.33% 15.33% | 20 14.60% 29.93% | 14 10.22% 40.15% | 15 10.95% 51.09% | 17 12.41% 63.50% | 11 8.03% 71.53% | 18 13.14% 84.67% | 21 15.33% 100.00% +system.ruby.L1Cache_Controller.MR.Store::total 137 +system.ruby.L1Cache_Controller.MR.L1_to_L2 | 85 11.52% 11.52% | 114 15.45% 26.96% | 93 12.60% 39.57% | 116 15.72% 55.28% | 75 10.16% 65.45% | 106 14.36% 79.81% | 89 12.06% 91.87% | 60 8.13% 100.00% +system.ruby.L1Cache_Controller.MR.L1_to_L2::total 738 +system.ruby.L1Cache_Controller.MMR.Load | 17 13.08% 13.08% | 15 11.54% 24.62% | 22 16.92% 41.54% | 14 10.77% 52.31% | 19 14.62% 66.92% | 16 12.31% 79.23% | 15 11.54% 90.77% | 12 9.23% 100.00% +system.ruby.L1Cache_Controller.MMR.Load::total 130 +system.ruby.L1Cache_Controller.MMR.Store | 11 15.28% 15.28% | 10 13.89% 29.17% | 10 13.89% 43.06% | 10 13.89% 56.94% | 10 13.89% 70.83% | 7 9.72% 80.56% | 6 8.33% 88.89% | 8 11.11% 100.00% +system.ruby.L1Cache_Controller.MMR.Store::total 72 +system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 92 24.40% 24.40% | 40 10.61% 35.01% | 50 13.26% 48.28% | 50 13.26% 61.54% | 56 14.85% 76.39% | 38 10.08% 86.47% | 37 9.81% 96.29% | 14 3.71% 100.00% +system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 377 +system.ruby.L1Cache_Controller.IM.L1_to_L2 | 279047 12.60% 12.60% | 277330 12.52% 25.12% | 275250 12.43% 37.55% | 279472 12.62% 50.17% | 278951 12.60% 62.76% | 271687 12.27% 75.03% | 273637 12.36% 87.39% | 279316 12.61% 100.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2214690 +system.ruby.L1Cache_Controller.IM.Other_GETX | 10 12.99% 12.99% | 7 9.09% 22.08% | 10 12.99% 35.06% | 8 10.39% 45.45% | 8 10.39% 55.84% | 12 15.58% 71.43% | 13 16.88% 88.31% | 9 11.69% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETX::total 77 +system.ruby.L1Cache_Controller.IM.Other_GETS | 14 9.93% 9.93% | 18 12.77% 22.70% | 9 6.38% 29.08% | 18 12.77% 41.84% | 24 17.02% 58.87% | 24 17.02% 75.89% | 23 16.31% 92.20% | 11 7.80% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETS::total 141 +system.ruby.L1Cache_Controller.IM.Ack | 192325 12.48% 12.48% | 194543 12.63% 25.11% | 192710 12.51% 37.62% | 193005 12.53% 50.15% | 192362 12.49% 62.64% | 190662 12.38% 75.01% | 191105 12.41% 87.42% | 193794 12.58% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1540506 +system.ruby.L1Cache_Controller.IM.Data | 1107 12.79% 12.79% | 1055 12.19% 24.98% | 1076 12.43% 37.41% | 1101 12.72% 50.13% | 1084 12.52% 62.65% | 1076 12.43% 75.08% | 1088 12.57% 87.65% | 1069 12.35% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 8656 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26870 12.46% 12.46% | 27253 12.64% 25.11% | 26946 12.50% 37.61% | 26984 12.52% 50.12% | 26942 12.50% 62.62% | 26653 12.36% 74.98% | 26748 12.41% 87.39% | 27179 12.61% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 215575 +system.ruby.L1Cache_Controller.SM.L1_to_L2 | 0 0.00% 0.00% | 3 5.17% 5.17% | 3 5.17% 10.34% | 11 18.97% 29.31% | 4 6.90% 36.21% | 11 18.97% 55.17% | 26 44.83% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.L1_to_L2::total 58 +system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 7 13.46% 13.46% | 14 26.92% 40.38% | 2 3.85% 44.23% | 7 13.46% 57.69% | 7 13.46% 71.15% | 15 28.85% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 52 +system.ruby.L1Cache_Controller.SM.Data | 0 0.00% 0.00% | 1 11.11% 11.11% | 2 22.22% 33.33% | 1 11.11% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 3 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Data::total 9 +system.ruby.L1Cache_Controller.OM.L1_to_L2 | 1 9.09% 9.09% | 10 90.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.L1_to_L2::total 11 +system.ruby.L1Cache_Controller.OM.Ack | 21 60.00% 60.00% | 7 20.00% 80.00% | 0 0.00% 80.00% | 7 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.Ack::total 35 +system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 3 60.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 5 +system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 6 +system.ruby.L1Cache_Controller.ISM.Ack | 103 13.09% 13.09% | 72 9.15% 22.24% | 81 10.29% 32.53% | 141 17.92% 50.44% | 104 13.21% 63.66% | 66 8.39% 72.05% | 123 15.63% 87.67% | 97 12.33% 100.00% +system.ruby.L1Cache_Controller.ISM.Ack::total 787 +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1107 12.78% 12.78% | 1056 12.19% 24.96% | 1078 12.44% 37.40% | 1102 12.72% 50.12% | 1085 12.52% 62.64% | 1077 12.43% 75.07% | 1091 12.59% 87.66% | 1069 12.34% 100.00% +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 8665 +system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 539 12.99% 12.99% | 495 11.93% 24.92% | 492 11.86% 36.77% | 419 10.10% 46.87% | 531 12.80% 59.66% | 564 13.59% 73.25% | 491 11.83% 85.08% | 619 14.92% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 4150 +system.ruby.L1Cache_Controller.M_W.Ack | 1679 12.46% 12.46% | 1730 12.83% 25.29% | 1809 13.42% 38.71% | 1706 12.66% 51.36% | 1691 12.54% 63.91% | 1597 11.85% 75.76% | 1608 11.93% 87.69% | 1660 12.31% 100.00% +system.ruby.L1Cache_Controller.M_W.Ack::total 13480 +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47493 12.48% 12.48% | 47526 12.49% 24.97% | 47535 12.49% 37.47% | 47618 12.52% 49.99% | 47488 12.48% 62.47% | 47930 12.60% 75.06% | 47754 12.55% 87.62% | 47113 12.38% 100.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 380457 +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 771 11.84% 11.84% | 740 11.36% 23.20% | 854 13.11% 36.31% | 604 9.27% 45.59% | 903 13.86% 59.45% | 860 13.20% 72.65% | 844 12.96% 85.61% | 937 14.39% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 6513 +system.ruby.L1Cache_Controller.MM_W.Ack | 2493 11.87% 11.87% | 2604 12.40% 24.26% | 2495 11.88% 36.14% | 2540 12.09% 48.23% | 2763 13.15% 61.38% | 2507 11.93% 73.31% | 2716 12.93% 86.24% | 2890 13.76% 100.00% +system.ruby.L1Cache_Controller.MM_W.Ack::total 21008 +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26870 12.46% 12.46% | 27253 12.64% 25.11% | 26946 12.50% 37.61% | 26984 12.52% 50.12% | 26942 12.50% 62.62% | 26653 12.36% 74.98% | 26748 12.41% 87.39% | 27179 12.61% 100.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 215575 +system.ruby.L1Cache_Controller.IS.L1_to_L2 | 498330 12.50% 12.50% | 498790 12.51% 25.01% | 499590 12.53% 37.54% | 497231 12.47% 50.01% | 499578 12.53% 62.54% | 501862 12.59% 75.12% | 498020 12.49% 87.61% | 493961 12.39% 100.00% +system.ruby.L1Cache_Controller.IS.L1_to_L2::total 3987362 +system.ruby.L1Cache_Controller.IS.Other_GETX | 16 11.51% 11.51% | 13 9.35% 20.86% | 20 14.39% 35.25% | 24 17.27% 52.52% | 18 12.95% 65.47% | 14 10.07% 75.54% | 20 14.39% 89.93% | 14 10.07% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETX::total 139 +system.ruby.L1Cache_Controller.IS.Other_GETS | 39 14.44% 14.44% | 43 15.93% 30.37% | 23 8.52% 38.89% | 35 12.96% 51.85% | 33 12.22% 64.07% | 32 11.85% 75.93% | 38 14.07% 90.00% | 27 10.00% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETS::total 270 +system.ruby.L1Cache_Controller.IS.Ack | 345718 12.46% 12.46% | 346858 12.50% 24.96% | 346646 12.49% 37.46% | 347061 12.51% 49.97% | 346855 12.50% 62.47% | 349503 12.60% 75.06% | 348504 12.56% 87.63% | 343326 12.37% 100.00% +system.ruby.L1Cache_Controller.IS.Ack::total 2774471 +system.ruby.L1Cache_Controller.IS.Shared_Ack | 44 11.43% 11.43% | 49 12.73% 24.16% | 57 14.81% 38.96% | 46 11.95% 50.91% | 36 9.35% 60.26% | 53 13.77% 74.03% | 48 12.47% 86.49% | 52 13.51% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Ack::total 385 +system.ruby.L1Cache_Controller.IS.Data | 1795 12.01% 12.01% | 1900 12.71% 24.72% | 1874 12.54% 37.26% | 1854 12.41% 49.67% | 1936 12.95% 62.62% | 1855 12.41% 75.04% | 1872 12.53% 87.56% | 1859 12.44% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 14945 +system.ruby.L1Cache_Controller.IS.Shared_Data | 1044 12.06% 12.06% | 1090 12.59% 24.65% | 1109 12.81% 37.47% | 1077 12.44% 49.91% | 1114 12.87% 62.78% | 1071 12.37% 75.15% | 1132 13.08% 88.23% | 1019 11.77% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Data::total 8656 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47493 12.48% 12.48% | 47526 12.49% 24.97% | 47535 12.49% 37.47% | 47618 12.52% 49.99% | 47488 12.48% 62.47% | 47930 12.60% 75.06% | 47754 12.55% 87.62% | 47113 12.38% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 380457 +system.ruby.L1Cache_Controller.SS.L1_to_L2 | 904 11.52% 11.52% | 1091 13.90% 25.42% | 1010 12.87% 38.29% | 1049 13.37% 51.66% | 1008 12.84% 64.50% | 1028 13.10% 77.60% | 970 12.36% 89.96% | 788 10.04% 100.00% +system.ruby.L1Cache_Controller.SS.L1_to_L2::total 7848 +system.ruby.L1Cache_Controller.SS.Ack | 2951 12.08% 12.08% | 3044 12.46% 24.53% | 3159 12.93% 37.46% | 3048 12.47% 49.93% | 3201 13.10% 63.03% | 2889 11.82% 74.86% | 3172 12.98% 87.84% | 2972 12.16% 100.00% +system.ruby.L1Cache_Controller.SS.Ack::total 24436 +system.ruby.L1Cache_Controller.SS.Shared_Ack | 2 7.41% 7.41% | 3 11.11% 18.52% | 3 11.11% 29.63% | 2 7.41% 37.04% | 2 7.41% 44.44% | 6 22.22% 66.67% | 1 3.70% 70.37% | 8 29.63% 100.00% +system.ruby.L1Cache_Controller.SS.Shared_Ack::total 27 +system.ruby.L1Cache_Controller.SS.All_acks | 1085 12.05% 12.05% | 1134 12.59% 24.64% | 1163 12.91% 37.55% | 1122 12.46% 50.01% | 1145 12.71% 62.72% | 1121 12.45% 75.16% | 1174 13.03% 88.20% | 1063 11.80% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks::total 9007 +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 1754 12.02% 12.02% | 1856 12.72% 24.74% | 1820 12.47% 37.21% | 1809 12.40% 49.60% | 1905 13.05% 62.66% | 1805 12.37% 75.02% | 1830 12.54% 87.56% | 1815 12.44% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 14594 +system.ruby.L1Cache_Controller.OI.Load | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OI.Load::total 3 -system.ruby.L1Cache_Controller.OI.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Other_GETX::total 2 -system.ruby.L1Cache_Controller.OI.Other_GETS | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETX | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 2 40.00% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETX::total 5 +system.ruby.L1Cache_Controller.OI.Other_GETS | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OI.Other_GETS::total 3 -system.ruby.L1Cache_Controller.OI.Merged_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Merged_GETS::total 1 -system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1085 12.95% 12.95% | 1073 12.81% 25.75% | 1027 12.26% 38.01% | 1041 12.42% 50.44% | 1020 12.17% 62.61% | 1047 12.50% 75.10% | 1077 12.85% 87.96% | 1009 12.04% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 8379 -system.ruby.L1Cache_Controller.MI.Load | 10 11.63% 11.63% | 11 12.79% 24.42% | 14 16.28% 40.70% | 12 13.95% 54.65% | 12 13.95% 68.60% | 8 9.30% 77.91% | 7 8.14% 86.05% | 12 13.95% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 86 -system.ruby.L1Cache_Controller.MI.Store | 7 12.07% 12.07% | 4 6.90% 18.97% | 4 6.90% 25.86% | 12 20.69% 46.55% | 9 15.52% 62.07% | 7 12.07% 74.14% | 8 13.79% 87.93% | 7 12.07% 100.00% -system.ruby.L1Cache_Controller.MI.Store::total 58 -system.ruby.L1Cache_Controller.MI.Other_GETX | 25 11.47% 11.47% | 32 14.68% 26.15% | 30 13.76% 39.91% | 25 11.47% 51.38% | 31 14.22% 65.60% | 29 13.30% 78.90% | 29 13.30% 92.20% | 17 7.80% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETX::total 218 -system.ruby.L1Cache_Controller.MI.Other_GETS | 47 13.31% 13.31% | 39 11.05% 24.36% | 39 11.05% 35.41% | 42 11.90% 47.31% | 48 13.60% 60.91% | 46 13.03% 73.94% | 63 17.85% 91.78% | 29 8.22% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETS::total 353 -system.ruby.L1Cache_Controller.MI.Merged_GETS | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MI.Merged_GETS::total 2 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 71509 12.46% 12.46% | 71917 12.54% 25.00% | 71762 12.51% 37.51% | 71899 12.53% 50.04% | 71741 12.51% 62.55% | 71488 12.46% 75.01% | 72063 12.56% 87.57% | 71314 12.43% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 573693 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 25 11.36% 11.36% | 32 14.55% 25.91% | 32 14.55% 40.45% | 25 11.36% 51.82% | 31 14.09% 65.91% | 29 13.18% 79.09% | 29 13.18% 92.27% | 17 7.73% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 220 -system.ruby.L1Cache_Controller.IT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% +system.ruby.L1Cache_Controller.OI.Merged_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Merged_GETS::total 2 +system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1055 12.45% 12.45% | 1057 12.47% 24.92% | 1035 12.21% 37.14% | 1081 12.76% 49.89% | 1041 12.28% 62.18% | 1043 12.31% 74.49% | 1099 12.97% 87.46% | 1063 12.54% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 8474 +system.ruby.L1Cache_Controller.MI.Load | 14 16.09% 16.09% | 13 14.94% 31.03% | 8 9.20% 40.23% | 11 12.64% 52.87% | 12 13.79% 66.67% | 8 9.20% 75.86% | 9 10.34% 86.21% | 12 13.79% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 87 +system.ruby.L1Cache_Controller.MI.Store | 5 10.20% 10.20% | 8 16.33% 26.53% | 5 10.20% 36.73% | 4 8.16% 44.90% | 7 14.29% 59.18% | 10 20.41% 79.59% | 4 8.16% 87.76% | 6 12.24% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 49 +system.ruby.L1Cache_Controller.MI.Other_GETX | 15 7.65% 7.65% | 26 13.27% 20.92% | 21 10.71% 31.63% | 15 7.65% 39.29% | 36 18.37% 57.65% | 32 16.33% 73.98% | 28 14.29% 88.27% | 23 11.73% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETX::total 196 +system.ruby.L1Cache_Controller.MI.Other_GETS | 43 10.75% 10.75% | 55 13.75% 24.50% | 44 11.00% 35.50% | 60 15.00% 50.50% | 44 11.00% 61.50% | 48 12.00% 73.50% | 49 12.25% 85.75% | 57 14.25% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETS::total 400 +system.ruby.L1Cache_Controller.MI.Merged_GETS | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MI.Merged_GETS::total 5 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72894 12.48% 12.48% | 73267 12.54% 25.02% | 73072 12.51% 37.52% | 73104 12.51% 50.04% | 72950 12.49% 62.52% | 73104 12.51% 75.03% | 73016 12.50% 87.53% | 72843 12.47% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 584250 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 16 7.96% 7.96% | 26 12.94% 20.90% | 21 10.45% 31.34% | 16 7.96% 39.30% | 36 17.91% 57.21% | 32 15.92% 73.13% | 29 14.43% 87.56% | 25 12.44% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 201 +system.ruby.L1Cache_Controller.IT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.IT.Load::total 3 -system.ruby.L1Cache_Controller.IT.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IT.Store::total 2 -system.ruby.L1Cache_Controller.IT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 4.17% 4.17% | 0 0.00% 4.17% | 11 45.83% 50.00% | 9 37.50% 87.50% | 3 12.50% 100.00% -system.ruby.L1Cache_Controller.IT.L1_to_L2::total 24 -system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 3 20.00% 20.00% | 0 0.00% 20.00% | 1 6.67% 26.67% | 2 13.33% 40.00% | 0 0.00% 40.00% | 4 26.67% 66.67% | 2 13.33% 80.00% | 3 20.00% 100.00% +system.ruby.L1Cache_Controller.IT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 15.38% 15.38% | 2 15.38% 30.77% | 9 69.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IT.L1_to_L2::total 13 +system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 2 13.33% 13.33% | 1 6.67% 20.00% | 3 20.00% 40.00% | 2 13.33% 53.33% | 2 13.33% 66.67% | 3 20.00% 86.67% | 0 0.00% 86.67% | 2 13.33% 100.00% system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total 15 -system.ruby.L1Cache_Controller.ST.Load | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00% -system.ruby.L1Cache_Controller.ST.Load::total 5 -system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.ST.Store::total 1 -system.ruby.L1Cache_Controller.ST.L1_to_L2 | 10 12.99% 12.99% | 21 27.27% 40.26% | 7 9.09% 49.35% | 9 11.69% 61.04% | 0 0.00% 61.04% | 0 0.00% 61.04% | 5 6.49% 67.53% | 25 32.47% 100.00% -system.ruby.L1Cache_Controller.ST.L1_to_L2::total 77 -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 2 8.70% 8.70% | 5 21.74% 30.43% | 4 17.39% 47.83% | 1 4.35% 52.17% | 0 0.00% 52.17% | 2 8.70% 60.87% | 3 13.04% 73.91% | 6 26.09% 100.00% -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 23 -system.ruby.L1Cache_Controller.OT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% -system.ruby.L1Cache_Controller.OT.Load::total 2 -system.ruby.L1Cache_Controller.OT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OT.L1_to_L2::total 6 -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 6 -system.ruby.L1Cache_Controller.MT.Load | 13 13.68% 13.68% | 7 7.37% 21.05% | 10 10.53% 31.58% | 13 13.68% 45.26% | 10 10.53% 55.79% | 14 14.74% 70.53% | 13 13.68% 84.21% | 15 15.79% 100.00% -system.ruby.L1Cache_Controller.MT.Load::total 95 -system.ruby.L1Cache_Controller.MT.Store | 6 10.71% 10.71% | 9 16.07% 26.79% | 9 16.07% 42.86% | 9 16.07% 58.93% | 9 16.07% 75.00% | 7 12.50% 87.50% | 5 8.93% 96.43% | 2 3.57% 100.00% -system.ruby.L1Cache_Controller.MT.Store::total 56 -system.ruby.L1Cache_Controller.MT.L1_to_L2 | 179 15.61% 15.61% | 117 10.20% 25.81% | 164 14.30% 40.10% | 171 14.91% 55.01% | 115 10.03% 65.04% | 155 13.51% 78.55% | 80 6.97% 85.53% | 166 14.47% 100.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1147 -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 49 13.14% 13.14% | 40 10.72% 23.86% | 60 16.09% 39.95% | 51 13.67% 53.62% | 41 10.99% 64.61% | 55 14.75% 79.36% | 37 9.92% 89.28% | 40 10.72% 100.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 373 -system.ruby.L1Cache_Controller.MMT.Load | 8 13.79% 13.79% | 11 18.97% 32.76% | 7 12.07% 44.83% | 8 13.79% 58.62% | 6 10.34% 68.97% | 4 6.90% 75.86% | 9 15.52% 91.38% | 5 8.62% 100.00% +system.ruby.L1Cache_Controller.ST.Load | 0 0.00% 0.00% | 2 22.22% 22.22% | 1 11.11% 33.33% | 3 33.33% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.ST.Load::total 9 +system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.Store::total 4 +system.ruby.L1Cache_Controller.ST.L1_to_L2 | 0 0.00% 0.00% | 15 17.24% 17.24% | 1 1.15% 18.39% | 19 21.84% 40.23% | 7 8.05% 48.28% | 14 16.09% 64.37% | 19 21.84% 86.21% | 12 13.79% 100.00% +system.ruby.L1Cache_Controller.ST.L1_to_L2::total 87 +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 0 0.00% 0.00% | 3 14.29% 14.29% | 4 19.05% 33.33% | 3 14.29% 47.62% | 3 14.29% 61.90% | 3 14.29% 76.19% | 3 14.29% 90.48% | 2 9.52% 100.00% +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 21 +system.ruby.L1Cache_Controller.OT.Load | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OT.Load::total 1 +system.ruby.L1Cache_Controller.OT.Store | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OT.Store::total 3 +system.ruby.L1Cache_Controller.OT.L1_to_L2 | 0 0.00% 0.00% | 12 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OT.L1_to_L2::total 12 +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 3 42.86% 42.86% | 2 28.57% 71.43% | 0 0.00% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 7 +system.ruby.L1Cache_Controller.MT.Load | 15 13.04% 13.04% | 15 13.04% 26.09% | 15 13.04% 39.13% | 18 15.65% 54.78% | 10 8.70% 63.48% | 19 16.52% 80.00% | 14 12.17% 92.17% | 9 7.83% 100.00% +system.ruby.L1Cache_Controller.MT.Load::total 115 +system.ruby.L1Cache_Controller.MT.Store | 9 15.00% 15.00% | 12 20.00% 35.00% | 6 10.00% 45.00% | 5 8.33% 53.33% | 9 15.00% 68.33% | 4 6.67% 75.00% | 5 8.33% 83.33% | 10 16.67% 100.00% +system.ruby.L1Cache_Controller.MT.Store::total 60 +system.ruby.L1Cache_Controller.MT.L1_to_L2 | 188 13.56% 13.56% | 221 15.95% 29.51% | 164 11.83% 41.34% | 173 12.48% 53.82% | 142 10.25% 64.07% | 170 12.27% 76.33% | 188 13.56% 89.90% | 140 10.10% 100.00% +system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1386 +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 52 13.27% 13.27% | 52 13.27% 26.53% | 42 10.71% 37.24% | 45 11.48% 48.72% | 46 11.73% 60.46% | 50 12.76% 73.21% | 49 12.50% 85.71% | 56 14.29% 100.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 392 +system.ruby.L1Cache_Controller.MMT.Load | 9 15.52% 15.52% | 7 12.07% 27.59% | 12 20.69% 48.28% | 6 10.34% 58.62% | 8 13.79% 72.41% | 7 12.07% 84.48% | 6 10.34% 94.83% | 3 5.17% 100.00% system.ruby.L1Cache_Controller.MMT.Load::total 58 -system.ruby.L1Cache_Controller.MMT.Store | 4 14.29% 14.29% | 3 10.71% 25.00% | 4 14.29% 39.29% | 2 7.14% 46.43% | 5 17.86% 64.29% | 3 10.71% 75.00% | 5 17.86% 92.86% | 2 7.14% 100.00% -system.ruby.L1Cache_Controller.MMT.Store::total 28 -system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 86 11.35% 11.35% | 139 18.34% 29.68% | 85 11.21% 40.90% | 97 12.80% 53.69% | 90 11.87% 65.57% | 91 12.01% 77.57% | 78 10.29% 87.86% | 92 12.14% 100.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 758 -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 21 10.29% 10.29% | 25 12.25% 22.55% | 34 16.67% 39.22% | 24 11.76% 50.98% | 25 12.25% 63.24% | 27 13.24% 76.47% | 27 13.24% 89.71% | 21 10.29% 100.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 204 -system.ruby.Directory_Controller.GETX 220023 0.00% 0.00% -system.ruby.Directory_Controller.GETS 406995 0.00% 0.00% -system.ruby.Directory_Controller.PUT 585083 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 220 0.00% 0.00% -system.ruby.Directory_Controller.UnblockS 23931 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 593445 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Clean 8030 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Dirty 349 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 360015 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 213674 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 597503 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 214013 0.00% 0.00% -system.ruby.Directory_Controller.All_Unblocks 439 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETX 61 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETS 97 0.00% 0.00% -system.ruby.Directory_Controller.NX.PUT 8595 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6880 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 12400 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 573697 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 8316 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 15375 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 201220 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 372612 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETX 205 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETS 439 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 2778 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockS 8092 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 592827 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockS 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockM 201 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.PUT 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockS 22 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockM 417 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.PUT 7 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.UnblockS 439 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 439 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETX 9 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETS 6 0.00% 0.00% -system.ruby.Directory_Controller.O_B.UnblockS 15374 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETX 1957 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETS 3492 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 582129 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETX 38 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETS 103 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.Memory_Data 15374 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 295 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 514 0.00% 0.00% -system.ruby.Directory_Controller.WB.PUT 4 0.00% 0.00% -system.ruby.Directory_Controller.WB.Unblock 220 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Clean 8030 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Dirty 349 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 360015 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 213674 0.00% 0.00% -system.ruby.Directory_Controller.WB_O_W.GETS 3 0.00% 0.00% -system.ruby.Directory_Controller.WB_O_W.Memory_Ack 348 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETX 1041 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 1953 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 213665 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.Store | 5 15.62% 15.62% | 6 18.75% 34.38% | 3 9.38% 43.75% | 7 21.88% 65.62% | 3 9.38% 75.00% | 3 9.38% 84.38% | 2 6.25% 90.62% | 3 9.38% 100.00% +system.ruby.L1Cache_Controller.MMT.Store::total 32 +system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 176 22.51% 22.51% | 96 12.28% 34.78% | 95 12.15% 46.93% | 80 10.23% 57.16% | 78 9.97% 67.14% | 94 12.02% 79.16% | 107 13.68% 92.84% | 56 7.16% 100.00% +system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 782 +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 28 13.86% 13.86% | 25 12.38% 26.24% | 32 15.84% 42.08% | 24 11.88% 53.96% | 29 14.36% 68.32% | 23 11.39% 79.70% | 21 10.40% 90.10% | 20 9.90% 100.00% +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 202 +system.ruby.Directory_Controller.GETX 227829 0.00% 0.00% +system.ruby.Directory_Controller.GETS 410069 0.00% 0.00% +system.ruby.Directory_Controller.PUT 595805 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 201 0.00% 0.00% +system.ruby.Directory_Controller.UnblockS 23601 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 604700 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Clean 8091 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Dirty 383 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 363032 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 221218 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 607721 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 221589 0.00% 0.00% +system.ruby.Directory_Controller.All_Unblocks 423 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETX 74 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETS 87 0.00% 0.00% +system.ruby.Directory_Controller.NX.PUT 8671 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 7327 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 12671 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 584254 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 8405 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 14947 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 208449 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 375946 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETX 243 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETS 423 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 2868 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockS 8198 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 604069 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.PUT 1 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockS 11 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockM 232 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockS 24 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockM 399 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.PUT 10 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.UnblockS 423 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 423 0.00% 0.00% +system.ruby.Directory_Controller.O_B.GETX 5 0.00% 0.00% +system.ruby.Directory_Controller.O_B.GETS 5 0.00% 0.00% +system.ruby.Directory_Controller.O_B.UnblockS 14945 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETX 1903 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETS 3455 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 592776 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETX 48 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETS 72 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.Memory_Data 14945 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 290 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 530 0.00% 0.00% +system.ruby.Directory_Controller.WB.PUT 1 0.00% 0.00% +system.ruby.Directory_Controller.WB.Unblock 201 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Clean 8091 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Dirty 383 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 363032 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 221218 0.00% 0.00% +system.ruby.Directory_Controller.WB_O_W.GETX 3 0.00% 0.00% +system.ruby.Directory_Controller.WB_O_W.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.WB_O_W.Memory_Ack 383 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETX 1082 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 1931 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 221206 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index ef37353bc..f296585bd 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,529 +1,529 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.008665 # Number of seconds simulated -sim_ticks 8664886 # Number of ticks simulated -final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.008851 # Number of seconds simulated +sim_ticks 8851106 # Number of ticks simulated +final_tick 8851106 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 160889 # Simulator tick rate (ticks/s) -host_mem_usage 306216 # Number of bytes of host memory used -host_seconds 53.86 # Real time elapsed on the host +host_tick_rate 251677 # Simulator tick rate (ticks/s) +host_mem_usage 263028 # Number of bytes of host memory used +host_seconds 35.17 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 1237687 # delay histogram for all message -system.ruby.delayHist::mean 0.014190 # delay histogram for all message -system.ruby.delayHist::stdev 0.298328 # delay histogram for all message -system.ruby.delayHist | 1235151 99.80% 99.80% | 1617 0.13% 99.93% | 897 0.07% 100.00% | 6 0.00% 100.00% | 12 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1237687 # delay histogram for all message +system.ruby.delayHist::samples 1264357 # delay histogram for all message +system.ruby.delayHist::mean 0.014702 # delay histogram for all message +system.ruby.delayHist::stdev 0.302971 # delay histogram for all message +system.ruby.delayHist | 1261652 99.79% 99.79% | 1743 0.14% 99.92% | 940 0.07% 100.00% | 5 0.00% 100.00% | 13 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1264357 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 617680 -system.ruby.outstanding_req_hist::mean 15.998443 -system.ruby.outstanding_req_hist::gmean 15.997160 -system.ruby.outstanding_req_hist::stdev 0.126732 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 18 0.00% 0.02% | 617558 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 617680 +system.ruby.outstanding_req_hist::samples 630979 +system.ruby.outstanding_req_hist::mean 15.998479 +system.ruby.outstanding_req_hist::gmean 15.997223 +system.ruby.outstanding_req_hist::stdev 0.125377 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 16 0.00% 0.02% | 630859 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 630979 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 617552 -system.ruby.latency_hist::mean 1795.769022 -system.ruby.latency_hist::gmean 1749.288930 -system.ruby.latency_hist::stdev 410.975839 -system.ruby.latency_hist | 49 0.01% 0.01% | 8521 1.38% 1.39% | 161856 26.21% 27.60% | 292941 47.44% 75.03% | 127050 20.57% 95.61% | 24164 3.91% 99.52% | 2669 0.43% 99.95% | 258 0.04% 99.99% | 42 0.01% 100.00% | 2 0.00% 100.00% -system.ruby.latency_hist::total 617552 +system.ruby.latency_hist::samples 630851 +system.ruby.latency_hist::mean 1795.719672 +system.ruby.latency_hist::gmean 1748.933148 +system.ruby.latency_hist::stdev 412.147444 +system.ruby.latency_hist | 49 0.01% 0.01% | 8914 1.41% 1.42% | 165687 26.26% 27.68% | 297783 47.20% 74.89% | 130737 20.72% 95.61% | 24608 3.90% 99.51% | 2780 0.44% 99.95% | 265 0.04% 100.00% | 24 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.latency_hist::total 630851 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 617552 -system.ruby.miss_latency_hist::mean 1795.769022 -system.ruby.miss_latency_hist::gmean 1749.288930 -system.ruby.miss_latency_hist::stdev 410.975839 -system.ruby.miss_latency_hist | 49 0.01% 0.01% | 8521 1.38% 1.39% | 161856 26.21% 27.60% | 292941 47.44% 75.03% | 127050 20.57% 95.61% | 24164 3.91% 99.52% | 2669 0.43% 99.95% | 258 0.04% 99.99% | 42 0.01% 100.00% | 2 0.00% 100.00% -system.ruby.miss_latency_hist::total 617552 -system.ruby.L1Cache.incomplete_times 8208 -system.ruby.Directory.incomplete_times 609337 +system.ruby.miss_latency_hist::samples 630851 +system.ruby.miss_latency_hist::mean 1795.719672 +system.ruby.miss_latency_hist::gmean 1748.933148 +system.ruby.miss_latency_hist::stdev 412.147444 +system.ruby.miss_latency_hist | 49 0.01% 0.01% | 8914 1.41% 1.42% | 165687 26.26% 27.68% | 297783 47.20% 74.89% | 130737 20.72% 95.61% | 24608 3.90% 99.51% | 2780 0.44% 99.95% | 265 0.04% 100.00% | 24 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.miss_latency_hist::total 630851 +system.ruby.L1Cache.incomplete_times 8485 +system.ruby.Directory.incomplete_times 622362 system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.cacheMemory.demand_misses 77331 # Number of cache demand misses -system.ruby.l1_cntrl4.cacheMemory.demand_accesses 77331 # Number of cache demand accesses +system.ruby.l1_cntrl4.cacheMemory.demand_misses 78801 # Number of cache demand misses +system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78801 # Number of cache demand accesses system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.cacheMemory.demand_misses 77389 # Number of cache demand misses -system.ruby.l1_cntrl5.cacheMemory.demand_accesses 77389 # Number of cache demand accesses +system.ruby.l1_cntrl5.cacheMemory.demand_misses 78712 # Number of cache demand misses +system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78712 # Number of cache demand accesses system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.cacheMemory.demand_misses 77354 # Number of cache demand misses -system.ruby.l1_cntrl6.cacheMemory.demand_accesses 77354 # Number of cache demand accesses +system.ruby.l1_cntrl6.cacheMemory.demand_misses 78682 # Number of cache demand misses +system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78682 # Number of cache demand accesses system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.cacheMemory.demand_misses 77281 # Number of cache demand misses -system.ruby.l1_cntrl7.cacheMemory.demand_accesses 77281 # Number of cache demand accesses +system.ruby.l1_cntrl7.cacheMemory.demand_misses 79132 # Number of cache demand misses +system.ruby.l1_cntrl7.cacheMemory.demand_accesses 79132 # Number of cache demand accesses system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 77377 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 77377 # Number of cache demand accesses +system.ruby.l1_cntrl0.cacheMemory.demand_misses 78906 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78906 # Number of cache demand accesses system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.cacheMemory.demand_misses 77193 # Number of cache demand misses -system.ruby.l1_cntrl1.cacheMemory.demand_accesses 77193 # Number of cache demand accesses +system.ruby.l1_cntrl1.cacheMemory.demand_misses 78862 # Number of cache demand misses +system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78862 # Number of cache demand accesses system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.cacheMemory.demand_misses 76824 # Number of cache demand misses -system.ruby.l1_cntrl2.cacheMemory.demand_accesses 76824 # Number of cache demand accesses +system.ruby.l1_cntrl2.cacheMemory.demand_misses 78717 # Number of cache demand misses +system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78717 # Number of cache demand accesses system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.cacheMemory.demand_misses 76825 # Number of cache demand misses -system.ruby.l1_cntrl3.cacheMemory.demand_accesses 76825 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 4.474669 -system.ruby.network.routers0.msg_count.Control::2 77377 -system.ruby.network.routers0.msg_count.Data::2 76667 -system.ruby.network.routers0.msg_count.Response_Data::4 78423 -system.ruby.network.routers0.msg_count.Writeback_Control::3 77713 -system.ruby.network.routers0.msg_bytes.Control::2 619016 -system.ruby.network.routers0.msg_bytes.Data::2 5520024 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5646456 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 621704 -system.ruby.network.routers1.percent_links_utilized 4.463498 -system.ruby.network.routers1.msg_count.Control::2 77193 -system.ruby.network.routers1.msg_count.Data::2 76469 -system.ruby.network.routers1.msg_count.Response_Data::4 78234 -system.ruby.network.routers1.msg_count.Writeback_Control::3 77508 -system.ruby.network.routers1.msg_bytes.Control::2 617544 -system.ruby.network.routers1.msg_bytes.Data::2 5505768 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5632848 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 620064 -system.ruby.network.routers2.percent_links_utilized 4.442205 -system.ruby.network.routers2.msg_count.Control::2 76824 -system.ruby.network.routers2.msg_count.Data::2 76104 -system.ruby.network.routers2.msg_count.Response_Data::4 77861 -system.ruby.network.routers2.msg_count.Writeback_Control::3 77139 -system.ruby.network.routers2.msg_bytes.Control::2 614592 -system.ruby.network.routers2.msg_bytes.Data::2 5479488 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5605992 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 617112 -system.ruby.network.routers3.percent_links_utilized 4.442687 -system.ruby.network.routers3.msg_count.Control::2 76823 -system.ruby.network.routers3.msg_count.Data::2 76096 -system.ruby.network.routers3.msg_count.Response_Data::4 77886 -system.ruby.network.routers3.msg_count.Writeback_Control::3 77157 -system.ruby.network.routers3.msg_bytes.Control::2 614584 -system.ruby.network.routers3.msg_bytes.Data::2 5478912 -system.ruby.network.routers3.msg_bytes.Response_Data::4 5607792 -system.ruby.network.routers3.msg_bytes.Writeback_Control::3 617256 -system.ruby.network.routers4.percent_links_utilized 4.471582 -system.ruby.network.routers4.msg_count.Control::2 77331 -system.ruby.network.routers4.msg_count.Data::2 76659 -system.ruby.network.routers4.msg_count.Response_Data::4 78324 -system.ruby.network.routers4.msg_count.Writeback_Control::3 77652 -system.ruby.network.routers4.msg_bytes.Control::2 618648 -system.ruby.network.routers4.msg_bytes.Data::2 5519448 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5639328 -system.ruby.network.routers4.msg_bytes.Writeback_Control::3 621216 -system.ruby.network.routers5.percent_links_utilized 4.475356 -system.ruby.network.routers5.msg_count.Control::2 77389 -system.ruby.network.routers5.msg_count.Data::2 76728 -system.ruby.network.routers5.msg_count.Response_Data::4 78386 -system.ruby.network.routers5.msg_count.Writeback_Control::3 77723 -system.ruby.network.routers5.msg_bytes.Control::2 619112 -system.ruby.network.routers5.msg_bytes.Data::2 5524416 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5643792 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 621784 -system.ruby.network.routers6.percent_links_utilized 4.472419 -system.ruby.network.routers6.msg_count.Control::2 77354 -system.ruby.network.routers6.msg_count.Data::2 76662 -system.ruby.network.routers6.msg_count.Response_Data::4 78350 -system.ruby.network.routers6.msg_count.Writeback_Control::3 77658 -system.ruby.network.routers6.msg_bytes.Control::2 618832 -system.ruby.network.routers6.msg_bytes.Data::2 5519664 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5641200 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 621264 -system.ruby.network.routers7.percent_links_utilized 4.468123 -system.ruby.network.routers7.msg_count.Control::2 77277 -system.ruby.network.routers7.msg_count.Data::2 76568 -system.ruby.network.routers7.msg_count.Response_Data::4 78296 -system.ruby.network.routers7.msg_count.Writeback_Control::3 77585 -system.ruby.network.routers7.msg_bytes.Control::2 618216 -system.ruby.network.routers7.msg_bytes.Data::2 5512896 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5637312 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 620680 +system.ruby.l1_cntrl3.cacheMemory.demand_misses 79057 # Number of cache demand misses +system.ruby.l1_cntrl3.cacheMemory.demand_accesses 79057 # Number of cache demand accesses +system.ruby.network.routers0.percent_links_utilized 4.466411 +system.ruby.network.routers0.msg_count.Control::2 78906 +system.ruby.network.routers0.msg_count.Data::2 78209 +system.ruby.network.routers0.msg_count.Response_Data::4 79922 +system.ruby.network.routers0.msg_count.Writeback_Control::3 79222 +system.ruby.network.routers0.msg_bytes.Control::2 631248 +system.ruby.network.routers0.msg_bytes.Data::2 5631048 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5754384 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 633776 +system.ruby.network.routers1.percent_links_utilized 4.464072 +system.ruby.network.routers1.msg_count.Control::2 78862 +system.ruby.network.routers1.msg_count.Data::2 78116 +system.ruby.network.routers1.msg_count.Response_Data::4 79932 +system.ruby.network.routers1.msg_count.Writeback_Control::3 79185 +system.ruby.network.routers1.msg_bytes.Control::2 630896 +system.ruby.network.routers1.msg_bytes.Data::2 5624352 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5755104 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 633480 +system.ruby.network.routers2.percent_links_utilized 4.456923 +system.ruby.network.routers2.msg_count.Control::2 78717 +system.ruby.network.routers2.msg_count.Data::2 78011 +system.ruby.network.routers2.msg_count.Response_Data::4 79784 +system.ruby.network.routers2.msg_count.Writeback_Control::3 79076 +system.ruby.network.routers2.msg_bytes.Control::2 629736 +system.ruby.network.routers2.msg_bytes.Data::2 5616792 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5744448 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 632608 +system.ruby.network.routers3.percent_links_utilized 4.475147 +system.ruby.network.routers3.msg_count.Control::2 79057 +system.ruby.network.routers3.msg_count.Data::2 78335 +system.ruby.network.routers3.msg_count.Response_Data::4 80105 +system.ruby.network.routers3.msg_count.Writeback_Control::3 79383 +system.ruby.network.routers3.msg_bytes.Control::2 632456 +system.ruby.network.routers3.msg_bytes.Data::2 5640120 +system.ruby.network.routers3.msg_bytes.Response_Data::4 5767560 +system.ruby.network.routers3.msg_bytes.Writeback_Control::3 635064 +system.ruby.network.routers4.percent_links_utilized 4.460937 +system.ruby.network.routers4.msg_count.Control::2 78801 +system.ruby.network.routers4.msg_count.Data::2 78061 +system.ruby.network.routers4.msg_count.Response_Data::4 79876 +system.ruby.network.routers4.msg_count.Writeback_Control::3 79135 +system.ruby.network.routers4.msg_bytes.Control::2 630408 +system.ruby.network.routers4.msg_bytes.Data::2 5620392 +system.ruby.network.routers4.msg_bytes.Response_Data::4 5751072 +system.ruby.network.routers4.msg_bytes.Writeback_Control::3 633080 +system.ruby.network.routers5.percent_links_utilized 4.455593 +system.ruby.network.routers5.msg_count.Control::2 78712 +system.ruby.network.routers5.msg_count.Data::2 77972 +system.ruby.network.routers5.msg_count.Response_Data::4 79776 +system.ruby.network.routers5.msg_count.Writeback_Control::3 79033 +system.ruby.network.routers5.msg_bytes.Control::2 629696 +system.ruby.network.routers5.msg_bytes.Data::2 5613984 +system.ruby.network.routers5.msg_bytes.Response_Data::4 5743872 +system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632264 +system.ruby.network.routers6.percent_links_utilized 4.454384 +system.ruby.network.routers6.msg_count.Control::2 78682 +system.ruby.network.routers6.msg_count.Data::2 77916 +system.ruby.network.routers6.msg_count.Response_Data::4 79789 +system.ruby.network.routers6.msg_count.Writeback_Control::3 79022 +system.ruby.network.routers6.msg_bytes.Control::2 629456 +system.ruby.network.routers6.msg_bytes.Data::2 5609952 +system.ruby.network.routers6.msg_bytes.Response_Data::4 5744808 +system.ruby.network.routers6.msg_bytes.Writeback_Control::3 632176 +system.ruby.network.routers7.percent_links_utilized 4.479124 +system.ruby.network.routers7.msg_count.Control::2 79132 +system.ruby.network.routers7.msg_count.Data::2 78429 +system.ruby.network.routers7.msg_count.Response_Data::4 80152 +system.ruby.network.routers7.msg_count.Writeback_Control::3 79450 +system.ruby.network.routers7.msg_bytes.Control::2 633056 +system.ruby.network.routers7.msg_bytes.Data::2 5646888 +system.ruby.network.routers7.msg_bytes.Response_Data::4 5770944 +system.ruby.network.routers7.msg_bytes.Writeback_Control::3 635600 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 1218678 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 609346 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 609308 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 60173 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 45858057 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 1522193 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 40100008 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 87480258 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 71.782914 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 7076344 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 12585722 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4642017 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1076094 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 9195209 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memNotOld 11282671 # memory stalls due to anti starvation -system.ruby.dir_cntrl0.memBuffer.memBankCount | 38404 3.15% 3.15% | 37646 3.09% 6.24% | 38381 3.15% 9.39% | 38273 3.14% 12.53% | 38109 3.13% 15.66% | 38021 3.12% 18.78% | 38580 3.17% 21.94% | 38357 3.15% 25.09% | 38057 3.12% 28.21% | 38004 3.12% 31.33% | 38123 3.13% 34.46% | 37658 3.09% 37.55% | 37751 3.10% 40.65% | 38546 3.16% 43.81% | 37560 3.08% 46.89% | 38514 3.16% 50.05% | 38232 3.14% 53.19% | 38045 3.12% 56.31% | 38749 3.18% 59.49% | 38589 3.17% 62.66% | 38066 3.12% 65.78% | 37687 3.09% 68.87% | 38032 3.12% 71.99% | 38060 3.12% 75.12% | 37804 3.10% 78.22% | 38206 3.14% 81.35% | 37726 3.10% 84.45% | 38148 3.13% 87.58% | 37682 3.09% 90.67% | 38049 3.12% 93.79% | 37701 3.09% 96.89% | 37918 3.11% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1218678 # Number of accesses per bank -system.ruby.network.routers8.percent_links_utilized 35.284146 -system.ruby.network.routers8.msg_count.Control::2 617562 -system.ruby.network.routers8.msg_count.Data::2 611948 -system.ruby.network.routers8.msg_count.Response_Data::4 609345 -system.ruby.network.routers8.msg_count.Writeback_Control::3 620135 -system.ruby.network.routers8.msg_bytes.Control::2 4940496 -system.ruby.network.routers8.msg_bytes.Data::2 44060256 -system.ruby.network.routers8.msg_bytes.Response_Data::4 43872840 -system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4961080 -system.ruby.network.routers9.percent_links_utilized 7.888285 -system.ruby.network.routers9.msg_count.Control::2 617562 -system.ruby.network.routers9.msg_count.Data::2 611948 -system.ruby.network.routers9.msg_count.Response_Data::4 617553 -system.ruby.network.routers9.msg_count.Writeback_Control::3 620135 -system.ruby.network.routers9.msg_bytes.Control::2 4940496 -system.ruby.network.routers9.msg_bytes.Data::2 44060256 -system.ruby.network.routers9.msg_bytes.Response_Data::4 44463816 -system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4961080 -system.ruby.network.msg_count.Control 1852692 -system.ruby.network.msg_count.Data 1835849 -system.ruby.network.msg_count.Response_Data 1852658 -system.ruby.network.msg_count.Writeback_Control 1860405 -system.ruby.network.msg_byte.Control 14821536 -system.ruby.network.msg_byte.Data 132181128 -system.ruby.network.msg_byte.Response_Data 133391376 -system.ruby.network.msg_byte.Writeback_Control 14883240 +system.ruby.dir_cntrl0.memBuffer.memReq 1244736 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 622369 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 622327 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 61466 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 46843919 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 1544719 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 40914855 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 89303493 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 71.744927 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 7226521 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 12850865 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4733152 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1096174 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 9395532 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memNotOld 11541675 # memory stalls due to anti starvation +system.ruby.dir_cntrl0.memBuffer.memBankCount | 39236 3.15% 3.15% | 39187 3.15% 6.30% | 38854 3.12% 9.42% | 39063 3.14% 12.56% | 38454 3.09% 15.65% | 39210 3.15% 18.80% | 39083 3.14% 21.94% | 39085 3.14% 25.08% | 38983 3.13% 28.21% | 39280 3.16% 31.37% | 39090 3.14% 34.51% | 38371 3.08% 37.59% | 38752 3.11% 40.70% | 38808 3.12% 43.82% | 39073 3.14% 46.96% | 38752 3.11% 50.07% | 38633 3.10% 53.18% | 39174 3.15% 56.32% | 38907 3.13% 59.45% | 39057 3.14% 62.59% | 38471 3.09% 65.68% | 38694 3.11% 68.79% | 38561 3.10% 71.88% | 38553 3.10% 74.98% | 38571 3.10% 78.08% | 38875 3.12% 81.20% | 39085 3.14% 84.34% | 39006 3.13% 87.48% | 39194 3.15% 90.63% | 38693 3.11% 93.74% | 38713 3.11% 96.85% | 39268 3.15% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1244736 # Number of accesses per bank +system.ruby.network.routers8.percent_links_utilized 35.281218 +system.ruby.network.routers8.msg_count.Control::2 630869 +system.ruby.network.routers8.msg_count.Data::2 625049 +system.ruby.network.routers8.msg_count.Response_Data::4 622367 +system.ruby.network.routers8.msg_count.Writeback_Control::3 633506 +system.ruby.network.routers8.msg_bytes.Control::2 5046952 +system.ruby.network.routers8.msg_bytes.Data::2 45003528 +system.ruby.network.routers8.msg_bytes.Response_Data::4 44810424 +system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5068048 +system.ruby.network.routers9.percent_links_utilized 7.888201 +system.ruby.network.routers9.msg_count.Control::2 630869 +system.ruby.network.routers9.msg_count.Data::2 625049 +system.ruby.network.routers9.msg_count.Response_Data::4 630851 +system.ruby.network.routers9.msg_count.Writeback_Control::3 633506 +system.ruby.network.routers9.msg_bytes.Control::2 5046952 +system.ruby.network.routers9.msg_bytes.Data::2 45003528 +system.ruby.network.routers9.msg_bytes.Response_Data::4 45421272 +system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5068048 +system.ruby.network.msg_count.Control 1892607 +system.ruby.network.msg_count.Data 1875147 +system.ruby.network.msg_count.Response_Data 1892554 +system.ruby.network.msg_count.Writeback_Control 1900518 +system.ruby.network.msg_byte.Control 15140856 +system.ruby.network.msg_byte.Data 135010584 +system.ruby.network.msg_byte.Response_Data 136263888 +system.ruby.network.msg_byte.Writeback_Control 15204144 system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 99885 # number of read accesses completed -system.cpu0.num_writes 54375 # number of write accesses completed +system.cpu0.num_reads 99672 # number of read accesses completed +system.cpu0.num_writes 55456 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99537 # number of read accesses completed -system.cpu1.num_writes 53839 # number of write accesses completed +system.cpu1.num_reads 99787 # number of read accesses completed +system.cpu1.num_writes 55562 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99297 # number of read accesses completed -system.cpu2.num_writes 53929 # number of write accesses completed +system.cpu2.num_reads 99865 # number of read accesses completed +system.cpu2.num_writes 55847 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99124 # number of read accesses completed -system.cpu3.num_writes 54072 # number of write accesses completed +system.cpu3.num_reads 99798 # number of read accesses completed +system.cpu3.num_writes 55621 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99259 # number of read accesses completed -system.cpu4.num_writes 54427 # number of write accesses completed +system.cpu4.num_reads 99867 # number of read accesses completed +system.cpu4.num_writes 55560 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99389 # number of read accesses completed -system.cpu5.num_writes 54074 # number of write accesses completed +system.cpu5.num_reads 99021 # number of read accesses completed +system.cpu5.num_writes 55459 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99658 # number of read accesses completed -system.cpu6.num_writes 54033 # number of write accesses completed +system.cpu6.num_reads 99570 # number of read accesses completed +system.cpu6.num_writes 55395 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 53796 # number of write accesses completed +system.cpu7.num_writes 56251 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers0.throttle0.link_utilization 4.466810 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 77375 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 77713 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5571000 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 621704 -system.ruby.network.routers0.throttle1.link_utilization 4.482529 -system.ruby.network.routers0.throttle1.msg_count.Control::2 77377 -system.ruby.network.routers0.throttle1.msg_count.Data::2 76667 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1048 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 619016 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5520024 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 75456 -system.ruby.network.routers1.throttle0.link_utilization 4.456123 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 77192 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 77508 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5557824 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 620064 -system.ruby.network.routers1.throttle1.link_utilization 4.470872 -system.ruby.network.routers1.throttle1.msg_count.Control::2 77193 -system.ruby.network.routers1.throttle1.msg_count.Data::2 76469 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1042 -system.ruby.network.routers1.throttle1.msg_bytes.Control::2 617544 -system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5505768 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 75024 -system.ruby.network.routers2.throttle0.link_utilization 4.434727 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 76821 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 77139 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5531112 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 617112 -system.ruby.network.routers2.throttle1.link_utilization 4.449683 -system.ruby.network.routers2.throttle1.msg_count.Control::2 76824 -system.ruby.network.routers2.throttle1.msg_count.Data::2 76104 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1040 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 614592 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5479488 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 74880 -system.ruby.network.routers3.throttle0.link_utilization 4.434830 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 76821 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 77157 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5531112 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 617256 -system.ruby.network.routers3.throttle1.link_utilization 4.450543 -system.ruby.network.routers3.throttle1.msg_count.Control::2 76823 -system.ruby.network.routers3.throttle1.msg_count.Data::2 76096 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1065 -system.ruby.network.routers3.throttle1.msg_bytes.Control::2 614584 -system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5478912 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 76680 -system.ruby.network.routers4.throttle0.link_utilization 4.464069 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 77329 -system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 77652 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5567688 -system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 621216 -system.ruby.network.routers4.throttle1.link_utilization 4.479095 -system.ruby.network.routers4.throttle1.msg_count.Control::2 77331 -system.ruby.network.routers4.throttle1.msg_count.Data::2 76659 -system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 995 -system.ruby.network.routers4.throttle1.msg_bytes.Control::2 618648 -system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5519448 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 71640 -system.ruby.network.routers5.throttle0.link_utilization 4.467387 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 77385 -system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 77723 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5571720 -system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 621784 -system.ruby.network.routers5.throttle1.link_utilization 4.483325 -system.ruby.network.routers5.throttle1.msg_count.Control::2 77389 -system.ruby.network.routers5.throttle1.msg_count.Data::2 76728 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1001 -system.ruby.network.routers5.throttle1.msg_bytes.Control::2 619112 -system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5524416 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 72072 -system.ruby.network.routers6.throttle0.link_utilization 4.465298 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 77352 -system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 77658 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5569344 -system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 621264 -system.ruby.network.routers6.throttle1.link_utilization 4.479540 -system.ruby.network.routers6.throttle1.msg_count.Control::2 77354 -system.ruby.network.routers6.throttle1.msg_count.Data::2 76662 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 998 -system.ruby.network.routers6.throttle1.msg_bytes.Control::2 618832 -system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5519664 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 71856 -system.ruby.network.routers7.throttle0.link_utilization 4.460982 -system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 77277 -system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 77585 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5563944 -system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 620680 -system.ruby.network.routers7.throttle1.link_utilization 4.475264 -system.ruby.network.routers7.throttle1.msg_count.Control::2 77277 -system.ruby.network.routers7.throttle1.msg_count.Data::2 76568 -system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1019 -system.ruby.network.routers7.throttle1.msg_bytes.Control::2 618216 -system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5512896 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 73368 -system.ruby.network.routers8.throttle0.link_utilization 35.344302 -system.ruby.network.routers8.throttle0.msg_count.Control::2 617562 -system.ruby.network.routers8.throttle0.msg_count.Data::2 611948 -system.ruby.network.routers8.throttle0.msg_bytes.Control::2 4940496 -system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44060256 -system.ruby.network.routers8.throttle1.link_utilization 35.223989 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 609345 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 620135 -system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43872840 -system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4961080 -system.ruby.network.routers9.throttle0.link_utilization 4.466810 -system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 77375 -system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 77713 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5571000 -system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 621704 -system.ruby.network.routers9.throttle1.link_utilization 4.456123 -system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 77192 -system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 77508 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5557824 -system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 620064 -system.ruby.network.routers9.throttle2.link_utilization 4.434727 -system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 76821 -system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 77139 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5531112 -system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 617112 -system.ruby.network.routers9.throttle3.link_utilization 4.434830 -system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 76821 -system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 77157 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5531112 -system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 617256 -system.ruby.network.routers9.throttle4.link_utilization 4.464081 -system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 77330 -system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 77652 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5567760 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 621216 -system.ruby.network.routers9.throttle5.link_utilization 4.467387 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 77385 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 77723 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5571720 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 621784 -system.ruby.network.routers9.throttle6.link_utilization 4.465298 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 77352 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 77658 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5569344 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 621264 -system.ruby.network.routers9.throttle7.link_utilization 4.460982 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 77277 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 77585 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5563944 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 620680 -system.ruby.network.routers9.throttle8.link_utilization 35.344325 -system.ruby.network.routers9.throttle8.msg_count.Control::2 617562 -system.ruby.network.routers9.throttle8.msg_count.Data::2 611948 -system.ruby.network.routers9.throttle8.msg_bytes.Control::2 4940496 -system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44060256 +system.ruby.network.routers0.throttle0.link_utilization 4.459092 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78904 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79222 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5681088 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 633776 +system.ruby.network.routers0.throttle1.link_utilization 4.473729 +system.ruby.network.routers0.throttle1.msg_count.Control::2 78906 +system.ruby.network.routers0.throttle1.msg_count.Data::2 78209 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1018 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 631248 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5631048 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 73296 +system.ruby.network.routers1.throttle0.link_utilization 4.456697 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78861 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 79185 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5677992 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 633480 +system.ruby.network.routers1.throttle1.link_utilization 4.471447 +system.ruby.network.routers1.throttle1.msg_count.Control::2 78862 +system.ruby.network.routers1.throttle1.msg_count.Data::2 78116 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1071 +system.ruby.network.routers1.throttle1.msg_bytes.Control::2 630896 +system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5624352 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 77112 +system.ruby.network.routers2.throttle0.link_utilization 4.448659 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78715 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79076 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5667480 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 632608 +system.ruby.network.routers2.throttle1.link_utilization 4.465188 +system.ruby.network.routers2.throttle1.msg_count.Control::2 78717 +system.ruby.network.routers2.throttle1.msg_count.Data::2 78011 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1069 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 629736 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5616792 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 76968 +system.ruby.network.routers3.throttle0.link_utilization 4.467628 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 79054 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 79383 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5691888 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 635064 +system.ruby.network.routers3.throttle1.link_utilization 4.482666 +system.ruby.network.routers3.throttle1.msg_count.Control::2 79057 +system.ruby.network.routers3.throttle1.msg_count.Data::2 78335 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1051 +system.ruby.network.routers3.throttle1.msg_bytes.Control::2 632456 +system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5640120 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 75672 +system.ruby.network.routers4.throttle0.link_utilization 4.453263 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78799 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 79135 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5673528 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 633080 +system.ruby.network.routers4.throttle1.link_utilization 4.468611 +system.ruby.network.routers4.throttle1.msg_count.Control::2 78801 +system.ruby.network.routers4.throttle1.msg_count.Data::2 78061 +system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1077 +system.ruby.network.routers4.throttle1.msg_bytes.Control::2 630408 +system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5620392 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 77544 +system.ruby.network.routers5.throttle0.link_utilization 4.448111 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78709 +system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79033 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5667048 +system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632264 +system.ruby.network.routers5.throttle1.link_utilization 4.463075 +system.ruby.network.routers5.throttle1.msg_count.Control::2 78712 +system.ruby.network.routers5.throttle1.msg_count.Data::2 77972 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1067 +system.ruby.network.routers5.throttle1.msg_bytes.Control::2 629696 +system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5613984 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 76824 +system.ruby.network.routers6.throttle0.link_utilization 4.446523 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78679 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 79022 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5664888 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 632176 +system.ruby.network.routers6.throttle1.link_utilization 4.462245 +system.ruby.network.routers6.throttle1.msg_count.Control::2 78682 +system.ruby.network.routers6.throttle1.msg_count.Data::2 77916 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1110 +system.ruby.network.routers6.throttle1.msg_bytes.Control::2 629456 +system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5609952 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 79920 +system.ruby.network.routers7.throttle0.link_utilization 4.471854 +system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 79130 +system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 79450 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5697360 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 635600 +system.ruby.network.routers7.throttle1.link_utilization 4.486394 +system.ruby.network.routers7.throttle1.msg_count.Control::2 79132 +system.ruby.network.routers7.throttle1.msg_count.Data::2 78429 +system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1022 +system.ruby.network.routers7.throttle1.msg_bytes.Control::2 633056 +system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5646888 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 73584 +system.ruby.network.routers8.throttle0.link_utilization 35.341967 +system.ruby.network.routers8.throttle0.msg_count.Control::2 630869 +system.ruby.network.routers8.throttle0.msg_count.Data::2 625049 +system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5046952 +system.ruby.network.routers8.throttle0.msg_bytes.Data::2 45003528 +system.ruby.network.routers8.throttle1.link_utilization 35.220468 +system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 622367 +system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 633506 +system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44810424 +system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5068048 +system.ruby.network.routers9.throttle0.link_utilization 4.459092 +system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78904 +system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 79222 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5681088 +system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 633776 +system.ruby.network.routers9.throttle1.link_utilization 4.456697 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78861 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 79185 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5677992 +system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 633480 +system.ruby.network.routers9.throttle2.link_utilization 4.448659 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78715 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 79076 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5667480 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 632608 +system.ruby.network.routers9.throttle3.link_utilization 4.467628 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 79054 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 79383 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5691888 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 635064 +system.ruby.network.routers9.throttle4.link_utilization 4.453263 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78799 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 79135 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5673528 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 633080 +system.ruby.network.routers9.throttle5.link_utilization 4.448111 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78709 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79033 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5667048 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632264 +system.ruby.network.routers9.throttle6.link_utilization 4.446523 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78679 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 79022 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5664888 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 632176 +system.ruby.network.routers9.throttle7.link_utilization 4.471871 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 79130 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 79450 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5697360 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 635600 +system.ruby.network.routers9.throttle8.link_utilization 35.341967 +system.ruby.network.routers9.throttle8.msg_count.Control::2 630869 +system.ruby.network.routers9.throttle8.msg_count.Data::2 625049 +system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5046952 +system.ruby.network.routers9.throttle8.msg_bytes.Data::2 45003528 system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 617552 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.002021 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.103548 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 617290 99.96% 99.96% | 0 0.00% 99.96% | 38 0.01% 99.96% | 0 0.00% 99.96% | 102 0.02% 99.98% | 0 0.00% 99.98% | 106 0.02% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 617552 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 630851 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.002302 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.111910 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 630553 99.95% 99.95% | 0 0.00% 99.95% | 42 0.01% 99.96% | 0 0.00% 99.96% | 109 0.02% 99.98% | 0 0.00% 99.98% | 122 0.02% 100.00% | 0 0.00% 100.00% | 25 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 630851 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 4 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 39 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 620135 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.026309 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.408237 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 617823 99.63% 99.63% | 1409 0.23% 99.85% | 881 0.14% 100.00% | 6 0.00% 100.00% | 12 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 620135 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 633506 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.027049 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.412821 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 631057 99.61% 99.61% | 1512 0.24% 99.85% | 915 0.14% 100.00% | 5 0.00% 100.00% | 13 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 633506 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 401489 -system.ruby.LD.latency_hist::mean 1796.245110 -system.ruby.LD.latency_hist::gmean 1749.779554 -system.ruby.LD.latency_hist::stdev 410.866792 -system.ruby.LD.latency_hist | 31 0.01% 0.01% | 5545 1.38% 1.39% | 105136 26.19% 27.58% | 190357 47.41% 74.99% | 82770 20.62% 95.60% | 15751 3.92% 99.53% | 1714 0.43% 99.95% | 157 0.04% 99.99% | 27 0.01% 100.00% | 1 0.00% 100.00% -system.ruby.LD.latency_hist::total 401489 +system.ruby.LD.latency_hist::samples 405837 +system.ruby.LD.latency_hist::mean 1795.827911 +system.ruby.LD.latency_hist::gmean 1749.100087 +system.ruby.LD.latency_hist::stdev 411.882283 +system.ruby.LD.latency_hist | 28 0.01% 0.01% | 5711 1.41% 1.41% | 106493 26.24% 27.65% | 191622 47.22% 74.87% | 84296 20.77% 95.64% | 15709 3.87% 99.51% | 1790 0.44% 99.95% | 171 0.04% 100.00% | 14 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.latency_hist::total 405837 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 401489 -system.ruby.LD.miss_latency_hist::mean 1796.245110 -system.ruby.LD.miss_latency_hist::gmean 1749.779554 -system.ruby.LD.miss_latency_hist::stdev 410.866792 -system.ruby.LD.miss_latency_hist | 31 0.01% 0.01% | 5545 1.38% 1.39% | 105136 26.19% 27.58% | 190357 47.41% 74.99% | 82770 20.62% 95.60% | 15751 3.92% 99.53% | 1714 0.43% 99.95% | 157 0.04% 99.99% | 27 0.01% 100.00% | 1 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 401489 +system.ruby.LD.miss_latency_hist::samples 405837 +system.ruby.LD.miss_latency_hist::mean 1795.827911 +system.ruby.LD.miss_latency_hist::gmean 1749.100087 +system.ruby.LD.miss_latency_hist::stdev 411.882283 +system.ruby.LD.miss_latency_hist | 28 0.01% 0.01% | 5711 1.41% 1.41% | 106493 26.24% 27.65% | 191622 47.22% 74.87% | 84296 20.77% 95.64% | 15709 3.87% 99.51% | 1790 0.44% 99.95% | 171 0.04% 100.00% | 14 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 405837 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 216063 -system.ruby.ST.latency_hist::mean 1794.884353 -system.ruby.ST.latency_hist::gmean 1748.377616 -system.ruby.ST.latency_hist::stdev 411.177879 -system.ruby.ST.latency_hist | 18 0.01% 0.01% | 2976 1.38% 1.39% | 56720 26.25% 27.64% | 102584 47.48% 75.12% | 44280 20.49% 95.61% | 8413 3.89% 99.50% | 955 0.44% 99.95% | 101 0.05% 99.99% | 15 0.01% 100.00% | 1 0.00% 100.00% -system.ruby.ST.latency_hist::total 216063 +system.ruby.ST.latency_hist::samples 225014 +system.ruby.ST.latency_hist::mean 1795.524452 +system.ruby.ST.latency_hist::gmean 1748.632095 +system.ruby.ST.latency_hist::stdev 412.626104 +system.ruby.ST.latency_hist | 21 0.01% 0.01% | 3203 1.42% 1.43% | 59194 26.31% 27.74% | 106161 47.18% 74.92% | 46441 20.64% 95.56% | 8899 3.95% 99.51% | 990 0.44% 99.95% | 94 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.ST.latency_hist::total 225014 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 216063 -system.ruby.ST.miss_latency_hist::mean 1794.884353 -system.ruby.ST.miss_latency_hist::gmean 1748.377616 -system.ruby.ST.miss_latency_hist::stdev 411.177879 -system.ruby.ST.miss_latency_hist | 18 0.01% 0.01% | 2976 1.38% 1.39% | 56720 26.25% 27.64% | 102584 47.48% 75.12% | 44280 20.49% 95.61% | 8413 3.89% 99.50% | 955 0.44% 99.95% | 101 0.05% 99.99% | 15 0.01% 100.00% | 1 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 216063 +system.ruby.ST.miss_latency_hist::samples 225014 +system.ruby.ST.miss_latency_hist::mean 1795.524452 +system.ruby.ST.miss_latency_hist::gmean 1748.632095 +system.ruby.ST.miss_latency_hist::stdev 412.626104 +system.ruby.ST.miss_latency_hist | 21 0.01% 0.01% | 3203 1.42% 1.43% | 59194 26.31% 27.74% | 106161 47.18% 74.92% | 46441 20.64% 95.56% | 8899 3.95% 99.51% | 990 0.44% 99.95% | 94 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 225014 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 8208 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1692.829678 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 1644.794246 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 406.296234 -system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 237 2.89% 2.89% | 2860 34.84% 37.73% | 3603 43.90% 81.63% | 1287 15.68% 97.31% | 196 2.39% 99.70% | 22 0.27% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 8208 +system.ruby.L1Cache.miss_mach_latency_hist::samples 8485 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1687.011432 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 1638.183403 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 410.098641 +system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 266 3.13% 3.13% | 3055 36.00% 39.14% | 3618 42.64% 81.78% | 1298 15.30% 97.08% | 223 2.63% 99.71% | 23 0.27% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 8485 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 609344 -system.ruby.Directory.miss_mach_latency_hist::mean 1797.155638 -system.ruby.Directory.miss_mach_latency_hist::gmean 1750.740893 -system.ruby.Directory.miss_mach_latency_hist::stdev 410.862833 -system.ruby.Directory.miss_mach_latency_hist | 49 0.01% 0.01% | 8284 1.36% 1.37% | 158996 26.09% 27.46% | 289338 47.48% 74.94% | 125763 20.64% 95.58% | 23968 3.93% 99.52% | 2647 0.43% 99.95% | 255 0.04% 99.99% | 42 0.01% 100.00% | 2 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 609344 +system.ruby.Directory.miss_mach_latency_hist::samples 622366 +system.ruby.Directory.miss_mach_latency_hist::mean 1797.201741 +system.ruby.Directory.miss_mach_latency_hist::gmean 1750.493671 +system.ruby.Directory.miss_mach_latency_hist::stdev 411.977479 +system.ruby.Directory.miss_mach_latency_hist | 49 0.01% 0.01% | 8648 1.39% 1.40% | 162632 26.13% 27.53% | 294165 47.27% 74.79% | 129439 20.80% 95.59% | 24385 3.92% 99.51% | 2757 0.44% 99.95% | 263 0.04% 100.00% | 24 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 622366 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 7 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 7 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 4 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 4 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 7 -system.ruby.Directory.miss_latency_hist.initial_to_forward | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 7 +system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 4 +system.ruby.Directory.miss_latency_hist.initial_to_forward | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.initial_to_forward::total 4 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 7 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 7 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 32 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 319 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 7 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 113.714286 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 104.188552 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 50.582323 -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 1 14.29% 14.29% | 3 42.86% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 3 42.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 7 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 4 +system.ruby.Directory.miss_latency_hist.forward_to_first_response | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 4 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 4 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75.250000 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 73.906370 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 17.211914 +system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 4 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5357 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1694.452679 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1647.221011 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 402.824830 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 154 2.87% 2.87% | 1856 34.65% 37.52% | 2366 44.17% 81.69% | 844 15.76% 97.44% | 121 2.26% 99.70% | 14 0.26% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5357 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5527 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1686.068572 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1637.388551 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 409.754972 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 173 3.13% 3.13% | 1989 35.99% 39.12% | 2361 42.72% 81.83% | 838 15.16% 97.00% | 151 2.73% 99.73% | 14 0.25% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5527 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 396132 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1797.621677 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1751.209372 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 410.802147 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 31 0.01% 0.01% | 5391 1.36% 1.37% | 103280 26.07% 27.44% | 187991 47.46% 74.90% | 81926 20.68% 95.58% | 15630 3.95% 99.52% | 1700 0.43% 99.95% | 155 0.04% 99.99% | 27 0.01% 100.00% | 1 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 396132 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 400310 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1797.343336 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1750.694650 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 411.707345 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 28 0.01% 0.01% | 5538 1.38% 1.39% | 104504 26.11% 27.50% | 189261 47.28% 74.77% | 83458 20.85% 95.62% | 15558 3.89% 99.51% | 1776 0.44% 99.95% | 170 0.04% 100.00% | 14 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 400310 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 2851 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1689.780077 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1640.244046 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 412.793948 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 83 2.91% 2.91% | 1004 35.22% 38.13% | 1237 43.39% 81.52% | 443 15.54% 97.05% | 75 2.63% 99.68% | 8 0.28% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 2851 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 2958 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1688.773158 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1639.669612 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 410.803541 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 93 3.14% 3.14% | 1066 36.04% 39.18% | 1257 42.49% 81.68% | 460 15.55% 97.23% | 72 2.43% 99.66% | 9 0.30% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 2958 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213212 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1796.289773 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1749.870827 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 410.975121 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 18 0.01% 0.01% | 2893 1.36% 1.37% | 55716 26.13% 27.50% | 101347 47.53% 75.03% | 43837 20.56% 95.59% | 8338 3.91% 99.50% | 947 0.44% 99.95% | 100 0.05% 99.99% | 15 0.01% 100.00% | 1 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213212 -system.ruby.L1Cache_Controller.Load | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50037 12.46% 37.53% | 49672 12.37% 49.90% | 50004 12.45% 62.35% | 50305 12.53% 74.88% | 50279 12.52% 87.40% | 50578 12.60% 100.00% -system.ruby.L1Cache_Controller.Load::total 401503 -system.ruby.L1Cache_Controller.Store | 27007 12.50% 12.50% | 26935 12.47% 24.96% | 26787 12.40% 37.36% | 27153 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.53% 75.11% | 27075 12.53% 87.64% | 26703 12.36% 100.00% -system.ruby.L1Cache_Controller.Store::total 216071 -system.ruby.L1Cache_Controller.Data | 77375 12.53% 12.53% | 77192 12.50% 25.03% | 76821 12.44% 37.47% | 76821 12.44% 49.91% | 77329 12.52% 62.43% | 77385 12.53% 74.96% | 77352 12.53% 87.49% | 77277 12.51% 100.00% -system.ruby.L1Cache_Controller.Data::total 617552 -system.ruby.L1Cache_Controller.Fwd_GETX | 1048 12.77% 12.77% | 1042 12.69% 25.46% | 1040 12.67% 38.13% | 1065 12.98% 51.11% | 995 12.12% 63.23% | 1001 12.20% 75.43% | 998 12.16% 87.59% | 1019 12.41% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 8208 -system.ruby.L1Cache_Controller.Replacement | 77373 12.53% 12.53% | 77189 12.50% 25.03% | 76820 12.44% 37.47% | 76821 12.44% 49.91% | 77327 12.52% 62.43% | 77385 12.53% 74.96% | 77350 12.53% 87.49% | 77277 12.51% 100.00% -system.ruby.L1Cache_Controller.Replacement::total 617542 -system.ruby.L1Cache_Controller.Writeback_Ack | 76323 12.53% 12.53% | 76144 12.50% 25.02% | 75775 12.44% 37.46% | 75751 12.43% 49.89% | 76330 12.53% 62.42% | 76378 12.54% 74.95% | 76350 12.53% 87.49% | 76253 12.51% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 609304 -system.ruby.L1Cache_Controller.Writeback_Nack | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 2623 -system.ruby.L1Cache_Controller.I.Load | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50037 12.46% 37.53% | 49672 12.37% 49.90% | 50004 12.45% 62.35% | 50305 12.53% 74.88% | 50279 12.52% 87.40% | 50578 12.60% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 401503 -system.ruby.L1Cache_Controller.I.Store | 27007 12.50% 12.50% | 26935 12.47% 24.96% | 26787 12.40% 37.36% | 27153 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.53% 75.11% | 27075 12.53% 87.64% | 26703 12.36% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 216071 -system.ruby.L1Cache_Controller.I.Replacement | 706 12.64% 12.64% | 720 12.89% 25.53% | 716 12.82% 38.35% | 724 12.96% 51.32% | 668 11.96% 63.28% | 657 11.76% 75.04% | 688 12.32% 87.36% | 706 12.64% 100.00% -system.ruby.L1Cache_Controller.I.Replacement::total 5585 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 2623 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 706 12.64% 12.64% | 720 12.89% 25.53% | 716 12.82% 38.35% | 724 12.96% 51.32% | 668 11.96% 63.28% | 657 11.76% 75.04% | 688 12.32% 87.36% | 706 12.64% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 5585 -system.ruby.L1Cache_Controller.M.Replacement | 76667 12.53% 12.53% | 76469 12.50% 25.02% | 76104 12.44% 37.46% | 76097 12.44% 49.90% | 76659 12.53% 62.42% | 76728 12.54% 74.96% | 76662 12.53% 87.49% | 76571 12.51% 100.00% -system.ruby.L1Cache_Controller.M.Replacement::total 611957 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 2623 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 76323 12.53% 12.53% | 76144 12.50% 25.02% | 75775 12.44% 37.46% | 75751 12.43% 49.89% | 76330 12.53% 62.42% | 76378 12.54% 74.95% | 76350 12.53% 87.49% | 76253 12.51% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 609304 -system.ruby.L1Cache_Controller.IS.Data | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50035 12.46% 37.53% | 49669 12.37% 49.90% | 50002 12.45% 62.35% | 50301 12.53% 74.88% | 50278 12.52% 87.40% | 50576 12.60% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 401489 -system.ruby.L1Cache_Controller.IM.Data | 27005 12.50% 12.50% | 26934 12.47% 24.96% | 26786 12.40% 37.36% | 27152 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.54% 75.11% | 27074 12.53% 87.64% | 26701 12.36% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 216063 -system.ruby.Directory_Controller.GETX 791175 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 609324 0.00% 0.00% -system.ruby.Directory_Controller.PUTX_NotOwner 2623 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 609345 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 609304 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 609354 0.00% 0.00% -system.ruby.Directory_Controller.M.GETX 8208 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 609324 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX_NotOwner 2623 0.00% 0.00% -system.ruby.Directory_Controller.IM.GETX 65257 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 609345 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 108356 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 609304 0.00% 0.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 222056 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1796.946482 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1750.131417 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 412.464819 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 21 0.01% 0.01% | 3110 1.40% 1.41% | 58128 26.18% 27.59% | 104904 47.24% 74.83% | 45981 20.71% 95.54% | 8827 3.98% 99.51% | 981 0.44% 99.95% | 93 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 222056 +system.ruby.L1Cache_Controller.Load | 50822 12.52% 12.52% | 50930 12.55% 25.07% | 50579 12.46% 37.53% | 50992 12.56% 50.10% | 50750 12.50% 62.60% | 50396 12.42% 75.02% | 50785 12.51% 87.53% | 50593 12.47% 100.00% +system.ruby.L1Cache_Controller.Load::total 405847 +system.ruby.L1Cache_Controller.Store | 28084 12.48% 12.48% | 27932 12.41% 24.89% | 28138 12.50% 37.40% | 28065 12.47% 49.87% | 28051 12.47% 62.34% | 28316 12.58% 74.92% | 27897 12.40% 87.32% | 28539 12.68% 100.00% +system.ruby.L1Cache_Controller.Store::total 225022 +system.ruby.L1Cache_Controller.Data | 78904 12.51% 12.51% | 78861 12.50% 25.01% | 78715 12.48% 37.49% | 79054 12.53% 50.02% | 78799 12.49% 62.51% | 78709 12.48% 74.98% | 78679 12.47% 87.46% | 79130 12.54% 100.00% +system.ruby.L1Cache_Controller.Data::total 630851 +system.ruby.L1Cache_Controller.Fwd_GETX | 1018 12.00% 12.00% | 1071 12.62% 24.62% | 1069 12.60% 37.22% | 1051 12.39% 49.61% | 1077 12.69% 62.30% | 1067 12.58% 74.87% | 1110 13.08% 87.96% | 1022 12.04% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 8485 +system.ruby.L1Cache_Controller.Replacement | 78902 12.51% 12.51% | 78858 12.50% 25.01% | 78713 12.48% 37.49% | 79053 12.53% 50.02% | 78797 12.49% 62.51% | 78708 12.48% 74.98% | 78678 12.47% 87.46% | 79128 12.54% 100.00% +system.ruby.L1Cache_Controller.Replacement::total 630837 +system.ruby.L1Cache_Controller.Writeback_Ack | 77879 12.51% 12.51% | 77785 12.50% 25.01% | 77640 12.48% 37.49% | 77999 12.53% 50.02% | 77717 12.49% 62.51% | 77635 12.48% 74.99% | 77564 12.46% 87.45% | 78105 12.55% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 622324 +system.ruby.L1Cache_Controller.Writeback_Nack | 325 12.05% 12.05% | 329 12.20% 24.25% | 367 13.61% 37.86% | 333 12.35% 50.20% | 341 12.64% 62.85% | 331 12.27% 75.12% | 348 12.90% 88.02% | 323 11.98% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 2697 +system.ruby.L1Cache_Controller.I.Load | 50822 12.52% 12.52% | 50930 12.55% 25.07% | 50579 12.46% 37.53% | 50992 12.56% 50.10% | 50750 12.50% 62.60% | 50396 12.42% 75.02% | 50785 12.51% 87.53% | 50593 12.47% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 405847 +system.ruby.L1Cache_Controller.I.Store | 28084 12.48% 12.48% | 27932 12.41% 24.89% | 28138 12.50% 37.40% | 28065 12.47% 49.87% | 28051 12.47% 62.34% | 28316 12.58% 74.92% | 27897 12.40% 87.32% | 28539 12.68% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 225022 +system.ruby.L1Cache_Controller.I.Replacement | 693 11.97% 11.97% | 742 12.82% 24.79% | 702 12.13% 36.92% | 718 12.40% 49.33% | 736 12.72% 62.04% | 736 12.72% 74.76% | 762 13.17% 87.92% | 699 12.08% 100.00% +system.ruby.L1Cache_Controller.I.Replacement::total 5788 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 325 12.05% 12.05% | 329 12.20% 24.25% | 367 13.61% 37.86% | 333 12.35% 50.20% | 341 12.64% 62.85% | 331 12.27% 75.12% | 348 12.90% 88.02% | 323 11.98% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 2697 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 693 11.97% 11.97% | 742 12.82% 24.79% | 702 12.13% 36.92% | 718 12.40% 49.33% | 736 12.72% 62.04% | 736 12.72% 74.76% | 762 13.17% 87.92% | 699 12.08% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 5788 +system.ruby.L1Cache_Controller.M.Replacement | 78209 12.51% 12.51% | 78116 12.50% 25.01% | 78011 12.48% 37.49% | 78335 12.53% 50.02% | 78061 12.49% 62.51% | 77972 12.47% 74.99% | 77916 12.47% 87.45% | 78429 12.55% 100.00% +system.ruby.L1Cache_Controller.M.Replacement::total 625049 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 325 12.05% 12.05% | 329 12.20% 24.25% | 367 13.61% 37.86% | 333 12.35% 50.20% | 341 12.64% 62.85% | 331 12.27% 75.12% | 348 12.90% 88.02% | 323 11.98% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 2697 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77879 12.51% 12.51% | 77785 12.50% 25.01% | 77640 12.48% 37.49% | 77999 12.53% 50.02% | 77717 12.49% 62.51% | 77635 12.48% 74.99% | 77564 12.46% 87.45% | 78105 12.55% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 622324 +system.ruby.L1Cache_Controller.IS.Data | 50821 12.52% 12.52% | 50929 12.55% 25.07% | 50577 12.46% 37.53% | 50990 12.56% 50.10% | 50750 12.51% 62.60% | 50395 12.42% 75.02% | 50783 12.51% 87.53% | 50592 12.47% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 405837 +system.ruby.L1Cache_Controller.IM.Data | 28083 12.48% 12.48% | 27932 12.41% 24.89% | 28138 12.50% 37.40% | 28064 12.47% 49.87% | 28049 12.47% 62.34% | 28314 12.58% 74.92% | 27896 12.40% 87.32% | 28538 12.68% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 225014 +system.ruby.Directory_Controller.GETX 808444 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 622352 0.00% 0.00% +system.ruby.Directory_Controller.PUTX_NotOwner 2697 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 622367 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 622324 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 622384 0.00% 0.00% +system.ruby.Directory_Controller.M.GETX 8485 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 622352 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX_NotOwner 2697 0.00% 0.00% +system.ruby.Directory_Controller.IM.GETX 68392 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 622367 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETX 109183 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 622324 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index d30a7aa16..ee0a55e41 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,663 +1,664 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000653 # Number of seconds simulated -sim_ticks 652606500 # Number of ticks simulated -final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000667 # Number of seconds simulated +sim_ticks 666669000 # Number of ticks simulated +final_tick 666669000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 148113487 # Simulator tick rate (ticks/s) -host_mem_usage 336812 # Number of bytes of host memory used -host_seconds 4.41 # Real time elapsed on the host +host_tick_rate 89799840 # Simulator tick rate (ticks/s) +host_mem_usage 343700 # Number of bytes of host memory used +host_seconds 7.42 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 79011 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 80501 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 83900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 78451 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 80299 # Number of bytes read from this memory -system.physmem.bytes_read::total 645272 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 398848 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5221 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5261 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5379 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5284 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5253 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5355 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5238 # Number of bytes written to this memory -system.physmem.bytes_written::total 441215 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11034 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11072 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88226 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6232 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5221 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5261 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5376 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5284 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5253 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5355 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5238 # Number of write requests responded to by this memory -system.physmem.num_writes::total 48599 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 122606808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 125725073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 124189692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 121069894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 123353047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 128561392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 120211797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 123043519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 988761221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 611161550 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 8000227 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 8061519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 8242333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 8237736 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 8096763 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 8049261 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 8205557 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 8026276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 676081222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 611161550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 130607035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 133786593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 132432025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 129307630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 131449809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 136610653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 128417354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 131069795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1664842443 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 1664833249 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 85134 # Transaction distribution -system.membus.trans_dist::ReadResp 85128 # Transaction distribution -system.membus.trans_dist::WriteReq 42367 # Transaction distribution -system.membus.trans_dist::WriteResp 42365 # Transaction distribution -system.membus.trans_dist::Writeback 6232 # Transaction distribution -system.membus.trans_dist::UpgradeReq 57414 # Transaction distribution -system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution -system.membus.trans_dist::ReadExReq 48586 # Transaction distribution -system.membus.trans_dist::ReadExResp 3092 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 417062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 417062 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1086481 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1086481 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1086481 # Total data (bytes) +system.physmem.bytes_read::cpu0 77587 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 78448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 79552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79510 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 77345 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78315 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 77919 # Number of bytes read from this memory +system.physmem.bytes_read::total 627100 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 389952 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5508 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5505 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5430 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5540 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5487 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5602 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory +system.physmem.bytes_written::total 433881 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10825 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10880 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10824 # Number of read requests responded to by this memory +system.physmem.num_reads::total 86938 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6093 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5508 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5505 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5430 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5540 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5487 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50022 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 116380093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 117635588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 117671588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 119327582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 119264583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 116017094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 117472089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 116878091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 940646708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 584925953 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 8261971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 8257471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 8144971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 8309971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 8053472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 8230471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 8402971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 8231971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 650819222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 584925953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 124642064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 125893059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 125816560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 127637553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 127318054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 124247565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 125875059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 125110062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1591465930 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1591365430 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 83865 # Transaction distribution +system.membus.trans_dist::ReadResp 83861 # Transaction distribution +system.membus.trans_dist::WriteReq 43929 # Transaction distribution +system.membus.trans_dist::WriteResp 43926 # Transaction distribution +system.membus.trans_dist::Writeback 6093 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58314 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47560 # Transaction distribution +system.membus.trans_dist::ReadExReq 50259 # Transaction distribution +system.membus.trans_dist::ReadExResp 3073 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 420880 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1060914 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1060914 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1060914 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 43.9 # Layer utilization (%) -system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 47.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 288472152 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 43.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 310892000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 46.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 13254 # number of replacements -system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use -system.l2c.tags.total_refs 149317 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks. +system.l2c.tags.replacements 13077 # number of replacements +system.l2c.tags.tagsinuse 783.417350 # Cycle average of tags in use +system.l2c.tags.total_refs 150095 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13853 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.834837 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 811 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 611 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.791992 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1942968 # Number of tag accesses -system.l2c.tags.data_accesses 1942968 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10808 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10838 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85773 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 74336 # number of Writeback hits -system.l2c.Writeback_hits::total 74336 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 322 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 337 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 354 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 353 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 378 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2757 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1930 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1860 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1868 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1850 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1871 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1809 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1953 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14999 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12565 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12612 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12658 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12594 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12557 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12678 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12696 # number of demand (read+write) hits -system.l2c.demand_hits::total 100772 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12565 # number of overall hits -system.l2c.overall_hits::cpu1 12412 # number of overall hits -system.l2c.overall_hits::cpu2 12612 # number of overall hits -system.l2c.overall_hits::cpu3 12658 # number of overall hits -system.l2c.overall_hits::cpu4 12594 # number of overall hits -system.l2c.overall_hits::cpu5 12557 # number of overall hits -system.l2c.overall_hits::cpu6 12678 # number of overall hits -system.l2c.overall_hits::cpu7 12696 # number of overall hits -system.l2c.overall_hits::total 100772 # number of overall hits -system.l2c.ReadReq_misses::cpu0 751 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 742 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 744 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 696 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 727 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 735 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 708 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 698 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5801 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1964 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1929 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1920 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1880 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1830 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1887 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1963 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15294 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4321 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4353 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4358 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4233 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4361 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4404 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4224 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4317 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34571 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5072 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5095 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5102 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 4929 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5088 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5139 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 4932 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5015 # number of demand (read+write) misses -system.l2c.demand_misses::total 40372 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5072 # number of overall misses -system.l2c.overall_misses::cpu1 5095 # number of overall misses -system.l2c.overall_misses::cpu2 5102 # number of overall misses -system.l2c.overall_misses::cpu3 4929 # number of overall misses -system.l2c.overall_misses::cpu4 5088 # number of overall misses -system.l2c.overall_misses::cpu5 5139 # number of overall misses -system.l2c.overall_misses::cpu6 4932 # number of overall misses -system.l2c.overall_misses::cpu7 5015 # number of overall misses -system.l2c.overall_misses::total 40372 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 46656500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 45888000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 46214500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 43225999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 45481000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 44732500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 43604500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 43142000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 358944999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 54482000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 56107500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 54698000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 55749000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 51718500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 55828000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 55452500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 58605500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 442641000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 232354499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 234531000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 234959000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 228552499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 234872500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 237965000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 227719000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 232651999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1863605497 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 279010999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 280419000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 281173500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 271778498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 280353500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 282697500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 271323500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 275793999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2222550496 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 279010999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 280419000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 281173500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 271778498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 280353500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 282697500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 271323500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 275793999 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2222550496 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11386 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11294 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11488 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11504 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11450 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11483 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11433 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11536 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 91574 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 74336 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 74336 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2296 # number of UpgradeReq accesses(hits+misses) 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6083 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6232 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6213 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6177 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6175 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 49570 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17637 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17507 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17714 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17587 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17682 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17696 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17610 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17711 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 141144 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17637 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17507 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17714 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17587 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17682 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17696 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17610 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17711 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 141144 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.065958 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.065699 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.064763 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.060501 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.063493 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.064008 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.061926 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.060506 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.063348 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.855401 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.856952 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.850687 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.841540 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.846438 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.842411 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.846256 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.838531 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.847266 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.691249 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.700628 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.699968 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.695874 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.699775 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.708836 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.683827 # miss rate for ReadExReq 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overall accesses -system.l2c.overall_miss_rate::cpu2 0.288021 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.280264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.287750 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.290405 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.280068 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.283157 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.286034 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 62125.832224 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61843.665768 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 62116.263441 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 62106.320402 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 62559.834938 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 60860.544218 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61588.276836 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61808.022923 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61876.400448 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 27740.325866 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 29086.314152 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28488.541667 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29653.723404 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28261.475410 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29585.585586 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28866.475794 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29855.068772 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28942.134170 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53773.316131 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.015162 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53914.410280 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53993.030711 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53857.486815 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54033.832879 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53910.748106 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53892.054436 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53906.612392 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55010.055008 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55038.076546 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55110.446884 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55138.668695 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55100.923742 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55010.215995 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55012.875101 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54993.818345 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55051.780838 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55010.055008 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55038.076546 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55110.446884 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55138.668695 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55100.923742 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55010.215995 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55012.875101 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54993.818345 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55051.780838 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 13487 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 730.528683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.960741 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.211335 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.682597 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.340197 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.666463 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 5.896963 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.159072 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.971301 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.713407 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006798 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006066 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006526 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006192 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.005759 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006991 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006808 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765056 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 556 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1967301 # Number of tag accesses +system.l2c.tags.data_accesses 1967301 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10709 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10684 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10837 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10726 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10672 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10767 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10772 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85828 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 76131 # number of Writeback hits +system.l2c.Writeback_hits::total 76131 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 391 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 342 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 349 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 350 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 327 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 361 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2756 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1955 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1901 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1956 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1993 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1935 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1923 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1905 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15515 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12656 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12639 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12738 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12682 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12654 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12607 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12690 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12677 # number of demand (read+write) hits +system.l2c.demand_hits::total 101343 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12656 # number of overall hits +system.l2c.overall_hits::cpu1 12639 # number of overall hits +system.l2c.overall_hits::cpu2 12738 # number of overall hits +system.l2c.overall_hits::cpu3 12682 # number of overall hits +system.l2c.overall_hits::cpu4 12654 # number of overall hits +system.l2c.overall_hits::cpu5 12607 # number of overall hits +system.l2c.overall_hits::cpu6 12690 # number of overall hits +system.l2c.overall_hits::cpu7 12677 # number of overall hits +system.l2c.overall_hits::total 101343 # number of overall hits +system.l2c.ReadReq_misses::cpu0 711 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 677 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 686 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 704 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 731 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 661 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 687 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 695 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5552 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1900 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1921 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1938 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1929 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1958 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1980 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1936 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1909 # number of UpgradeReq misses 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(read+write) miss cycles +system.l2c.demand_miss_latency::total 2238512918 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 279097860 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 277664360 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 279105869 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 279297372 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 281885883 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 284747363 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 279798360 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 276915851 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2238512918 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11420 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11361 # number of ReadReq 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2228 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2278 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2304 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2330 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2263 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2270 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18227 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6303 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6325 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6299 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6336 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6403 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6471 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6326 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6246 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50709 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17723 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17686 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17822 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17766 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17795 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17804 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17780 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17713 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 142089 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17723 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17686 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17822 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17766 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17795 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17804 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17780 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17713 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 142089 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.062259 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.059590 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.059533 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.061592 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.064168 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.058325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.059979 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.060609 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.060757 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.829332 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.848873 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.869838 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.846795 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.849826 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.849785 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.855502 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.840969 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.848796 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.691099 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.690909 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.698206 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.691288 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.688740 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.700974 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.696016 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.695005 # miss rate for ReadExReq accesses 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accesses +system.l2c.overall_miss_rate::cpu3 0.286165 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.288901 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291901 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.286277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.284311 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.286764 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 62377.513361 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 62169.748892 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 62452.510204 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61630.573864 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 60510.854993 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61168.568835 # average ReadReq miss latency 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latency +system.l2c.UpgradeReq_avg_miss_latency::total 28885.073945 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53890.598714 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53907.423341 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53720.656435 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.604566 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53889.443991 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 53861.318122 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53943.320463 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53817.424326 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53861.369807 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55081.480166 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55015.724193 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54898.872738 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54936.540519 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54830.943980 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 54790.718299 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54970.208251 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54987.261914 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54938.225053 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55081.480166 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55015.724193 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54898.872738 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54936.540519 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54830.943980 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 54790.718299 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54970.208251 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54987.261914 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54938.225053 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 12282 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1906 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1706 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.076076 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.199297 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6233 # number of writebacks -system.l2c.writebacks::total 6233 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 3 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6093 # number of writebacks +system.l2c.writebacks::total 6093 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu4 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 38 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 30 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 745 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 734 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 736 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 693 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 721 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 731 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 703 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 693 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5756 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1963 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1929 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1920 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1879 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1830 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1887 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1921 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1963 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15292 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4318 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4350 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4355 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4230 # number of ReadExReq MSHR misses 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-system.l2c.demand_mshr_misses::cpu7 5007 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40297 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5063 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5084 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5091 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 4923 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5077 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5129 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 4923 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5007 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40297 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 37430000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 36700000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 36861500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 34765499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 36517000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 35579500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 34789500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 34507000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 287149999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 80503500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 79250000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78828500 # number of UpgradeReq MSHR miss cycles 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-system.l2c.demand_mshr_miss_latency::cpu5 220090500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 211270000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 214878999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1731470996 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 217410999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 218389000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 218983500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 211967998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 218480000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 220090500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 211270000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 214878999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1731470996 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408599000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 409928000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 408199000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 411446500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 412339500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 409840000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 407063000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 414602500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3282017500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 219448000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222166000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 226500000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 227574000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 224253000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 222853000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 225951500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 221581000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1790326500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 628047000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 632094000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 634699000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 639020500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 636592500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 632693000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 633014500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 636183500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5072344000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065431 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064990 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064067 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060240 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.062969 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.063659 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.061489 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060073 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.062856 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854965 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856952 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.850687 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841092 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846438 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.842411 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.846256 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838531 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.847155 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690769 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.700145 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.699486 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.695381 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.698973 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.707871 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.683180 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698623 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.696813 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.287067 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.279923 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287128 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.289840 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.282706 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285503 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.287067 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.279923 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287128 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.289840 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.282706 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285503 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50241.610738 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50083.559783 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50166.665224 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50647.711512 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48672.366621 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49487.197724 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49793.650794 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49887.074183 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41010.443199 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41083.462934 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41056.510417 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41096.327834 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41046.994536 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41059.088500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41058.042686 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40995.160469 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41050.385823 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41681.565308 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41767.586207 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41819.058553 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41891.843735 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41772.956841 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41953.387904 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41820.023697 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41810.848169 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41814.683912 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits 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hits +system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 710 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 673 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 684 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 697 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 725 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 651 # number of ReadReq MSHR misses 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UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.840969 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.848631 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690782 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689960 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.697730 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.690341 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687803 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.700665 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.695068 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.694364 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.693348 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.285730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.284802 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.284985 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.285433 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.288227 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.291227 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.285883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.283690 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.286250 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.285730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.284802 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.284985 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.285433 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.288227 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.291227 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.285883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.283690 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.286250 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50354.101408 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50233.166419 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50336.144737 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49774.639885 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.222069 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49502.958525 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49475.830904 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50454.088663 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49838.479325 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41049.998421 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40981.517439 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41048.265359 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41030.340768 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41011.750128 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41039.138889 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41074.378616 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41002.617601 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41029.801073 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41788.343822 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41826.979835 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41623.309898 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41769.649749 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41787.794732 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41752.522938 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41854.432568 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41729.522481 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41766.505020 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42989.309044 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42950.141155 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42796.686356 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42869.921514 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42753.438097 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42725.624879 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42883.013968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42924.050149 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42860.814914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42989.309044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42950.141155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42796.686356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42869.921514 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42753.438097 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42725.624879 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42883.013968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42924.050149 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42860.814914 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -688,169 +689,169 @@ system.l2c.overall_avg_mshr_uncacheable_latency::total inf system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) -system.toL2Bus.throughput 51078499831 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 368070 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 368059 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 42367 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 42365 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 74336 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 28719 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118285 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 118639 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 118896 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118813 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 118602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 118904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 950354 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1731443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1726092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1741657 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1748194 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742487 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1735937 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741406 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1745057 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 13912273 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 13912273 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 157373515 # Layer occupancy (ticks) +system.toL2Bus.throughput 51067763763 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 370706 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370692 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43929 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43926 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 76131 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28975 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28973 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161585 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161579 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120187 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120466 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120511 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120525 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120880 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 963916 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756245 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1754904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1765350 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754211 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1769359 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757581 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1758989 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 14087855 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 14087855 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 19957440 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 655042579 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 160407425 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 158243013 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 161285735 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 157858027 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 157862988 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 158148657 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 157838676 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 158178516 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 160748299 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 160702936 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 160745511 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 24.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 160832963 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 161488791 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 157763244 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 24.2 # Layer utilization (%) -system.cpu0.num_reads 98977 # number of read accesses completed -system.cpu0.num_writes 53590 # number of write accesses completed +system.toL2Bus.respLayer7.occupancy 160912467 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 24.1 # Layer utilization (%) +system.cpu0.num_reads 99051 # number of read accesses completed +system.cpu0.num_writes 54715 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.tags.replacements 21970 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks. +system.cpu0.l1c.tags.replacements 22485 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.562401 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13294 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22895 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.580651 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 330568 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 330568 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1118 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9803 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9803 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9803 # number of overall hits -system.cpu0.l1c.overall_hits::total 9803 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35704 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35704 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23289 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23289 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58993 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58993 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58993 # number of overall misses -system.cpu0.l1c.overall_misses::total 58993 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 937059642 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 937059642 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 866806760 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 866806760 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1803866402 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1803866402 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1803866402 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1803866402 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44389 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44389 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24407 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24407 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68796 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68796 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68796 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68796 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804343 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.804343 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954193 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954193 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.857506 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.857506 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.857506 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.857506 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26245.228602 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 26245.228602 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37219.578342 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 37219.578342 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30577.634669 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30577.634669 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30577.634669 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30577.634669 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1018391 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 393.562401 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.768677 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.768677 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 336265 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 336265 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8671 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8671 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1068 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1068 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9739 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9739 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9739 # number of overall hits +system.cpu0.l1c.overall_hits::total 9739 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36428 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36428 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23756 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23756 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60184 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60184 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60184 # number of overall misses +system.cpu0.l1c.overall_misses::total 60184 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 963275637 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 963275637 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 887897909 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 887897909 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1851173546 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1851173546 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1851173546 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1851173546 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45099 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45099 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24824 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24824 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 69923 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 69923 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 69923 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 69923 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807734 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807734 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956977 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956977 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860718 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860718 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860718 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860718 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26443.275420 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 26443.275420 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37375.732825 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 37375.732825 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 30758.566164 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 30758.566164 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 30758.566164 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 30758.566164 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1029913 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 62068 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 62692 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.407666 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.428141 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9494 # number of writebacks -system.cpu0.l1c.writebacks::total 9494 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35704 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35704 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23289 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23289 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58993 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58993 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58993 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58993 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 860700776 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 860700776 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 817560778 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 817560778 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1678261554 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1678261554 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1678261554 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1678261554 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 703193894 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 703193894 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1636775658 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1636775658 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2339969552 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2339969552 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804343 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804343 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954193 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954193 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857506 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.857506 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857506 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.857506 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24106.564419 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24106.564419 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35105.018592 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35105.018592 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28448.486329 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28448.486329 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28448.486329 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28448.486329 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9798 # number of writebacks +system.cpu0.l1c.writebacks::total 9798 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36428 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36428 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23756 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23756 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60184 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60184 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60184 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60184 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 885441811 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 885441811 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 837618111 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 837618111 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1723059922 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1723059922 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1723059922 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1723059922 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 694921548 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 694921548 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1720175961 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1720175961 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2415097509 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2415097509 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807734 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807734 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956977 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956977 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860718 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860718 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860718 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860718 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24306.627073 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24306.627073 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35259.223396 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35259.223396 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28629.867108 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28629.867108 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28629.867108 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28629.867108 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -858,120 +859,120 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99824 # number of read accesses completed -system.cpu1.num_writes 53636 # number of write accesses completed +system.cpu1.num_reads 99180 # number of read accesses completed +system.cpu1.num_writes 55130 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.tags.replacements 22223 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks. +system.cpu1.l1c.tags.replacements 22560 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.358014 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13364 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22961 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.582030 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 332439 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 332439 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1135 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9892 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9892 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9892 # number of overall hits -system.cpu1.l1c.overall_hits::total 9892 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36260 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36260 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23033 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23033 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 59293 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 59293 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 59293 # number of overall misses -system.cpu1.l1c.overall_misses::total 59293 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 947629716 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 947629716 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 858813201 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 858813201 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1806442917 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1806442917 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1806442917 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1806442917 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45017 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45017 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24168 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24168 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 69185 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 69185 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 69185 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 69185 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805473 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805473 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953037 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953037 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857021 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857021 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857021 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857021 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26134.299945 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 26134.299945 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37286.206790 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 37286.206790 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30466.377431 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30466.377431 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30466.377431 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30466.377431 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1020302 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.358014 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.768277 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.768277 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338096 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338096 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8639 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8639 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9791 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9791 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9791 # number of overall hits +system.cpu1.l1c.overall_hits::total 9791 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36744 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36744 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23766 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23766 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60510 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60510 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60510 # number of overall misses +system.cpu1.l1c.overall_misses::total 60510 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 969995629 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 969995629 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 886374819 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 886374819 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1856370448 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1856370448 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1856370448 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1856370448 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45383 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45383 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24918 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24918 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70301 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70301 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70301 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70301 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809642 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.809642 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953768 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953768 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860727 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860727 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860727 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860727 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26398.748884 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 26398.748884 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37295.919339 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 37295.919339 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 30678.738192 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 30678.738192 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 30678.738192 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 30678.738192 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1031479 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62395 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 63034 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.352304 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.363851 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9512 # number of writebacks -system.cpu1.l1c.writebacks::total 9512 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36260 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36260 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23033 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 59293 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 59293 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 59293 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 59293 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 870111848 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 870111848 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 810087173 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 810087173 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1680199021 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1680199021 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1680199021 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1680199021 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702431869 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702431869 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1631991143 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1631991143 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2334423012 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2334423012 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805473 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805473 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953037 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953037 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857021 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857021 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857021 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857021 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23996.465747 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23996.465747 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35170.719099 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35170.719099 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.223972 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.223972 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.223972 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.223972 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9822 # number of writebacks +system.cpu1.l1c.writebacks::total 9822 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36744 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36744 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23766 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23766 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60510 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60510 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60510 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60510 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 891488909 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 891488909 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 836075987 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 836075987 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1727564896 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1727564896 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1727564896 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1727564896 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 694858067 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 694858067 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1710734008 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1710734008 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2405592075 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2405592075 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809642 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809642 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953768 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953768 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860727 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860727 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860727 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860727 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24262.162775 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24262.162775 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35179.499579 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35179.499579 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28550.072649 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28550.072649 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28550.072649 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28550.072649 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -979,120 +980,120 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99336 # number of read accesses completed -system.cpu2.num_writes 53403 # number of write accesses completed +system.cpu2.num_reads 99086 # number of read accesses completed +system.cpu2.num_writes 55118 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.tags.replacements 22214 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks. +system.cpu2.l1c.tags.replacements 22404 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.163299 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13438 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.589567 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 331261 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 331261 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8708 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8708 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1070 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1070 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9778 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9778 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9778 # number of overall hits -system.cpu2.l1c.overall_hits::total 9778 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36160 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36160 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22990 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22990 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59150 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59150 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59150 # number of overall misses -system.cpu2.l1c.overall_misses::total 59150 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 947354858 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 947354858 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 856510547 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 856510547 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1803865405 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1803865405 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1803865405 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1803865405 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44868 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44868 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24060 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24060 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68928 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68928 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68928 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68928 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805920 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805920 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955528 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955528 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858142 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858142 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858142 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858142 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26198.972843 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26198.972843 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37255.787168 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 37255.787168 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30496.456551 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30496.456551 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30496.456551 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30496.456551 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1016435 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.163299 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.767897 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.767897 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337674 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337674 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8791 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8791 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1160 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1160 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9951 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9951 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9951 # number of overall hits +system.cpu2.l1c.overall_hits::total 9951 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36516 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36516 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23770 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23770 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60286 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60286 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60286 # number of overall misses +system.cpu2.l1c.overall_misses::total 60286 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 967487980 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 967487980 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 890162777 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 890162777 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1857650757 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1857650757 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1857650757 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1857650757 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45307 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45307 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24930 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24930 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70237 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70237 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70237 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70237 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805968 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805968 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953470 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953470 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858323 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858323 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858323 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858323 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26494.905795 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 26494.905795 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37449.001977 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 37449.001977 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 30813.966045 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 30813.966045 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 30813.966045 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 30813.966045 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1030263 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62092 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 62774 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.369822 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.412257 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9582 # number of writebacks -system.cpu2.l1c.writebacks::total 9582 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36160 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36160 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22990 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22990 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59150 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59150 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59150 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59150 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 870067956 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 870067956 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 807866531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 807866531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1677934487 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1677934487 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1677934487 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1677934487 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 699720514 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 699720514 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1649553128 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1649553128 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2349273642 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2349273642 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805920 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805920 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955528 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955528 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858142 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858142 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858142 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858142 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24061.613827 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24061.613827 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35139.910004 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35139.910004 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28367.446948 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28367.446948 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28367.446948 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28367.446948 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9856 # number of writebacks +system.cpu2.l1c.writebacks::total 9856 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36516 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36516 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23770 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23770 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60286 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60286 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60286 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60286 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 889398318 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 889398318 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 839809073 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 839809073 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1729207391 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1729207391 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1729207391 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1729207391 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 693154089 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 693154089 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1689336031 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1689336031 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2382490120 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2382490120 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805968 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805968 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953470 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953470 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858323 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858323 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858323 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858323 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24356.400427 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24356.400427 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35330.629912 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35330.629912 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28683.398982 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28683.398982 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28683.398982 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28683.398982 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1100,120 +1101,120 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 53536 # number of write accesses completed +system.cpu3.num_reads 99021 # number of read accesses completed +system.cpu3.num_writes 54970 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.tags.replacements 22464 # number of replacements -system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks. +system.cpu3.l1c.tags.replacements 22272 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.391803 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13521 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22662 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.596638 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 331508 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 331508 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8781 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8781 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1109 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1109 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9890 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9890 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9890 # number of overall hits -system.cpu3.l1c.overall_hits::total 9890 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36107 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36107 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23001 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23001 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59108 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59108 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59108 # number of overall misses -system.cpu3.l1c.overall_misses::total 59108 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 940989779 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 940989779 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 850325185 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 850325185 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1791314964 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1791314964 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1791314964 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1791314964 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44888 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44888 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24110 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24110 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68998 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68998 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68998 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68998 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804380 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.804380 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954002 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954002 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.856663 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.856663 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.856663 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.856663 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26061.145457 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 26061.145457 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36969.052867 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 36969.052867 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30305.795561 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30305.795561 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30305.795561 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30305.795561 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1013074 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.391803 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768343 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768343 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337590 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337590 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8806 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8806 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1159 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1159 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9965 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9965 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9965 # number of overall hits +system.cpu3.l1c.overall_hits::total 9965 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36397 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36397 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23878 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23878 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60275 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60275 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60275 # number of overall misses +system.cpu3.l1c.overall_misses::total 60275 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 959708337 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 959708337 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 888157516 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 888157516 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1847865853 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1847865853 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1847865853 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1847865853 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45203 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45203 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25037 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25037 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70240 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70240 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70240 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70240 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805190 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805190 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953709 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953709 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858129 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858129 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858129 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858129 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26367.786823 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 26367.786823 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 37195.641008 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 37195.641008 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 30657.251813 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 30657.251813 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 30657.251813 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 30657.251813 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1032981 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 62000 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 63001 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.339903 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.396264 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9786 # number of writebacks -system.cpu3.l1c.writebacks::total 9786 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36107 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36107 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23001 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23001 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59108 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59108 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59108 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59108 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 863727177 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 863727177 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 801703041 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 801703041 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1665430218 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1665430218 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1665430218 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1665430218 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 709371346 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 709371346 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1619504156 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1619504156 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2328875502 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2328875502 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804380 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804380 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954002 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954002 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856663 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.856663 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856663 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.856663 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23921.322098 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23921.322098 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34855.138516 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34855.138516 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28176.054307 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28176.054307 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28176.054307 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28176.054307 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9730 # number of writebacks +system.cpu3.l1c.writebacks::total 9730 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36397 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36397 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23878 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23878 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60275 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60275 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60275 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60275 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 882022203 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882022203 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 837608778 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 837608778 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1719630981 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1719630981 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719630981 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1719630981 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 701721013 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 701721013 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1702236593 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1702236593 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2403957606 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2403957606 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805190 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805190 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953709 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953709 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858129 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858129 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858129 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858129 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24233.376460 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24233.376460 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 35078.682385 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35078.682385 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28529.754973 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28529.754973 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28529.754973 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28529.754973 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1221,120 +1222,120 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99830 # number of read accesses completed -system.cpu4.num_writes 54064 # number of write accesses completed +system.cpu4.num_reads 99302 # number of read accesses completed +system.cpu4.num_writes 55134 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.tags.replacements 22082 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks. +system.cpu4.l1c.tags.replacements 22459 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.483256 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13509 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.591255 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 331555 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 331555 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8712 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8712 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1102 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1102 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9814 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9814 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9814 # number of overall hits -system.cpu4.l1c.overall_hits::total 9814 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35977 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35977 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23176 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23176 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59153 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59153 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59153 # number of overall misses -system.cpu4.l1c.overall_misses::total 59153 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 943945635 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 943945635 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 856485364 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 856485364 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1800430999 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1800430999 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1800430999 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1800430999 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44689 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44689 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24278 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24278 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68967 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68967 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68967 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68967 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805053 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.805053 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954609 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954609 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857700 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857700 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857700 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857700 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26237.474915 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 26237.474915 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 36955.702623 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 36955.702623 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30436.850185 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30436.850185 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30436.850185 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30436.850185 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1017670 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 393.483256 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.768522 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.768522 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 356 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337715 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337715 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1196 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1196 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9935 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9935 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9935 # number of overall hits +system.cpu4.l1c.overall_hits::total 9935 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36407 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36407 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23914 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23914 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60321 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60321 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60321 # number of overall misses +system.cpu4.l1c.overall_misses::total 60321 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 962640133 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 962640133 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 889456301 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 889456301 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1852096434 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1852096434 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1852096434 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1852096434 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45146 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45146 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25110 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70256 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70256 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70256 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70256 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806428 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806428 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952370 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952370 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858589 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858589 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858589 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858589 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26441.072678 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 26441.072678 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37193.957556 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 37193.957556 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 30704.007460 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 30704.007460 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 30704.007460 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 30704.007460 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1036597 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 62294 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 63051 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.336565 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.440612 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9622 # number of writebacks -system.cpu4.l1c.writebacks::total 9622 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35977 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35977 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23176 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23176 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59153 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59153 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59153 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59153 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 867154515 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 867154515 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 807437346 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 807437346 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1674591861 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1674591861 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674591861 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1674591861 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 707224870 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 707224870 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1620907679 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1620907679 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2328132549 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2328132549 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805053 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805053 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954609 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954609 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857700 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857700 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857700 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857700 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24103.024571 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24103.024571 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34839.374612 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34839.374612 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28309.500127 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28309.500127 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28309.500127 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28309.500127 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9933 # number of writebacks +system.cpu4.l1c.writebacks::total 9933 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36407 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36407 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23914 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23914 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60321 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60321 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 884868259 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 884868259 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 838892397 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 838892397 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1723760656 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1723760656 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1723760656 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1723760656 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 703520432 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 703520432 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1658146550 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1658146550 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2361666982 # number of overall MSHR uncacheable cycles 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+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24304.893537 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35079.551602 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35079.551602 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28576.460205 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28576.460205 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28576.460205 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28576.460205 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1342,120 +1343,120 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99630 # number of read accesses completed -system.cpu5.num_writes 53500 # number of write accesses completed +system.cpu5.num_reads 99936 # number of read accesses completed +system.cpu5.num_writes 55294 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.tags.replacements 22051 # number of replacements -system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks. +system.cpu5.l1c.tags.replacements 22607 # number of replacements +system.cpu5.l1c.tags.tagsinuse 394.741985 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13577 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 23024 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.589689 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 332072 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 332072 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8824 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8824 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1160 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1160 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9984 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9984 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9984 # number of overall hits -system.cpu5.l1c.overall_hits::total 9984 # number of overall hits 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number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.803614 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.803614 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952048 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952048 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.855562 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.855562 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.855562 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.855562 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26281.724078 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26281.724078 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37392.651296 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 37392.651296 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30608.746259 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30608.746259 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30608.746259 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30608.746259 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1024769 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 394.741985 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.770980 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.770980 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id 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number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23955 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23955 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60395 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60395 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60395 # number of overall misses +system.cpu5.l1c.overall_misses::total 60395 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 954691213 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 954691213 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 898328721 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 898328721 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1853019934 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1853019934 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1853019934 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1853019934 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45266 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45266 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25078 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25078 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70344 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70344 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70344 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70344 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805019 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.805019 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955220 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.955220 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858566 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858566 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858566 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858566 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26198.990477 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 26198.990477 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37500.677145 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 37500.677145 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 30681.677854 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 30681.677854 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 30681.677854 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 30681.677854 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1031399 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 62427 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 62997 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.415477 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.372192 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9521 # number of writebacks -system.cpu5.l1c.writebacks::total 9521 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36108 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36108 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23031 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23031 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59139 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59139 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59139 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59139 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 871850549 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 871850549 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 812508000 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 812508000 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1684358549 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1684358549 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1684358549 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1684358549 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 704255884 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 704255884 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1614286606 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1614286606 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2318542490 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2318542490 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.803614 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.803614 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952048 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952048 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.855562 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.855562 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.855562 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.855562 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24145.633904 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24145.633904 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35278.884981 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35278.884981 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9959 # number of writebacks +system.cpu5.l1c.writebacks::total 9959 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36440 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36440 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23955 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23955 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60395 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60395 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60395 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60395 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 876841351 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 876841351 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 847650833 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 847650833 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1724492184 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1724492184 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1724492184 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1724492184 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 699333550 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 699333550 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1696976001 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1696976001 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2396309551 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2396309551 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805019 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805019 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955220 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955220 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858566 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858566 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858566 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858566 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24062.605681 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24062.605681 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35385.131831 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35385.131831 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28553.558805 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28553.558805 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28553.558805 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28553.558805 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1463,120 +1464,120 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99897 # number of read accesses completed -system.cpu6.num_writes 53584 # number of write accesses completed +system.cpu6.num_reads 100001 # number of read accesses completed +system.cpu6.num_writes 55113 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.tags.replacements 22385 # number of replacements -system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks. +system.cpu6.l1c.tags.replacements 22596 # number of replacements +system.cpu6.l1c.tags.tagsinuse 393.612008 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13438 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 23004 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.584159 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_blocks::cpu6 393.612008 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.768773 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.768773 # Average percentage of cache occupancy system.cpu6.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu6.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 332017 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 332017 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8715 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8715 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1094 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1094 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9809 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9809 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9809 # number of overall hits -system.cpu6.l1c.overall_hits::total 9809 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36235 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36235 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23035 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23035 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 59270 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 59270 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 59270 # number of overall misses -system.cpu6.l1c.overall_misses::total 59270 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 950668375 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 950668375 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 850880053 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 850880053 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1801548428 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1801548428 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1801548428 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1801548428 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44950 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44950 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24129 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24129 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 69079 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 69079 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 69079 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 69079 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806118 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806118 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954660 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954660 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858003 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858003 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858003 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858003 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26236.190838 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 26236.190838 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36938.574040 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 36938.574040 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 30395.620516 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 30395.620516 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 30395.620516 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30395.620516 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1011987 # number of cycles access was blocked +system.cpu6.l1c.tags.tag_accesses 338625 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338625 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8756 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8756 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9900 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9900 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9900 # number of overall hits +system.cpu6.l1c.overall_hits::total 9900 # number of overall hits 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1853099710 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1853099710 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1853099710 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1853099710 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45536 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45536 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24888 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24888 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70424 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70424 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70424 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70424 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807713 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954034 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954034 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859423 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859423 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859423 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859423 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26312.345840 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 26312.345840 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37286.541021 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 37286.541021 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 30617.601447 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 30617.601447 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 30617.601447 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 30617.601447 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1031115 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61933 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 63035 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.340029 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.357817 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9690 # number of writebacks -system.cpu6.l1c.writebacks::total 9690 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36235 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36235 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23035 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23035 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 59270 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 59270 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 59270 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 59270 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 873220563 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 873220563 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 802141037 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 802141037 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1675361600 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1675361600 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1675361600 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1675361600 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 697661939 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 697661939 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1639994129 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1639994129 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2337656068 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2337656068 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806118 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806118 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954660 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954660 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858003 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858003 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24098.815041 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24098.815041 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34822.706186 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34822.706186 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9778 # number of writebacks +system.cpu6.l1c.writebacks::total 9778 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36780 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36780 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23744 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23744 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60524 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60524 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60524 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60524 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 889223312 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 889223312 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 835020954 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 835020954 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1724244266 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1724244266 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1724244266 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1724244266 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 698387416 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 698387416 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1741021536 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1741021536 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2439408952 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2439408952 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807713 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954034 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954034 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859423 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859423 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859423 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859423 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24176.816531 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24176.816531 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 35167.661472 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 35167.661472 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28488.603959 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28488.603959 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28488.603959 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28488.603959 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1584,120 +1585,120 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99207 # number of read accesses completed -system.cpu7.num_writes 53401 # number of write accesses completed +system.cpu7.num_reads 99455 # number of read accesses completed +system.cpu7.num_writes 55321 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.tags.replacements 22143 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks. +system.cpu7.l1c.tags.replacements 22276 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.282274 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13267 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22648 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.585791 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 331300 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 331300 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1078 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9713 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9713 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9713 # number of overall hits -system.cpu7.l1c.overall_hits::total 9713 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36141 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36141 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23098 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23098 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59239 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59239 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59239 # number of overall misses -system.cpu7.l1c.overall_misses::total 59239 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 942615817 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 942615817 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 859348059 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 859348059 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1801963876 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1801963876 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1801963876 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1801963876 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44776 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44776 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24176 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68952 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68952 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807151 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807151 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955410 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955410 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859134 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859134 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859134 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859134 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26081.619684 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 26081.619684 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37204.435839 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37204.435839 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30418.539746 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30418.539746 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30418.539746 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30418.539746 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1024987 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 392.282274 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766176 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766176 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 356 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337172 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337172 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8517 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8517 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1168 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1168 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9685 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9685 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9685 # number of overall hits +system.cpu7.l1c.overall_hits::total 9685 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36632 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36632 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23782 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23782 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60414 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60414 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60414 # number of overall misses +system.cpu7.l1c.overall_misses::total 60414 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 969238606 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 969238606 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 880763834 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 880763834 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1850002440 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1850002440 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1850002440 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1850002440 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45149 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45149 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24950 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70099 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70099 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70099 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70099 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.811358 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.811358 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953186 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953186 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.861838 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.861838 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.861838 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.861838 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26458.795752 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 26458.795752 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37034.893365 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 37034.893365 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 30622.081637 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 30622.081637 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 30622.081637 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 30622.081637 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1029627 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62690 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 62765 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.350088 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.404477 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9629 # number of writebacks -system.cpu7.l1c.writebacks::total 9629 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36141 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36141 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23098 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23098 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59239 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59239 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59239 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59239 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 865505701 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 865505701 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 810567819 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 810567819 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1676073520 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1676073520 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1676073520 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1676073520 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 711693302 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 711693302 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1603062205 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1603062205 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2314755507 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2314755507 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807151 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807151 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955410 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955410 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859134 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859134 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23948.028582 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23948.028582 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35092.554290 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35092.554290 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9888 # number of writebacks +system.cpu7.l1c.writebacks::total 9888 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36632 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36632 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23782 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23782 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60414 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60414 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60414 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60414 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 891054702 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 891054702 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 830452960 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 830452960 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1721507662 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1721507662 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1721507662 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1721507662 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 698299057 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 698299057 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1725454906 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1725454906 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2423753963 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2423753963 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.811358 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.811358 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953186 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953186 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.861838 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.861838 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.861838 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.861838 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24324.489572 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24324.489572 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34919.391136 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34919.391136 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28495.177641 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28495.177641 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28495.177641 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28495.177641 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index 4cbff215b..c1d5ff6e5 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000312 # Number of seconds simulated -sim_ticks 312261 # Number of ticks simulated -final_tick 312261 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000328 # Number of seconds simulated +sim_ticks 327571 # Number of ticks simulated +final_tick 327571 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1203947 # Simulator tick rate (ticks/s) -host_mem_usage 170440 # Number of bytes of host memory used +host_tick_rate 1251967 # Simulator tick rate (ticks/s) +host_mem_usage 128368 # Number of bytes of host memory used host_seconds 0.26 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 512 # delay histogram for all message system.ruby.delayHist::max_bucket 5119 # delay histogram for all message -system.ruby.delayHist::samples 6975 # delay histogram for all message -system.ruby.delayHist::mean 57.310251 # delay histogram for all message -system.ruby.delayHist::stdev 258.377513 # delay histogram for all message -system.ruby.delayHist | 6687 95.87% 95.87% | 165 2.37% 98.24% | 67 0.96% 99.20% | 29 0.42% 99.61% | 15 0.22% 99.83% | 8 0.11% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 6975 # delay histogram for all message +system.ruby.delayHist::samples 7183 # delay histogram for all message +system.ruby.delayHist::mean 55.693443 # delay histogram for all message +system.ruby.delayHist::stdev 252.452700 # delay histogram for all message +system.ruby.delayHist | 6908 96.17% 96.17% | 159 2.21% 98.39% | 57 0.79% 99.18% | 31 0.43% 99.61% | 18 0.25% 99.86% | 9 0.13% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 7183 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 983 -system.ruby.outstanding_req_hist::mean 15.827060 -system.ruby.outstanding_req_hist::gmean 15.727011 -system.ruby.outstanding_req_hist::stdev 1.133008 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.31% | 2 0.20% 0.51% | 2 0.20% 0.71% | 2 0.20% 0.92% | 2 0.20% 1.12% | 2 0.20% 1.32% | 52 5.29% 6.61% | 918 93.39% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 983 +system.ruby.outstanding_req_hist::samples 1017 +system.ruby.outstanding_req_hist::mean 15.830875 +system.ruby.outstanding_req_hist::gmean 15.734065 +system.ruby.outstanding_req_hist::stdev 1.114909 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.69% | 2 0.20% 0.88% | 2 0.20% 1.08% | 2 0.20% 1.28% | 54 5.31% 6.59% | 950 93.41% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 1017 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 968 -system.ruby.latency_hist::mean 5101.012397 -system.ruby.latency_hist::gmean 2832.118198 -system.ruby.latency_hist::stdev 2084.563420 -system.ruby.latency_hist | 125 12.91% 12.91% | 22 2.27% 15.19% | 2 0.21% 15.39% | 4 0.41% 15.81% | 57 5.89% 21.69% | 468 48.35% 70.04% | 263 27.17% 97.21% | 27 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 968 +system.ruby.latency_hist::samples 1002 +system.ruby.latency_hist::mean 5171.353293 +system.ruby.latency_hist::gmean 2828.922262 +system.ruby.latency_hist::stdev 2096.025855 +system.ruby.latency_hist | 135 13.47% 13.47% | 12 1.20% 14.67% | 4 0.40% 15.07% | 4 0.40% 15.47% | 30 2.99% 18.46% | 460 45.91% 64.37% | 320 31.94% 96.31% | 37 3.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 1002 system.ruby.hit_latency_hist::bucket_size 16 system.ruby.hit_latency_hist::max_bucket 159 -system.ruby.hit_latency_hist::samples 74 -system.ruby.hit_latency_hist::mean 11.527027 -system.ruby.hit_latency_hist::gmean 3.324632 -system.ruby.hit_latency_hist::stdev 29.929242 -system.ruby.hit_latency_hist | 68 91.89% 91.89% | 0 0.00% 91.89% | 0 0.00% 91.89% | 0 0.00% 91.89% | 0 0.00% 91.89% | 0 0.00% 91.89% | 2 2.70% 94.59% | 4 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 74 +system.ruby.hit_latency_hist::samples 77 +system.ruby.hit_latency_hist::mean 9.597403 +system.ruby.hit_latency_hist::gmean 2.761367 +system.ruby.hit_latency_hist::stdev 27.303489 +system.ruby.hit_latency_hist | 72 93.51% 93.51% | 0 0.00% 93.51% | 0 0.00% 93.51% | 0 0.00% 93.51% | 0 0.00% 93.51% | 0 0.00% 93.51% | 2 2.60% 96.10% | 3 3.90% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 77 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 894 -system.ruby.miss_latency_hist::mean 5522.289709 -system.ruby.miss_latency_hist::gmean 4950.736161 -system.ruby.miss_latency_hist::stdev 1543.133800 -system.ruby.miss_latency_hist | 51 5.70% 5.70% | 22 2.46% 8.17% | 2 0.22% 8.39% | 4 0.45% 8.84% | 57 6.38% 15.21% | 468 52.35% 67.56% | 263 29.42% 96.98% | 27 3.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 894 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 74 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 839 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 913 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 925 +system.ruby.miss_latency_hist::mean 5601.034595 +system.ruby.miss_latency_hist::gmean 5037.610012 +system.ruby.miss_latency_hist::stdev 1534.352398 +system.ruby.miss_latency_hist | 58 6.27% 6.27% | 12 1.30% 7.57% | 4 0.43% 8.00% | 4 0.43% 8.43% | 30 3.24% 11.68% | 460 49.73% 61.41% | 320 34.59% 96.00% | 37 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 925 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 77 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 881 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 958 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 57 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_misses 46 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 46 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -64,355 +64,355 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 5 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 80 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load -system.ruby.network.routers0.percent_links_utilized 1.779361 -system.ruby.network.routers0.msg_count.Control::0 896 -system.ruby.network.routers0.msg_count.Request_Control::2 559 -system.ruby.network.routers0.msg_count.Response_Data::1 894 -system.ruby.network.routers0.msg_count.Response_Control::1 812 -system.ruby.network.routers0.msg_count.Response_Control::2 837 -system.ruby.network.routers0.msg_count.Writeback_Data::0 726 -system.ruby.network.routers0.msg_count.Writeback_Data::1 501 -system.ruby.network.routers0.msg_count.Writeback_Control::0 32 -system.ruby.network.routers0.msg_bytes.Control::0 7168 -system.ruby.network.routers0.msg_bytes.Request_Control::2 4472 -system.ruby.network.routers0.msg_bytes.Response_Data::1 64368 -system.ruby.network.routers0.msg_bytes.Response_Control::1 6496 -system.ruby.network.routers0.msg_bytes.Response_Control::2 6696 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 52272 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 36072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 256 -system.ruby.l2_cntrl0.L2cache.demand_hits 32 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 864 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 896 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 3.102133 -system.ruby.network.routers1.msg_count.Control::0 1759 -system.ruby.network.routers1.msg_count.Request_Control::2 559 -system.ruby.network.routers1.msg_count.Response_Data::1 2529 -system.ruby.network.routers1.msg_count.Response_Control::1 1756 -system.ruby.network.routers1.msg_count.Response_Control::2 837 -system.ruby.network.routers1.msg_count.Writeback_Data::0 726 -system.ruby.network.routers1.msg_count.Writeback_Data::1 501 -system.ruby.network.routers1.msg_count.Writeback_Control::0 32 -system.ruby.network.routers1.msg_bytes.Control::0 14072 -system.ruby.network.routers1.msg_bytes.Request_Control::2 4472 -system.ruby.network.routers1.msg_bytes.Response_Data::1 182088 -system.ruby.network.routers1.msg_bytes.Response_Control::1 14048 -system.ruby.network.routers1.msg_bytes.Response_Control::2 6696 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 52272 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 36072 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 256 +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 110 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 10 # Number of times a load aliased with a pending store +system.ruby.network.routers0.percent_links_utilized 1.749086 +system.ruby.network.routers0.msg_count.Control::0 925 +system.ruby.network.routers0.msg_count.Request_Control::2 563 +system.ruby.network.routers0.msg_count.Response_Data::1 925 +system.ruby.network.routers0.msg_count.Response_Control::1 827 +system.ruby.network.routers0.msg_count.Response_Control::2 877 +system.ruby.network.routers0.msg_count.Writeback_Data::0 742 +system.ruby.network.routers0.msg_count.Writeback_Data::1 520 +system.ruby.network.routers0.msg_count.Writeback_Control::0 43 +system.ruby.network.routers0.msg_bytes.Control::0 7400 +system.ruby.network.routers0.msg_bytes.Request_Control::2 4504 +system.ruby.network.routers0.msg_bytes.Response_Data::1 66600 +system.ruby.network.routers0.msg_bytes.Response_Control::1 6616 +system.ruby.network.routers0.msg_bytes.Response_Control::2 7016 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 53424 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 37440 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 344 +system.ruby.l2_cntrl0.L2cache.demand_hits 41 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 884 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 925 # Number of cache demand accesses +system.ruby.network.routers1.percent_links_utilized 3.043386 +system.ruby.network.routers1.msg_count.Control::0 1809 +system.ruby.network.routers1.msg_count.Request_Control::2 563 +system.ruby.network.routers1.msg_count.Response_Data::1 2604 +system.ruby.network.routers1.msg_count.Response_Control::1 1791 +system.ruby.network.routers1.msg_count.Response_Control::2 877 +system.ruby.network.routers1.msg_count.Writeback_Data::0 742 +system.ruby.network.routers1.msg_count.Writeback_Data::1 520 +system.ruby.network.routers1.msg_count.Writeback_Control::0 43 +system.ruby.network.routers1.msg_bytes.Control::0 14472 +system.ruby.network.routers1.msg_bytes.Request_Control::2 4504 +system.ruby.network.routers1.msg_bytes.Response_Data::1 187488 +system.ruby.network.routers1.msg_bytes.Response_Control::1 14328 +system.ruby.network.routers1.msg_bytes.Response_Control::2 7016 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 53424 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 37440 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 344 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 1633 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 863 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 770 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 2168 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 631 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 4 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 681 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.417024 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 209 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 210 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 102 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 76 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 34 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 41 2.51% 2.51% | 47 2.88% 5.39% | 57 3.49% 8.88% | 77 4.72% 13.59% | 68 4.16% 17.76% | 61 3.74% 21.49% | 66 4.04% 25.54% | 57 3.49% 29.03% | 48 2.94% 31.97% | 40 2.45% 34.42% | 51 3.12% 37.54% | 55 3.37% 40.91% | 46 2.82% 43.72% | 63 3.86% 47.58% | 42 2.57% 50.15% | 41 2.51% 52.66% | 40 2.45% 55.11% | 63 3.86% 58.97% | 38 2.33% 61.30% | 41 2.51% 63.81% | 44 2.69% 66.50% | 54 3.31% 69.81% | 50 3.06% 72.87% | 49 3.00% 75.87% | 56 3.43% 79.30% | 41 2.51% 81.81% | 55 3.37% 85.18% | 35 2.14% 87.32% | 45 2.76% 90.08% | 56 3.43% 93.51% | 51 3.12% 96.63% | 55 3.37% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1633 # Number of accesses per bank -system.ruby.network.routers2.percent_links_utilized 1.321331 -system.ruby.network.routers2.msg_count.Control::0 863 -system.ruby.network.routers2.msg_count.Response_Data::1 1633 -system.ruby.network.routers2.msg_count.Response_Control::1 944 -system.ruby.network.routers2.msg_bytes.Control::0 6904 -system.ruby.network.routers2.msg_bytes.Response_Data::1 117576 -system.ruby.network.routers2.msg_bytes.Response_Control::1 7552 -system.ruby.network.routers3.percent_links_utilized 2.067608 -system.ruby.network.routers3.msg_count.Control::0 1759 -system.ruby.network.routers3.msg_count.Request_Control::2 559 -system.ruby.network.routers3.msg_count.Response_Data::1 2528 -system.ruby.network.routers3.msg_count.Response_Control::1 1756 -system.ruby.network.routers3.msg_count.Response_Control::2 837 -system.ruby.network.routers3.msg_count.Writeback_Data::0 726 -system.ruby.network.routers3.msg_count.Writeback_Data::1 501 -system.ruby.network.routers3.msg_count.Writeback_Control::0 32 -system.ruby.network.routers3.msg_bytes.Control::0 14072 -system.ruby.network.routers3.msg_bytes.Request_Control::2 4472 -system.ruby.network.routers3.msg_bytes.Response_Data::1 182016 -system.ruby.network.routers3.msg_bytes.Response_Control::1 14048 -system.ruby.network.routers3.msg_bytes.Response_Control::2 6696 -system.ruby.network.routers3.msg_bytes.Writeback_Data::0 52272 -system.ruby.network.routers3.msg_bytes.Writeback_Data::1 36072 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 256 -system.ruby.network.msg_count.Control 5277 -system.ruby.network.msg_count.Request_Control 1677 -system.ruby.network.msg_count.Response_Data 7584 -system.ruby.network.msg_count.Response_Control 7779 -system.ruby.network.msg_count.Writeback_Data 3681 -system.ruby.network.msg_count.Writeback_Control 96 -system.ruby.network.msg_byte.Control 42216 -system.ruby.network.msg_byte.Request_Control 13416 -system.ruby.network.msg_byte.Response_Data 546048 -system.ruby.network.msg_byte.Response_Control 62232 -system.ruby.network.msg_byte.Writeback_Data 265032 -system.ruby.network.msg_byte.Writeback_Control 768 -system.ruby.network.routers0.throttle0.link_utilization 1.498906 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 559 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 894 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 756 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 4472 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 64368 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6048 -system.ruby.network.routers0.throttle1.link_utilization 2.059815 -system.ruby.network.routers0.throttle1.msg_count.Control::0 896 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 56 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 837 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 726 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 501 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 32 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7168 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 448 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6696 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 52272 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 36072 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 256 -system.ruby.network.routers1.throttle0.link_utilization 3.440711 -system.ruby.network.routers1.throttle0.msg_count.Control::0 896 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 863 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 913 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 837 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 726 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 501 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 32 -system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7168 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62136 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7304 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6696 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 52272 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 36072 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 256 -system.ruby.network.routers1.throttle1.link_utilization 2.763554 -system.ruby.network.routers1.throttle1.msg_count.Control::0 863 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 559 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1666 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 843 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6904 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 4472 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 119952 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 6744 -system.ruby.network.routers2.throttle0.link_utilization 1.261765 -system.ruby.network.routers2.throttle0.msg_count.Control::0 863 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 770 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 87 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6904 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 55440 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 696 -system.ruby.network.routers2.throttle1.link_utilization 1.380896 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 863 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 857 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62136 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6856 -system.ruby.network.routers3.throttle0.link_utilization 1.498906 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 559 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 894 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 756 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 4472 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 64368 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6048 -system.ruby.network.routers3.throttle1.link_utilization 3.440711 -system.ruby.network.routers3.throttle1.msg_count.Control::0 896 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 863 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 913 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 837 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 726 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 501 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 32 -system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7168 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62136 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7304 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6696 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 52272 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 36072 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 256 -system.ruby.network.routers3.throttle2.link_utilization 1.263206 -system.ruby.network.routers3.throttle2.msg_count.Control::0 863 -system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 771 -system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 87 -system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6904 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 55512 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 696 +system.ruby.dir_cntrl0.memBuffer.memReq 1679 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 884 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 795 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 2274 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 511 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 43 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 554 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.329958 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 149 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 180 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 93 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 60 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 29 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 59 3.51% 3.51% | 51 3.04% 6.55% | 42 2.50% 9.05% | 102 6.08% 15.13% | 61 3.63% 18.76% | 47 2.80% 21.56% | 70 4.17% 25.73% | 56 3.34% 29.06% | 51 3.04% 32.10% | 62 3.69% 35.80% | 53 3.16% 38.95% | 35 2.08% 41.04% | 65 3.87% 44.91% | 50 2.98% 47.89% | 40 2.38% 50.27% | 53 3.16% 53.42% | 36 2.14% 55.57% | 55 3.28% 58.84% | 66 3.93% 62.78% | 41 2.44% 65.22% | 49 2.92% 68.14% | 43 2.56% 70.70% | 65 3.87% 74.57% | 53 3.16% 77.72% | 50 2.98% 80.70% | 53 3.16% 83.86% | 51 3.04% 86.90% | 48 2.86% 89.76% | 44 2.62% 92.38% | 41 2.44% 94.82% | 41 2.44% 97.26% | 46 2.74% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1679 # Number of accesses per bank +system.ruby.network.routers2.percent_links_utilized 1.294300 +system.ruby.network.routers2.msg_count.Control::0 884 +system.ruby.network.routers2.msg_count.Response_Data::1 1679 +system.ruby.network.routers2.msg_count.Response_Control::1 964 +system.ruby.network.routers2.msg_bytes.Control::0 7072 +system.ruby.network.routers2.msg_bytes.Response_Data::1 120888 +system.ruby.network.routers2.msg_bytes.Response_Control::1 7712 +system.ruby.network.routers3.percent_links_utilized 2.028924 +system.ruby.network.routers3.msg_count.Control::0 1809 +system.ruby.network.routers3.msg_count.Request_Control::2 563 +system.ruby.network.routers3.msg_count.Response_Data::1 2604 +system.ruby.network.routers3.msg_count.Response_Control::1 1791 +system.ruby.network.routers3.msg_count.Response_Control::2 877 +system.ruby.network.routers3.msg_count.Writeback_Data::0 742 +system.ruby.network.routers3.msg_count.Writeback_Data::1 520 +system.ruby.network.routers3.msg_count.Writeback_Control::0 43 +system.ruby.network.routers3.msg_bytes.Control::0 14472 +system.ruby.network.routers3.msg_bytes.Request_Control::2 4504 +system.ruby.network.routers3.msg_bytes.Response_Data::1 187488 +system.ruby.network.routers3.msg_bytes.Response_Control::1 14328 +system.ruby.network.routers3.msg_bytes.Response_Control::2 7016 +system.ruby.network.routers3.msg_bytes.Writeback_Data::0 53424 +system.ruby.network.routers3.msg_bytes.Writeback_Data::1 37440 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 344 +system.ruby.network.msg_count.Control 5427 +system.ruby.network.msg_count.Request_Control 1689 +system.ruby.network.msg_count.Response_Data 7812 +system.ruby.network.msg_count.Response_Control 8004 +system.ruby.network.msg_count.Writeback_Data 3786 +system.ruby.network.msg_count.Writeback_Control 129 +system.ruby.network.msg_byte.Control 43416 +system.ruby.network.msg_byte.Request_Control 13512 +system.ruby.network.msg_byte.Response_Data 562464 +system.ruby.network.msg_byte.Response_Control 64032 +system.ruby.network.msg_byte.Writeback_Data 272592 +system.ruby.network.msg_byte.Writeback_Control 1032 +system.ruby.network.routers0.throttle0.link_utilization 1.476321 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 563 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 925 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 784 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 4504 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 66600 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6272 +system.ruby.network.routers0.throttle1.link_utilization 2.021852 +system.ruby.network.routers0.throttle1.msg_count.Control::0 925 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 43 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 877 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 742 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 520 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 43 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7400 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 344 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 7016 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 53424 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 37440 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 344 +system.ruby.network.routers1.throttle0.link_utilization 3.370414 +system.ruby.network.routers1.throttle0.msg_count.Control::0 925 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 884 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 922 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 877 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 742 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 520 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 43 +system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7400 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 63648 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7376 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 7016 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 53424 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 37440 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 344 +system.ruby.network.routers1.throttle1.link_utilization 2.716358 +system.ruby.network.routers1.throttle1.msg_count.Control::0 884 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 563 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1720 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 869 +system.ruby.network.routers1.throttle1.msg_bytes.Control::0 7072 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 4504 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 123840 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 6952 +system.ruby.network.routers2.throttle0.link_utilization 1.240037 +system.ruby.network.routers2.throttle0.msg_count.Control::0 884 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 795 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 85 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 7072 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 57240 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 680 +system.ruby.network.routers2.throttle1.link_utilization 1.348563 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 884 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 879 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 63648 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 7032 +system.ruby.network.routers3.throttle0.link_utilization 1.476321 +system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 563 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 925 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 784 +system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 4504 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 66600 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6272 +system.ruby.network.routers3.throttle1.link_utilization 3.370414 +system.ruby.network.routers3.throttle1.msg_count.Control::0 925 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 884 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 922 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 877 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 742 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 520 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 43 +system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7400 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 63648 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7376 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 7016 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 53424 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 37440 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 344 +system.ruby.network.routers3.throttle2.link_utilization 1.240037 +system.ruby.network.routers3.throttle2.msg_count.Control::0 884 +system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 795 +system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 85 +system.ruby.network.routers3.throttle2.msg_bytes.Control::0 7072 +system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 57240 +system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 680 system.ruby.delayVCHist.vnet_0::bucket_size 512 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 5119 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 2489 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 159.486139 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 413.379625 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 2201 88.43% 88.43% | 165 6.63% 95.06% | 67 2.69% 97.75% | 29 1.17% 98.92% | 15 0.60% 99.52% | 8 0.32% 99.84% | 4 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 2489 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 2586 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 153.589327 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 402.594576 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 2311 89.37% 89.37% | 159 6.15% 95.51% | 57 2.20% 97.72% | 31 1.20% 98.92% | 18 0.70% 99.61% | 9 0.35% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 2586 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 3927 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.706901 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 2.143932 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 3546 90.30% 90.30% | 268 6.82% 97.12% | 81 2.06% 99.19% | 28 0.71% 99.90% | 1 0.03% 99.92% | 3 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 3927 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4034 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.709470 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 2.104009 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 3622 89.79% 89.79% | 315 7.81% 97.60% | 68 1.69% 99.28% | 23 0.57% 99.85% | 5 0.12% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4034 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 559 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.003578 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.084591 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 558 99.82% 99.82% | 0 0.00% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 559 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 563 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.003552 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.084290 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 562 99.82% 99.82% | 0 0.00% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 563 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 1024 system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 43 -system.ruby.LD.latency_hist::mean 5169.837209 -system.ruby.LD.latency_hist::gmean 2077.331542 -system.ruby.LD.latency_hist::stdev 2197.240205 -system.ruby.LD.latency_hist | 6 13.95% 13.95% | 0 0.00% 13.95% | 0 0.00% 13.95% | 0 0.00% 13.95% | 2 4.65% 18.60% | 22 51.16% 69.77% | 10 23.26% 93.02% | 3 6.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 43 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 6 -system.ruby.LD.hit_latency_hist::mean 3.166667 -system.ruby.LD.hit_latency_hist::gmean 3.086164 -system.ruby.LD.hit_latency_hist::stdev 0.752773 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 16.67% 16.67% | 3 50.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 6 +system.ruby.LD.latency_hist::samples 54 +system.ruby.LD.latency_hist::mean 5695.537037 +system.ruby.LD.latency_hist::gmean 3661.591532 +system.ruby.LD.latency_hist::stdev 1733.262348 +system.ruby.LD.latency_hist | 4 7.41% 7.41% | 0 0.00% 7.41% | 0 0.00% 7.41% | 0 0.00% 7.41% | 3 5.56% 12.96% | 19 35.19% 48.15% | 24 44.44% 92.59% | 4 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 54 +system.ruby.LD.hit_latency_hist::bucket_size 16 +system.ruby.LD.hit_latency_hist::max_bucket 159 +system.ruby.LD.hit_latency_hist::samples 4 +system.ruby.LD.hit_latency_hist::mean 29.500000 +system.ruby.LD.hit_latency_hist::gmean 6.027587 +system.ruby.LD.hit_latency_hist::stdev 53.681157 +system.ruby.LD.hit_latency_hist | 3 75.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 4 system.ruby.LD.miss_latency_hist::bucket_size 1024 system.ruby.LD.miss_latency_hist::max_bucket 10239 -system.ruby.LD.miss_latency_hist::samples 37 -system.ruby.LD.miss_latency_hist::mean 6007.675676 -system.ruby.LD.miss_latency_hist::gmean 5971.927068 -system.ruby.LD.miss_latency_hist::stdev 679.672881 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 5.41% 5.41% | 22 59.46% 64.86% | 10 27.03% 91.89% | 3 8.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 37 +system.ruby.LD.miss_latency_hist::samples 50 +system.ruby.LD.miss_latency_hist::mean 6148.820000 +system.ruby.LD.miss_latency_hist::gmean 6114.374114 +system.ruby.LD.miss_latency_hist::stdev 647.202668 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 19 38.00% 44.00% | 24 48.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 50 system.ruby.ST.latency_hist::bucket_size 1024 system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 868 -system.ruby.ST.latency_hist::mean 5376.413594 -system.ruby.ST.latency_hist::gmean 3136.848535 -system.ruby.ST.latency_hist::stdev 1827.946779 -system.ruby.ST.latency_hist | 82 9.45% 9.45% | 2 0.23% 9.68% | 2 0.23% 9.91% | 4 0.46% 10.37% | 55 6.34% 16.71% | 446 51.38% 68.09% | 253 29.15% 97.24% | 24 2.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 868 +system.ruby.ST.latency_hist::samples 902 +system.ruby.ST.latency_hist::mean 5364.286031 +system.ruby.ST.latency_hist::gmean 2990.478756 +system.ruby.ST.latency_hist::stdev 1912.037218 +system.ruby.ST.latency_hist | 94 10.42% 10.42% | 4 0.44% 10.86% | 3 0.33% 11.20% | 4 0.44% 11.64% | 27 2.99% 14.63% | 441 48.89% 63.53% | 296 32.82% 96.34% | 33 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 902 system.ruby.ST.hit_latency_hist::bucket_size 16 system.ruby.ST.hit_latency_hist::max_bucket 159 -system.ruby.ST.hit_latency_hist::samples 68 -system.ruby.ST.hit_latency_hist::mean 12.264706 -system.ruby.ST.hit_latency_hist::gmean 3.346538 -system.ruby.ST.hit_latency_hist::stdev 31.130739 -system.ruby.ST.hit_latency_hist | 62 91.18% 91.18% | 0 0.00% 91.18% | 0 0.00% 91.18% | 0 0.00% 91.18% | 0 0.00% 91.18% | 0 0.00% 91.18% | 2 2.94% 94.12% | 4 5.88% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 68 +system.ruby.ST.hit_latency_hist::samples 73 +system.ruby.ST.hit_latency_hist::mean 8.506849 +system.ruby.ST.hit_latency_hist::gmean 2.645743 +system.ruby.ST.hit_latency_hist::stdev 25.369559 +system.ruby.ST.hit_latency_hist | 69 94.52% 94.52% | 0 0.00% 94.52% | 0 0.00% 94.52% | 0 0.00% 94.52% | 0 0.00% 94.52% | 0 0.00% 94.52% | 1 1.37% 95.89% | 3 4.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 73 system.ruby.ST.miss_latency_hist::bucket_size 1024 system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 800 -system.ruby.ST.miss_latency_hist::mean 5832.366250 -system.ruby.ST.miss_latency_hist::gmean 5611.834584 -system.ruby.ST.miss_latency_hist::stdev 984.210196 -system.ruby.ST.miss_latency_hist | 14 1.75% 1.75% | 2 0.25% 2.00% | 2 0.25% 2.25% | 4 0.50% 2.75% | 55 6.88% 9.62% | 446 55.75% 65.38% | 253 31.62% 97.00% | 24 3.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 800 +system.ruby.ST.miss_latency_hist::samples 829 +system.ruby.ST.miss_latency_hist::mean 5835.904704 +system.ruby.ST.miss_latency_hist::gmean 5553.905612 +system.ruby.ST.miss_latency_hist::stdev 1107.483624 +system.ruby.ST.miss_latency_hist | 21 2.53% 2.53% | 4 0.48% 3.02% | 3 0.36% 3.38% | 4 0.48% 3.86% | 27 3.26% 7.12% | 441 53.20% 60.31% | 296 35.71% 96.02% | 33 3.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 829 system.ruby.IFETCH.latency_hist::bucket_size 256 system.ruby.IFETCH.latency_hist::max_bucket 2559 -system.ruby.IFETCH.latency_hist::samples 57 -system.ruby.IFETCH.latency_hist::mean 855.263158 -system.ruby.IFETCH.latency_hist::gmean 754.746405 -system.ruby.IFETCH.latency_hist::stdev 394.368008 -system.ruby.IFETCH.latency_hist | 3 5.26% 5.26% | 8 14.04% 19.30% | 15 26.32% 45.61% | 11 19.30% 64.91% | 12 21.05% 85.96% | 6 10.53% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 57 +system.ruby.IFETCH.latency_hist::samples 46 +system.ruby.IFETCH.latency_hist::mean 772.847826 +system.ruby.IFETCH.latency_hist::gmean 703.281758 +system.ruby.IFETCH.latency_hist::stdev 370.399662 +system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 10 21.74% 21.74% | 20 43.48% 65.22% | 7 15.22% 80.43% | 3 6.52% 86.96% | 4 8.70% 95.65% | 1 2.17% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 46 system.ruby.IFETCH.miss_latency_hist::bucket_size 256 system.ruby.IFETCH.miss_latency_hist::max_bucket 2559 -system.ruby.IFETCH.miss_latency_hist::samples 57 -system.ruby.IFETCH.miss_latency_hist::mean 855.263158 -system.ruby.IFETCH.miss_latency_hist::gmean 754.746405 -system.ruby.IFETCH.miss_latency_hist::stdev 394.368008 -system.ruby.IFETCH.miss_latency_hist | 3 5.26% 5.26% | 8 14.04% 19.30% | 15 26.32% 45.61% | 11 19.30% 64.91% | 12 21.05% 85.96% | 6 10.53% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 57 -system.ruby.L1Cache_Controller.Load 43 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 63 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 870 0.00% 0.00% -system.ruby.L1Cache_Controller.Inv 559 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 9999 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Exclusive 37 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_all_Acks 857 0.00% 0.00% -system.ruby.L1Cache_Controller.WB_Ack 756 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 37 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 57 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 802 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Inv 1 0.00% 0.00% -system.ruby.L1Cache_Controller.I.L1_Replacement 127 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Inv 35 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 6 0.00% 0.00% +system.ruby.IFETCH.miss_latency_hist::samples 46 +system.ruby.IFETCH.miss_latency_hist::mean 772.847826 +system.ruby.IFETCH.miss_latency_hist::gmean 703.281758 +system.ruby.IFETCH.miss_latency_hist::stdev 370.399662 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 10 21.74% 21.74% | 20 43.48% 65.22% | 7 15.22% 80.43% | 3 6.52% 86.96% | 4 8.70% 95.65% | 1 2.17% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 46 +system.ruby.L1Cache_Controller.Load 54 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 54 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 904 0.00% 0.00% +system.ruby.L1Cache_Controller.Inv 563 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 10554 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_Exclusive 50 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_all_Acks 875 0.00% 0.00% +system.ruby.L1Cache_Controller.WB_Ack 784 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Load 50 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Ifetch 46 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Store 831 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Inv 2 0.00% 0.00% +system.ruby.L1Cache_Controller.I.L1_Replacement 125 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Inv 28 0.00% 0.00% +system.ruby.L1Cache_Controller.S.L1_Replacement 10 0.00% 0.00% +system.ruby.L1Cache_Controller.E.Store 1 0.00% 0.00% system.ruby.L1Cache_Controller.E.Inv 5 0.00% 0.00% -system.ruby.L1Cache_Controller.E.L1_Replacement 32 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 6 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 68 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Inv 73 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 726 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Inv 16 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 433 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive 37 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks 41 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 8675 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks 800 0.00% 0.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 16 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.Ifetch 6 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.Inv 429 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack 329 0.00% 0.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 427 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GET_INSTR 57 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 37 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 802 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 335 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 787 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 283 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 1213 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 863 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 857 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 488 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 13 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 56 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 837 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 52 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 36 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 776 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 321 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 5 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 52 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GET_INSTR 5 0.00% 0.00% +system.ruby.L1Cache_Controller.E.L1_Replacement 44 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 4 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 72 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Inv 86 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement 743 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Inv 8 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement 519 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive 50 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks 38 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement 9113 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks 829 0.00% 0.00% +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 8 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.Ifetch 8 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.Inv 434 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack 351 0.00% 0.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 433 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GET_INSTR 47 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 50 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 829 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 358 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 826 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 302 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 1188 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 884 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 878 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 493 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 27 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 43 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 877 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 38 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 49 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 797 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_PUTX_old 309 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 8 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 38 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GET_INSTR 8 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 21 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 283 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 18 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 329 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 507 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 106 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 857 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 206 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 488 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 13 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 24 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 302 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 15 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 351 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 525 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GET_INSTR 1 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 124 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 878 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 215 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 493 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 27 0.00% 0.00% system.ruby.L2Cache_Controller.MCT_I.Ack_all 5 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 51 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 12 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 36 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 51 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 52 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 231 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 775 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 6 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 154 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 342 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 832 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 863 0.00% 0.00% -system.ruby.Directory_Controller.Data 770 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 863 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 770 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 87 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 863 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 770 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 87 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 863 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 770 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 38 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 16 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 49 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 19 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 38 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 224 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 797 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 8 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 7 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 178 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 351 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 869 0.00% 0.00% +system.ruby.Directory_Controller.Fetch 884 0.00% 0.00% +system.ruby.Directory_Controller.Data 795 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 884 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 795 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 85 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 884 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 795 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 85 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 884 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 795 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index aefa03a40..26ba1fbd4 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -1,391 +1,404 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000327 # Number of seconds simulated -sim_ticks 327361 # Number of ticks simulated -final_tick 327361 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000338 # Number of seconds simulated +sim_ticks 338071 # Number of ticks simulated +final_tick 338071 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 771883 # Simulator tick rate (ticks/s) -host_mem_usage 124808 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host +host_tick_rate 719839 # Simulator tick rate (ticks/s) +host_mem_usage 158348 # Number of bytes of host memory used +host_seconds 0.47 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 1000 -system.ruby.outstanding_req_hist::mean 15.813000 -system.ruby.outstanding_req_hist::gmean 15.714362 -system.ruby.outstanding_req_hist::stdev 1.128408 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 2 0.20% 0.90% | 2 0.20% 1.10% | 2 0.20% 1.30% | 69 6.90% 8.20% | 918 91.80% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 1000 +system.ruby.outstanding_req_hist::samples 987 +system.ruby.outstanding_req_hist::mean 15.827761 +system.ruby.outstanding_req_hist::gmean 15.728108 +system.ruby.outstanding_req_hist::stdev 1.130761 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 2 0.20% 0.91% | 2 0.20% 1.11% | 2 0.20% 1.32% | 52 5.27% 6.59% | 922 93.41% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 987 system.ruby.latency_hist::bucket_size 4096 system.ruby.latency_hist::max_bucket 40959 -system.ruby.latency_hist::samples 985 -system.ruby.latency_hist::mean 5192.155330 -system.ruby.latency_hist::gmean 1411.192372 -system.ruby.latency_hist::stdev 6963.102626 -system.ruby.latency_hist | 695 70.56% 70.56% | 43 4.37% 74.92% | 33 3.35% 78.27% | 91 9.24% 87.51% | 85 8.63% 96.14% | 28 2.84% 98.98% | 9 0.91% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 985 +system.ruby.latency_hist::samples 972 +system.ruby.latency_hist::mean 5437.663580 +system.ruby.latency_hist::gmean 1650.672742 +system.ruby.latency_hist::stdev 7600.061844 +system.ruby.latency_hist | 700 72.02% 72.02% | 56 5.76% 77.78% | 10 1.03% 78.81% | 35 3.60% 82.41% | 92 9.47% 91.87% | 63 6.48% 98.35% | 14 1.44% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 972 system.ruby.hit_latency_hist::bucket_size 16 system.ruby.hit_latency_hist::max_bucket 159 -system.ruby.hit_latency_hist::samples 78 -system.ruby.hit_latency_hist::mean 9.089744 -system.ruby.hit_latency_hist::gmean 2.589753 -system.ruby.hit_latency_hist::stdev 26.203591 -system.ruby.hit_latency_hist | 73 93.59% 93.59% | 0 0.00% 93.59% | 0 0.00% 93.59% | 0 0.00% 93.59% | 0 0.00% 93.59% | 0 0.00% 93.59% | 4 5.13% 98.72% | 1 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 78 +system.ruby.hit_latency_hist::samples 57 +system.ruby.hit_latency_hist::mean 21.684211 +system.ruby.hit_latency_hist::gmean 4.921220 +system.ruby.hit_latency_hist::stdev 41.339257 +system.ruby.hit_latency_hist | 47 82.46% 82.46% | 0 0.00% 82.46% | 0 0.00% 82.46% | 0 0.00% 82.46% | 0 0.00% 82.46% | 0 0.00% 82.46% | 6 10.53% 92.98% | 4 7.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 57 system.ruby.miss_latency_hist::bucket_size 4096 system.ruby.miss_latency_hist::max_bucket 40959 -system.ruby.miss_latency_hist::samples 907 -system.ruby.miss_latency_hist::mean 5637.887541 -system.ruby.miss_latency_hist::gmean 2426.075868 -system.ruby.miss_latency_hist::stdev 7081.470328 -system.ruby.miss_latency_hist | 617 68.03% 68.03% | 43 4.74% 72.77% | 33 3.64% 76.41% | 91 10.03% 86.44% | 85 9.37% 95.81% | 28 3.09% 98.90% | 9 0.99% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 907 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 78 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 930 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 8 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 111 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 15 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 2 # Number of times a load aliased with a pending load -system.ruby.network.routers0.percent_links_utilized 1.520569 -system.ruby.network.routers0.msg_count.Request_Control::0 908 -system.ruby.network.routers0.msg_count.Response_Data::2 854 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 53 -system.ruby.network.routers0.msg_count.Writeback_Data::2 903 -system.ruby.network.routers0.msg_count.Writeback_Control::0 1806 -system.ruby.network.routers0.msg_count.Unblock_Control::2 907 -system.ruby.network.routers0.msg_bytes.Request_Control::0 7264 -system.ruby.network.routers0.msg_bytes.Response_Data::2 61488 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 3816 -system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65016 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14448 -system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7256 -system.ruby.l2_cntrl0.L2cache.demand_hits 53 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 855 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 908 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 2.898940 -system.ruby.network.routers1.msg_count.Request_Control::0 908 -system.ruby.network.routers1.msg_count.Request_Control::1 855 -system.ruby.network.routers1.msg_count.Response_Data::2 1708 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 53 -system.ruby.network.routers1.msg_count.Writeback_Data::2 1668 -system.ruby.network.routers1.msg_count.Writeback_Control::0 1806 -system.ruby.network.routers1.msg_count.Writeback_Control::1 1692 -system.ruby.network.routers1.msg_count.Writeback_Control::2 80 -system.ruby.network.routers1.msg_count.Unblock_Control::2 1758 -system.ruby.network.routers1.msg_bytes.Request_Control::0 7264 -system.ruby.network.routers1.msg_bytes.Request_Control::1 6840 -system.ruby.network.routers1.msg_bytes.Response_Data::2 122976 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 3816 -system.ruby.network.routers1.msg_bytes.Writeback_Data::2 120096 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14448 -system.ruby.network.routers1.msg_bytes.Writeback_Control::1 13536 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 640 -system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14064 +system.ruby.miss_latency_hist::samples 915 +system.ruby.miss_latency_hist::mean 5775.052459 +system.ruby.miss_latency_hist::gmean 2371.333869 +system.ruby.miss_latency_hist::stdev 7708.420615 +system.ruby.miss_latency_hist | 643 70.27% 70.27% | 56 6.12% 76.39% | 10 1.09% 77.49% | 35 3.83% 81.31% | 92 10.05% 91.37% | 63 6.89% 98.25% | 14 1.53% 99.78% | 2 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 915 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 54 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 862 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 916 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 3 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 55 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 58 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 87 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 3 # Number of times a load aliased with a pending store +system.ruby.network.routers0.percent_links_utilized 1.484895 +system.ruby.network.routers0.msg_count.Request_Control::0 917 +system.ruby.network.routers0.msg_count.Response_Data::2 860 +system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 55 +system.ruby.network.routers0.msg_count.Writeback_Data::2 910 +system.ruby.network.routers0.msg_count.Writeback_Control::0 1823 +system.ruby.network.routers0.msg_count.Unblock_Control::2 915 +system.ruby.network.routers0.msg_bytes.Request_Control::0 7336 +system.ruby.network.routers0.msg_bytes.Response_Data::2 61920 +system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 3960 +system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65520 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14584 +system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7320 +system.ruby.l2_cntrl0.L2cache.demand_hits 55 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 862 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 917 # Number of cache demand accesses +system.ruby.network.routers1.percent_links_utilized 2.834981 +system.ruby.network.routers1.msg_count.Request_Control::0 917 +system.ruby.network.routers1.msg_count.Request_Control::1 862 +system.ruby.network.routers1.msg_count.Response_Data::2 1721 +system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 55 +system.ruby.network.routers1.msg_count.Writeback_Data::2 1689 +system.ruby.network.routers1.msg_count.Writeback_Control::0 1823 +system.ruby.network.routers1.msg_count.Writeback_Control::1 1704 +system.ruby.network.routers1.msg_count.Writeback_Control::2 73 +system.ruby.network.routers1.msg_count.Unblock_Control::2 1773 +system.ruby.network.routers1.msg_bytes.Request_Control::0 7336 +system.ruby.network.routers1.msg_bytes.Request_Control::1 6896 +system.ruby.network.routers1.msg_bytes.Response_Data::2 123912 +system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 3960 +system.ruby.network.routers1.msg_bytes.Writeback_Data::2 121608 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14584 +system.ruby.network.routers1.msg_bytes.Writeback_Control::1 13632 +system.ruby.network.routers1.msg_bytes.Writeback_Control::2 584 +system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14184 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 1619 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 854 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 765 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 2273 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 420 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memReq 1640 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 861 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 779 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 2346 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 430 # Delay stalled at the head of the bank queue system.ruby.dir_cntrl0.memBuffer.memInputQ 26 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 446 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.275479 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 163 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 144 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.totalStalls 456 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.278049 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 167 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 152 # memory stalls due to busy bus system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 21 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 60 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 58 # memory stalls due to read read turnaround system.ruby.dir_cntrl0.memBuffer.memArbWait 32 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 49 3.03% 3.03% | 44 2.72% 5.74% | 48 2.96% 8.71% | 84 5.19% 13.90% | 49 3.03% 16.92% | 52 3.21% 20.14% | 64 3.95% 24.09% | 51 3.15% 27.24% | 40 2.47% 29.71% | 45 2.78% 32.49% | 48 2.96% 35.45% | 41 2.53% 37.99% | 74 4.57% 42.56% | 47 2.90% 45.46% | 51 3.15% 48.61% | 38 2.35% 50.96% | 56 3.46% 54.42% | 62 3.83% 58.25% | 37 2.29% 60.53% | 58 3.58% 64.11% | 46 2.84% 66.95% | 50 3.09% 70.04% | 55 3.40% 73.44% | 36 2.22% 75.66% | 49 3.03% 78.69% | 71 4.39% 83.08% | 52 3.21% 86.29% | 40 2.47% 88.76% | 42 2.59% 91.35% | 33 2.04% 93.39% | 48 2.96% 96.36% | 59 3.64% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1619 # Number of accesses per bank -system.ruby.network.routers2.percent_links_utilized 1.378219 -system.ruby.network.routers2.msg_count.Request_Control::1 854 -system.ruby.network.routers2.msg_count.Response_Data::2 854 -system.ruby.network.routers2.msg_count.Writeback_Data::2 765 -system.ruby.network.routers2.msg_count.Writeback_Control::1 1690 -system.ruby.network.routers2.msg_count.Writeback_Control::2 80 -system.ruby.network.routers2.msg_count.Unblock_Control::2 852 -system.ruby.network.routers2.msg_bytes.Request_Control::1 6832 -system.ruby.network.routers2.msg_bytes.Response_Data::2 61488 -system.ruby.network.routers2.msg_bytes.Writeback_Data::2 55080 -system.ruby.network.routers2.msg_bytes.Writeback_Control::1 13520 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 640 -system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6816 -system.ruby.network.routers3.percent_links_utilized 1.932474 -system.ruby.network.routers3.msg_count.Request_Control::0 908 -system.ruby.network.routers3.msg_count.Request_Control::1 854 -system.ruby.network.routers3.msg_count.Response_Data::2 1708 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 53 -system.ruby.network.routers3.msg_count.Writeback_Data::2 1668 -system.ruby.network.routers3.msg_count.Writeback_Control::0 1806 -system.ruby.network.routers3.msg_count.Writeback_Control::1 1690 -system.ruby.network.routers3.msg_count.Writeback_Control::2 80 -system.ruby.network.routers3.msg_count.Unblock_Control::2 1758 -system.ruby.network.routers3.msg_bytes.Request_Control::0 7264 -system.ruby.network.routers3.msg_bytes.Request_Control::1 6832 -system.ruby.network.routers3.msg_bytes.Response_Data::2 122976 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 3816 -system.ruby.network.routers3.msg_bytes.Writeback_Data::2 120096 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14448 -system.ruby.network.routers3.msg_bytes.Writeback_Control::1 13520 -system.ruby.network.routers3.msg_bytes.Writeback_Control::2 640 -system.ruby.network.routers3.msg_bytes.Unblock_Control::2 14064 -system.ruby.network.msg_count.Request_Control 5287 -system.ruby.network.msg_count.Response_Data 5124 -system.ruby.network.msg_count.ResponseL2hit_Data 159 -system.ruby.network.msg_count.Writeback_Data 5004 -system.ruby.network.msg_count.Writeback_Control 10730 -system.ruby.network.msg_count.Unblock_Control 5275 -system.ruby.network.msg_byte.Request_Control 42296 -system.ruby.network.msg_byte.Response_Data 368928 -system.ruby.network.msg_byte.ResponseL2hit_Data 11448 -system.ruby.network.msg_byte.Writeback_Data 360288 -system.ruby.network.msg_byte.Writeback_Control 85840 -system.ruby.network.msg_byte.Unblock_Control 42200 -system.ruby.network.routers0.throttle0.link_utilization 1.384710 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 854 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 53 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 903 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 61488 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 3816 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7224 -system.ruby.network.routers0.throttle1.link_utilization 1.656428 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 908 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 903 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 903 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 907 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7264 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 65016 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7224 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7256 -system.ruby.network.routers1.throttle0.link_utilization 2.959271 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 908 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 854 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 903 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 903 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 845 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 906 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7264 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 61488 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 65016 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7224 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6760 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7248 -system.ruby.network.routers1.throttle1.link_utilization 2.838609 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 855 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 854 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 53 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 765 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 903 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 847 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 80 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 852 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6840 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 61488 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 3816 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 55080 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7224 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6776 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 640 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6816 -system.ruby.network.routers2.throttle0.link_utilization 1.453441 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 854 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 765 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 845 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::2 80 -system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 852 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6832 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 55080 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6760 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::2 640 -system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6816 -system.ruby.network.routers2.throttle1.link_utilization 1.302996 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 854 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 845 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 61488 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6760 -system.ruby.network.routers3.throttle0.link_utilization 1.384710 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 854 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 53 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 903 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 61488 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 3816 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7224 -system.ruby.network.routers3.throttle1.link_utilization 2.959271 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 908 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 854 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 903 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 903 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 845 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 906 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7264 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 61488 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 65016 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7224 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6760 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7248 -system.ruby.network.routers3.throttle2.link_utilization 1.453441 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 854 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 765 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 845 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::2 80 -system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 852 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6832 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 55080 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6760 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::2 640 -system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6816 +system.ruby.dir_cntrl0.memBuffer.memBankCount | 58 3.54% 3.54% | 44 2.68% 6.22% | 40 2.44% 8.66% | 88 5.37% 14.02% | 64 3.90% 17.93% | 67 4.09% 22.01% | 55 3.35% 25.37% | 38 2.32% 27.68% | 52 3.17% 30.85% | 39 2.38% 33.23% | 42 2.56% 35.79% | 42 2.56% 38.35% | 49 2.99% 41.34% | 50 3.05% 44.39% | 48 2.93% 47.32% | 55 3.35% 50.67% | 48 2.93% 53.60% | 48 2.93% 56.52% | 50 3.05% 59.57% | 46 2.80% 62.38% | 49 2.99% 65.37% | 70 4.27% 69.63% | 43 2.62% 72.26% | 63 3.84% 76.10% | 59 3.60% 79.70% | 46 2.80% 82.50% | 53 3.23% 85.73% | 56 3.41% 89.15% | 35 2.13% 91.28% | 46 2.80% 94.09% | 42 2.56% 96.65% | 55 3.35% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1640 # Number of accesses per bank +system.ruby.network.routers2.percent_links_utilized 1.350086 +system.ruby.network.routers2.msg_count.Request_Control::1 861 +system.ruby.network.routers2.msg_count.Response_Data::2 861 +system.ruby.network.routers2.msg_count.Writeback_Data::2 779 +system.ruby.network.routers2.msg_count.Writeback_Control::1 1704 +system.ruby.network.routers2.msg_count.Writeback_Control::2 73 +system.ruby.network.routers2.msg_count.Unblock_Control::2 859 +system.ruby.network.routers2.msg_bytes.Request_Control::1 6888 +system.ruby.network.routers2.msg_bytes.Response_Data::2 61992 +system.ruby.network.routers2.msg_bytes.Writeback_Data::2 56088 +system.ruby.network.routers2.msg_bytes.Writeback_Control::1 13632 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 584 +system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6872 +system.ruby.network.routers3.percent_links_utilized 1.890037 +system.ruby.network.routers3.msg_count.Request_Control::0 917 +system.ruby.network.routers3.msg_count.Request_Control::1 862 +system.ruby.network.routers3.msg_count.Response_Data::2 1721 +system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 55 +system.ruby.network.routers3.msg_count.Writeback_Data::2 1689 +system.ruby.network.routers3.msg_count.Writeback_Control::0 1823 +system.ruby.network.routers3.msg_count.Writeback_Control::1 1704 +system.ruby.network.routers3.msg_count.Writeback_Control::2 73 +system.ruby.network.routers3.msg_count.Unblock_Control::2 1774 +system.ruby.network.routers3.msg_bytes.Request_Control::0 7336 +system.ruby.network.routers3.msg_bytes.Request_Control::1 6896 +system.ruby.network.routers3.msg_bytes.Response_Data::2 123912 +system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 3960 +system.ruby.network.routers3.msg_bytes.Writeback_Data::2 121608 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14584 +system.ruby.network.routers3.msg_bytes.Writeback_Control::1 13632 +system.ruby.network.routers3.msg_bytes.Writeback_Control::2 584 +system.ruby.network.routers3.msg_bytes.Unblock_Control::2 14192 +system.ruby.network.msg_count.Request_Control 5336 +system.ruby.network.msg_count.Response_Data 5163 +system.ruby.network.msg_count.ResponseL2hit_Data 165 +system.ruby.network.msg_count.Writeback_Data 5067 +system.ruby.network.msg_count.Writeback_Control 10800 +system.ruby.network.msg_count.Unblock_Control 5321 +system.ruby.network.msg_byte.Request_Control 42688 +system.ruby.network.msg_byte.Response_Data 371736 +system.ruby.network.msg_byte.ResponseL2hit_Data 11880 +system.ruby.network.msg_byte.Writeback_Data 364824 +system.ruby.network.msg_byte.Writeback_Control 86400 +system.ruby.network.msg_byte.Unblock_Control 42568 +system.ruby.network.routers0.throttle0.link_utilization 1.352674 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 860 +system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 55 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 911 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 61920 +system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 3960 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7288 +system.ruby.network.routers0.throttle1.link_utilization 1.617116 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 917 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 910 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 912 +system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 915 +system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7336 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 65520 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7296 +system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7320 +system.ruby.network.routers1.throttle0.link_utilization 2.889038 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 917 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 861 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 910 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 912 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 852 +system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 914 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7336 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 61992 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 65520 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7296 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6816 +system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7312 +system.ruby.network.routers1.throttle1.link_utilization 2.780925 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 862 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 860 +system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 55 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 779 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 911 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 852 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 73 +system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 859 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6896 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 61920 +system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 3960 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 56088 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7288 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6816 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 584 +system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6872 +system.ruby.network.routers2.throttle0.link_utilization 1.428102 +system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 861 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 779 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 852 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::2 73 +system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 859 +system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6888 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 56088 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6816 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::2 584 +system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6872 +system.ruby.network.routers2.throttle1.link_utilization 1.272070 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 861 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 852 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 61992 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6816 +system.ruby.network.routers3.throttle0.link_utilization 1.352674 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 860 +system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 55 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 911 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 61920 +system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 3960 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7288 +system.ruby.network.routers3.throttle1.link_utilization 2.889186 +system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 917 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 861 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 910 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 912 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 852 +system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 915 +system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7336 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 61992 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 65520 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7296 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6816 +system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7320 +system.ruby.network.routers3.throttle2.link_utilization 1.428250 +system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 862 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 779 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 852 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::2 73 +system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 859 +system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6896 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 56088 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6816 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::2 584 +system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6872 system.ruby.LD.latency_hist::bucket_size 4096 system.ruby.LD.latency_hist::max_bucket 40959 -system.ruby.LD.latency_hist::samples 44 -system.ruby.LD.latency_hist::mean 5510.704545 -system.ruby.LD.latency_hist::gmean 869.978187 -system.ruby.LD.latency_hist::stdev 7880.576607 -system.ruby.LD.latency_hist | 32 72.73% 72.73% | 0 0.00% 72.73% | 1 2.27% 75.00% | 4 9.09% 84.09% | 5 11.36% 95.45% | 1 2.27% 97.73% | 1 2.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 44 +system.ruby.LD.latency_hist::samples 43 +system.ruby.LD.latency_hist::mean 6256.744186 +system.ruby.LD.latency_hist::gmean 1688.376032 +system.ruby.LD.latency_hist::stdev 8068.365932 +system.ruby.LD.latency_hist | 29 67.44% 67.44% | 1 2.33% 69.77% | 1 2.33% 72.09% | 3 6.98% 79.07% | 4 9.30% 88.37% | 5 11.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 43 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 6 -system.ruby.LD.hit_latency_hist::mean 2.166667 -system.ruby.LD.hit_latency_hist::gmean 1.906369 -system.ruby.LD.hit_latency_hist::stdev 1.169045 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 2 33.33% 33.33% | 2 33.33% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 6 +system.ruby.LD.hit_latency_hist::samples 3 +system.ruby.LD.hit_latency_hist::mean 3.666667 +system.ruby.LD.hit_latency_hist::gmean 3.634241 +system.ruby.LD.hit_latency_hist::stdev 0.577350 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 3 system.ruby.LD.miss_latency_hist::bucket_size 4096 system.ruby.LD.miss_latency_hist::max_bucket 40959 -system.ruby.LD.miss_latency_hist::samples 38 -system.ruby.LD.miss_latency_hist::mean 6380.473684 -system.ruby.LD.miss_latency_hist::gmean 2287.694735 -system.ruby.LD.miss_latency_hist::stdev 8153.326443 -system.ruby.LD.miss_latency_hist | 26 68.42% 68.42% | 0 0.00% 68.42% | 1 2.63% 71.05% | 4 10.53% 81.58% | 5 13.16% 94.74% | 1 2.63% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 38 +system.ruby.LD.miss_latency_hist::samples 40 +system.ruby.LD.miss_latency_hist::mean 6725.725000 +system.ruby.LD.miss_latency_hist::gmean 2676.075339 +system.ruby.LD.miss_latency_hist::stdev 8177.576523 +system.ruby.LD.miss_latency_hist | 26 65.00% 65.00% | 1 2.50% 67.50% | 1 2.50% 70.00% | 3 7.50% 77.50% | 4 10.00% 87.50% | 5 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 40 system.ruby.ST.latency_hist::bucket_size 4096 system.ruby.ST.latency_hist::max_bucket 40959 -system.ruby.ST.latency_hist::samples 885 -system.ruby.ST.latency_hist::mean 5462.276836 -system.ruby.ST.latency_hist::gmean 1523.559741 -system.ruby.ST.latency_hist::stdev 7040.777523 -system.ruby.ST.latency_hist | 607 68.59% 68.59% | 43 4.86% 73.45% | 32 3.62% 77.06% | 87 9.83% 86.89% | 80 9.04% 95.93% | 27 3.05% 98.98% | 8 0.90% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 885 +system.ruby.ST.latency_hist::samples 872 +system.ruby.ST.latency_hist::mean 5714.713303 +system.ruby.ST.latency_hist::gmean 1797.126289 +system.ruby.ST.latency_hist::stdev 7719.803155 +system.ruby.ST.latency_hist | 614 70.41% 70.41% | 55 6.31% 76.72% | 9 1.03% 77.75% | 32 3.67% 81.42% | 88 10.09% 91.51% | 58 6.65% 98.17% | 14 1.61% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 872 system.ruby.ST.hit_latency_hist::bucket_size 16 system.ruby.ST.hit_latency_hist::max_bucket 159 -system.ruby.ST.hit_latency_hist::samples 72 -system.ruby.ST.hit_latency_hist::mean 9.666667 -system.ruby.ST.hit_latency_hist::gmean 2.656722 -system.ruby.ST.hit_latency_hist::stdev 27.206047 -system.ruby.ST.hit_latency_hist | 67 93.06% 93.06% | 0 0.00% 93.06% | 0 0.00% 93.06% | 0 0.00% 93.06% | 0 0.00% 93.06% | 0 0.00% 93.06% | 4 5.56% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 72 +system.ruby.ST.hit_latency_hist::samples 51 +system.ruby.ST.hit_latency_hist::mean 21.803922 +system.ruby.ST.hit_latency_hist::gmean 4.911597 +system.ruby.ST.hit_latency_hist::stdev 41.550942 +system.ruby.ST.hit_latency_hist | 42 82.35% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 5 9.80% 92.16% | 4 7.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 51 system.ruby.ST.miss_latency_hist::bucket_size 4096 system.ruby.ST.miss_latency_hist::max_bucket 40959 -system.ruby.ST.miss_latency_hist::samples 813 -system.ruby.ST.miss_latency_hist::mean 5945.164822 -system.ruby.ST.miss_latency_hist::gmean 2673.966009 -system.ruby.ST.miss_latency_hist::stdev 7148.312268 -system.ruby.ST.miss_latency_hist | 535 65.81% 65.81% | 43 5.29% 71.09% | 32 3.94% 75.03% | 87 10.70% 85.73% | 80 9.84% 95.57% | 27 3.32% 98.89% | 8 0.98% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 813 -system.ruby.IFETCH.latency_hist::bucket_size 256 -system.ruby.IFETCH.latency_hist::max_bucket 2559 -system.ruby.IFETCH.latency_hist::samples 56 -system.ruby.IFETCH.latency_hist::mean 672.982143 -system.ruby.IFETCH.latency_hist::gmean 614.909107 -system.ruby.IFETCH.latency_hist::stdev 260.614623 -system.ruby.IFETCH.latency_hist | 4 7.14% 7.14% | 9 16.07% 23.21% | 24 42.86% 66.07% | 17 30.36% 96.43% | 1 1.79% 98.21% | 1 1.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 56 -system.ruby.IFETCH.miss_latency_hist::bucket_size 256 -system.ruby.IFETCH.miss_latency_hist::max_bucket 2559 -system.ruby.IFETCH.miss_latency_hist::samples 56 -system.ruby.IFETCH.miss_latency_hist::mean 672.982143 -system.ruby.IFETCH.miss_latency_hist::gmean 614.909107 -system.ruby.IFETCH.miss_latency_hist::stdev 260.614623 -system.ruby.IFETCH.miss_latency_hist | 4 7.14% 7.14% | 9 16.07% 23.21% | 24 42.86% 66.07% | 17 30.36% 96.43% | 1 1.79% 98.21% | 1 1.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 56 +system.ruby.ST.miss_latency_hist::samples 821 +system.ruby.ST.miss_latency_hist::mean 6068.353228 +system.ruby.ST.miss_latency_hist::gmean 2593.060445 +system.ruby.ST.miss_latency_hist::stdev 7820.542647 +system.ruby.ST.miss_latency_hist | 563 68.57% 68.57% | 55 6.70% 75.27% | 9 1.10% 76.37% | 32 3.90% 80.27% | 88 10.72% 90.99% | 58 7.06% 98.05% | 14 1.71% 99.76% | 2 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 821 +system.ruby.IFETCH.latency_hist::bucket_size 128 +system.ruby.IFETCH.latency_hist::max_bucket 1279 +system.ruby.IFETCH.latency_hist::samples 57 +system.ruby.IFETCH.latency_hist::mean 581.385965 +system.ruby.IFETCH.latency_hist::gmean 442.065920 +system.ruby.IFETCH.latency_hist::stdev 271.884544 +system.ruby.IFETCH.latency_hist | 3 5.26% 5.26% | 3 5.26% 10.53% | 9 15.79% 26.32% | 6 10.53% 36.84% | 11 19.30% 56.14% | 10 17.54% 73.68% | 8 14.04% 87.72% | 3 5.26% 92.98% | 4 7.02% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 57 +system.ruby.IFETCH.hit_latency_hist::bucket_size 16 +system.ruby.IFETCH.hit_latency_hist::max_bucket 159 +system.ruby.IFETCH.hit_latency_hist::samples 3 +system.ruby.IFETCH.hit_latency_hist::mean 37.666667 +system.ruby.IFETCH.hit_latency_hist::gmean 6.889419 +system.ruby.IFETCH.hit_latency_hist::stdev 61.784572 +system.ruby.IFETCH.hit_latency_hist | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 3 +system.ruby.IFETCH.miss_latency_hist::bucket_size 128 +system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 +system.ruby.IFETCH.miss_latency_hist::samples 54 +system.ruby.IFETCH.miss_latency_hist::mean 611.592593 +system.ruby.IFETCH.miss_latency_hist::gmean 557.048280 +system.ruby.IFETCH.miss_latency_hist::stdev 245.556320 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 3 5.56% 5.56% | 9 16.67% 22.22% | 6 11.11% 33.33% | 11 20.37% 53.70% | 10 18.52% 72.22% | 8 14.81% 87.04% | 3 5.56% 92.59% | 4 7.41% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 54 system.ruby.L1Cache_Controller.Load 44 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 192 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 1001 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 465203 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 907 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data 903 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks 813 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_Timeout 905 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 38 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 56 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 814 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 307 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 1014 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 481138 0.00% 0.00% +system.ruby.L1Cache_Controller.Exclusive_Data 915 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data 911 0.00% 0.00% +system.ruby.L1Cache_Controller.All_acks 821 0.00% 0.00% +system.ruby.L1Cache_Controller.Use_Timeout 914 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 40 0.00% 0.00% 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-system.ruby.L1Cache_Controller.OM.L1_Replacement 17168 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.All_acks 813 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 16103 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Load 2 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 49 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement 820 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Store 2 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement 30008 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Use_Timeout 821 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement 410291 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data 821 0.00% 0.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement 20607 0.00% 0.00% +system.ruby.L1Cache_Controller.OM.All_acks 821 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement 17859 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Exclusive_Data 94 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 136 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Store 115 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 903 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 127 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 895 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 2308 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 766 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 766 0.00% 0.00% -system.ruby.L2Cache_Controller.Data_Exclusive 88 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 86 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 817 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 845 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 906 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 847 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 88 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 767 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 903 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 47 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 847 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETS 33 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA 86 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 817 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_PUTX 65 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data_Exclusive 88 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock 87 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 766 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTX 1324 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 766 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 766 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_PUTX 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 47 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_PUTX 11 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 6 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETX 81 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 845 0.00% 0.00% -system.ruby.Directory_Controller.GETX 837 0.00% 0.00% -system.ruby.Directory_Controller.GETS 88 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 845 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 852 0.00% 0.00% -system.ruby.Directory_Controller.Clean_Writeback 80 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 765 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 854 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 765 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 766 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 88 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 760 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 845 0.00% 0.00% -system.ruby.Directory_Controller.IS.Exclusive_Unblock 87 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 88 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 765 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 766 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 4 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 71 0.00% 0.00% -system.ruby.Directory_Controller.MI.Clean_Writeback 80 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 765 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Load 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Ifetch 249 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Store 141 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 911 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 142 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 948 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 2296 0.00% 0.00% +system.ruby.L2Cache_Controller.All_Acks 782 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 782 0.00% 0.00% +system.ruby.L2Cache_Controller.Data_Exclusive 79 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 77 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 833 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Ack 852 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 914 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 923 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 80 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 782 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTX 912 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 15 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 40 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 852 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETS 30 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETX 85 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA 77 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 833 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_PUTX 25 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data_Exclusive 79 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock 78 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.Data 782 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTX 1344 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.All_Acks 782 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 781 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_PUTX 15 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 40 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 15 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L2_Replacement 71 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETS 17 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETX 41 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.Writeback_Ack 852 0.00% 0.00% +system.ruby.Directory_Controller.GETX 792 0.00% 0.00% +system.ruby.Directory_Controller.GETS 79 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 852 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 859 0.00% 0.00% +system.ruby.Directory_Controller.Clean_Writeback 73 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 779 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 861 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 779 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 782 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 79 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 775 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 852 0.00% 0.00% +system.ruby.Directory_Controller.IS.Exclusive_Unblock 78 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 79 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Ack 2 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 781 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 782 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 2 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETX 10 0.00% 0.00% +system.ruby.Directory_Controller.MI.Clean_Writeback 73 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 779 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 389c45695..b6763f2e1 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -1,492 +1,495 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000225 # Number of seconds simulated -sim_ticks 225141 # Number of ticks simulated -final_tick 225141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000230 # Number of seconds simulated +sim_ticks 229551 # Number of ticks simulated +final_tick 229551 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1830870 # Simulator tick rate (ticks/s) -host_mem_usage 123716 # Number of bytes of host memory used +host_tick_rate 1899298 # Simulator tick rate (ticks/s) +host_mem_usage 157300 # Number of bytes of host memory used host_seconds 0.12 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 1007 -system.ruby.outstanding_req_hist::mean 15.821251 -system.ruby.outstanding_req_hist::gmean 15.723382 -system.ruby.outstanding_req_hist::stdev 1.122615 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 2 0.20% 0.89% | 2 0.20% 1.09% | 2 0.20% 1.29% | 62 6.16% 7.45% | 932 92.55% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 1007 +system.ruby.outstanding_req_hist::samples 985 +system.ruby.outstanding_req_hist::mean 15.815228 +system.ruby.outstanding_req_hist::gmean 15.715128 +system.ruby.outstanding_req_hist::stdev 1.136234 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 2 0.20% 0.91% | 2 0.20% 1.12% | 2 0.20% 1.32% | 63 6.40% 7.72% | 909 92.28% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 985 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 992 -system.ruby.latency_hist::mean 3579.074597 -system.ruby.latency_hist::gmean 1947.833541 -system.ruby.latency_hist::stdev 1577.291313 -system.ruby.latency_hist | 164 16.53% 16.53% | 5 0.50% 17.04% | 9 0.91% 17.94% | 298 30.04% 47.98% | 470 47.38% 95.36% | 46 4.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 992 +system.ruby.latency_hist::samples 969 +system.ruby.latency_hist::mean 3745.879257 +system.ruby.latency_hist::gmean 2201.717205 +system.ruby.latency_hist::stdev 1540.597184 +system.ruby.latency_hist | 143 14.76% 14.76% | 5 0.52% 15.27% | 8 0.83% 16.10% | 232 23.94% 40.04% | 512 52.84% 92.88% | 69 7.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 969 system.ruby.hit_latency_hist::bucket_size 1024 system.ruby.hit_latency_hist::max_bucket 10239 -system.ruby.hit_latency_hist::samples 126 -system.ruby.hit_latency_hist::mean 988.373016 -system.ruby.hit_latency_hist::gmean 33.259483 -system.ruby.hit_latency_hist::stdev 1726.172973 -system.ruby.hit_latency_hist | 99 78.57% 78.57% | 0 0.00% 78.57% | 0 0.00% 78.57% | 12 9.52% 88.10% | 13 10.32% 98.41% | 2 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 126 +system.ruby.hit_latency_hist::samples 109 +system.ruby.hit_latency_hist::mean 1139 +system.ruby.hit_latency_hist::gmean 39.996322 +system.ruby.hit_latency_hist::stdev 1803.950983 +system.ruby.hit_latency_hist | 82 75.23% 75.23% | 0 0.00% 75.23% | 0 0.00% 75.23% | 12 11.01% 86.24% | 14 12.84% 99.08% | 1 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 109 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 866 -system.ruby.miss_latency_hist::mean 3956.012702 -system.ruby.miss_latency_hist::gmean 3521.573885 -system.ruby.miss_latency_hist::stdev 1140.061981 -system.ruby.miss_latency_hist | 65 7.51% 7.51% | 5 0.58% 8.08% | 9 1.04% 9.12% | 286 33.03% 42.15% | 457 52.77% 94.92% | 44 5.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 866 -system.ruby.Directory.incomplete_times 866 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 82 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 864 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 946 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 47 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 47 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 860 +system.ruby.miss_latency_hist::mean 4076.286047 +system.ruby.miss_latency_hist::gmean 3659.235822 +system.ruby.miss_latency_hist::stdev 1137.467741 +system.ruby.miss_latency_hist | 61 7.09% 7.09% | 5 0.58% 7.67% | 8 0.93% 8.60% | 220 25.58% 34.19% | 498 57.91% 92.09% | 68 7.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 860 +system.ruby.Directory.incomplete_times 860 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 65 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 858 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 923 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 49 # Number of cache demand accesses system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 10 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 87 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load -system.ruby.network.routers0.percent_links_utilized 2.173860 -system.ruby.network.routers0.msg_count.Request_Control::1 911 -system.ruby.network.routers0.msg_count.Response_Data::4 925 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 40 -system.ruby.network.routers0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.msg_count.Writeback_Data::4 1026 -system.ruby.network.routers0.msg_count.Persistent_Control::3 746 -system.ruby.network.routers0.msg_bytes.Request_Control::1 7288 -system.ruby.network.routers0.msg_bytes.Response_Data::4 66600 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 2880 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.msg_bytes.Writeback_Data::4 73872 -system.ruby.network.routers0.msg_bytes.Persistent_Control::3 5968 -system.ruby.l2_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 872 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 911 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 1.983424 -system.ruby.network.routers1.msg_count.Request_Control::1 911 -system.ruby.network.routers1.msg_count.Request_Control::2 872 -system.ruby.network.routers1.msg_count.Response_Data::4 28 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 40 -system.ruby.network.routers1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.msg_count.Writeback_Data::4 1669 -system.ruby.network.routers1.msg_count.Writeback_Control::4 72 -system.ruby.network.routers1.msg_count.Persistent_Control::3 373 -system.ruby.network.routers1.msg_bytes.Request_Control::1 7288 -system.ruby.network.routers1.msg_bytes.Request_Control::2 6976 -system.ruby.network.routers1.msg_bytes.Response_Data::4 2016 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 2880 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.msg_bytes.Writeback_Data::4 120168 -system.ruby.network.routers1.msg_bytes.Writeback_Control::4 576 -system.ruby.network.routers1.msg_bytes.Persistent_Control::3 2984 +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 96 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 2 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 3 # Number of times a load aliased with a pending load +system.ruby.network.routers0.percent_links_utilized 2.057604 +system.ruby.network.routers0.msg_count.Request_Control::1 906 +system.ruby.network.routers0.msg_count.Response_Data::4 885 +system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 39 +system.ruby.network.routers0.msg_count.Writeback_Data::4 1007 +system.ruby.network.routers0.msg_count.Persistent_Control::3 608 +system.ruby.network.routers0.msg_bytes.Request_Control::1 7248 +system.ruby.network.routers0.msg_bytes.Response_Data::4 63720 +system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 2808 +system.ruby.network.routers0.msg_bytes.Writeback_Data::4 72504 +system.ruby.network.routers0.msg_bytes.Persistent_Control::3 4864 +system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 866 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 904 # Number of cache demand accesses +system.ruby.network.routers1.percent_links_utilized 1.916676 +system.ruby.network.routers1.msg_count.Request_Control::1 904 +system.ruby.network.routers1.msg_count.Request_Control::2 866 +system.ruby.network.routers1.msg_count.Response_Data::4 15 +system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 39 +system.ruby.network.routers1.msg_count.Writeback_Data::4 1663 +system.ruby.network.routers1.msg_count.Writeback_Control::4 80 +system.ruby.network.routers1.msg_count.Persistent_Control::3 301 +system.ruby.network.routers1.msg_bytes.Request_Control::1 7232 +system.ruby.network.routers1.msg_bytes.Request_Control::2 6928 +system.ruby.network.routers1.msg_bytes.Response_Data::4 1080 +system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 2808 +system.ruby.network.routers1.msg_bytes.Writeback_Data::4 119736 +system.ruby.network.routers1.msg_bytes.Writeback_Control::4 640 +system.ruby.network.routers1.msg_bytes.Persistent_Control::3 2408 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 1655 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 868 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 787 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 1564 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 469 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 34 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 503 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.303927 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 134 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 192 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 48 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memReq 1634 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 861 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 773 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 1593 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 544 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 45 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 1 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 590 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.361077 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 168 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 199 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 85 # memory stalls due to read write turnaround system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 56 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 39 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 51 3.08% 3.08% | 47 2.84% 5.92% | 34 2.05% 7.98% | 94 5.68% 13.66% | 74 4.47% 18.13% | 59 3.56% 21.69% | 55 3.32% 25.02% | 45 2.72% 27.73% | 53 3.20% 30.94% | 55 3.32% 34.26% | 62 3.75% 38.01% | 49 2.96% 40.97% | 52 3.14% 44.11% | 51 3.08% 47.19% | 44 2.66% 49.85% | 57 3.44% 53.29% | 49 2.96% 56.25% | 51 3.08% 59.34% | 46 2.78% 62.11% | 44 2.66% 64.77% | 46 2.78% 67.55% | 41 2.48% 70.03% | 54 3.26% 73.29% | 56 3.38% 76.68% | 46 2.78% 79.46% | 55 3.32% 82.78% | 50 3.02% 85.80% | 43 2.60% 88.40% | 43 2.60% 91.00% | 47 2.84% 93.84% | 62 3.75% 97.58% | 40 2.42% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1655 # Number of accesses per bank -system.ruby.network.routers2.percent_links_utilized 1.823191 -system.ruby.network.routers2.msg_count.Request_Control::2 872 -system.ruby.network.routers2.msg_count.Response_Data::4 897 -system.ruby.network.routers2.msg_count.Writeback_Data::4 781 -system.ruby.network.routers2.msg_count.Writeback_Control::4 72 -system.ruby.network.routers2.msg_count.Persistent_Control::3 373 -system.ruby.network.routers2.msg_bytes.Request_Control::2 6976 -system.ruby.network.routers2.msg_bytes.Response_Data::4 64584 -system.ruby.network.routers2.msg_bytes.Writeback_Data::4 56232 -system.ruby.network.routers2.msg_bytes.Writeback_Control::4 576 -system.ruby.network.routers2.msg_bytes.Persistent_Control::3 2984 -system.ruby.network.routers3.percent_links_utilized 1.993491 -system.ruby.network.routers3.msg_count.Request_Control::1 911 -system.ruby.network.routers3.msg_count.Request_Control::2 872 -system.ruby.network.routers3.msg_count.Response_Data::4 925 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 40 -system.ruby.network.routers3.msg_count.Response_Control::4 1 -system.ruby.network.routers3.msg_count.Writeback_Data::4 1738 -system.ruby.network.routers3.msg_count.Writeback_Control::4 72 -system.ruby.network.routers3.msg_count.Persistent_Control::3 746 -system.ruby.network.routers3.msg_bytes.Request_Control::1 7288 -system.ruby.network.routers3.msg_bytes.Request_Control::2 6976 -system.ruby.network.routers3.msg_bytes.Response_Data::4 66600 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 2880 -system.ruby.network.routers3.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.msg_bytes.Writeback_Data::4 125136 -system.ruby.network.routers3.msg_bytes.Writeback_Control::4 576 -system.ruby.network.routers3.msg_bytes.Persistent_Control::3 5968 -system.ruby.network.msg_count.Request_Control 5349 -system.ruby.network.msg_count.Response_Data 2775 -system.ruby.network.msg_count.ResponseL2hit_Data 120 -system.ruby.network.msg_count.Response_Control 3 -system.ruby.network.msg_count.Writeback_Data 5214 -system.ruby.network.msg_count.Writeback_Control 216 -system.ruby.network.msg_count.Persistent_Control 2238 -system.ruby.network.msg_byte.Request_Control 42792 -system.ruby.network.msg_byte.Response_Data 199800 -system.ruby.network.msg_byte.ResponseL2hit_Data 8640 -system.ruby.network.msg_byte.Response_Control 24 -system.ruby.network.msg_byte.Writeback_Data 375408 -system.ruby.network.msg_byte.Writeback_Control 1728 -system.ruby.network.msg_byte.Persistent_Control 17904 -system.ruby.network.routers0.throttle0.link_utilization 2.077809 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 898 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 40 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 60 -system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 373 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 64656 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 2880 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 4320 -system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 2984 -system.ruby.network.routers0.throttle1.link_utilization 2.269911 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 911 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 27 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 966 -system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 373 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 7288 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 1944 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 69552 -system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 2984 -system.ruby.network.routers1.throttle0.link_utilization 2.096020 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 911 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 906 -system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 373 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 7288 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 65232 -system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 2984 -system.ruby.network.routers1.throttle1.link_utilization 1.870828 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 872 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 28 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 40 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 763 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 72 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6976 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2016 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 2880 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 54936 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 576 -system.ruby.network.routers2.throttle0.link_utilization 1.889483 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 872 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 27 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 772 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 72 -system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 373 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6976 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 1944 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 55584 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 576 -system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 2984 -system.ruby.network.routers2.throttle1.link_utilization 1.756899 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 870 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::4 9 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 62640 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::4 648 -system.ruby.network.routers3.throttle0.link_utilization 1.994972 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 898 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 40 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 60 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 64656 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 2880 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 4320 -system.ruby.network.routers3.throttle1.link_utilization 2.096020 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 911 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 906 -system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 373 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 7288 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 65232 -system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 2984 -system.ruby.network.routers3.throttle2.link_utilization 1.889483 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 872 -system.ruby.network.routers3.throttle2.msg_count.Response_Data::4 27 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 772 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 72 -system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 373 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6976 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::4 1944 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 55584 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 576 -system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 2984 +system.ruby.dir_cntrl0.memBuffer.memArbWait 36 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 45 2.75% 2.75% | 38 2.33% 5.08% | 48 2.94% 8.02% | 106 6.49% 14.50% | 75 4.59% 19.09% | 81 4.96% 24.05% | 55 3.37% 27.42% | 64 3.92% 31.33% | 51 3.12% 34.46% | 56 3.43% 37.88% | 37 2.26% 40.15% | 37 2.26% 42.41% | 56 3.43% 45.84% | 37 2.26% 48.10% | 48 2.94% 51.04% | 54 3.30% 54.35% | 44 2.69% 57.04% | 44 2.69% 59.73% | 44 2.69% 62.42% | 38 2.33% 64.75% | 55 3.37% 68.12% | 45 2.75% 70.87% | 57 3.49% 74.36% | 42 2.57% 76.93% | 41 2.51% 79.44% | 50 3.06% 82.50% | 35 2.14% 84.64% | 53 3.24% 87.88% | 47 2.88% 90.76% | 50 3.06% 93.82% | 49 3.00% 96.82% | 52 3.18% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1634 # Number of accesses per bank +system.ruby.network.routers2.percent_links_utilized 1.744384 +system.ruby.network.routers2.msg_count.Request_Control::2 865 +system.ruby.network.routers2.msg_count.Response_Data::4 870 +system.ruby.network.routers2.msg_count.Writeback_Data::4 771 +system.ruby.network.routers2.msg_count.Writeback_Control::4 80 +system.ruby.network.routers2.msg_count.Persistent_Control::3 303 +system.ruby.network.routers2.msg_bytes.Request_Control::2 6920 +system.ruby.network.routers2.msg_bytes.Response_Data::4 62640 +system.ruby.network.routers2.msg_bytes.Writeback_Data::4 55512 +system.ruby.network.routers2.msg_bytes.Writeback_Control::4 640 +system.ruby.network.routers2.msg_bytes.Persistent_Control::3 2424 +system.ruby.network.routers3.percent_links_utilized 1.906766 +system.ruby.network.routers3.msg_count.Request_Control::1 905 +system.ruby.network.routers3.msg_count.Request_Control::2 865 +system.ruby.network.routers3.msg_count.Response_Data::4 885 +system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 39 +system.ruby.network.routers3.msg_count.Writeback_Data::4 1721 +system.ruby.network.routers3.msg_count.Writeback_Control::4 80 +system.ruby.network.routers3.msg_count.Persistent_Control::3 607 +system.ruby.network.routers3.msg_bytes.Request_Control::1 7240 +system.ruby.network.routers3.msg_bytes.Request_Control::2 6920 +system.ruby.network.routers3.msg_bytes.Response_Data::4 63720 +system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 2808 +system.ruby.network.routers3.msg_bytes.Writeback_Data::4 123912 +system.ruby.network.routers3.msg_bytes.Writeback_Control::4 640 +system.ruby.network.routers3.msg_bytes.Persistent_Control::3 4856 +system.ruby.network.msg_count.Request_Control 5311 +system.ruby.network.msg_count.Response_Data 2655 +system.ruby.network.msg_count.ResponseL2hit_Data 117 +system.ruby.network.msg_count.Writeback_Data 5162 +system.ruby.network.msg_count.Writeback_Control 240 +system.ruby.network.msg_count.Persistent_Control 1819 +system.ruby.network.msg_byte.Request_Control 42488 +system.ruby.network.msg_byte.Response_Data 191160 +system.ruby.network.msg_byte.ResponseL2hit_Data 8424 +system.ruby.network.msg_byte.Writeback_Data 371664 +system.ruby.network.msg_byte.Writeback_Control 1920 +system.ruby.network.msg_byte.Persistent_Control 14552 +system.ruby.network.routers0.throttle0.link_utilization 1.963834 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 875 +system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 39 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 54 +system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 304 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 63000 +system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 2808 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 3888 +system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 2432 +system.ruby.network.routers0.throttle1.link_utilization 2.151374 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 906 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 10 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 953 +system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 304 +system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 7248 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 720 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 68616 +system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 2432 +system.ruby.network.routers1.throttle0.link_utilization 2.023733 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 904 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 899 +system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 301 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 7232 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 64728 +system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 2408 +system.ruby.network.routers1.throttle1.link_utilization 1.809620 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 866 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 15 +system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 39 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 764 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 80 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6928 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 1080 +system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 2808 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 55008 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 640 +system.ruby.network.routers2.throttle0.link_utilization 1.795026 +system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 865 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 10 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 767 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 80 +system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 303 +system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6920 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 720 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 55224 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 640 +system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 2424 +system.ruby.network.routers2.throttle1.link_utilization 1.693741 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 860 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::4 4 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 61920 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::4 288 +system.ruby.network.routers3.throttle0.link_utilization 1.897618 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 875 +system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 39 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 54 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 63000 +system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 2808 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 3888 +system.ruby.network.routers3.throttle1.link_utilization 2.025476 +system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 905 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 899 +system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 303 +system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 7240 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 64728 +system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 2424 +system.ruby.network.routers3.throttle2.link_utilization 1.797204 +system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 865 +system.ruby.network.routers3.throttle2.msg_count.Response_Data::4 10 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 768 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 80 +system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 304 +system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6920 +system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::4 720 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 55296 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 640 +system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 2432 system.ruby.LD.latency_hist::bucket_size 1024 system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 53 -system.ruby.LD.latency_hist::mean 3847.981132 -system.ruby.LD.latency_hist::gmean 2117.840098 -system.ruby.LD.latency_hist::stdev 1453.914034 -system.ruby.LD.latency_hist | 6 11.32% 11.32% | 0 0.00% 11.32% | 1 1.89% 13.21% | 15 28.30% 41.51% | 26 49.06% 90.57% | 5 9.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 53 +system.ruby.LD.latency_hist::samples 52 +system.ruby.LD.latency_hist::mean 4084.307692 +system.ruby.LD.latency_hist::gmean 2925.833819 +system.ruby.LD.latency_hist::stdev 1345.909453 +system.ruby.LD.latency_hist | 5 9.62% 9.62% | 0 0.00% 9.62% | 0 0.00% 9.62% | 7 13.46% 23.08% | 34 65.38% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 52 system.ruby.LD.hit_latency_hist::bucket_size 512 system.ruby.LD.hit_latency_hist::max_bucket 5119 -system.ruby.LD.hit_latency_hist::samples 7 -system.ruby.LD.hit_latency_hist::mean 1354.142857 -system.ruby.LD.hit_latency_hist::gmean 28.155273 -system.ruby.LD.hit_latency_hist::stdev 2279.826048 -system.ruby.LD.hit_latency_hist | 5 71.43% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 1 14.29% 85.71% | 1 14.29% 100.00% -system.ruby.LD.hit_latency_hist::total 7 +system.ruby.LD.hit_latency_hist::samples 5 +system.ruby.LD.hit_latency_hist::mean 997.400000 +system.ruby.LD.hit_latency_hist::gmean 89.277594 +system.ruby.LD.hit_latency_hist::stdev 1774.639344 +system.ruby.LD.hit_latency_hist | 4 80.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 5 system.ruby.LD.miss_latency_hist::bucket_size 1024 system.ruby.LD.miss_latency_hist::max_bucket 10239 -system.ruby.LD.miss_latency_hist::samples 46 -system.ruby.LD.miss_latency_hist::mean 4227.478261 -system.ruby.LD.miss_latency_hist::gmean 4087.164963 -system.ruby.LD.miss_latency_hist::stdev 796.882195 -system.ruby.LD.miss_latency_hist | 1 2.17% 2.17% | 0 0.00% 2.17% | 1 2.17% 4.35% | 15 32.61% 36.96% | 24 52.17% 89.13% | 5 10.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 46 +system.ruby.LD.miss_latency_hist::samples 47 +system.ruby.LD.miss_latency_hist::mean 4412.702128 +system.ruby.LD.miss_latency_hist::gmean 4241.054205 +system.ruby.LD.miss_latency_hist::stdev 767.181372 +system.ruby.LD.miss_latency_hist | 1 2.13% 2.13% | 0 0.00% 2.13% | 0 0.00% 2.13% | 7 14.89% 17.02% | 33 70.21% 87.23% | 6 12.77% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 47 system.ruby.ST.latency_hist::bucket_size 1024 system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 892 -system.ruby.ST.latency_hist::mean 3728.136771 -system.ruby.ST.latency_hist::gmean 2108.403124 -system.ruby.ST.latency_hist::stdev 1448.246319 -system.ruby.ST.latency_hist | 111 12.44% 12.44% | 5 0.56% 13.00% | 8 0.90% 13.90% | 283 31.73% 45.63% | 444 49.78% 95.40% | 41 4.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 892 +system.ruby.ST.latency_hist::samples 869 +system.ruby.ST.latency_hist::mean 3909.064442 +system.ruby.ST.latency_hist::gmean 2393.585593 +system.ruby.ST.latency_hist::stdev 1376.670697 +system.ruby.ST.latency_hist | 90 10.36% 10.36% | 5 0.58% 10.93% | 8 0.92% 11.85% | 225 25.89% 37.74% | 478 55.01% 92.75% | 63 7.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 869 system.ruby.ST.hit_latency_hist::bucket_size 1024 system.ruby.ST.hit_latency_hist::max_bucket 10239 -system.ruby.ST.hit_latency_hist::samples 114 -system.ruby.ST.hit_latency_hist::mean 981.052632 -system.ruby.ST.hit_latency_hist::gmean 29.537745 -system.ruby.ST.hit_latency_hist::stdev 1733.689885 -system.ruby.ST.hit_latency_hist | 89 78.07% 78.07% | 0 0.00% 78.07% | 0 0.00% 78.07% | 12 10.53% 88.60% | 11 9.65% 98.25% | 2 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 114 +system.ruby.ST.hit_latency_hist::samples 97 +system.ruby.ST.hit_latency_hist::mean 1199.505155 +system.ruby.ST.hit_latency_hist::gmean 34.143629 +system.ruby.ST.hit_latency_hist::stdev 1865.494830 +system.ruby.ST.hit_latency_hist | 71 73.20% 73.20% | 0 0.00% 73.20% | 0 0.00% 73.20% | 12 12.37% 85.57% | 13 13.40% 98.97% | 1 1.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 97 system.ruby.ST.miss_latency_hist::bucket_size 1024 system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 778 -system.ruby.ST.miss_latency_hist::mean 4130.665810 -system.ruby.ST.miss_latency_hist::gmean 3940.554861 -system.ruby.ST.miss_latency_hist::stdev 835.813724 -system.ruby.ST.miss_latency_hist | 22 2.83% 2.83% | 5 0.64% 3.47% | 8 1.03% 4.50% | 271 34.83% 39.33% | 433 55.66% 94.99% | 39 5.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 778 +system.ruby.ST.miss_latency_hist::samples 772 +system.ruby.ST.miss_latency_hist::mean 4249.514249 +system.ruby.ST.miss_latency_hist::gmean 4082.834729 +system.ruby.ST.miss_latency_hist::stdev 812.787360 +system.ruby.ST.miss_latency_hist | 19 2.46% 2.46% | 5 0.65% 3.11% | 8 1.04% 4.15% | 213 27.59% 31.74% | 465 60.23% 91.97% | 62 8.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 772 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 47 -system.ruby.IFETCH.latency_hist::mean 446.829787 -system.ruby.IFETCH.latency_hist::gmean 394.156540 -system.ruby.IFETCH.latency_hist::stdev 206.945941 -system.ruby.IFETCH.latency_hist | 2 4.26% 4.26% | 10 21.28% 25.53% | 6 12.77% 38.30% | 9 19.15% 57.45% | 10 21.28% 78.72% | 6 12.77% 91.49% | 4 8.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 47 +system.ruby.IFETCH.latency_hist::samples 48 +system.ruby.IFETCH.latency_hist::mean 424.916667 +system.ruby.IFETCH.latency_hist::gmean 356.475043 +system.ruby.IFETCH.latency_hist::stdev 182.937012 +system.ruby.IFETCH.latency_hist | 3 6.25% 6.25% | 4 8.33% 14.58% | 13 27.08% 41.67% | 11 22.92% 64.58% | 11 22.92% 87.50% | 5 10.42% 97.92% | 1 2.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 48 system.ruby.IFETCH.hit_latency_hist::bucket_size 128 system.ruby.IFETCH.hit_latency_hist::max_bucket 1279 -system.ruby.IFETCH.hit_latency_hist::samples 5 -system.ruby.IFETCH.hit_latency_hist::mean 643.200000 -system.ruby.IFETCH.hit_latency_hist::gmean 628.468542 -system.ruby.IFETCH.hit_latency_hist::stdev 152.681695 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 5 +system.ruby.IFETCH.hit_latency_hist::samples 7 +system.ruby.IFETCH.hit_latency_hist::mean 401.714286 +system.ruby.IFETCH.hit_latency_hist::gmean 201.865504 +system.ruby.IFETCH.hit_latency_hist::stdev 292.445844 +system.ruby.IFETCH.hit_latency_hist | 1 14.29% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 7 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 42 -system.ruby.IFETCH.miss_latency_hist::mean 423.452381 -system.ruby.IFETCH.miss_latency_hist::gmean 372.861830 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system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 1024 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 10239 -system.ruby.L2Cache.hit_mach_latency_hist::samples 44 -system.ruby.L2Cache.hit_mach_latency_hist::mean 2796.318182 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 1779.985903 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 1876.082197 -system.ruby.L2Cache.hit_mach_latency_hist | 17 38.64% 38.64% | 0 0.00% 38.64% | 0 0.00% 38.64% | 12 27.27% 65.91% | 13 29.55% 95.45% | 2 4.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 44 +system.ruby.L2Cache.hit_mach_latency_hist::samples 43 +system.ruby.L2Cache.hit_mach_latency_hist::mean 2866.116279 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 1934.532931 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 1822.821364 +system.ruby.L2Cache.hit_mach_latency_hist | 16 37.21% 37.21% | 0 0.00% 37.21% | 0 0.00% 37.21% | 12 27.91% 65.12% | 14 32.56% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 43 system.ruby.Directory.miss_mach_latency_hist::bucket_size 1024 system.ruby.Directory.miss_mach_latency_hist::max_bucket 10239 -system.ruby.Directory.miss_mach_latency_hist::samples 866 -system.ruby.Directory.miss_mach_latency_hist::mean 3956.012702 -system.ruby.Directory.miss_mach_latency_hist::gmean 3521.573885 -system.ruby.Directory.miss_mach_latency_hist::stdev 1140.061981 -system.ruby.Directory.miss_mach_latency_hist | 65 7.51% 7.51% | 5 0.58% 8.08% | 9 1.04% 9.12% | 286 33.03% 42.15% | 457 52.77% 94.92% | 44 5.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 866 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 16 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 159 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0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 860 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 2 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 3 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2.828427 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev 1.414214 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 2 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 2 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-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 1821.766406 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 12 32.43% 32.43% | 0 0.00% 32.43% | 0 0.00% 32.43% | 12 32.43% 64.86% | 11 29.73% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 37 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 34 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 3395.676471 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 2727.100257 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 1571.778046 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 8 23.53% 23.53% | 0 0.00% 23.53% | 0 0.00% 23.53% | 12 35.29% 58.82% | 13 38.24% 97.06% | 1 2.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 34 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 1024 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 10239 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 778 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 4130.665810 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 3940.554861 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 835.813724 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 22 2.83% 2.83% | 5 0.64% 3.47% | 8 1.03% 4.50% | 271 34.83% 39.33% | 433 55.66% 94.99% | 39 5.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 778 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 772 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 4249.514249 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 4082.834729 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 812.787360 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 19 2.46% 2.46% | 5 0.65% 3.11% | 8 1.04% 4.15% | 213 27.59% 31.74% | 465 60.23% 91.97% | 62 8.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 772 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 3 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 3.000000 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::stdev nan +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 1 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 128 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 5 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 643.200000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 628.468542 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 152.681695 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 5 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 6 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 468.166667 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 407.116701 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 255.999544 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 1 16.67% 16.67% | 2 33.33% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 6 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 128 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 42 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 423.452381 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 372.861830 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 201.277530 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 2 4.76% 4.76% | 10 23.81% 28.57% | 6 14.29% 42.86% | 8 19.05% 61.90% | 9 21.43% 83.33% | 4 9.52% 92.86% | 3 7.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 42 -system.ruby.L1Cache_Controller.Load 53 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 47 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 893 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 19950 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Shared 3 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 41 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 428.878049 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 392.820579 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 162.430015 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 2 4.88% 4.88% | 3 7.32% 12.20% | 11 26.83% 39.02% | 11 26.83% 65.85% | 10 24.39% 90.24% | 4 9.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 41 +system.ruby.L1Cache_Controller.Load 52 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 49 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 871 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 19827 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_Shared 7 0.00% 0.00% system.ruby.L1Cache_Controller.Data_Owner 1 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_All_Tokens 993 0.00% 0.00% -system.ruby.L1Cache_Controller.Ack_All_Tokens 1 0.00% 0.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 373 0.00% 0.00% -system.ruby.L1Cache_Controller.Request_Timeout 509 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 906 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 48 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 47 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 816 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Data_All_Tokens 87 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 180 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 3 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_All_Tokens 960 0.00% 0.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 304 0.00% 0.00% +system.ruby.L1Cache_Controller.Request_Timeout 548 0.00% 0.00% +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 895 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Load 50 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Ifetch 48 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Store 807 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Data_All_Tokens 64 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 146 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00% +system.ruby.L1Cache_Controller.S.L1_Replacement 5 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Data_Owner 1 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Own_Lock_or_Unlock 2 0.00% 0.00% +system.ruby.L1Cache_Controller.O.Ifetch 1 0.00% 0.00% +system.ruby.L1Cache_Controller.O.L1_Replacement 1 0.00% 0.00% system.ruby.L1Cache_Controller.M.L1_Replacement 89 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 18 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 5 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 66 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 814 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock 15 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement 468 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 91 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 7711 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock 25 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 815 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 10210 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_Owner 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens 814 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 114 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Request_Timeout 443 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.Ack_All_Tokens 1 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock 1 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.Request_Timeout 6 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 655 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Shared 3 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens 92 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 19 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout 60 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 95 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 816 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 817 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 11 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Load 2 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 59 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement 805 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock 16 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement 419 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 89 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Store 4 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement 7837 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock 12 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 806 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement 10077 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data_All_Tokens 805 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 105 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Request_Timeout 510 0.00% 0.00% +system.ruby.L1Cache_Controller.SM.Data_All_Tokens 1 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement 594 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Shared 7 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens 90 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 12 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Request_Timeout 38 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 97 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 807 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 807 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_Shared_Data 1 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 905 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETX 163 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 24 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 186 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 91 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 779 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 821 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 158 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_All_Tokens 898 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETX 135 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS 16 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 150 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 89 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 774 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 1 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 810 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 134 0.00% 0.00% system.ruby.L2Cache_Controller.I.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 32 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 31 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L2_Replacement 12 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 33 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 1 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 1 0.00% 0.00% system.ruby.L2Cache_Controller.O.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 2 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 3 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 36 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 784 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETX 23 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L2_Replacement 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 51 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 139 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 19 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 28 0.00% 0.00% -system.ruby.Directory_Controller.GETX 789 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L2_Replacement 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 4 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Persistent_GETS 1 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 31 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 793 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETX 12 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETS 2 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 50 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETX 122 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETS 13 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 15 0.00% 0.00% +system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 1 0.00% 0.00% +system.ruby.Directory_Controller.GETX 784 0.00% 0.00% system.ruby.Directory_Controller.GETS 94 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 187 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 186 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 799 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 72 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 787 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 86 0.00% 0.00% -system.ruby.Directory_Controller.O.Lockdown 14 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 2 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 4 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 166 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 787 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 72 0.00% 0.00% -system.ruby.Directory_Controller.L.GETX 10 0.00% 0.00% -system.ruby.Directory_Controller.L.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 185 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_All_Tokens 12 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 152 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 151 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 1 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 776 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 79 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 1 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 861 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 773 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 765 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 88 0.00% 0.00% +system.ruby.Directory_Controller.O.Lockdown 8 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 5 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 133 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 772 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 79 0.00% 0.00% +system.ruby.Directory_Controller.L.GETX 5 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 150 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_All_Tokens 4 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 4 0.00% 0.00% system.ruby.Directory_Controller.O_W.Memory_Data 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 787 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 773 0.00% 0.00% system.ruby.Directory_Controller.L_O_W.GETX 9 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETS 2 0.00% 0.00% system.ruby.Directory_Controller.L_O_W.Unlockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Data 13 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 7 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 7 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 847 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Data 7 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 11 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 11 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 842 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 618345d21..d9bed26dd 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -1,448 +1,443 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000172 # Number of seconds simulated -sim_ticks 172201 # Number of ticks simulated -final_tick 172201 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000180 # Number of seconds simulated +sim_ticks 180141 # Number of ticks simulated +final_tick 180141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1805084 # Simulator tick rate (ticks/s) -host_mem_usage 124680 # Number of bytes of host memory used +host_tick_rate 1826543 # Simulator tick rate (ticks/s) +host_mem_usage 157212 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 986 -system.ruby.outstanding_req_hist::mean 15.788032 -system.ruby.outstanding_req_hist::gmean 15.687524 -system.ruby.outstanding_req_hist::stdev 1.144707 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 2 0.20% 0.91% | 2 0.20% 1.12% | 2 0.20% 1.32% | 88 8.92% 10.24% | 885 89.76% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 986 +system.ruby.outstanding_req_hist::samples 1006 +system.ruby.outstanding_req_hist::mean 15.782306 +system.ruby.outstanding_req_hist::gmean 15.683612 +system.ruby.outstanding_req_hist::stdev 1.136165 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 2 0.20% 0.89% | 2 0.20% 1.09% | 2 0.20% 1.29% | 98 9.74% 11.03% | 895 88.97% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 1006 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 971 -system.ruby.latency_hist::mean 2802.392379 -system.ruby.latency_hist::gmean 1451.351840 -system.ruby.latency_hist::stdev 1327.570901 -system.ruby.latency_hist | 157 16.17% 16.17% | 29 2.99% 19.16% | 1 0.10% 19.26% | 3 0.31% 19.57% | 15 1.54% 21.11% | 152 15.65% 36.77% | 362 37.28% 74.05% | 199 20.49% 94.54% | 42 4.33% 98.87% | 11 1.13% 100.00% -system.ruby.latency_hist::total 971 +system.ruby.latency_hist::samples 991 +system.ruby.latency_hist::mean 2874.908174 +system.ruby.latency_hist::gmean 1571.008914 +system.ruby.latency_hist::stdev 1325.547924 +system.ruby.latency_hist | 153 15.44% 15.44% | 26 2.62% 18.06% | 4 0.40% 18.47% | 0 0.00% 18.47% | 24 2.42% 20.89% | 118 11.91% 32.80% | 341 34.41% 67.20% | 267 26.94% 94.15% | 51 5.15% 99.29% | 7 0.71% 100.00% +system.ruby.latency_hist::total 991 system.ruby.hit_latency_hist::bucket_size 512 system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 125 -system.ruby.hit_latency_hist::mean 762.232000 -system.ruby.hit_latency_hist::gmean 22.623560 -system.ruby.hit_latency_hist::stdev 1395.728456 -system.ruby.hit_latency_hist | 97 77.60% 77.60% | 1 0.80% 78.40% | 0 0.00% 78.40% | 0 0.00% 78.40% | 1 0.80% 79.20% | 7 5.60% 84.80% | 10 8.00% 92.80% | 7 5.60% 98.40% | 2 1.60% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 125 +system.ruby.hit_latency_hist::samples 118 +system.ruby.hit_latency_hist::mean 809.601695 +system.ruby.hit_latency_hist::gmean 26.745437 +system.ruby.hit_latency_hist::stdev 1402.420911 +system.ruby.hit_latency_hist | 88 74.58% 74.58% | 2 1.69% 76.27% | 0 0.00% 76.27% | 0 0.00% 76.27% | 2 1.69% 77.97% | 8 6.78% 84.75% | 11 9.32% 94.07% | 6 5.08% 99.15% | 1 0.85% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 118 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 846 -system.ruby.miss_latency_hist::mean 3103.834515 -system.ruby.miss_latency_hist::gmean 2684.081643 -system.ruby.miss_latency_hist::stdev 1015.184360 -system.ruby.miss_latency_hist | 60 7.09% 7.09% | 28 3.31% 10.40% | 1 0.12% 10.52% | 3 0.35% 10.87% | 14 1.65% 12.53% | 145 17.14% 29.67% | 352 41.61% 71.28% | 192 22.70% 93.97% | 40 4.73% 98.70% | 11 1.30% 100.00% -system.ruby.miss_latency_hist::total 846 -system.ruby.Directory.incomplete_times 846 +system.ruby.miss_latency_hist::samples 873 +system.ruby.miss_latency_hist::mean 3154.067583 +system.ruby.miss_latency_hist::gmean 2724.443878 +system.ruby.miss_latency_hist::stdev 1037.171502 +system.ruby.miss_latency_hist | 65 7.45% 7.45% | 24 2.75% 10.19% | 4 0.46% 10.65% | 0 0.00% 10.65% | 22 2.52% 13.17% | 110 12.60% 25.77% | 330 37.80% 63.57% | 261 29.90% 93.47% | 50 5.73% 99.20% | 7 0.80% 100.00% +system.ruby.miss_latency_hist::total 873 +system.ruby.Directory.incomplete_times 873 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.L1Dcache.demand_hits 70 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 848 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 65 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 875 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 940 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 49 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 49 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 848 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 897 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 11 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 2 # Number of times a load aliased with a pending load -system.ruby.network.routers0.percent_links_utilized 2.616564 -system.ruby.network.routers0.msg_count.Request_Control::2 852 -system.ruby.network.routers0.msg_count.Response_Data::4 850 -system.ruby.network.routers0.msg_count.Writeback_Data::5 768 -system.ruby.network.routers0.msg_count.Writeback_Control::2 845 -system.ruby.network.routers0.msg_count.Writeback_Control::3 844 -system.ruby.network.routers0.msg_count.Writeback_Control::5 75 -system.ruby.network.routers0.msg_count.Unblock_Control::5 845 -system.ruby.network.routers0.msg_bytes.Request_Control::2 6816 -system.ruby.network.routers0.msg_bytes.Response_Data::4 61200 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 55296 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6760 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6752 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 600 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6760 -system.ruby.dir_cntrl0.memBuffer.memReq 1617 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 850 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 767 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 1196 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 550 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 48 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 1 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 599 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.370439 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 172 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 204 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 82 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 60 3.71% 3.71% | 50 3.09% 6.80% | 58 3.59% 10.39% | 80 4.95% 15.34% | 69 4.27% 19.60% | 77 4.76% 24.37% | 71 4.39% 28.76% | 48 2.97% 31.73% | 48 2.97% 34.69% | 38 2.35% 37.04% | 42 2.60% 39.64% | 44 2.72% 42.36% | 39 2.41% 44.77% | 57 3.53% 48.30% | 47 2.91% 51.21% | 44 2.72% 53.93% | 42 2.60% 56.52% | 45 2.78% 59.31% | 53 3.28% 62.59% | 54 3.34% 65.92% | 55 3.40% 69.33% | 41 2.54% 71.86% | 48 2.97% 74.83% | 56 3.46% 78.29% | 29 1.79% 80.09% | 45 2.78% 82.87% | 43 2.66% 85.53% | 51 3.15% 88.68% | 47 2.91% 91.59% | 51 3.15% 94.74% | 42 2.60% 97.34% | 43 2.66% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1617 # Number of accesses per bank +system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 51 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 50 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 875 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 925 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 83 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store +system.ruby.network.routers0.percent_links_utilized 2.571180 +system.ruby.network.routers0.msg_count.Request_Control::2 876 +system.ruby.network.routers0.msg_count.Response_Data::4 874 +system.ruby.network.routers0.msg_count.Writeback_Data::5 789 +system.ruby.network.routers0.msg_count.Writeback_Control::2 869 +system.ruby.network.routers0.msg_count.Writeback_Control::3 866 +system.ruby.network.routers0.msg_count.Writeback_Control::5 76 +system.ruby.network.routers0.msg_count.Unblock_Control::5 873 +system.ruby.network.routers0.msg_bytes.Request_Control::2 7008 +system.ruby.network.routers0.msg_bytes.Response_Data::4 62928 +system.ruby.network.routers0.msg_bytes.Writeback_Data::5 56808 +system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6952 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6928 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 608 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6984 +system.ruby.dir_cntrl0.memBuffer.memReq 1663 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 874 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 789 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 1251 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 540 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 5 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 591 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.355382 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 182 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 208 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 34 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 83 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 33 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 66 3.97% 3.97% | 48 2.89% 6.86% | 54 3.25% 10.10% | 88 5.29% 15.39% | 64 3.85% 19.24% | 67 4.03% 23.27% | 67 4.03% 27.30% | 52 3.13% 30.43% | 60 3.61% 34.03% | 53 3.19% 37.22% | 57 3.43% 40.65% | 32 1.92% 42.57% | 42 2.53% 45.10% | 48 2.89% 47.99% | 35 2.10% 50.09% | 37 2.22% 52.32% | 52 3.13% 55.44% | 55 3.31% 58.75% | 45 2.71% 61.46% | 46 2.77% 64.22% | 43 2.59% 66.81% | 60 3.61% 70.41% | 49 2.95% 73.36% | 52 3.13% 76.49% | 54 3.25% 79.74% | 44 2.65% 82.38% | 47 2.83% 85.21% | 51 3.07% 88.27% | 37 2.22% 90.50% | 52 3.13% 93.63% | 50 3.01% 96.63% | 56 3.37% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1663 # Number of accesses per bank system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 2.614822 -system.ruby.network.routers1.msg_count.Request_Control::2 851 -system.ruby.network.routers1.msg_count.Response_Data::4 850 -system.ruby.network.routers1.msg_count.Writeback_Data::5 767 -system.ruby.network.routers1.msg_count.Writeback_Control::2 843 -system.ruby.network.routers1.msg_count.Writeback_Control::3 844 -system.ruby.network.routers1.msg_count.Writeback_Control::5 75 -system.ruby.network.routers1.msg_count.Unblock_Control::5 845 -system.ruby.network.routers1.msg_bytes.Request_Control::2 6808 -system.ruby.network.routers1.msg_bytes.Response_Data::4 61200 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 55224 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6744 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6752 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 600 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6760 -system.ruby.network.routers2.percent_links_utilized 2.616129 -system.ruby.network.routers2.msg_count.Request_Control::2 851 -system.ruby.network.routers2.msg_count.Response_Data::4 850 -system.ruby.network.routers2.msg_count.Writeback_Data::5 768 -system.ruby.network.routers2.msg_count.Writeback_Control::2 843 -system.ruby.network.routers2.msg_count.Writeback_Control::3 844 -system.ruby.network.routers2.msg_count.Writeback_Control::5 75 -system.ruby.network.routers2.msg_count.Unblock_Control::5 845 -system.ruby.network.routers2.msg_bytes.Request_Control::2 6808 -system.ruby.network.routers2.msg_bytes.Response_Data::4 61200 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 55296 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6744 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6752 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 600 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6760 -system.ruby.network.msg_count.Request_Control 2554 -system.ruby.network.msg_count.Response_Data 2550 -system.ruby.network.msg_count.Writeback_Data 2303 -system.ruby.network.msg_count.Writeback_Control 5288 -system.ruby.network.msg_count.Unblock_Control 2535 -system.ruby.network.msg_byte.Request_Control 20432 -system.ruby.network.msg_byte.Response_Data 183600 -system.ruby.network.msg_byte.Writeback_Data 165816 -system.ruby.network.msg_byte.Writeback_Control 42304 -system.ruby.network.msg_byte.Unblock_Control 20280 -system.ruby.network.routers0.throttle0.link_utilization 2.466304 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 850 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 844 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 61200 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6752 -system.ruby.network.routers0.throttle1.link_utilization 2.766825 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 852 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 768 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 845 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 75 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 845 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 6816 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 55296 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 6760 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 600 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 6760 -system.ruby.network.routers1.throttle0.link_utilization 2.763341 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 851 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 767 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 843 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 75 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 845 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 6808 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 55224 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 6744 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 600 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 6760 -system.ruby.network.routers1.throttle1.link_utilization 2.466304 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 850 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 844 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 61200 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 6752 -system.ruby.network.routers2.throttle0.link_utilization 2.466304 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 850 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 844 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 61200 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6752 -system.ruby.network.routers2.throttle1.link_utilization 2.765954 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 851 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 768 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-system.ruby.LD.latency_hist::stdev 1378.721224 -system.ruby.LD.latency_hist | 9 18.00% 18.00% | 1 2.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 2.00% 22.00% | 8 16.00% 38.00% | 15 30.00% 68.00% | 14 28.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 50 +system.ruby.LD.latency_hist::samples 49 +system.ruby.LD.latency_hist::mean 3191.306122 +system.ruby.LD.latency_hist::gmean 2107.747152 +system.ruby.LD.latency_hist::stdev 1000.724721 +system.ruby.LD.latency_hist | 4 8.16% 8.16% | 0 0.00% 8.16% | 0 0.00% 8.16% | 0 0.00% 8.16% | 0 0.00% 8.16% | 5 10.20% 18.37% | 25 51.02% 69.39% | 15 30.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 49 system.ruby.LD.hit_latency_hist::bucket_size 16 system.ruby.LD.hit_latency_hist::max_bucket 159 -system.ruby.LD.hit_latency_hist::samples 5 -system.ruby.LD.hit_latency_hist::mean 24 -system.ruby.LD.hit_latency_hist::gmean 3.987421 -system.ruby.LD.hit_latency_hist::stdev 49.203658 -system.ruby.LD.hit_latency_hist | 4 80.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 5 +system.ruby.LD.hit_latency_hist::samples 4 +system.ruby.LD.hit_latency_hist::mean 31.750000 +system.ruby.LD.hit_latency_hist::gmean 8.056049 +system.ruby.LD.hit_latency_hist::stdev 56.835288 +system.ruby.LD.hit_latency_hist | 3 75.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 4 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 system.ruby.LD.miss_latency_hist::samples 45 -system.ruby.LD.miss_latency_hist::mean 3086.733333 -system.ruby.LD.miss_latency_hist::gmean 2560.470465 -system.ruby.LD.miss_latency_hist::stdev 1075.782430 -system.ruby.LD.miss_latency_hist | 4 8.89% 8.89% | 1 2.22% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 1 2.22% 13.33% | 8 17.78% 31.11% | 15 33.33% 64.44% | 14 31.11% 95.56% | 2 4.44% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 3472.155556 +system.ruby.LD.miss_latency_hist::gmean 3457.202829 +system.ruby.LD.miss_latency_hist::stdev 322.606216 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 11.11% 11.11% | 25 55.56% 66.67% | 15 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 45 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 866 -system.ruby.ST.latency_hist::mean 2940.797921 -system.ruby.ST.latency_hist::gmean 1643.954154 -system.ruby.ST.latency_hist::stdev 1219.878101 -system.ruby.ST.latency_hist | 110 12.70% 12.70% | 16 1.85% 14.55% | 1 0.12% 14.67% | 3 0.35% 15.01% | 14 1.62% 16.63% | 144 16.63% 33.26% | 345 39.84% 73.09% | 183 21.13% 94.23% | 39 4.50% 98.73% | 11 1.27% 100.00% -system.ruby.ST.latency_hist::total 866 +system.ruby.ST.latency_hist::samples 889 +system.ruby.ST.latency_hist::mean 3004.976378 +system.ruby.ST.latency_hist::gmean 1749.500693 +system.ruby.ST.latency_hist::stdev 1224.459726 +system.ruby.ST.latency_hist | 109 12.26% 12.26% | 14 1.57% 13.84% | 4 0.45% 14.29% | 0 0.00% 14.29% | 24 2.70% 16.99% | 113 12.71% 29.70% | 316 35.55% 65.24% | 251 28.23% 93.48% | 51 5.74% 99.21% | 7 0.79% 100.00% +system.ruby.ST.latency_hist::total 889 system.ruby.ST.hit_latency_hist::bucket_size 512 system.ruby.ST.hit_latency_hist::max_bucket 5119 -system.ruby.ST.hit_latency_hist::samples 105 -system.ruby.ST.hit_latency_hist::mean 726.142857 -system.ruby.ST.hit_latency_hist::gmean 21.587264 -system.ruby.ST.hit_latency_hist::stdev 1344.515765 -system.ruby.ST.hit_latency_hist | 82 78.10% 78.10% | 1 0.95% 79.05% | 0 0.00% 79.05% | 0 0.00% 79.05% | 1 0.95% 80.00% | 7 6.67% 86.67% | 8 7.62% 94.29% | 5 4.76% 99.05% | 1 0.95% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 105 +system.ruby.ST.hit_latency_hist::samples 102 +system.ruby.ST.hit_latency_hist::mean 887.392157 +system.ruby.ST.hit_latency_hist::gmean 28.209510 +system.ruby.ST.hit_latency_hist::stdev 1444.836166 +system.ruby.ST.hit_latency_hist | 74 72.55% 72.55% | 1 0.98% 73.53% | 0 0.00% 73.53% | 0 0.00% 73.53% | 2 1.96% 75.49% | 8 7.84% 83.33% | 11 10.78% 94.12% | 5 4.90% 99.02% | 1 0.98% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 102 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 761 -system.ruby.ST.miss_latency_hist::mean 3246.367937 -system.ruby.ST.miss_latency_hist::gmean 2988.950366 -system.ruby.ST.miss_latency_hist::stdev 821.708353 -system.ruby.ST.miss_latency_hist | 28 3.68% 3.68% | 15 1.97% 5.65% | 1 0.13% 5.78% | 3 0.39% 6.18% | 13 1.71% 7.88% | 137 18.00% 25.89% | 337 44.28% 70.17% | 178 23.39% 93.56% | 38 4.99% 98.55% | 11 1.45% 100.00% -system.ruby.ST.miss_latency_hist::total 761 +system.ruby.ST.miss_latency_hist::samples 787 +system.ruby.ST.miss_latency_hist::mean 3279.428208 +system.ruby.ST.miss_latency_hist::gmean 2987.001628 +system.ruby.ST.miss_latency_hist::stdev 876.519166 +system.ruby.ST.miss_latency_hist | 35 4.45% 4.45% | 13 1.65% 6.10% | 4 0.51% 6.61% | 0 0.00% 6.61% | 22 2.80% 9.40% | 105 13.34% 22.74% | 305 38.75% 61.50% | 246 31.26% 92.76% | 50 6.35% 99.11% | 7 0.89% 100.00% +system.ruby.ST.miss_latency_hist::total 787 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 50 -system.ruby.IFETCH.latency_hist::mean 332.280000 -system.ruby.IFETCH.latency_hist::gmean 165.036201 -system.ruby.IFETCH.latency_hist::stdev 230.031678 -system.ruby.IFETCH.latency_hist | 12 24.00% 24.00% | 6 12.00% 36.00% | 11 22.00% 58.00% | 9 18.00% 76.00% | 7 14.00% 90.00% | 4 8.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 50 +system.ruby.IFETCH.latency_hist::samples 51 +system.ruby.IFETCH.latency_hist::mean 325.960784 +system.ruby.IFETCH.latency_hist::gmean 181.443736 +system.ruby.IFETCH.latency_hist::stdev 223.289316 +system.ruby.IFETCH.latency_hist | 11 21.57% 21.57% | 8 15.69% 37.25% | 11 21.57% 58.82% | 10 19.61% 78.43% | 7 13.73% 92.16% | 3 5.88% 98.04% | 0 0.00% 98.04% | 1 1.96% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 51 system.ruby.IFETCH.hit_latency_hist::bucket_size 16 system.ruby.IFETCH.hit_latency_hist::max_bucket 159 system.ruby.IFETCH.hit_latency_hist::samples 10 -system.ruby.IFETCH.hit_latency_hist::mean 15.900000 -system.ruby.IFETCH.hit_latency_hist::gmean 6.857887 -system.ruby.IFETCH.hit_latency_hist::stdev 32.084784 -system.ruby.IFETCH.hit_latency_hist | 9 90.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::mean 28 +system.ruby.IFETCH.hit_latency_hist::gmean 11.094785 +system.ruby.IFETCH.hit_latency_hist::stdev 45.397014 +system.ruby.IFETCH.hit_latency_hist | 8 80.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 10 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 40 -system.ruby.IFETCH.miss_latency_hist::mean 411.375000 -system.ruby.IFETCH.miss_latency_hist::gmean 365.532878 -system.ruby.IFETCH.miss_latency_hist::stdev 184.831550 -system.ruby.IFETCH.miss_latency_hist | 2 5.00% 5.00% | 6 15.00% 20.00% | 11 27.50% 47.50% | 9 22.50% 70.00% | 7 17.50% 87.50% | 4 10.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 40 +system.ruby.IFETCH.miss_latency_hist::samples 41 +system.ruby.IFETCH.miss_latency_hist::mean 398.634146 +system.ruby.IFETCH.miss_latency_hist::gmean 358.713406 +system.ruby.IFETCH.miss_latency_hist::stdev 185.068468 +system.ruby.IFETCH.miss_latency_hist | 1 2.44% 2.44% | 8 19.51% 21.95% | 11 26.83% 48.78% | 10 24.39% 73.17% | 7 17.07% 90.24% | 3 7.32% 97.56% | 0 0.00% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 41 system.ruby.FLUSH.latency_hist::bucket_size 512 system.ruby.FLUSH.latency_hist::max_bucket 5119 -system.ruby.FLUSH.latency_hist::samples 5 -system.ruby.FLUSH.latency_hist::mean 3751 -system.ruby.FLUSH.latency_hist::gmean 3739.394420 -system.ruby.FLUSH.latency_hist::stdev 332.267212 -system.ruby.FLUSH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.latency_hist::total 5 +system.ruby.FLUSH.latency_hist::samples 2 +system.ruby.FLUSH.latency_hist::mean 2306 +system.ruby.FLUSH.latency_hist::gmean 1583.874995 +system.ruby.FLUSH.latency_hist::stdev 2370.221931 +system.ruby.FLUSH.latency_hist | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.latency_hist::total 2 system.ruby.FLUSH.hit_latency_hist::bucket_size 512 system.ruby.FLUSH.hit_latency_hist::max_bucket 5119 -system.ruby.FLUSH.hit_latency_hist::samples 5 -system.ruby.FLUSH.hit_latency_hist::mean 3751 -system.ruby.FLUSH.hit_latency_hist::gmean 3739.394420 -system.ruby.FLUSH.hit_latency_hist::stdev 332.267212 -system.ruby.FLUSH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.hit_latency_hist::total 5 +system.ruby.FLUSH.hit_latency_hist::samples 2 +system.ruby.FLUSH.hit_latency_hist::mean 2306 +system.ruby.FLUSH.hit_latency_hist::gmean 1583.874995 +system.ruby.FLUSH.hit_latency_hist::stdev 2370.221931 +system.ruby.FLUSH.hit_latency_hist | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.hit_latency_hist::total 2 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.hit_mach_latency_hist::samples 76 -system.ruby.L1Cache.hit_mach_latency_hist::mean 256.355263 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 4.735297 -system.ruby.L1Cache.hit_mach_latency_hist::stdev 937.091695 -system.ruby.L1Cache.hit_mach_latency_hist | 71 93.42% 93.42% | 0 0.00% 93.42% | 0 0.00% 93.42% | 0 0.00% 93.42% | 0 0.00% 93.42% | 0 0.00% 93.42% | 2 2.63% 96.05% | 2 2.63% 98.68% | 1 1.32% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 76 +system.ruby.L1Cache.hit_mach_latency_hist::samples 68 +system.ruby.L1Cache.hit_mach_latency_hist::mean 81.279412 +system.ruby.L1Cache.hit_mach_latency_hist::gmean 4.024527 +system.ruby.L1Cache.hit_mach_latency_hist::stdev 486.967063 +system.ruby.L1Cache.hit_mach_latency_hist | 66 97.06% 97.06% | 1 1.47% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 68 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 512 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L2Cache.hit_mach_latency_hist::samples 49 -system.ruby.L2Cache.hit_mach_latency_hist::mean 1546.857143 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 255.879347 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 1620.719799 -system.ruby.L2Cache.hit_mach_latency_hist | 26 53.06% 53.06% | 1 2.04% 55.10% | 0 0.00% 55.10% | 0 0.00% 55.10% | 1 2.04% 57.14% | 7 14.29% 71.43% | 8 16.33% 87.76% | 5 10.20% 97.96% | 1 2.04% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 49 +system.ruby.L2Cache.hit_mach_latency_hist::samples 50 +system.ruby.L2Cache.hit_mach_latency_hist::mean 1800.120000 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 351.477196 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 1623.164265 +system.ruby.L2Cache.hit_mach_latency_hist | 22 44.00% 44.00% | 1 2.00% 46.00% | 0 0.00% 46.00% | 0 0.00% 46.00% | 2 4.00% 50.00% | 8 16.00% 66.00% | 11 22.00% 88.00% | 5 10.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 50 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 846 -system.ruby.Directory.miss_mach_latency_hist::mean 3103.834515 -system.ruby.Directory.miss_mach_latency_hist::gmean 2684.081643 -system.ruby.Directory.miss_mach_latency_hist::stdev 1015.184360 -system.ruby.Directory.miss_mach_latency_hist | 60 7.09% 7.09% | 28 3.31% 10.40% | 1 0.12% 10.52% | 3 0.35% 10.87% | 14 1.65% 12.53% | 145 17.14% 29.67% | 352 41.61% 71.28% | 192 22.70% 93.97% | 40 4.73% 98.70% | 11 1.30% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 846 +system.ruby.Directory.miss_mach_latency_hist::samples 873 +system.ruby.Directory.miss_mach_latency_hist::mean 3154.067583 +system.ruby.Directory.miss_mach_latency_hist::gmean 2724.443878 +system.ruby.Directory.miss_mach_latency_hist::stdev 1037.171502 +system.ruby.Directory.miss_mach_latency_hist | 65 7.45% 7.45% | 24 2.75% 10.19% | 4 0.46% 10.65% | 0 0.00% 10.65% | 22 2.52% 13.17% | 110 12.60% 25.77% | 330 37.80% 63.57% | 261 29.90% 93.47% | 50 5.73% 99.20% | 7 0.80% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 873 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 16 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 159 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 5 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 24 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 3.987421 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev 49.203658 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 4 80.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 5 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 4 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 31.750000 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 8.056049 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev 56.835288 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 3 75.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 4 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 45 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 3086.733333 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 2560.470465 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 1075.782430 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 4 8.89% 8.89% | 1 2.22% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 1 2.22% 13.33% | 8 17.78% 31.11% | 15 33.33% 64.44% | 14 31.11% 95.56% | 2 4.44% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 3472.155556 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 3457.202829 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 322.606216 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 11.11% 11.11% | 25 55.56% 66.67% | 15 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 45 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 16 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 159 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 65 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 9.338462 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2.941703 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev 26.601384 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 61 93.85% 93.85% | 0 0.00% 93.85% | 0 0.00% 93.85% | 0 0.00% 93.85% | 0 0.00% 93.85% | 0 0.00% 93.85% | 2 3.08% 96.92% | 2 3.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 65 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 61 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 11.114754 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2.994444 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev 29.103893 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 56 91.80% 91.80% | 0 0.00% 91.80% | 0 0.00% 91.80% | 0 0.00% 91.80% | 0 0.00% 91.80% | 0 0.00% 91.80% | 4 6.56% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 61 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 40 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1890.950000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 550.548503 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 1603.595990 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 17 42.50% 42.50% | 1 2.50% 45.00% | 0 0.00% 45.00% | 0 0.00% 45.00% | 1 2.50% 47.50% | 7 17.50% 65.00% | 8 20.00% 85.00% | 5 12.50% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 40 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 41 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 2191.121951 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 793.662103 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 1535.123207 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 13 31.71% 31.71% | 1 2.44% 34.15% | 0 0.00% 34.15% | 0 0.00% 34.15% | 2 4.88% 39.02% | 8 19.51% 58.54% | 11 26.83% 85.37% | 5 12.20% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 41 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 761 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3246.367937 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 2988.950366 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 821.708353 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 28 3.68% 3.68% | 15 1.97% 5.65% | 1 0.13% 5.78% | 3 0.39% 6.18% | 13 1.71% 7.88% | 137 18.00% 25.89% | 337 44.28% 70.17% | 178 23.39% 93.56% | 38 4.99% 98.55% | 11 1.45% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 761 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 787 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3279.428208 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 2987.001628 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 876.519166 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 35 4.45% 4.45% | 13 1.65% 6.10% | 4 0.51% 6.61% | 0 0.00% 6.61% | 22 2.80% 9.40% | 105 13.34% 22.74% | 305 38.75% 61.50% | 246 31.26% 92.76% | 50 6.35% 99.11% | 7 0.89% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 787 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 16 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 159 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 110 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8.493767 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 33.574958 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 8 88.89% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 18.888889 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 8.598482 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::stdev 37.210363 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 8 88.89% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 9 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 128 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 40 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 411.375000 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 365.532878 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 184.831550 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 2 5.00% 5.00% | 6 15.00% 20.00% | 11 27.50% 47.50% | 9 22.50% 70.00% | 7 17.50% 87.50% | 4 10.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 40 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 41 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 398.634146 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 358.713406 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 185.068468 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 1 2.44% 2.44% | 8 19.51% 21.95% | 11 26.83% 48.78% | 10 24.39% 73.17% | 7 17.07% 90.24% | 3 7.32% 97.56% | 0 0.00% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 41 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples 5 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 3751 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 3739.394420 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 332.267212 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 5 -system.ruby.L1Cache_Controller.Load 52 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 53 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 888 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 840 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 16587 0.00% 0.00% +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples 2 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 2306 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 1583.874995 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 2370.221931 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 2 +system.ruby.L1Cache_Controller.Load 49 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 911 0.00% 0.00% +system.ruby.L1Cache_Controller.L2_Replacement 868 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_to_L2 16881 0.00% 0.00% system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 41 0.00% 0.00% system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 9 0.00% 0.00% system.ruby.L1Cache_Controller.Complete_L2_to_L1 50 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 850 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 843 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 850 0.00% 0.00% -system.ruby.L1Cache_Controller.Flush_line 5 0.00% 0.00% +system.ruby.L1Cache_Controller.Exclusive_Data 874 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 865 0.00% 0.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers 874 0.00% 0.00% +system.ruby.L1Cache_Controller.Flush_line 2 0.00% 0.00% system.ruby.L1Cache_Controller.Block_Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 46 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 40 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 762 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Flush_line 4 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 71 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 83 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 5 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 62 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement 769 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2 809 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 30 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 45 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 41 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 789 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Flush_line 1 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L2_Replacement 76 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_to_L2 85 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 9 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Ifetch 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 59 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement 792 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2 834 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 32 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Store 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2 90 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Flush_line 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MR.Store 9 0.00% 0.00% +system.ruby.L1Cache_Controller.MR.L1_to_L2 39 0.00% 0.00% system.ruby.L1Cache_Controller.MMR.Ifetch 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Store 29 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2 25 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Flush_line 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2 9996 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 761 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2 306 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 85 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 3 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 4592 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 761 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2 529 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 85 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Load 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 3 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 838 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Store 2 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2 54 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Store 18 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2 103 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 39 0.00% 0.00% -system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 5 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.Store 32 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.L1_to_L2 55 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2 10347 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data 787 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2 238 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 86 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Store 2 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 4618 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 787 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_to_L2 572 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data 86 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Ifetch 4 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 863 0.00% 0.00% +system.ruby.L1Cache_Controller.MT.L1_to_L2 26 0.00% 0.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 9 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.Store 20 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.L1_to_L2 67 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 41 0.00% 0.00% +system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 2 0.00% 0.00% system.ruby.L1Cache_Controller.MM_F.Block_Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 4 0.00% 0.00% -system.ruby.Directory_Controller.GETX 761 0.00% 0.00% +system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 1 0.00% 0.00% +system.ruby.Directory_Controller.GETX 787 0.00% 0.00% system.ruby.Directory_Controller.GETS 87 0.00% 0.00% -system.ruby.Directory_Controller.PUT 913 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 845 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 75 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 767 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 850 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 767 0.00% 0.00% -system.ruby.Directory_Controller.GETF 5 0.00% 0.00% -system.ruby.Directory_Controller.PUTF 5 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 838 0.00% 0.00% +system.ruby.Directory_Controller.PUT 932 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 870 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 76 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 789 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 874 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 789 0.00% 0.00% +system.ruby.Directory_Controller.GETF 2 0.00% 0.00% +system.ruby.Directory_Controller.PUTF 2 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 866 0.00% 0.00% system.ruby.Directory_Controller.NO.GETF 1 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 761 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 85 0.00% 0.00% -system.ruby.Directory_Controller.E.GETF 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 75 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 845 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 846 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 787 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 86 0.00% 0.00% +system.ruby.Directory_Controller.E.GETF 1 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 66 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 870 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 873 0.00% 0.00% system.ruby.Directory_Controller.WB.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 75 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 767 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 767 0.00% 0.00% -system.ruby.Directory_Controller.NO_F.PUTF 5 0.00% 0.00% -system.ruby.Directory_Controller.NO_F_W.Memory_Data 4 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 76 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 789 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 789 0.00% 0.00% +system.ruby.Directory_Controller.NO_F.PUTF 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_F_W.Memory_Data 1 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 83714cb16..f36d287b9 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -1,276 +1,285 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000222 # Number of seconds simulated -sim_ticks 221941 # Number of ticks simulated -final_tick 221941 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000228 # Number of seconds simulated +sim_ticks 228001 # Number of ticks simulated +final_tick 228001 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2110232 # Simulator tick rate (ticks/s) -host_mem_usage 170916 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 3675993 # Simulator tick rate (ticks/s) +host_mem_usage 127868 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 4 # delay histogram for all message -system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 1828 # delay histogram for all message -system.ruby.delayHist::mean 0.560175 # delay histogram for all message -system.ruby.delayHist::stdev 2.065483 # delay histogram for all message -system.ruby.delayHist | 1690 92.45% 92.45% | 89 4.87% 97.32% | 33 1.81% 99.12% | 11 0.60% 99.73% | 4 0.22% 99.95% | 0 0.00% 99.95% | 1 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1828 # delay histogram for all message +system.ruby.delayHist::bucket_size 2 # delay histogram for all message +system.ruby.delayHist::max_bucket 19 # delay histogram for all message +system.ruby.delayHist::samples 1875 # delay histogram for all message +system.ruby.delayHist::mean 0.413867 # delay histogram for all message +system.ruby.delayHist::stdev 1.755437 # delay histogram for all message +system.ruby.delayHist | 1737 92.64% 92.64% | 40 2.13% 94.77% | 28 1.49% 96.27% | 28 1.49% 97.76% | 24 1.28% 99.04% | 9 0.48% 99.52% | 3 0.16% 99.68% | 1 0.05% 99.73% | 3 0.16% 99.89% | 2 0.11% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1875 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 969 -system.ruby.outstanding_req_hist::mean 15.737874 -system.ruby.outstanding_req_hist::gmean 15.630840 -system.ruby.outstanding_req_hist::stdev 1.200645 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.52% | 3 0.31% 0.83% | 2 0.21% 1.03% | 2 0.21% 1.24% | 2 0.21% 1.44% | 119 12.28% 13.73% | 836 86.27% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 969 +system.ruby.outstanding_req_hist::samples 993 +system.ruby.outstanding_req_hist::mean 15.769386 +system.ruby.outstanding_req_hist::gmean 15.669183 +system.ruby.outstanding_req_hist::stdev 1.147486 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 2 0.20% 0.91% | 2 0.20% 1.11% | 2 0.20% 1.31% | 106 10.67% 11.98% | 874 88.02% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 993 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 954 -system.ruby.latency_hist::mean 3683.388889 -system.ruby.latency_hist::gmean 3615.866127 -system.ruby.latency_hist::stdev 578.018149 -system.ruby.latency_hist | 6 0.63% 0.63% | 5 0.52% 1.15% | 97 10.17% 11.32% | 613 64.26% 75.58% | 232 24.32% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 954 +system.ruby.latency_hist::samples 978 +system.ruby.latency_hist::mean 3693.343558 +system.ruby.latency_hist::gmean 3643.123362 +system.ruby.latency_hist::stdev 533.362444 +system.ruby.latency_hist | 4 0.41% 0.41% | 4 0.41% 0.82% | 73 7.46% 8.28% | 689 70.45% 78.73% | 206 21.06% 99.80% | 2 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 978 system.ruby.hit_latency_hist::bucket_size 512 system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 38 -system.ruby.hit_latency_hist::mean 3245.526316 -system.ruby.hit_latency_hist::gmean 3205.871342 -system.ruby.hit_latency_hist::stdev 508.824864 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.63% 2.63% | 2 5.26% 7.89% | 13 34.21% 42.11% | 14 36.84% 78.95% | 5 13.16% 92.11% | 3 7.89% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 38 +system.ruby.hit_latency_hist::samples 39 +system.ruby.hit_latency_hist::mean 3214.641026 +system.ruby.hit_latency_hist::gmean 3186.126692 +system.ruby.hit_latency_hist::stdev 431.722041 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 7.69% 7.69% | 10 25.64% 33.33% | 17 43.59% 76.92% | 8 20.51% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 39 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 916 -system.ruby.miss_latency_hist::mean 3701.553493 -system.ruby.miss_latency_hist::gmean 3633.963773 -system.ruby.miss_latency_hist::stdev 573.775637 -system.ruby.miss_latency_hist | 6 0.66% 0.66% | 4 0.44% 1.09% | 82 8.95% 10.04% | 594 64.85% 74.89% | 229 25.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 916 -system.ruby.Directory.incomplete_times 916 +system.ruby.miss_latency_hist::samples 939 +system.ruby.miss_latency_hist::mean 3713.225772 +system.ruby.miss_latency_hist::gmean 3663.461061 +system.ruby.miss_latency_hist::stdev 528.042705 +system.ruby.miss_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.85% | 60 6.39% 7.24% | 664 70.71% 77.96% | 205 21.83% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 939 +system.ruby.Directory.incomplete_times 939 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 38 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 917 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 955 # Number of cache demand accesses +system.ruby.l1_cntrl0.cacheMemory.demand_hits 39 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 941 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 980 # Number of cache demand accesses system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 10 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 116 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 9 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 112 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 2 # Number of times a load aliased with a pending load -system.ruby.network.routers0.percent_links_utilized 2.061246 -system.ruby.network.routers0.msg_count.Control::2 916 -system.ruby.network.routers0.msg_count.Data::2 914 -system.ruby.network.routers0.msg_count.Response_Data::4 916 -system.ruby.network.routers0.msg_count.Writeback_Control::3 913 -system.ruby.network.routers0.msg_bytes.Control::2 7328 -system.ruby.network.routers0.msg_bytes.Data::2 65808 -system.ruby.network.routers0.msg_bytes.Response_Data::4 65952 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7304 -system.ruby.dir_cntrl0.memBuffer.memReq 1830 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 916 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 914 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 1542 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1745 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 182 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 3 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 1930 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 1.054645 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 343 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 617 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 556 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 62 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 167 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 64 3.50% 3.50% | 60 3.28% 6.78% | 44 2.40% 9.18% | 96 5.25% 14.43% | 107 5.85% 20.27% | 64 3.50% 23.77% | 62 3.39% 27.16% | 38 2.08% 29.23% | 55 3.01% 32.24% | 54 2.95% 35.19% | 54 2.95% 38.14% | 36 1.97% 40.11% | 48 2.62% 42.73% | 34 1.86% 44.59% | 66 3.61% 48.20% | 48 2.62% 50.82% | 56 3.06% 53.88% | 54 2.95% 56.83% | 60 3.28% 60.11% | 70 3.83% 63.93% | 56 3.06% 66.99% | 62 3.39% 70.38% | 44 2.40% 72.79% | 62 3.39% 76.17% | 48 2.62% 78.80% | 58 3.17% 81.97% | 64 3.50% 85.46% | 72 3.93% 89.40% | 46 2.51% 91.91% | 46 2.51% 94.43% | 36 1.97% 96.39% | 66 3.61% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1830 # Number of accesses per bank -system.ruby.network.routers1.percent_links_utilized 2.061246 -system.ruby.network.routers1.msg_count.Control::2 916 -system.ruby.network.routers1.msg_count.Data::2 914 -system.ruby.network.routers1.msg_count.Response_Data::4 916 -system.ruby.network.routers1.msg_count.Writeback_Control::3 913 -system.ruby.network.routers1.msg_bytes.Control::2 7328 -system.ruby.network.routers1.msg_bytes.Data::2 65808 -system.ruby.network.routers1.msg_bytes.Response_Data::4 65952 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7304 -system.ruby.network.routers2.percent_links_utilized 2.061246 -system.ruby.network.routers2.msg_count.Control::2 916 -system.ruby.network.routers2.msg_count.Data::2 914 -system.ruby.network.routers2.msg_count.Response_Data::4 916 -system.ruby.network.routers2.msg_count.Writeback_Control::3 913 -system.ruby.network.routers2.msg_bytes.Control::2 7328 -system.ruby.network.routers2.msg_bytes.Data::2 65808 -system.ruby.network.routers2.msg_bytes.Response_Data::4 65952 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7304 -system.ruby.network.msg_count.Control 2748 -system.ruby.network.msg_count.Data 2742 -system.ruby.network.msg_count.Response_Data 2748 -system.ruby.network.msg_count.Writeback_Control 2739 -system.ruby.network.msg_byte.Control 21984 -system.ruby.network.msg_byte.Data 197424 -system.ruby.network.msg_byte.Response_Data 197856 -system.ruby.network.msg_byte.Writeback_Control 21912 -system.ruby.network.routers0.throttle0.link_utilization 2.062936 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 916 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 913 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 65952 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7304 -system.ruby.network.routers0.throttle1.link_utilization 2.059556 -system.ruby.network.routers0.throttle1.msg_count.Control::2 916 -system.ruby.network.routers0.throttle1.msg_count.Data::2 914 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7328 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 65808 -system.ruby.network.routers1.throttle0.link_utilization 2.059556 -system.ruby.network.routers1.throttle0.msg_count.Control::2 916 -system.ruby.network.routers1.throttle0.msg_count.Data::2 914 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7328 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 65808 -system.ruby.network.routers1.throttle1.link_utilization 2.062936 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 916 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 913 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 65952 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7304 -system.ruby.network.routers2.throttle0.link_utilization 2.062936 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 916 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 913 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 65952 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7304 -system.ruby.network.routers2.throttle1.link_utilization 2.059556 -system.ruby.network.routers2.throttle1.msg_count.Control::2 916 -system.ruby.network.routers2.throttle1.msg_count.Data::2 914 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7328 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 65808 +system.ruby.network.routers0.percent_links_utilized 2.055583 +system.ruby.network.routers0.msg_count.Control::2 939 +system.ruby.network.routers0.msg_count.Data::2 936 +system.ruby.network.routers0.msg_count.Response_Data::4 939 +system.ruby.network.routers0.msg_count.Writeback_Control::3 936 +system.ruby.network.routers0.msg_bytes.Control::2 7512 +system.ruby.network.routers0.msg_bytes.Data::2 67392 +system.ruby.network.routers0.msg_bytes.Response_Data::4 67608 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7488 +system.ruby.dir_cntrl0.memBuffer.memReq 1875 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 939 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 936 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 1584 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1797 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 156 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 18 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 1971 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 1.051200 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 297 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 648 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 605 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 60 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 187 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 59 3.15% 3.15% | 68 3.63% 6.77% | 62 3.31% 10.08% | 78 4.16% 14.24% | 119 6.35% 20.59% | 54 2.88% 23.47% | 61 3.25% 26.72% | 54 2.88% 29.60% | 40 2.13% 31.73% | 64 3.41% 35.15% | 46 2.45% 37.60% | 60 3.20% 40.80% | 54 2.88% 43.68% | 68 3.63% 47.31% | 52 2.77% 50.08% | 44 2.35% 52.43% | 50 2.67% 55.09% | 42 2.24% 57.33% | 44 2.35% 59.68% | 64 3.41% 63.09% | 64 3.41% 66.51% | 44 2.35% 68.85% | 64 3.41% 72.27% | 52 2.77% 75.04% | 62 3.31% 78.35% | 58 3.09% 81.44% | 60 3.20% 84.64% | 56 2.99% 87.63% | 52 2.77% 90.40% | 64 3.41% 93.81% | 52 2.77% 96.59% | 64 3.41% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1875 # Number of accesses per bank +system.ruby.network.routers1.percent_links_utilized 2.055912 +system.ruby.network.routers1.msg_count.Control::2 939 +system.ruby.network.routers1.msg_count.Data::2 936 +system.ruby.network.routers1.msg_count.Response_Data::4 939 +system.ruby.network.routers1.msg_count.Writeback_Control::3 936 +system.ruby.network.routers1.msg_bytes.Control::2 7512 +system.ruby.network.routers1.msg_bytes.Data::2 67392 +system.ruby.network.routers1.msg_bytes.Response_Data::4 67608 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7488 +system.ruby.network.routers2.percent_links_utilized 2.055912 +system.ruby.network.routers2.msg_count.Control::2 939 +system.ruby.network.routers2.msg_count.Data::2 936 +system.ruby.network.routers2.msg_count.Response_Data::4 939 +system.ruby.network.routers2.msg_count.Writeback_Control::3 936 +system.ruby.network.routers2.msg_bytes.Control::2 7512 +system.ruby.network.routers2.msg_bytes.Data::2 67392 +system.ruby.network.routers2.msg_bytes.Response_Data::4 67608 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7488 +system.ruby.network.msg_count.Control 2817 +system.ruby.network.msg_count.Data 2808 +system.ruby.network.msg_count.Response_Data 2817 +system.ruby.network.msg_count.Writeback_Control 2808 +system.ruby.network.msg_byte.Control 22536 +system.ruby.network.msg_byte.Data 202176 +system.ruby.network.msg_byte.Response_Data 202824 +system.ruby.network.msg_byte.Writeback_Control 22464 +system.ruby.network.routers0.throttle0.link_utilization 2.057886 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 939 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 936 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 67608 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7488 +system.ruby.network.routers0.throttle1.link_utilization 2.053280 +system.ruby.network.routers0.throttle1.msg_count.Control::2 939 +system.ruby.network.routers0.throttle1.msg_count.Data::2 936 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7512 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 67392 +system.ruby.network.routers1.throttle0.link_utilization 2.053280 +system.ruby.network.routers1.throttle0.msg_count.Control::2 939 +system.ruby.network.routers1.throttle0.msg_count.Data::2 936 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7512 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 67392 +system.ruby.network.routers1.throttle1.link_utilization 2.058544 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 939 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 936 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 67608 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7488 +system.ruby.network.routers2.throttle0.link_utilization 2.058544 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 939 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 936 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 67608 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7488 +system.ruby.network.routers2.throttle1.link_utilization 2.053280 +system.ruby.network.routers2.throttle1.msg_count.Control::2 939 +system.ruby.network.routers2.throttle1.msg_count.Data::2 936 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7512 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 67392 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 916 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.530568 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 1.830567 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 824 89.96% 89.96% | 19 2.07% 92.03% | 30 3.28% 95.31% | 28 3.06% 98.36% | 3 0.33% 98.69% | 6 0.66% 99.34% | 4 0.44% 99.78% | 2 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 916 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 4 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 39 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 912 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.589912 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 2.277805 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 847 92.87% 92.87% | 31 3.40% 96.27% | 24 2.63% 98.90% | 5 0.55% 99.45% | 4 0.44% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 912 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_1::samples 939 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.470714 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 1.775198 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 854 90.95% 90.95% | 28 2.98% 93.93% | 18 1.92% 95.85% | 17 1.81% 97.66% | 12 1.28% 98.94% | 5 0.53% 99.47% | 3 0.32% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 939 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 2 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 19 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 936 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.356838 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 1.734462 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 883 94.34% 94.34% | 12 1.28% 95.62% | 10 1.07% 96.69% | 11 1.18% 97.86% | 12 1.28% 99.15% | 4 0.43% 99.57% | 0 0.00% 99.57% | 0 0.00% 99.57% | 2 0.21% 99.79% | 2 0.21% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 936 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 42 -system.ruby.LD.latency_hist::mean 3722.095238 -system.ruby.LD.latency_hist::gmean 3693.389751 -system.ruby.LD.latency_hist::stdev 463.961143 -system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 11.90% 11.90% | 11 26.19% 38.10% | 18 42.86% 80.95% | 8 19.05% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 42 +system.ruby.LD.latency_hist::samples 50 +system.ruby.LD.latency_hist::mean 3717.400000 +system.ruby.LD.latency_hist::gmean 3691.585103 +system.ruby.LD.latency_hist::stdev 435.779386 +system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 4.00% 4.00% | 18 36.00% 40.00% | 20 40.00% 80.00% | 10 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 50 +system.ruby.LD.hit_latency_hist::bucket_size 512 +system.ruby.LD.hit_latency_hist::max_bucket 5119 +system.ruby.LD.hit_latency_hist::samples 2 +system.ruby.LD.hit_latency_hist::mean 2856 +system.ruby.LD.hit_latency_hist::gmean 2844.049050 +system.ruby.LD.hit_latency_hist::stdev 369.109740 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 2 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 42 -system.ruby.LD.miss_latency_hist::mean 3722.095238 -system.ruby.LD.miss_latency_hist::gmean 3693.389751 -system.ruby.LD.miss_latency_hist::stdev 463.961143 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 11.90% 11.90% | 11 26.19% 38.10% | 18 42.86% 80.95% | 8 19.05% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 42 +system.ruby.LD.miss_latency_hist::samples 48 +system.ruby.LD.miss_latency_hist::mean 3753.291667 +system.ruby.LD.miss_latency_hist::gmean 3731.923305 +system.ruby.LD.miss_latency_hist::stdev 402.734903 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.08% 2.08% | 17 35.42% 37.50% | 20 41.67% 79.17% | 10 20.83% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 48 system.ruby.ST.latency_hist::bucket_size 1024 system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 854 -system.ruby.ST.latency_hist::mean 3677.291569 -system.ruby.ST.latency_hist::gmean 3606.100027 -system.ruby.ST.latency_hist::stdev 585.222193 -system.ruby.ST.latency_hist | 6 0.70% 0.70% | 5 0.59% 1.29% | 85 9.95% 11.24% | 549 64.29% 75.53% | 208 24.36% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 854 +system.ruby.ST.latency_hist::samples 878 +system.ruby.ST.latency_hist::mean 3684.186788 +system.ruby.ST.latency_hist::gmean 3631.018183 +system.ruby.ST.latency_hist::stdev 544.872418 +system.ruby.ST.latency_hist | 4 0.46% 0.46% | 4 0.46% 0.91% | 70 7.97% 8.88% | 611 69.59% 78.47% | 188 21.41% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 878 system.ruby.ST.hit_latency_hist::bucket_size 512 system.ruby.ST.hit_latency_hist::max_bucket 5119 system.ruby.ST.hit_latency_hist::samples 36 -system.ruby.ST.hit_latency_hist::mean 3241 -system.ruby.ST.hit_latency_hist::gmean 3199.557019 -system.ruby.ST.hit_latency_hist::stdev 520.842724 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.78% 2.78% | 2 5.56% 8.33% | 13 36.11% 44.44% | 12 33.33% 77.78% | 5 13.89% 91.67% | 3 8.33% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::mean 3222.750000 +system.ruby.ST.hit_latency_hist::gmean 3194.454829 +system.ruby.ST.hit_latency_hist::stdev 431.138120 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 8.33% 8.33% | 9 25.00% 33.33% | 16 44.44% 77.78% | 7 19.44% 97.22% | 1 2.78% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 36 system.ruby.ST.miss_latency_hist::bucket_size 1024 system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 818 -system.ruby.ST.miss_latency_hist::mean 3696.492665 -system.ruby.ST.miss_latency_hist::gmean 3625.133340 -system.ruby.ST.miss_latency_hist::stdev 580.687585 -system.ruby.ST.miss_latency_hist | 6 0.73% 0.73% | 4 0.49% 1.22% | 70 8.56% 9.78% | 532 65.04% 74.82% | 205 25.06% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 818 -system.ruby.IFETCH.latency_hist::bucket_size 512 -system.ruby.IFETCH.latency_hist::max_bucket 5119 -system.ruby.IFETCH.latency_hist::samples 58 -system.ruby.IFETCH.latency_hist::mean 3745.137931 -system.ruby.IFETCH.latency_hist::gmean 3705.404222 -system.ruby.IFETCH.latency_hist::stdev 548.056325 -system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 12.07% 12.07% | 17 29.31% 41.38% | 18 31.03% 72.41% | 14 24.14% 96.55% | 2 3.45% 100.00% -system.ruby.IFETCH.latency_hist::total 58 +system.ruby.ST.miss_latency_hist::samples 842 +system.ruby.ST.miss_latency_hist::mean 3703.915677 +system.ruby.ST.miss_latency_hist::gmean 3650.959161 +system.ruby.ST.miss_latency_hist::stdev 540.698215 +system.ruby.ST.miss_latency_hist | 4 0.48% 0.48% | 4 0.48% 0.95% | 58 6.89% 7.84% | 588 69.83% 77.67% | 187 22.21% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 842 +system.ruby.IFETCH.latency_hist::bucket_size 1024 +system.ruby.IFETCH.latency_hist::max_bucket 10239 +system.ruby.IFETCH.latency_hist::samples 50 +system.ruby.IFETCH.latency_hist::mean 3830.080000 +system.ruby.IFETCH.latency_hist::gmean 3811.685277 +system.ruby.IFETCH.latency_hist::stdev 383.882042 +system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.00% 2.00% | 40 80.00% 82.00% | 8 16.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 50 system.ruby.IFETCH.hit_latency_hist::bucket_size 512 system.ruby.IFETCH.hit_latency_hist::max_bucket 5119 -system.ruby.IFETCH.hit_latency_hist::samples 2 -system.ruby.IFETCH.hit_latency_hist::mean 3327 -system.ruby.IFETCH.hit_latency_hist::gmean 3321.684061 -system.ruby.IFETCH.hit_latency_hist::stdev 265.872150 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2 -system.ruby.IFETCH.miss_latency_hist::bucket_size 512 -system.ruby.IFETCH.miss_latency_hist::max_bucket 5119 -system.ruby.IFETCH.miss_latency_hist::samples 56 -system.ruby.IFETCH.miss_latency_hist::mean 3760.071429 -system.ruby.IFETCH.miss_latency_hist::gmean 3719.899517 -system.ruby.IFETCH.miss_latency_hist::stdev 550.833942 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 12.50% 12.50% | 15 26.79% 39.29% | 18 32.14% 71.43% | 14 25.00% 96.43% | 2 3.57% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 56 +system.ruby.IFETCH.hit_latency_hist::samples 1 +system.ruby.IFETCH.hit_latency_hist::mean 3640 +system.ruby.IFETCH.hit_latency_hist::gmean 3640.000000 +system.ruby.IFETCH.hit_latency_hist::stdev nan +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 1 +system.ruby.IFETCH.miss_latency_hist::bucket_size 1024 +system.ruby.IFETCH.miss_latency_hist::max_bucket 10239 +system.ruby.IFETCH.miss_latency_hist::samples 49 +system.ruby.IFETCH.miss_latency_hist::mean 3833.959184 +system.ruby.IFETCH.miss_latency_hist::gmean 3815.272105 +system.ruby.IFETCH.miss_latency_hist::stdev 386.868785 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.04% 2.04% | 39 79.59% 81.63% | 8 16.33% 97.96% | 1 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 49 system.ruby.Directory.miss_mach_latency_hist::bucket_size 1024 system.ruby.Directory.miss_mach_latency_hist::max_bucket 10239 -system.ruby.Directory.miss_mach_latency_hist::samples 916 -system.ruby.Directory.miss_mach_latency_hist::mean 3701.553493 -system.ruby.Directory.miss_mach_latency_hist::gmean 3633.963773 -system.ruby.Directory.miss_mach_latency_hist::stdev 573.775637 -system.ruby.Directory.miss_mach_latency_hist | 6 0.66% 0.66% | 4 0.44% 1.09% | 82 8.95% 10.04% | 594 64.85% 74.89% | 229 25.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 916 +system.ruby.Directory.miss_mach_latency_hist::samples 939 +system.ruby.Directory.miss_mach_latency_hist::mean 3713.225772 +system.ruby.Directory.miss_mach_latency_hist::gmean 3663.461061 +system.ruby.Directory.miss_mach_latency_hist::stdev 528.042705 +system.ruby.Directory.miss_mach_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.85% | 60 6.39% 7.24% | 664 70.71% 77.96% | 205 21.83% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 939 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 42 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 3722.095238 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 3693.389751 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 463.961143 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 11.90% 11.90% | 11 26.19% 38.10% | 18 42.86% 80.95% | 8 19.05% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 42 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 48 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 3753.291667 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 3731.923305 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 402.734903 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.08% 2.08% | 17 35.42% 37.50% | 20 41.67% 79.17% | 10 20.83% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 48 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 1024 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 10239 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 818 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3696.492665 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 3625.133340 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 580.687585 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 6 0.73% 0.73% | 4 0.49% 1.22% | 70 8.56% 9.78% | 532 65.04% 74.82% | 205 25.06% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 818 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 512 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 56 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 3760.071429 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 3719.899517 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 550.833942 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 12.50% 12.50% | 15 26.79% 39.29% | 18 32.14% 71.43% | 14 25.00% 96.43% | 2 3.57% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 56 -system.ruby.L1Cache_Controller.Load 42 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 58 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 855 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 916 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 914 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 912 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 42 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 56 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 819 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 842 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3703.915677 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 3650.959161 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 540.698215 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 4 0.48% 0.48% | 4 0.48% 0.95% | 58 6.89% 7.84% | 588 69.83% 77.67% | 187 22.21% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 842 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 1024 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 10239 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 49 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 3833.959184 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 3815.272105 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 386.868785 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.04% 2.04% | 39 79.59% 81.63% | 8 16.33% 97.96% | 1 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 49 +system.ruby.L1Cache_Controller.Load 50 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 50 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 880 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 939 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 938 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 936 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 48 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 49 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 844 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 2 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 36 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 914 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 912 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 98 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 818 0.00% 0.00% -system.ruby.Directory_Controller.GETX 916 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 914 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 916 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 914 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 916 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 914 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 916 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 914 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 938 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 936 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 97 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 842 0.00% 0.00% +system.ruby.Directory_Controller.GETX 939 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 936 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 939 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 936 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 939 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 936 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 939 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 936 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index bc520582f..779d261ee 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,99 +4,99 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 14337554787 # Simulator tick rate (ticks/s) -host_mem_usage 228672 # Number of bytes of host memory used -host_seconds 6.97 # Real time elapsed on the host +host_tick_rate 10849136429 # Simulator tick rate (ticks/s) +host_mem_usage 200176 # Number of bytes of host memory used +host_seconds 9.22 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu 106798016 # Number of bytes read from this memory -system.physmem.bytes_read::total 106798016 # Number of bytes read from this memory -system.physmem.bytes_written::cpu 106535680 # Number of bytes written to this memory -system.physmem.bytes_written::total 106535680 # Number of bytes written to this memory -system.physmem.num_reads::cpu 1668719 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1668719 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu 1664620 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1664620 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu 1067980160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1067980160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu 1065356800 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1065356800 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu 2133336960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2133336960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1668720 # Number of read requests accepted -system.physmem.writeReqs 1664620 # Number of write requests accepted -system.physmem.readBursts 1668720 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1664620 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 106797184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 896 # Total number of bytes read from write queue -system.physmem.bytesWritten 106533952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 106798080 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 106535680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 14 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 8 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory +system.physmem.bytes_read::total 106649408 # Number of bytes read from this memory +system.physmem.bytes_written::cpu 106680256 # Number of bytes written to this memory +system.physmem.bytes_written::total 106680256 # Number of bytes written to this memory +system.physmem.num_reads::cpu 1666397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1666397 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu 1666879 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1666879 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu 1066494080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1066494080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu 1066802560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1066802560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu 2133296640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2133296640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1666397 # Number of read requests accepted +system.physmem.writeReqs 1666879 # Number of write requests accepted +system.physmem.readBursts 1666397 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1666879 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 106647616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1792 # Total number of bytes read from write queue +system.physmem.bytesWritten 106676608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 106649408 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 106680256 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 28 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 104195 # Per bank write bursts -system.physmem.perBankRdBursts::1 104188 # Per bank write bursts -system.physmem.perBankRdBursts::2 104541 # Per bank write bursts -system.physmem.perBankRdBursts::3 104589 # Per bank write bursts -system.physmem.perBankRdBursts::4 103994 # Per bank write bursts -system.physmem.perBankRdBursts::5 104203 # Per bank write bursts -system.physmem.perBankRdBursts::6 104803 # Per bank write bursts -system.physmem.perBankRdBursts::7 104557 # Per bank write bursts -system.physmem.perBankRdBursts::8 104630 # Per bank write bursts -system.physmem.perBankRdBursts::9 104040 # Per bank write bursts -system.physmem.perBankRdBursts::10 104372 # Per bank write bursts -system.physmem.perBankRdBursts::11 104177 # Per bank write bursts -system.physmem.perBankRdBursts::12 103805 # Per bank write bursts -system.physmem.perBankRdBursts::13 104138 # Per bank write bursts -system.physmem.perBankRdBursts::14 103922 # Per bank write bursts -system.physmem.perBankRdBursts::15 104552 # Per bank write bursts -system.physmem.perBankWrBursts::0 103587 # Per bank write bursts -system.physmem.perBankWrBursts::1 104082 # Per bank write bursts -system.physmem.perBankWrBursts::2 103950 # Per bank write bursts -system.physmem.perBankWrBursts::3 104334 # Per bank write bursts -system.physmem.perBankWrBursts::4 104264 # Per bank write bursts -system.physmem.perBankWrBursts::5 104509 # Per bank write bursts -system.physmem.perBankWrBursts::6 103927 # Per bank write bursts -system.physmem.perBankWrBursts::7 104060 # Per bank write bursts -system.physmem.perBankWrBursts::8 104076 # Per bank write bursts -system.physmem.perBankWrBursts::9 104072 # Per bank write bursts -system.physmem.perBankWrBursts::10 104151 # Per bank write bursts -system.physmem.perBankWrBursts::11 104328 # Per bank write bursts -system.physmem.perBankWrBursts::12 103712 # Per bank write bursts -system.physmem.perBankWrBursts::13 103871 # Per bank write bursts -system.physmem.perBankWrBursts::14 103773 # Per bank write bursts -system.physmem.perBankWrBursts::15 103897 # Per bank write bursts +system.physmem.perBankRdBursts::0 104030 # Per bank write bursts +system.physmem.perBankRdBursts::1 103995 # Per bank write bursts +system.physmem.perBankRdBursts::2 104918 # Per bank write bursts +system.physmem.perBankRdBursts::3 104597 # Per bank write bursts +system.physmem.perBankRdBursts::4 103868 # Per bank write bursts +system.physmem.perBankRdBursts::5 103934 # Per bank write bursts +system.physmem.perBankRdBursts::6 103649 # Per bank write bursts +system.physmem.perBankRdBursts::7 104312 # Per bank write bursts +system.physmem.perBankRdBursts::8 103869 # Per bank write bursts +system.physmem.perBankRdBursts::9 104353 # Per bank write bursts +system.physmem.perBankRdBursts::10 103834 # Per bank write bursts +system.physmem.perBankRdBursts::11 104272 # Per bank write bursts +system.physmem.perBankRdBursts::12 104075 # Per bank write bursts +system.physmem.perBankRdBursts::13 104034 # Per bank write bursts +system.physmem.perBankRdBursts::14 104583 # Per bank write bursts +system.physmem.perBankRdBursts::15 104046 # Per bank write bursts +system.physmem.perBankWrBursts::0 104355 # Per bank write bursts +system.physmem.perBankWrBursts::1 104090 # Per bank write bursts +system.physmem.perBankWrBursts::2 104175 # Per bank write bursts +system.physmem.perBankWrBursts::3 103885 # Per bank write bursts +system.physmem.perBankWrBursts::4 104730 # Per bank write bursts +system.physmem.perBankWrBursts::5 104507 # Per bank write bursts +system.physmem.perBankWrBursts::6 104082 # Per bank write bursts +system.physmem.perBankWrBursts::7 104224 # Per bank write bursts +system.physmem.perBankWrBursts::8 104318 # Per bank write bursts +system.physmem.perBankWrBursts::9 104219 # Per bank write bursts +system.physmem.perBankWrBursts::10 104228 # Per bank write bursts +system.physmem.perBankWrBursts::11 103701 # Per bank write bursts +system.physmem.perBankWrBursts::12 104103 # Per bank write bursts +system.physmem.perBankWrBursts::13 103984 # Per bank write bursts +system.physmem.perBankWrBursts::14 104297 # Per bank write bursts +system.physmem.perBankWrBursts::15 103924 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 99999960227 # Total gap between requests +system.physmem.totGap 99999956143 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1668720 # Read request sizes (log2) +system.physmem.readPktSize::6 1666397 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1664620 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 766507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 779035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 72986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1666879 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 765065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 778270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 73012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -131,33 +131,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 21583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 101142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 110031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 109380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 103714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 100305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 100049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 122199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 111635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 105240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 100495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 98624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 98614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 98524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 98476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 98391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 101252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 110536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 109573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 103779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 100515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 100211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 122657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 111795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 105251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 100593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 98735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 98627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 98577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 98503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -180,12 +180,12 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3296563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 64.713043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 64.189923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 23.988602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3288788 99.76% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5620 0.17% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 3296334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.715403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.191581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 23.992085 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3288433 99.76% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5746 0.17% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 32 0.00% 99.94% # Bytes accessed per row activation @@ -193,76 +193,76 @@ system.physmem.bytesPerActivate::640-767 32 0.00% 99.94% # By system.physmem.bytesPerActivate::768-895 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 1963 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3296563 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97746 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.071819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 15.727304 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.831001 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 97745 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 3296334 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97889 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.022975 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 15.667690 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.738588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 97888 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97746 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97746 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.029781 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.939241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.836351 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73134 74.82% 74.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 545 0.56% 75.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 655 0.67% 76.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1612 1.65% 77.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16208 16.58% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5168 5.29% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 147 0.15% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 85 0.09% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 66 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 49 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 29 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 26 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 16 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97746 # Writes before turning the bus around for reads -system.physmem.totQLat 58049969454 # Total ticks spent queuing -system.physmem.totMemAccLat 89338206954 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8343530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34787.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 97889 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.027674 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.937663 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.829790 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73237 74.82% 74.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 524 0.54% 75.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 736 0.75% 76.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1545 1.58% 77.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16291 16.64% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5161 5.27% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 155 0.16% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 78 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 59 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 41 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 31 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 13 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97889 # Writes before turning the bus around for reads +system.physmem.totQLat 57937365003 # Total ticks spent queuing +system.physmem.totMemAccLat 89181783753 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8331845000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34768.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53537.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1067.97 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1065.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1067.98 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1065.36 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53518.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1066.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1066.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1066.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1066.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 16.67 # Data bus utilization in percentage -system.physmem.busUtilRead 8.34 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 8.32 # Data bus utilization in percentage for writes +system.physmem.busUtilRead 8.33 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 8.33 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing -system.physmem.readRowHits 32203 # Number of row buffer hits during reads -system.physmem.writeRowHits 4525 # Number of row buffer hits during writes +system.physmem.readRowHits 32168 # Number of row buffer hits during reads +system.physmem.writeRowHits 4679 # Number of row buffer hits during writes system.physmem.readRowHitRate 1.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 0.27 # Row buffer hit rate for writes -system.physmem.avgGap 29999.93 # Average gap between requests -system.physmem.pageHitRate 1.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 5508849 # Time in different power states +system.physmem.writeRowHitRate 0.28 # Row buffer hit rate for writes +system.physmem.avgGap 30000.50 # Average gap between requests +system.physmem.pageHitRate 1.11 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 5459951 # Time in different power states system.physmem.memoryStateTime::REF 3339180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 96654451752 # Time in different power states +system.physmem.memoryStateTime::ACT 96654442549 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2133336960 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1668720 # Transaction distribution -system.membus.trans_dist::ReadResp 1668719 # Transaction distribution -system.membus.trans_dist::WriteReq 1664620 # Transaction distribution -system.membus.trans_dist::WriteResp 1664620 # Transaction distribution -system.membus.pkt_count_system.monitor-master::system.physmem.port 6666679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6666679 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 213333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 213333696 # Total data (bytes) -system.membus.reqLayer0.occupancy 11669983278 # Layer occupancy (ticks) +system.membus.throughput 2133296640 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1666397 # Transaction distribution +system.membus.trans_dist::ReadResp 1666397 # Transaction distribution +system.membus.trans_dist::WriteReq 1666879 # Transaction distribution +system.membus.trans_dist::WriteResp 1666879 # Transaction distribution +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666552 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 213329664 # Total data (bytes) +system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11409038076 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11400175366 # Layer occupancy (ticks) system.membus.respLayer0.utilization 11.4 # Layer utilization (%) -system.monitor.readBurstLengthHist::samples 1668720 # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets @@ -282,12 +282,12 @@ system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00% # H system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets -system.monitor.readBurstLengthHist::64-67 1668720 100.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::64-67 1666397 100.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets -system.monitor.readBurstLengthHist::total 1668720 # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::samples 1664620 # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::total 1666397 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::samples 1666879 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets @@ -307,15 +307,15 @@ system.monitor.writeBurstLengthHist::48-51 0 0.00% 0.00% # system.monitor.writeBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::64-67 1664620 100.00% 100.00% # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::64-67 1666879 100.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets -system.monitor.writeBurstLengthHist::total 1664620 # Histogram of burst lengths of transmitted packets +system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::mean 1067980160 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1064651766.271052 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107759819.009425 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154518.573643 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107916008.948195 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -337,12 +337,12 @@ system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09 0 0.00% system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.averageReadBandwidth 1067980160 0.00% 0.00% # Average read bandwidth (bytes/s) -system.monitor.totalReadBytes 106798016 # Number of bytes read +system.monitor.averageReadBandwidth 1066494080 0.00% 0.00% # Average read bandwidth (bytes/s) +system.monitor.totalReadBytes 106649408 # Number of bytes read system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::mean 1065356800 # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::mean 1066802560 # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::gmean 0 # Histogram of write bandwidth (bytes/s) -system.monitor.writeBandwidthHist::stdev 107770982.104450 # Histogram of write bandwidth (bytes/s) +system.monitor.writeBandwidthHist::stdev 107924720.268046 # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::0-6.71089e+07 1 1.00% 1.00% # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::6.71089e+07-1.34218e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::1.34218e+08-2.01327e+08 0 0.00% 1.00% # Histogram of write bandwidth (bytes/s) @@ -364,37 +364,37 @@ system.monitor.writeBandwidthHist::1.14085e+09-1.20796e+09 0 0.0 system.monitor.writeBandwidthHist::1.20796e+09-1.27507e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::1.27507e+09-1.34218e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s) system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s) -system.monitor.averageWriteBandwidth 1065356800 0.00% 0.00% # Average write bandwidth (bytes/s) -system.monitor.totalWrittenBytes 106535680 # Number of bytes written -system.monitor.readLatencyHist::samples 1668719 # Read request-response latency -system.monitor.readLatencyHist::mean 73576.537902 # Read request-response latency -system.monitor.readLatencyHist::gmean 68507.812375 # Read request-response latency -system.monitor.readLatencyHist::stdev 39270.153648 # Read request-response latency -system.monitor.readLatencyHist::0-32767 14 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 454232 27.22% 27.22% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1043171 62.51% 89.73% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 73085 4.38% 94.11% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 46931 2.81% 96.93% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 12458 0.75% 97.67% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 7854 0.47% 98.14% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7990 0.48% 98.62% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 8124 0.49% 99.11% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7849 0.47% 99.58% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 4246 0.25% 99.83% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1108 0.07% 99.90% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 866 0.05% 99.95% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 601 0.04% 99.99% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 183 0.01% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 7 0.00% 100.00% # Read request-response latency +system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) +system.monitor.totalWrittenBytes 106680256 # Number of bytes written +system.monitor.readLatencyHist::samples 1666397 # Read request-response latency +system.monitor.readLatencyHist::mean 73557.268741 # Read request-response latency +system.monitor.readLatencyHist::gmean 68501.179139 # Read request-response latency +system.monitor.readLatencyHist::stdev 39156.791762 # Read request-response latency +system.monitor.readLatencyHist::0-32767 28 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 454399 27.27% 27.27% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1040506 62.44% 89.71% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 73250 4.40% 94.11% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 47036 2.82% 96.93% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 12641 0.76% 97.69% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 7802 0.47% 98.16% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7940 0.48% 98.63% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 8093 0.49% 99.12% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7856 0.47% 99.59% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 4214 0.25% 99.84% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1043 0.06% 99.90% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 827 0.05% 99.95% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 590 0.04% 99.99% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 166 0.01% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 6 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::524288-557055 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::total 1668719 # Read request-response latency -system.monitor.writeLatencyHist::samples 1664620 # Write request-response latency -system.monitor.writeLatencyHist::mean 10570.968616 # Write request-response latency -system.monitor.writeLatencyHist::gmean 10511.906115 # Write request-response latency -system.monitor.writeLatencyHist::stdev 1198.829619 # Write request-response latency +system.monitor.readLatencyHist::total 1666397 # Read request-response latency +system.monitor.writeLatencyHist::samples 1666879 # Write request-response latency +system.monitor.writeLatencyHist::mean 10569.121768 # Write request-response latency +system.monitor.writeLatencyHist::gmean 10510.211461 # Write request-response latency +system.monitor.writeLatencyHist::stdev 1197.318213 # Write request-response latency system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency @@ -404,91 +404,91 @@ system.monitor.writeLatencyHist::5120-6143 0 0.00% 0.00% # system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::9216-10239 1266039 76.06% 76.06% # Write request-response latency -system.monitor.writeLatencyHist::10240-11263 92649 5.57% 81.62% # Write request-response latency -system.monitor.writeLatencyHist::11264-12287 113174 6.80% 88.42% # Write request-response latency -system.monitor.writeLatencyHist::12288-13311 92637 5.57% 93.99% # Write request-response latency -system.monitor.writeLatencyHist::13312-14335 63204 3.80% 97.78% # Write request-response latency -system.monitor.writeLatencyHist::14336-15359 32757 1.97% 99.75% # Write request-response latency -system.monitor.writeLatencyHist::15360-16383 4158 0.25% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::16384-17407 2 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::9216-10239 1268910 76.12% 76.12% # Write request-response latency +system.monitor.writeLatencyHist::10240-11263 92420 5.54% 81.67% # Write request-response latency +system.monitor.writeLatencyHist::11264-12287 113112 6.79% 88.46% # Write request-response latency +system.monitor.writeLatencyHist::12288-13311 92715 5.56% 94.02% # Write request-response latency +system.monitor.writeLatencyHist::13312-14335 62904 3.77% 97.79% # Write request-response latency +system.monitor.writeLatencyHist::14336-15359 32645 1.96% 99.75% # Write request-response latency +system.monitor.writeLatencyHist::15360-16383 4173 0.25% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::16384-17407 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::19456-20479 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::total 1664620 # Write request-response latency -system.monitor.ittReadRead::samples 1668719 # Read-to-read inter transaction time -system.monitor.ittReadRead::mean 59926.183034 # Read-to-read inter transaction time -system.monitor.ittReadRead::stdev 42757.593151 # Read-to-read inter transaction time +system.monitor.writeLatencyHist::total 1666879 # Write request-response latency +system.monitor.ittReadRead::samples 1666396 # Read-to-read inter transaction time +system.monitor.ittReadRead::mean 60009.683149 # Read-to-read inter transaction time +system.monitor.ittReadRead::stdev 42949.620471 # Read-to-read inter transaction time system.monitor.ittReadRead::underflows 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::1-5000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::5001-10000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::10001-15000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::15001-20000 0 0.00% 0.00% # Read-to-read inter transaction time system.monitor.ittReadRead::20001-25000 0 0.00% 0.00% # Read-to-read inter transaction time -system.monitor.ittReadRead::25001-30000 438300 26.27% 26.27% # Read-to-read inter transaction time -system.monitor.ittReadRead::30001-35000 404751 24.26% 50.52% # Read-to-read inter transaction time -system.monitor.ittReadRead::35001-40000 3 0.00% 50.52% # Read-to-read inter transaction time -system.monitor.ittReadRead::40001-45000 3 0.00% 50.52% # Read-to-read inter transaction time -system.monitor.ittReadRead::45001-50000 0 0.00% 50.52% # Read-to-read inter transaction time -system.monitor.ittReadRead::50001-55000 3 0.00% 50.52% # Read-to-read inter transaction time -system.monitor.ittReadRead::55001-60000 204975 12.28% 62.80% # Read-to-read inter transaction time -system.monitor.ittReadRead::60001-65000 204546 12.26% 75.06% # Read-to-read inter transaction time -system.monitor.ittReadRead::65001-70000 3 0.00% 75.06% # Read-to-read inter transaction time -system.monitor.ittReadRead::70001-75000 3 0.00% 75.06% # Read-to-read inter transaction time -system.monitor.ittReadRead::75001-80000 2 0.00% 75.06% # Read-to-read inter transaction time -system.monitor.ittReadRead::80001-85000 527 0.03% 75.09% # Read-to-read inter transaction time -system.monitor.ittReadRead::85001-90000 102490 6.14% 81.24% # Read-to-read inter transaction time -system.monitor.ittReadRead::90001-95000 102495 6.14% 87.38% # Read-to-read inter transaction time -system.monitor.ittReadRead::95001-100000 551 0.03% 87.41% # Read-to-read inter transaction time -system.monitor.ittReadRead::overflows 210067 12.59% 100.00% # Read-to-read inter transaction time +system.monitor.ittReadRead::25001-30000 438119 26.29% 26.29% # Read-to-read inter transaction time +system.monitor.ittReadRead::30001-35000 404012 24.24% 50.54% # Read-to-read inter transaction time +system.monitor.ittReadRead::35001-40000 1 0.00% 50.54% # Read-to-read inter transaction time +system.monitor.ittReadRead::40001-45000 3 0.00% 50.54% # Read-to-read inter transaction time +system.monitor.ittReadRead::45001-50000 3 0.00% 50.54% # Read-to-read inter transaction time +system.monitor.ittReadRead::50001-55000 4 0.00% 50.54% # Read-to-read inter transaction time +system.monitor.ittReadRead::55001-60000 203859 12.23% 62.77% # Read-to-read inter transaction time +system.monitor.ittReadRead::60001-65000 203873 12.23% 75.00% # Read-to-read inter transaction time +system.monitor.ittReadRead::65001-70000 6 0.00% 75.00% # Read-to-read inter transaction time +system.monitor.ittReadRead::70001-75000 2 0.00% 75.01% # Read-to-read inter transaction time +system.monitor.ittReadRead::75001-80000 4 0.00% 75.01% # Read-to-read inter transaction time +system.monitor.ittReadRead::80001-85000 571 0.03% 75.04% # Read-to-read inter transaction time +system.monitor.ittReadRead::85001-90000 102408 6.15% 81.19% # Read-to-read inter transaction time +system.monitor.ittReadRead::90001-95000 102628 6.16% 87.34% # Read-to-read inter transaction time +system.monitor.ittReadRead::95001-100000 570 0.03% 87.38% # Read-to-read inter transaction time +system.monitor.ittReadRead::overflows 210333 12.62% 100.00% # Read-to-read inter transaction time system.monitor.ittReadRead::min_value 28000 # Read-to-read inter transaction time -system.monitor.ittReadRead::max_value 1041420 # Read-to-read inter transaction time -system.monitor.ittReadRead::total 1668719 # Read-to-read inter transaction time -system.monitor.ittWriteWrite::samples 1664619 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::mean 59472.389997 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::stdev 41840.398153 # Write-to-write inter transaction time +system.monitor.ittReadRead::max_value 1130700 # Read-to-read inter transaction time +system.monitor.ittReadRead::total 1666396 # Read-to-read inter transaction time +system.monitor.ittWriteWrite::samples 1666878 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::mean 59391.842015 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::stdev 41837.032784 # Write-to-write inter transaction time system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::5001-10000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::10001-15000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::15001-20000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::20001-25000 0 0.00% 0.00% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::25001-30000 419825 25.22% 25.22% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::30001-35000 419112 25.18% 50.40% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::35001-40000 4 0.00% 50.40% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::40001-45000 6 0.00% 50.40% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::45001-50000 6 0.00% 50.40% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::50001-55000 6 0.00% 50.40% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::55001-60000 208578 12.53% 62.93% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::60001-65000 207985 12.49% 75.42% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::65001-70000 3 0.00% 75.42% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::70001-75000 3 0.00% 75.42% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::75001-80000 3 0.00% 75.42% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::80001-85000 552 0.03% 75.46% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::85001-90000 102802 6.18% 81.63% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::90001-95000 102817 6.18% 87.81% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::95001-100000 552 0.03% 87.84% # Write-to-write inter transaction time -system.monitor.ittWriteWrite::overflows 202365 12.16% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::25001-30000 422194 25.33% 25.33% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::30001-35000 420422 25.22% 50.55% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::35001-40000 7 0.00% 50.55% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::40001-45000 3 0.00% 50.55% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::45001-50000 3 0.00% 50.55% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::50001-55000 1 0.00% 50.55% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::55001-60000 208021 12.48% 63.03% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::60001-65000 207862 12.47% 75.50% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::65001-70000 4 0.00% 75.50% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::70001-75000 2 0.00% 75.50% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::75001-80000 2 0.00% 75.50% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::80001-85000 506 0.03% 75.53% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::85001-90000 102058 6.12% 81.65% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::90001-95000 103058 6.18% 87.84% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::95001-100000 512 0.03% 87.87% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::overflows 202223 12.13% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::min_value 28000 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::max_value 598079 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::total 1664619 # Write-to-write inter transaction time -system.monitor.ittReqReq::samples 3333339 # Request-to-request inter transaction time -system.monitor.ittReqReq::mean 29999.937068 # Request-to-request inter transaction time -system.monitor.ittReqReq::stdev 1278.967916 # Request-to-request inter transaction time +system.monitor.ittWriteWrite::max_value 600949 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::total 1666878 # Write-to-write inter transaction time +system.monitor.ittReqReq::samples 3333275 # Request-to-request inter transaction time +system.monitor.ittReqReq::mean 30000.511852 # Request-to-request inter transaction time +system.monitor.ittReqReq::stdev 1280.006862 # Request-to-request inter transaction time system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::1-5000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::5001-10000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::25001-30000 1684541 50.54% 50.54% # Request-to-request inter transaction time -system.monitor.ittReqReq::30001-35000 1648718 49.46% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::25001-30000 1684866 50.55% 50.55% # Request-to-request inter transaction time +system.monitor.ittReqReq::30001-35000 1648324 49.45% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::35001-40000 18 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::40001-45000 15 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::45001-50000 11 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::50001-55000 20 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::55001-60000 13 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::60001-65000 2 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::40001-45000 13 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::45001-50000 13 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::50001-55000 16 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::55001-60000 16 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::60001-65000 8 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::65001-70000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::70001-75000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::75001-80000 0 0.00% 100.00% # Request-to-request inter transaction time @@ -498,21 +498,21 @@ system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Re system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::min_value 28000 # Request-to-request inter transaction time -system.monitor.ittReqReq::max_value 1041420 # Request-to-request inter transaction time -system.monitor.ittReqReq::total 3333339 # Request-to-request inter transaction time +system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time +system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.030000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.160000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 0.881402 # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.212061 # Outstanding read transactions system.monitor.outstandingReadsHist::0 28 28.00% 28.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 47 47.00% 75.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 21 21.00% 96.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 3 3.00% 99.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::4 0 0.00% 99.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::5 1 1.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 45 45.00% 73.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 19 19.00% 92.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 5 5.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 0 0.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 2 2.00% 99.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::6 0 0.00% 99.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::7 0 0.00% 99.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::8 1 1.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::11 0 0.00% 100.00% # Outstanding read transactions @@ -526,11 +526,11 @@ system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions -system.monitor.outstandingWritesHist::mean 0.150000 # Outstanding write transactions +system.monitor.outstandingWritesHist::mean 0.190000 # Outstanding write transactions system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions -system.monitor.outstandingWritesHist::stdev 0.358870 # Outstanding write transactions -system.monitor.outstandingWritesHist::0 85 85.00% 85.00% # Outstanding write transactions -system.monitor.outstandingWritesHist::1 15 15.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::stdev 0.394277 # Outstanding write transactions +system.monitor.outstandingWritesHist::0 81 81.00% 81.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::1 19 19.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions @@ -551,9 +551,9 @@ system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period -system.monitor.readTransHist::mean 16687.200000 # Histogram of read transactions per sample period -system.monitor.readTransHist::gmean 16635.188141 # Histogram of read transactions per sample period -system.monitor.readTransHist::stdev 1683.853859 # Histogram of read transactions per sample period +system.monitor.readTransHist::mean 16663.970000 # Histogram of read transactions per sample period +system.monitor.readTransHist::gmean 16611.784927 # Histogram of read transactions per sample period +system.monitor.readTransHist::stdev 1686.281945 # Histogram of read transactions per sample period system.monitor.readTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::4096-6143 0 0.00% 0.00% # Histogram of read transactions per sample period @@ -561,8 +561,8 @@ system.monitor.readTransHist::6144-8191 0 0.00% 0.00% # Hi system.monitor.readTransHist::8192-10239 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::10240-12287 0 0.00% 0.00% # Histogram of read transactions per sample period system.monitor.readTransHist::12288-14335 0 0.00% 0.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::14336-16383 5 5.00% 5.00% # Histogram of read transactions per sample period -system.monitor.readTransHist::16384-18431 94 94.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::14336-16383 12 12.00% 12.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::16384-18431 87 87.00% 99.00% # Histogram of read transactions per sample period system.monitor.readTransHist::18432-20479 0 0.00% 99.00% # Histogram of read transactions per sample period system.monitor.readTransHist::20480-22527 0 0.00% 99.00% # Histogram of read transactions per sample period system.monitor.readTransHist::22528-24575 0 0.00% 99.00% # Histogram of read transactions per sample period @@ -576,9 +576,9 @@ system.monitor.readTransHist::36864-38911 0 0.00% 100.00% # H system.monitor.readTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period -system.monitor.writeTransHist::mean 16646.200000 # Histogram of read transactions per sample period +system.monitor.writeTransHist::mean 16668.790000 # Histogram of read transactions per sample period system.monitor.writeTransHist::gmean 0 # Histogram of read transactions per sample period -system.monitor.writeTransHist::stdev 1683.921595 # Histogram of read transactions per sample period +system.monitor.writeTransHist::stdev 1686.323754 # Histogram of read transactions per sample period system.monitor.writeTransHist::0-1023 1 1.00% 1.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::1024-2047 0 0.00% 1.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::2048-3071 0 0.00% 1.00% # Histogram of read transactions per sample period @@ -600,7 +600,7 @@ system.monitor.writeTransHist::17408-18431 0 0.00% 100.00% # system.monitor.writeTransHist::18432-19455 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::19456-20479 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period -system.cpu.numPackets 3333340 # Number of packets generated +system.cpu.numPackets 3333276 # Number of packets generated system.cpu.numRetries 0 # Number of retries system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) |