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authorNilay Vaish <nilay@cs.wisc.edu>2012-01-10 09:59:01 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-01-10 09:59:01 -0600
commita5a2b9ecbdeeefcfa8d5a5d116c385cdf59e0256 (patch)
tree0d018e4f474bb9dd45bffad990de8e753114e6c2 /tests/quick
parentacbc03ae464b027fe93dca3a0bc796ef63f53113 (diff)
downloadgem5-a5a2b9ecbdeeefcfa8d5a5d116c385cdf59e0256.tar.xz
X86 Regressions: Update stats due to fence instruction
Diffstat (limited to 'tests/quick')
-rw-r--r--tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini2
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/o3-timing/simout6
-rw-r--r--tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt80
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini3
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic/simout18
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt38
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini124
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats69
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout18
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt38
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini3
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing/simout18
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt374
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini119
-rwxr-xr-xtests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr8
-rwxr-xr-xtests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout21
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt450
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini119
-rwxr-xr-xtests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr8
-rwxr-xr-xtests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout19
-rw-r--r--tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt12
24 files changed, 793 insertions, 763 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
index 43fbd9cf3..9ae1576ae 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
index 1cc0d7d05..e8531dc26 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 13:24:14
-gem5 started Aug 20 2011 13:24:28
-gem5 executing on zizzer
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:28:31
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
index 1b6fe9e6f..e3bb4b417 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -3,26 +3,26 @@
sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 11087000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 51481 # Simulator instruction rate (inst/s)
-host_tick_rate 58182623 # Simulator tick rate (ticks/s)
-host_mem_usage 209228 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 74834 # Simulator instruction rate (inst/s)
+host_tick_rate 84571612 # Simulator tick rate (ticks/s)
+host_mem_usage 239776 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 9809 # Number of instructions simulated
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 22175 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 3057 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3057 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 3056 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3056 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2732 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 2731 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 995 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 5895 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14000 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3057 # Number of branches that fetch encountered
+system.cpu.fetch.Insts 13997 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3056 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2221 # Number of cycles fetch has spent squashing
@@ -48,8 +48,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 13088 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.137858 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.631342 # Number of inst fetches per cycle
+system.cpu.fetch.branchRate 0.137813 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.631206 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3565 # Number of cycles decode is running
@@ -66,34 +66,34 @@ system.cpu.rename.RenamedInsts 22712 # Nu
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 272 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 21252 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 47663 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 47647 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 21246 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 47645 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 47629 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 11884 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 11878 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 1613 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2239 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1783 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads 2238 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1782 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 20542 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 16960 # Number of instructions issued
+system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 20539 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 16958 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 12997 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 12992 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.295844 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.003369 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.295691 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.003315 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1107 8.46% 69.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1108 8.47% 69.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1006 7.69% 77.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 734 5.61% 82.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle
@@ -138,7 +138,7 @@ system.cpu.iq.fu_full::MemWrite 23 16.31% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 13642 80.44% 80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued
@@ -167,28 +167,28 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.46% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1844 10.87% 91.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1843 10.87% 91.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 16960 # Type of FU issued
-system.cpu.iq.rate 0.764825 # Inst issue rate
+system.cpu.iq.FU_type_0::total 16958 # Type of FU issued
+system.cpu.iq.rate 0.764735 # Inst issue rate
system.cpu.iq.fu_busy_cnt 141 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008314 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 47204 # Number of integer instruction queue reads
+system.cpu.iq.fu_busy_rate 0.008315 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 47200 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 30804 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 15755 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 17093 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 17091 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1183 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 848 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
@@ -199,9 +199,9 @@ system.cpu.iew.iewBlockCycles 144 # Nu
system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 23 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2239 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1783 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispLoadInsts 2238 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1782 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
@@ -210,7 +210,7 @@ system.cpu.iew.predictedNotTakenIncorrect 523 # N
system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 16100 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 860 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 858 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3105 # number of memory reference insts executed
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index ee37f754f..b1b2b6764 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -66,7 +67,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
@@ -1,7 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index abc865e69..65af79972 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -1,14 +1,12 @@
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:22:35
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:28:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 26beb56a5..2f19e2e68 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 918185 # Simulator instruction rate (inst/s)
-host_mem_usage 200072 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 520394424 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
sim_ticks 5651000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 855797 # Simulator instruction rate (inst/s)
+host_tick_rate 492033087 # Simulator tick rate (ticks/s)
+host_mem_usage 229652 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+sim_insts 9810 # Number of instructions simulated
+system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 11303 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 11303 # Number of busy cycles
-system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 9810 # Number of instructions executed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
system.cpu.num_int_insts 9715 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
-system.cpu.num_load_insts 1056 # Number of load instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1990 # number of memory refs
+system.cpu.num_load_insts 1056 # Number of load instructions
system.cpu.num_store_insts 934 # Number of store instructions
-system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 11303 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index f9c7081f4..752669beb 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -9,6 +9,7 @@ time_sync_spin_threshold=100000
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -41,8 +42,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=X86TLB
@@ -63,7 +64,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -78,11 +79,13 @@ uid=100
type=Directory_Controller
children=directory memBuffer
buffer_size=0
+cntrl_id=1
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -117,16 +120,43 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
+children=cacheMemory sequencer
buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
cache_response_latency=12
+cntrl_id=0
issue_latency=2
number_of_TBEs=256
recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.physmem]
type=PhysicalMemory
file=
@@ -135,44 +165,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler tracer
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
@@ -180,59 +184,77 @@ children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
-endpoint_bandwidth=10000
-link_latency=1
+endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
-children=ext_links0 ext_links1 int_links0 int_links1
+children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
-num_int_nodes=3
print_config=false
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
ext_node=system.l1_cntrl0
-int_node=0
+int_node=system.ruby.network.topology.routers0
latency=1
+link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
ext_node=system.dir_cntrl0
-int_node=1
+int_node=system.ruby.network.topology.routers1
latency=1
+link_id=1
weight=1
[system.ruby.network.topology.int_links0]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
latency=1
-node_a=0
-node_b=2
+link_id=2
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links1]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
latency=1
-node_a=1
-node_b=2
+link_id=3
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers2
weight=1
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
[system.ruby.tracer]
type=RubyTracer
+ruby_system=system.ruby
warmup_length=100000
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 5b362fa1f..b05082262 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Apr/19/2011 12:26:55
+Real time: Jan/09/2012 14:28:32
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.17
-Virtual_time_in_minutes: 0.00283333
-Virtual_time_in_hours: 4.72222e-05
-Virtual_time_in_days: 1.96759e-06
+Virtual_time_in_seconds: 0.31
+Virtual_time_in_minutes: 0.00516667
+Virtual_time_in_hours: 8.61111e-05
+Virtual_time_in_days: 3.58796e-06
Ruby_current_time: 276484
Ruby_start_time: 0
Ruby_cycles: 276484
-mbytes_resident: 39.5938
-mbytes_total: 212.965
-resident_ratio: 0.185935
+mbytes_resident: 40.0625
+mbytes_total: 241.918
+resident_ratio: 0.165652
ruby_cycles_executed: [ 276485 ]
@@ -125,11 +125,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10428
-page_faults: 0
+page_reclaims: 11175
+page_faults: 4
swaps: 0
block_inputs: 0
-block_outputs: 64
+block_outputs: 0
Network Stats
-------------
@@ -142,9 +142,9 @@ total_msgs: 16500 total_bytes: 660000
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.155303
- links_utilized_percent_switch_0_link_0: 0.0622369 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.248369 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 2.48658
+ links_utilized_percent_switch_0_link_0: 2.48947 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 2.48369 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
@@ -153,9 +153,9 @@ links_utilized_percent_switch_0: 0.155303
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.15552
- links_utilized_percent_switch_1_link_0: 0.0620922 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.248947 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 2.48658
+ links_utilized_percent_switch_1_link_0: 2.48369 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 2.48947 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
@@ -164,27 +164,27 @@ links_utilized_percent_switch_1: 0.15552
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.248658
- links_utilized_percent_switch_2_link_0: 0.248947 bw: 160000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.248369 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 2.48658
+ links_utilized_percent_switch_2_link_0: 2.48947 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 2.48369 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
- system.ruby.cpu_ruby_ports.dcache_total_misses: 1377
- system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1377
- system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+ system.l1_cntrl0.cacheMemory_total_misses: 1377
+ system.l1_cntrl0.cacheMemory_total_demand_misses: 1377
+ system.l1_cntrl0.cacheMemory_total_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382%
- system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185%
- system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433%
+ system.l1_cntrl0.cacheMemory_request_type_LD: 36.2382%
+ system.l1_cntrl0.cacheMemory_request_type_ST: 18.5185%
+ system.l1_cntrl0.cacheMemory_request_type_IFETCH: 45.2433%
- system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 1377 100%
+ system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1377 100%
--- L1Cache ---
- Event Counts -
@@ -230,9 +230,9 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_reads: 1377
memory_writes: 1373
memory_refreshes: 576
- memory_total_request_delays: 3664
- memory_delays_per_request: 1.33236
- memory_delays_in_input_queue: 1372
+ memory_total_request_delays: 3035
+ memory_delays_per_request: 1.10364
+ memory_delays_in_input_queue: 743
memory_delays_behind_head_of_bank_queue: 6
memory_delays_stalled_at_head_of_bank_queue: 2286
memory_stalls_for_bank_busy: 791
@@ -310,4 +310,5 @@ ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
-ID_W Memory_Ack \ No newline at end of file
+ID_W Memory_Ack [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
@@ -1,7 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 91b45434a..52f9aeb2f 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -1,14 +1,12 @@
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simout
+Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:26:55
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:28:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index fddfe7f1a..58cff044f 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 147176 # Simulator instruction rate (inst/s)
-host_mem_usage 218080 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-host_tick_rate 4140017 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000276 # Number of seconds simulated
sim_ticks 276484 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 73084 # Simulator instruction rate (inst/s)
+host_tick_rate 2059440 # Simulator tick rate (ticks/s)
+host_mem_usage 247728 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+sim_insts 9810 # Number of instructions simulated
+system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 276484 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 276484 # Number of busy cycles
-system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 9810 # Number of instructions executed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
system.cpu.num_int_insts 9715 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
-system.cpu.num_load_insts 1056 # Number of load instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1990 # number of memory refs
+system.cpu.num_load_insts 1056 # Number of load instructions
system.cpu.num_store_insts 934 # Number of store instructions
-system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 276484 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index 673c6e4e6..acea7ec29 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -169,7 +170,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
@@ -1,7 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index 894d72125..045ceeef4 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,14 +1,12 @@
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:39:44
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:28:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index b1998f7b5..eb8aa1f61 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,218 +1,218 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 743049 # Simulator instruction rate (inst/s)
-host_mem_usage 207784 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2149305775 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000029 # Number of seconds simulated
sim_ticks 28768000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 524711 # Simulator instruction rate (inst/s)
+host_tick_rate 1537080573 # Simulator tick rate (ticks/s)
+host_mem_usage 238628 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+sim_insts 9810 # Number of instructions simulated
+system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.numCycles 57536 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 9810 # Number of instructions executed
+system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
+system.cpu.num_int_insts 9715 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
+system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 1990 # number of memory refs
+system.cpu.num_load_insts 1056 # Number of load instructions
+system.cpu.num_store_insts 934 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 57536 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
+system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits
+system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 6683 # number of overall hits
+system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
+system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 228 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits
+system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 1856 # number of overall hits
+system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses
+system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 134 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses
+system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1856 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 134 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
-system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses
-system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 6683 # number of overall hits
-system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses
-system.cpu.icache.overall_misses 228 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
-system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
+system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 1 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 361 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 361 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 57536 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 57536 # Number of busy cycles
-system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 9810 # Number of instructions executed
-system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
-system.cpu.num_int_insts 9715 # number of integer instructions
-system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
-system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
-system.cpu.num_load_insts 1056 # Number of load instructions
-system.cpu.num_mem_refs 1990 # number of memory refs
-system.cpu.num_store_insts 934 # Number of store instructions
-system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 1f83b404b..bea7090e9 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -15,9 +15,11 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
readfile=tests/halt.sh
smbios_table=system.smbios_table
@@ -707,6 +709,7 @@ port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.
[system.membus.badaddr_responder]
type=IsaFake
+fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
@@ -729,6 +732,7 @@ system=system
[system.pc.behind_pci]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854779128
pio_latency=1000
pio_size=8
@@ -745,15 +749,31 @@ pio=system.iobus.port[12]
[system.pc.com_1]
type=Uart8250
+children=terminal
pio_addr=9223372036854776824
pio_latency=1000
platform=system.pc
system=system
-terminal=system.pc.terminal
+terminal=system.pc.com_1.terminal
pio=system.iobus.port[13]
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
[system.pc.fake_com_2]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776568
pio_latency=1000
pio_size=8
@@ -770,6 +790,7 @@ pio=system.iobus.port[14]
[system.pc.fake_com_3]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776808
pio_latency=1000
pio_size=8
@@ -786,6 +807,7 @@ pio=system.iobus.port[15]
[system.pc.fake_com_4]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776552
pio_latency=1000
pio_size=8
@@ -802,6 +824,7 @@ pio=system.iobus.port[16]
[system.pc.fake_floppy]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776818
pio_latency=1000
pio_size=2
@@ -818,6 +841,7 @@ pio=system.iobus.port[17]
[system.pc.i_dont_exist]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854775936
pio_latency=1000
pio_size=1
@@ -846,7 +870,6 @@ type=SouthBridge
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
cmos=system.pc.south_bridge.cmos
dma1=system.pc.south_bridge.dma1
-int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
io_apic=system.pc.south_bridge.io_apic
keyboard=system.pc.south_bridge.keyboard
pic1=system.pc.south_bridge.pic1
@@ -858,7 +881,8 @@ speaker=system.pc.south_bridge.speaker
[system.pc.south_bridge.cmos]
type=Cmos
-int_pin=system.pc.south_bridge.int_lines2.source
+children=int_pin
+int_pin=system.pc.south_bridge.cmos.int_pin
pio_addr=9223372036854775920
pio_latency=1000
platform=system.pc
@@ -866,6 +890,9 @@ system=system
time=Sun Jan 1 00:00:00 2012
pio=system.iobus.port[1]
+[system.pc.south_bridge.cmos.int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.dma1]
type=I8237
pio_addr=9223372036854775808
@@ -948,7 +975,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@@ -968,70 +995,58 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.int_lines0.source
+source=system.pc.south_bridge.pic1.output
[system.pc.south_bridge.int_lines0.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=0
-[system.pc.south_bridge.int_lines0.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines1]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.int_lines1.source
+source=system.pc.south_bridge.pic2.output
[system.pc.south_bridge.int_lines1.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
number=2
-[system.pc.south_bridge.int_lines1.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines2]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.int_lines2.source
+source=system.pc.south_bridge.cmos.int_pin
[system.pc.south_bridge.int_lines2.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic2
number=0
-[system.pc.south_bridge.int_lines2.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines3]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.int_lines3.source
+source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines3.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
number=0
-[system.pc.south_bridge.int_lines3.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines4]
type=X86IntLine
children=sink
sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.int_lines3.source
+source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines4.sink]
type=X86IntSinkPin
@@ -1040,32 +1055,26 @@ number=2
[system.pc.south_bridge.int_lines5]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.int_lines5.source
+source=system.pc.south_bridge.keyboard.keyboard_int_pin
[system.pc.south_bridge.int_lines5.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=1
-[system.pc.south_bridge.int_lines5.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines6]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.int_lines6.source
+source=system.pc.south_bridge.keyboard.mouse_int_pin
[system.pc.south_bridge.int_lines6.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=12
-[system.pc.south_bridge.int_lines6.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.io_apic]
type=I82094AA
apic_id=1
@@ -1080,20 +1089,28 @@ pio=system.iobus.port[9]
[system.pc.south_bridge.keyboard]
type=I8042
+children=keyboard_int_pin mouse_int_pin
command_port=9223372036854775908
data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.int_lines5.source
-mouse_int_pin=system.pc.south_bridge.int_lines6.source
+keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
+mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[4]
+[system.pc.south_bridge.keyboard.keyboard_int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.keyboard.mouse_int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pic1]
type=I8259
+children=output
mode=I8259Master
-output=system.pc.south_bridge.int_lines0.source
+output=system.pc.south_bridge.pic1.output
pio_addr=9223372036854775840
pio_latency=1000
platform=system.pc
@@ -1101,10 +1118,14 @@ slave=system.pc.south_bridge.pic2
system=system
pio=system.iobus.port[5]
+[system.pc.south_bridge.pic1.output]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pic2]
type=I8259
+children=output
mode=I8259Slave
-output=system.pc.south_bridge.int_lines1.source
+output=system.pc.south_bridge.pic2.output
pio_addr=9223372036854775968
pio_latency=1000
platform=system.pc
@@ -1112,15 +1133,22 @@ slave=Null
system=system
pio=system.iobus.port[6]
+[system.pc.south_bridge.pic2.output]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pit]
type=I8254
-int_pin=system.pc.south_bridge.int_lines3.source
+children=int_pin
+int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[7]
+[system.pc.south_bridge.pit.int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.speaker]
type=PcSpeaker
i8254=system.pc.south_bridge.pit
@@ -1130,13 +1158,6 @@ platform=system.pc
system=system
pio=system.iobus.port[8]
-[system.pc.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
[system.physmem]
type=PhysicalMemory
file=
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
index 99f9676e9..fd09f1faf 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
@@ -1,17 +1,9 @@
warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
warn: Reading current count from inactive timer.
-For more information see: http://www.m5sim.org/warn/1ea2be46
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: Don't know what interrupt to clear for console.
-For more information see: http://www.m5sim.org/warn/7fe1004f
warn: instruction 'fxsave' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: Tried to clear PCI interrupt 14
-For more information see: http://www.m5sim.org/warn/77378d57
warn: Unknown mouse command 0xe1.
-For more information see: http://www.m5sim.org/warn/2447512a
warn: instruction 'wbinvd' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index b12d01305..bd3613cfe 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -1,15 +1,12 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:44:38
-M5 started Apr 19 2011 12:44:44
-M5 executing on maize
-command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
+gem5 compiled Jan 9 2012 20:47:38
+gem5 started Jan 9 2012 21:03:15
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
+warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112051446000 because m5_exit instruction encountered
+Exiting @ tick 5112043255000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index eef6427c6..dc005fb66 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,79 +1,79 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.112037 # Number of seconds simulated
-sim_ticks 5112036996000 # Number of ticks simulated
+sim_seconds 5.112043 # Number of seconds simulated
+sim_ticks 5112043255000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2883648 # Simulator instruction rate (inst/s)
-host_tick_rate 36256565088 # Simulator tick rate (ticks/s)
-host_mem_usage 375496 # Number of bytes of host memory used
-host_seconds 141.00 # Real time elapsed on the host
-sim_insts 406583262 # Number of instructions simulated
-system.l2c.replacements 163860 # number of replacements
-system.l2c.tagsinuse 36838.766351 # Cycle average of tags in use
-system.l2c.total_refs 3334365 # Total number of references to valid blocks.
-system.l2c.sampled_refs 195829 # Sample count of references to valid blocks.
-system.l2c.avg_refs 17.026921 # Average number of references to valid blocks.
+host_inst_rate 2860366 # Simulator instruction rate (inst/s)
+host_tick_rate 35739722021 # Simulator tick rate (ticks/s)
+host_mem_usage 375540 # Number of bytes of host memory used
+host_seconds 143.04 # Real time elapsed on the host
+sim_insts 409133277 # Number of instructions simulated
+system.l2c.replacements 164044 # number of replacements
+system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
+system.l2c.total_refs 3332458 # Total number of references to valid blocks.
+system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
+system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 9696.304444 # Average occupied blocks per context
-system.l2c.occ_blocks::1 27142.461907 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.147954 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.414161 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 2042982 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 10263 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2053245 # number of ReadReq hits
-system.l2c.Writeback_hits::0 1528802 # number of Writeback hits
-system.l2c.Writeback_hits::total 1528802 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 168885 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 168885 # number of ReadExReq hits
-system.l2c.demand_hits::0 2211867 # number of demand (read+write) hits
-system.l2c.demand_hits::1 10263 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2222130 # number of demand (read+write) hits
-system.l2c.overall_hits::0 2211867 # number of overall hits
-system.l2c.overall_hits::1 10263 # number of overall hits
-system.l2c.overall_hits::total 2222130 # number of overall hits
-system.l2c.ReadReq_misses::0 56047 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 29 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 56076 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 1784 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1784 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 144391 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 144391 # number of ReadExReq misses
-system.l2c.demand_misses::0 200438 # number of demand (read+write) misses
-system.l2c.demand_misses::1 29 # number of demand (read+write) misses
-system.l2c.demand_misses::total 200467 # number of demand (read+write) misses
-system.l2c.overall_misses::0 200438 # number of overall misses
-system.l2c.overall_misses::1 29 # number of overall misses
-system.l2c.overall_misses::total 200467 # number of overall misses
+system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context
+system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
+system.l2c.Writeback_hits::0 1529403 # number of Writeback hits
+system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
+system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits
+system.l2c.demand_hits::1 9538 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
+system.l2c.overall_hits::0 2211865 # number of overall hits
+system.l2c.overall_hits::1 9538 # number of overall hits
+system.l2c.overall_hits::total 2221403 # number of overall hits
+system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
+system.l2c.demand_misses::0 200611 # number of demand (read+write) misses
+system.l2c.demand_misses::1 27 # number of demand (read+write) misses
+system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
+system.l2c.overall_misses::0 200611 # number of overall misses
+system.l2c.overall_misses::1 27 # number of overall misses
+system.l2c.overall_misses::total 200638 # number of overall misses
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2099029 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 10292 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2109321 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 1528802 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1528802 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 1812 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1812 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 313276 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 313276 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2412305 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 10292 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2422597 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2412305 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 10292 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2422597 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.026701 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.002818 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.029519 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.984547 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.460907 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.083090 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.002818 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.085908 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.083090 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.002818 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.085908 # miss rate for overall accesses
+system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
@@ -88,7 +88,7 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 144360 # number of writebacks
+system.l2c.writebacks 144472 # number of writebacks
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
@@ -109,42 +109,42 @@ system.l2c.overall_avg_mshr_uncacheable_latency no_value
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 47572 # number of replacements
-system.iocache.tagsinuse 0.042404 # Cycle average of tags in use
+system.iocache.replacements 47570 # number of replacements
+system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47588 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4994772178509 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 0.042404 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.002650 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context
+system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.ReadReq_misses::1 907 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
+system.iocache.ReadReq_misses::1 905 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 47627 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
+system.iocache.demand_misses::1 47625 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 47627 # number of overall misses
-system.iocache.overall_misses::total 47627 # number of overall misses
+system.iocache.overall_misses::1 47625 # number of overall misses
+system.iocache.overall_misses::total 47625 # number of overall misses
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
@@ -200,68 +200,68 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 10224074013 # number of cpu cycles simulated
+system.cpu.numCycles 10224086531 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 406583262 # Number of instructions executed
-system.cpu.num_int_alu_accesses 391790000 # Number of integer alu accesses
+system.cpu.num_insts 409133277 # Number of instructions executed
+system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 42454615 # number of instructions that are conditional controls
-system.cpu.num_int_insts 391790000 # number of integer instructions
+system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
+system.cpu.num_int_insts 374297244 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 836247135 # number of times the integer registers were read
-system.cpu.num_int_register_writes 419118732 # number of times the integer registers were written
+system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read
+system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 38123075 # number of memory refs
-system.cpu.num_load_insts 29716799 # Number of load instructions
-system.cpu.num_store_insts 8406276 # Number of store instructions
-system.cpu.num_idle_cycles 9770647500.086761 # Number of idle cycles
-system.cpu.num_busy_cycles 453426512.913238 # Number of busy cycles
-system.cpu.not_idle_fraction 0.044349 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.955651 # Percentage of idle cycles
+system.cpu.num_mem_refs 35626519 # number of memory refs
+system.cpu.num_load_insts 27217784 # Number of load instructions
+system.cpu.num_store_insts 8408735 # Number of store instructions
+system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
+system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
+system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.icache.replacements 790768 # number of replacements
-system.cpu.icache.tagsinuse 510.627880 # Cycle average of tags in use
-system.cpu.icache.total_refs 253353258 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 791280 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 320.181551 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 148756117000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 510.627880 # Average occupied blocks per context
+system.cpu.icache.replacements 790795 # number of replacements
+system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
+system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0 253353258 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 253353258 # number of ReadReq hits
-system.cpu.icache.demand_hits::0 253353258 # number of demand (read+write) hits
+system.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
+system.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 253353258 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0 253353258 # number of overall hits
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system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 253353258 # number of overall hits
-system.cpu.icache.ReadReq_misses::0 791287 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 791287 # number of ReadReq misses
-system.cpu.icache.demand_misses::0 791287 # number of demand (read+write) misses
+system.cpu.icache.overall_hits::total 243365777 # number of overall hits
+system.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
+system.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 791287 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0 791287 # number of overall misses
+system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0 791314 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 791287 # number of overall misses
+system.cpu.icache.overall_misses::total 791314 # number of overall misses
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0 254144545 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 254144545 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0 254144545 # number of demand (read+write) accesses
+system.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 254144545 # number of overall (read+write) accesses
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+system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0 0.003114 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::0 0.003241 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
@@ -278,7 +278,7 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 806 # number of writebacks
+system.cpu.icache.writebacks 809 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
@@ -299,50 +299,50 @@ system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements 3656 # number of replacements
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-system.cpu.itb_walker_cache.sampled_refs 3666 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs 2.103928 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5105310674000 # Cycle when the warmup percentage was hit.
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+system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit.
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system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses)
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system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
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system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
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+system.cpu.itb_walker_cache.overall_miss_rate::1 0.349881 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency
@@ -358,7 +358,7 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks 405 # number of writebacks
+system.cpu.itb_walker_cache.writebacks 518 # number of writebacks
system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
@@ -379,46 +379,46 @@ system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value
system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 8177 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 5.011395 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 12378 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 8191 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.511171 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5101233676500 # Cycle when the warmup percentage was hit.
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system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
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system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
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system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency
@@ -434,7 +434,7 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks 2332 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks
system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
@@ -455,52 +455,52 @@ system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value
system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21760587 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.097900 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.037579 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.074626 # miss rate for demand accesses
+system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.074626 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
@@ -517,7 +517,7 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 1525259 # number of writebacks
+system.cpu.dcache.writebacks 1525559 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index f05a137d3..3130a22aa 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -15,9 +15,11 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
readfile=tests/halt.sh
smbios_table=system.smbios_table
@@ -704,6 +706,7 @@ port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.
[system.membus.badaddr_responder]
type=IsaFake
+fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
@@ -726,6 +729,7 @@ system=system
[system.pc.behind_pci]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854779128
pio_latency=1000
pio_size=8
@@ -742,15 +746,31 @@ pio=system.iobus.port[12]
[system.pc.com_1]
type=Uart8250
+children=terminal
pio_addr=9223372036854776824
pio_latency=1000
platform=system.pc
system=system
-terminal=system.pc.terminal
+terminal=system.pc.com_1.terminal
pio=system.iobus.port[13]
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
[system.pc.fake_com_2]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776568
pio_latency=1000
pio_size=8
@@ -767,6 +787,7 @@ pio=system.iobus.port[14]
[system.pc.fake_com_3]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776808
pio_latency=1000
pio_size=8
@@ -783,6 +804,7 @@ pio=system.iobus.port[15]
[system.pc.fake_com_4]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776552
pio_latency=1000
pio_size=8
@@ -799,6 +821,7 @@ pio=system.iobus.port[16]
[system.pc.fake_floppy]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776818
pio_latency=1000
pio_size=2
@@ -815,6 +838,7 @@ pio=system.iobus.port[17]
[system.pc.i_dont_exist]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854775936
pio_latency=1000
pio_size=1
@@ -843,7 +867,6 @@ type=SouthBridge
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
cmos=system.pc.south_bridge.cmos
dma1=system.pc.south_bridge.dma1
-int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
io_apic=system.pc.south_bridge.io_apic
keyboard=system.pc.south_bridge.keyboard
pic1=system.pc.south_bridge.pic1
@@ -855,7 +878,8 @@ speaker=system.pc.south_bridge.speaker
[system.pc.south_bridge.cmos]
type=Cmos
-int_pin=system.pc.south_bridge.int_lines2.source
+children=int_pin
+int_pin=system.pc.south_bridge.cmos.int_pin
pio_addr=9223372036854775920
pio_latency=1000
platform=system.pc
@@ -863,6 +887,9 @@ system=system
time=Sun Jan 1 00:00:00 2012
pio=system.iobus.port[1]
+[system.pc.south_bridge.cmos.int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.dma1]
type=I8237
pio_addr=9223372036854775808
@@ -945,7 +972,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@@ -965,70 +992,58 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.int_lines0.source
+source=system.pc.south_bridge.pic1.output
[system.pc.south_bridge.int_lines0.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=0
-[system.pc.south_bridge.int_lines0.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines1]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.int_lines1.source
+source=system.pc.south_bridge.pic2.output
[system.pc.south_bridge.int_lines1.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
number=2
-[system.pc.south_bridge.int_lines1.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines2]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.int_lines2.source
+source=system.pc.south_bridge.cmos.int_pin
[system.pc.south_bridge.int_lines2.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic2
number=0
-[system.pc.south_bridge.int_lines2.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines3]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.int_lines3.source
+source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines3.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
number=0
-[system.pc.south_bridge.int_lines3.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines4]
type=X86IntLine
children=sink
sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.int_lines3.source
+source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines4.sink]
type=X86IntSinkPin
@@ -1037,32 +1052,26 @@ number=2
[system.pc.south_bridge.int_lines5]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.int_lines5.source
+source=system.pc.south_bridge.keyboard.keyboard_int_pin
[system.pc.south_bridge.int_lines5.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=1
-[system.pc.south_bridge.int_lines5.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines6]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.int_lines6.source
+source=system.pc.south_bridge.keyboard.mouse_int_pin
[system.pc.south_bridge.int_lines6.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=12
-[system.pc.south_bridge.int_lines6.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.io_apic]
type=I82094AA
apic_id=1
@@ -1077,20 +1086,28 @@ pio=system.iobus.port[9]
[system.pc.south_bridge.keyboard]
type=I8042
+children=keyboard_int_pin mouse_int_pin
command_port=9223372036854775908
data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.int_lines5.source
-mouse_int_pin=system.pc.south_bridge.int_lines6.source
+keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
+mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[4]
+[system.pc.south_bridge.keyboard.keyboard_int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.keyboard.mouse_int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pic1]
type=I8259
+children=output
mode=I8259Master
-output=system.pc.south_bridge.int_lines0.source
+output=system.pc.south_bridge.pic1.output
pio_addr=9223372036854775840
pio_latency=1000
platform=system.pc
@@ -1098,10 +1115,14 @@ slave=system.pc.south_bridge.pic2
system=system
pio=system.iobus.port[5]
+[system.pc.south_bridge.pic1.output]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pic2]
type=I8259
+children=output
mode=I8259Slave
-output=system.pc.south_bridge.int_lines1.source
+output=system.pc.south_bridge.pic2.output
pio_addr=9223372036854775968
pio_latency=1000
platform=system.pc
@@ -1109,15 +1130,22 @@ slave=Null
system=system
pio=system.iobus.port[6]
+[system.pc.south_bridge.pic2.output]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pit]
type=I8254
-int_pin=system.pc.south_bridge.int_lines3.source
+children=int_pin
+int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[7]
+[system.pc.south_bridge.pit.int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.speaker]
type=PcSpeaker
i8254=system.pc.south_bridge.pit
@@ -1127,13 +1155,6 @@ platform=system.pc
system=system
pio=system.iobus.port[8]
-[system.pc.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
[system.physmem]
type=PhysicalMemory
file=
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
index 99f9676e9..fd09f1faf 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
@@ -1,17 +1,9 @@
warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
warn: Reading current count from inactive timer.
-For more information see: http://www.m5sim.org/warn/1ea2be46
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: Don't know what interrupt to clear for console.
-For more information see: http://www.m5sim.org/warn/7fe1004f
warn: instruction 'fxsave' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: Tried to clear PCI interrupt 14
-For more information see: http://www.m5sim.org/warn/77378d57
warn: Unknown mouse command 0xe1.
-For more information see: http://www.m5sim.org/warn/2447512a
warn: instruction 'wbinvd' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index f1baa96ff..ec51a2abf 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,15 +1,12 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:44:38
-M5 started Apr 19 2011 12:46:29
-M5 executing on maize
-command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
+gem5 compiled Jan 9 2012 20:47:38
+gem5 started Jan 9 2012 21:05:49
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
+warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5195470393000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index f2563a156..3c6185134 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -3,11 +3,11 @@
sim_seconds 5.195470 # Number of seconds simulated
sim_ticks 5195470393000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1914891 # Simulator instruction rate (inst/s)
-host_tick_rate 37635937594 # Simulator tick rate (ticks/s)
-host_mem_usage 372104 # Number of bytes of host memory used
-host_seconds 138.05 # Real time elapsed on the host
-sim_insts 264342001 # Number of instructions simulated
+host_inst_rate 1858401 # Simulator instruction rate (inst/s)
+host_tick_rate 36414646229 # Simulator tick rate (ticks/s)
+host_mem_usage 372180 # Number of bytes of host memory used
+host_seconds 142.68 # Real time elapsed on the host
+sim_insts 265147881 # Number of instructions simulated
system.l2c.replacements 136133 # number of replacements
system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
system.l2c.total_refs 3363370 # Total number of references to valid blocks.
@@ -257,7 +257,7 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1
system.cpu.numCycles 10390940786 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 264342001 # Number of instructions executed
+system.cpu.num_insts 265147881 # Number of instructions executed
system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured