diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-11-03 10:14:42 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-11-03 10:14:42 -0600 |
| commit | ae82551496155588786751a3a92191069488d7f3 (patch) | |
| tree | e4521fdada5b41c67f3ba02e5ea058350364c33d /tests/quick | |
| parent | 2c2c3a4ce98480a4b14a72ceb6e43e268e7a1aee (diff) | |
| download | gem5-ae82551496155588786751a3a92191069488d7f3.tar.xz | |
tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
Diffstat (limited to 'tests/quick')
16 files changed, 3701 insertions, 3696 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index e4e3f0a2b..aaf42338c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index c57bb127b..62e4f1a91 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:58:03 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x530db00 0x530db00 - 0: system.cpu1.isa: ISA system set to: 0x530db00 0x530db00 + 0: system.cpu0.isa: ISA system set to: 0x53ff680 0x53ff680 + 0: system.cpu1.isa: ISA system set to: 0x53ff680 0x53ff680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2802882496500 because m5_exit instruction encountered +Exiting @ tick 2802882713500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 53a29a0e7..560fdc0dc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,312 +1,313 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.802882 # Number of seconds simulated -sim_ticks 2802882496500 # Number of ticks simulated -final_tick 2802882496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.802883 # Number of seconds simulated +sim_ticks 2802882713500 # Number of ticks simulated +final_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1330236 # Simulator instruction rate (inst/s) -host_op_rate 1620871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25395755903 # Simulator tick rate (ticks/s) -host_mem_usage 564312 # Number of bytes of host memory used -host_seconds 110.37 # Real time elapsed on the host -sim_insts 146815698 # Number of instructions simulated -sim_ops 178892459 # Number of ops (including micro ops) simulated +host_inst_rate 1349319 # Simulator instruction rate (inst/s) +host_op_rate 1644123 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25757810314 # Simulator tick rate (ticks/s) +host_mem_usage 564420 # Number of bytes of host memory used +host_seconds 108.82 # Real time elapsed on the host +sim_insts 146828498 # Number of instructions simulated +sim_ops 178908222 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 19 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1117476 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9458684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149780 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082912 # Number of bytes read from this memory -system.physmem.bytes_read::total 11810580 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1117476 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149780 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1267256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6081216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory +system.physmem.bytes_read::total 11808788 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8417296 # Number of bytes written to this memory +system.physmem.bytes_written::total 8408464 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25914 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193697 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95019 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory +system.physmem.num_reads::total 193669 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135679 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135541 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3374627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4213726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2169629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3003086 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2169629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3380944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7216812 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 75963 # Transaction distribution -system.membus.trans_dist::ReadResp 75963 # Transaction distribution -system.membus.trans_dist::WriteReq 30903 # Transaction distribution -system.membus.trans_dist::WriteResp 30903 # Transaction distribution -system.membus.trans_dist::Writeback 95019 # Transaction distribution +system.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 75957 # Transaction distribution +system.membus.trans_dist::ReadResp 75957 # Transaction distribution +system.membus.trans_dist::WriteReq 30905 # Transaction distribution +system.membus.trans_dist::WriteResp 30905 # Transaction distribution +system.membus.trans_dist::Writeback 94881 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60332 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40886 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15607 # Transaction distribution -system.membus.trans_dist::ReadExReq 196321 # Transaction distribution -system.membus.trans_dist::ReadExResp 152216 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60384 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15620 # Transaction distribution +system.membus.trans_dist::ReadExReq 196326 # Transaction distribution +system.membus.trans_dist::ReadExResp 152193 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652185 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773609 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846561 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17908580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18098400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20432864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 460731 # Request fanout histogram +system.membus.snoop_fanout::samples 460689 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 460731 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460731 # Request fanout histogram +system.membus.snoop_fanout::total 460689 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 107723 # number of replacements -system.l2c.tags.tagsinuse 62123.921751 # Cycle average of tags in use -system.l2c.tags.total_refs 208051 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168144 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237338 # Average number of references to valid blocks. +system.l2c.tags.replacements 107632 # number of replacements +system.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use +system.l2c.tags.total_refs 207938 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48622.171138 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.975943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7348.709599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3778.182164 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823425 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1628.255131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 741.773959 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741915 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742920 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.112132 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.057650 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.057357 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024845 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011319 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947936 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60415 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60384 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1884 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13069 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.921860 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4905185 # Number of tag accesses -system.l2c.tags.data_accesses 4905185 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 74 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 28057 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 75985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11512 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11347 # number of ReadReq hits -system.l2c.ReadReq_hits::total 127129 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 225966 # number of Writeback hits -system.l2c.Writeback_hits::total 225966 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 512 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1024::2 1906 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 12994 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45387 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.921387 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4903910 # Number of tag accesses +system.l2c.tags.data_accesses 4903910 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 59 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 28044 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 76113 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 38 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 35 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11456 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11379 # number of ReadReq hits +system.l2c.ReadReq_hits::total 127193 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 225882 # number of Writeback hits +system.l2c.Writeback_hits::total 225882 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 506 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 577 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 56 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 11 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13971 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3083 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17054 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 74 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28057 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89956 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11512 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14430 # number of demand (read+write) hits -system.l2c.demand_hits::total 144183 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 74 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28057 # number of overall hits -system.l2c.overall_hits::cpu0.data 89956 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11512 # number of overall hits -system.l2c.overall_hits::cpu1.data 14430 # number of overall hits -system.l2c.overall_hits::total 144183 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses +system.l2c.UpgradeReq_hits::total 571 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13825 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3137 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16962 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 59 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28044 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89938 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11456 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14516 # number of demand (read+write) hits +system.l2c.demand_hits::total 144155 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 59 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28044 # number of overall hits +system.l2c.overall_hits::cpu0.data 89938 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11456 # number of overall hits +system.l2c.overall_hits::cpu1.data 14516 # number of overall hits +system.l2c.overall_hits::total 144155 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16897 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 11316 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16888 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 11308 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2330 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1142 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31697 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9967 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3302 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13269 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 763 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1181 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1944 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15814 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152610 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 2363 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31692 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 9982 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3290 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13272 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 756 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1185 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1941 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136781 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152600 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16897 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 148112 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16888 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 148089 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2330 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16956 # number of demand (read+write) misses -system.l2c.demand_misses::total 184307 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses +system.l2c.demand_misses::cpu1.inst 2363 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16941 # number of demand (read+write) misses +system.l2c.demand_misses::total 184292 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16897 # number of overall misses -system.l2c.overall_misses::cpu0.data 148112 # number of overall misses +system.l2c.overall_misses::cpu0.inst 16888 # number of overall misses +system.l2c.overall_misses::cpu0.data 148089 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2330 # number of overall misses -system.l2c.overall_misses::cpu1.data 16956 # number of overall misses -system.l2c.overall_misses::total 184307 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 76 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 44954 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 87301 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 44 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13842 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12489 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 158826 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 225966 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225966 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10479 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3367 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13846 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2011 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150767 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18897 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169664 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 44954 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238068 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 44 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13842 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31386 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328490 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 44954 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238068 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 44 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13842 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31386 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328490 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.026316 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.375873 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.129621 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.168328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.091440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.199571 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951140 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980695 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.958327 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.931624 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.990772 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966683 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907334 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.836852 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899484 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.026316 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.375873 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.622142 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.168328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.540241 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.561073 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.026316 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.375873 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.622142 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.168328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.540241 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.561073 # miss rate for overall accesses +system.l2c.overall_misses::cpu1.inst 2363 # number of overall misses +system.l2c.overall_misses::cpu1.data 16941 # number of overall misses +system.l2c.overall_misses::total 184292 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 76 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 61 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 44932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 87421 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 40 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12501 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 225882 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150606 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18956 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169562 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 76 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238027 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 40 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31457 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328447 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 76 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 61 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 40 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.032787 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.032787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.375857 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.032787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,8 +316,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95019 # number of writebacks -system.l2c.writebacks::total 95019 # number of writebacks +system.l2c.writebacks::writebacks 94881 # number of writebacks +system.l2c.writebacks::total 94881 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -355,34 +356,34 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 305028 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305028 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30903 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30903 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225966 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60515 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40953 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101468 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213769 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213769 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117772 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34667382 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10427306 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45094688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838693 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043491 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203961 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802217 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838693 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram system.iobus.trans_dist::ReadReq 31002 # Transaction distribution system.iobus.trans_dist::ReadResp 31002 # Transaction distribution system.iobus.trans_dist::WriteReq 59433 # Transaction distribution @@ -461,9 +462,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20338466 # DTB read hits +system.cpu0.dtb.read_hits 20339791 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16389914 # DTB write hits +system.cpu0.dtb.write_hits 16391007 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -474,12 +475,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20345337 # DTB read accesses -system.cpu0.dtb.write_accesses 16391007 # DTB write accesses +system.cpu0.dtb.read_accesses 20346662 # DTB read accesses +system.cpu0.dtb.write_accesses 16392100 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36728380 # DTB hits +system.cpu0.dtb.hits 36730798 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36736344 # DTB accesses +system.cpu0.dtb.accesses 36738762 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -501,7 +502,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 97433991 # ITB inst hits +system.cpu0.itb.inst_hits 97439560 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -518,38 +519,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97437349 # ITB inst accesses -system.cpu0.itb.hits 97433991 # DTB hits +system.cpu0.itb.inst_accesses 97442918 # ITB inst accesses +system.cpu0.itb.hits 97439560 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97437349 # DTB accesses -system.cpu0.numCycles 5605766965 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442918 # DTB accesses +system.cpu0.numCycles 5605767393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95421538 # Number of instructions committed -system.cpu0.committedOps 115553717 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100756647 # Number of integer alu accesses +system.cpu0.committedInsts 95427097 # Number of instructions committed +system.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 7999979 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13203645 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100756647 # number of integer instructions +system.cpu0.num_func_calls 8000275 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762762 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182446507 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69131058 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349951369 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44905035 # number of times the CC registers were written -system.cpu0.num_mem_refs 37871263 # number of memory refs -system.cpu0.num_load_insts 20596038 # Number of load instructions -system.cpu0.num_store_insts 17275225 # Number of store instructions -system.cpu0.num_idle_cycles 5488189135.402444 # Number of idle cycles -system.cpu0.num_busy_cycles 117577829.597556 # Number of busy cycles -system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles -system.cpu0.Branches 21940727 # Number of branches fetched +system.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873781 # number of memory refs +system.cpu0.num_load_insts 20597370 # Number of load instructions +system.cpu0.num_store_insts 17276411 # Number of store instructions +system.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles +system.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles +system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles +system.cpu0.Branches 21941666 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78883166 67.49% 67.50% # Class of executed instruction -system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -577,19 +578,19 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20596038 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17275225 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116875407 # Class of executed instruction +system.cpu0.op_class::total 116882229 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1971 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1109428 # number of replacements +system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 1109631 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96326384 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1109940 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.785217 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6345717500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.total_refs 96331750 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.774181 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy @@ -598,32 +599,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195982615 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195982615 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96326384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96326384 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96326384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96326384 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96326384 # number of overall hits -system.cpu0.icache.overall_hits::total 96326384 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1109949 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1109949 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1109949 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1109949 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1109949 # number of overall misses -system.cpu0.icache.overall_misses::total 1109949 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97436333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97436333 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97436333 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97436333 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97436333 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011392 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011392 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011392 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011392 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011392 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011392 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 195993956 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993956 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331750 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331750 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331750 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331750 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331750 # number of overall hits +system.cpu0.icache.overall_hits::total 96331750 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses +system.cpu0.icache.overall_misses::total 1110152 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441902 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441902 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441902 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441902 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441902 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441902 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,123 +643,123 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 252470 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16140.899010 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1809063 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268660 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.733652 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 1814551000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8130.897895 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.403919 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.095149 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4678.277611 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3330.224436 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.496271 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000086 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285539 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.203261 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985162 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5558 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 252387 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16137.494570 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1809761 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268581 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.738232 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.802195 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.197687 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081095 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.849314 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.564278 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201328 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16188 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5625 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7524 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39435786 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39435786 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7516 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3210 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1064995 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 352145 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1427866 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511188 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511188 # number of Writeback hits +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988037 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39447588 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39447588 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7603 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3246 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065220 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 351970 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1428039 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511617 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511617 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94088 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94088 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7516 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3210 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1064995 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446233 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1521954 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7516 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3210 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1064995 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446233 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1521954 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44954 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128031 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173336 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26217 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26217 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18426 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18426 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175429 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175429 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44954 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303460 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44954 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303460 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7732 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3345 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1109949 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480176 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601202 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511188 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511188 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26234 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26234 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18426 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18426 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7732 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3345 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1109949 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749693 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1870719 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7732 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3345 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1109949 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749693 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1870719 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040359 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040501 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266633 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108254 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94214 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94214 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7603 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3246 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065220 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446184 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1522253 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7603 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3246 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065220 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446184 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1522253 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 205 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 119 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44932 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128186 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173442 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26232 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26232 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175300 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175300 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 205 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 119 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44932 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303486 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 348742 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 205 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 119 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44932 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303486 # number of overall misses +system.cpu0.l2cache.overall_misses::total 348742 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7808 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3365 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1601481 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511617 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511617 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26249 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26249 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7808 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3365 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1870995 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7808 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3365 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1870995 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035364 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040474 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266967 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650901 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650901 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040359 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040501 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404779 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186434 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040359 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040501 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404779 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186434 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,81 +768,81 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192932 # number of writebacks -system.cpu0.l2cache.writebacks::total 192932 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks +system.cpu0.l2cache.writebacks::total 192916 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 693475 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.745909 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35929913 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.773179 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23662000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.745909 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966301 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966301 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 693468 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74108905 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74108905 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19107323 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19107323 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15689235 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15689235 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346054 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346054 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379605 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379605 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363036 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363036 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34796558 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34796558 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35142612 # number of overall hits -system.cpu0.dcache.overall_hits::total 35142612 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373110 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373110 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295751 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295751 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100324 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100324 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18426 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18426 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668861 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668861 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769185 # number of overall misses -system.cpu0.dcache.overall_misses::total 769185 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19480433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984986 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15984986 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446378 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446378 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386347 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386347 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381462 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381462 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35465419 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35465419 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35911797 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35911797 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019153 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019153 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224751 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224751 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048304 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048304 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018860 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018860 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021419 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021419 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145013 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses +system.cpu0.dcache.overall_misses::total 769179 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,45 +851,45 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511188 # number of writebacks -system.cpu0.dcache.writebacks::total 511188 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks +system.cpu0.dcache.writebacks::total 511617 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28399 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28399 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511188 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26234 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18426 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44660 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2237944 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2219872 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4499440 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71072828 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887162 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152043238 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 321922 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2655621 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082587 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275257 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322119 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2436302 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219319 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2655621 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -912,9 +913,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12172110 # DTB read hits +system.cpu1.dtb.read_hits 12173926 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7585805 # DTB write hits +system.cpu1.dtb.write_hits 7587211 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -925,12 +926,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12174963 # DTB read accesses -system.cpu1.dtb.write_accesses 7586311 # DTB write accesses +system.cpu1.dtb.read_accesses 12176779 # DTB read accesses +system.cpu1.dtb.write_accesses 7587717 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19757915 # DTB hits +system.cpu1.dtb.hits 19761137 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19761274 # DTB accesses +system.cpu1.dtb.accesses 19764496 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -952,7 +953,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 53664371 # ITB inst hits +system.cpu1.itb.inst_hits 53671662 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -969,38 +970,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53666105 # ITB inst accesses -system.cpu1.itb.hits 53664371 # DTB hits +system.cpu1.itb.inst_accesses 53673396 # ITB inst accesses +system.cpu1.itb.hits 53671662 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53666105 # DTB accesses -system.cpu1.numCycles 5605295863 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673396 # DTB accesses +system.cpu1.numCycles 5605296302 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51394160 # Number of instructions committed -system.cpu1.committedOps 63338742 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56976202 # Number of integer alu accesses +system.cpu1.committedInsts 51401401 # Number of instructions committed +system.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170283 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5966381 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56976202 # number of integer instructions +system.cpu1.num_func_calls 9170855 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984315 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110660301 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41292600 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196241872 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18891627 # number of times the CC registers were written -system.cpu1.num_mem_refs 20022980 # number of memory refs -system.cpu1.num_load_insts 12287666 # Number of load instructions -system.cpu1.num_store_insts 7735314 # Number of store instructions -system.cpu1.num_idle_cycles 5539691262.121797 # Number of idle cycles -system.cpu1.num_busy_cycles 65604600.878203 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles -system.cpu1.Branches 15216192 # Number of branches fetched +system.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026390 # number of memory refs +system.cpu1.num_load_insts 12289548 # Number of load instructions +system.cpu1.num_store_insts 7736842 # Number of store instructions +system.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles +system.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles +system.cpu1.Branches 15217497 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45395839 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28345 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401373 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28395 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -1024,56 +1025,56 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12287666 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7735314 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736842 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65450545 # Class of executed instruction +system.cpu1.op_class::total 65459543 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 523179 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711075 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53141770 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 523691 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.475431 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 76931405000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711075 # Average occupied blocks per requestor +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 523402 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148838 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.445730 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107854613 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107854613 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53141770 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53141770 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53141770 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53141770 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53141770 # number of overall hits -system.cpu1.icache.overall_hits::total 53141770 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523691 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523691 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523691 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523691 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523691 # number of overall misses -system.cpu1.icache.overall_misses::total 523691 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53665461 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53665461 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53665461 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53665461 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53665461 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53665461 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009758 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009758 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009758 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 107869418 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869418 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148838 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148838 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148838 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148838 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148838 # number of overall hits +system.cpu1.icache.overall_hits::total 53148838 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses +system.cpu1.icache.overall_misses::total 523914 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672752 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672752 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672752 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672752 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672752 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672752 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1092,121 +1093,121 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 48552 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15311.760536 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716558 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63379 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.305922 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48605 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15302.416394 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716648 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.297716 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8243.045220 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.958358 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015688 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3303.816337 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.924934 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.503116 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201649 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229488 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934556 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14809 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.635884 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.959660 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.032491 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.997092 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.791267 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.505959 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200378 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227221 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 540 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9336 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4933 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903870 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15206583 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15206583 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3143 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1725 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 509849 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99406 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614123 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120669 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120669 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19820 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19820 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3143 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1725 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 509849 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119226 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 633943 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3143 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1725 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 509849 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119226 # number of overall hits -system.cpu1.l2cache.overall_hits::total 633943 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13842 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73217 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87678 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28845 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28845 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22527 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22527 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43793 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43793 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13842 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117010 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131471 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13842 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117010 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131471 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3491 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523691 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172623 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 701801 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120669 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120669 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28853 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28853 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22527 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22527 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63613 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63613 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3491 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 523691 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 236236 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765414 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3491 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 523691 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 236236 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765414 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135772 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026432 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424144 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.124933 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9351 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4901 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15213580 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15213580 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3243 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1759 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510095 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99336 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614433 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120654 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120654 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19759 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19759 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3243 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1759 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510095 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119095 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634192 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3243 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1759 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510095 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119095 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634192 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 343 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13819 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73339 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87768 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28855 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28855 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22557 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22557 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43856 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43856 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 343 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13819 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117195 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131624 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 343 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13819 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117195 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131624 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3586 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2026 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 702201 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120654 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120654 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28862 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28862 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22557 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22557 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3586 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2026 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 765816 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3586 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2026 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 765816 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.131787 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026376 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424723 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.124990 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688428 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688428 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135772 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026432 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495310 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171765 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135772 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026432 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495310 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171765 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689397 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689397 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.131787 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026376 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495980 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171874 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.131787 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026376 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495980 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171874 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1215,80 +1216,80 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 33034 # number of writebacks -system.cpu1.l2cache.writebacks::total 33034 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks +system.cpu1.l2cache.writebacks::total 32966 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 191901 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.757627 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19500351 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192255 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.429617 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105851562500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757627 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 191947 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503515 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39745522 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39745522 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11856979 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11856979 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7396120 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7396120 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50084 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50084 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91418 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 91418 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72426 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72426 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19253099 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19253099 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19303183 # number of overall hits -system.cpu1.dcache.overall_hits::total 19303183 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136590 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136590 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92466 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92466 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30716 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30716 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5317 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5317 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22527 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22527 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229056 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229056 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259772 # number of overall misses -system.cpu1.dcache.overall_misses::total 259772 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993569 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11993569 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7488586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96735 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96735 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19482155 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19482155 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19562955 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19562955 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011389 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011389 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054965 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054965 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237244 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237244 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 39752012 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39752012 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858696 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858696 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397487 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397487 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72422 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72422 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256183 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256183 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306283 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306283 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92477 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92477 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22557 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22557 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229116 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229116 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259834 # number of overall misses +system.cpu1.dcache.overall_misses::total 259834 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995335 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995335 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489964 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489964 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 19485299 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485299 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566117 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566117 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237495 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1297,52 +1298,52 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120669 # number of writebacks -system.cpu1.dcache.writebacks::total 120669 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120654 # number of writebacks +system.cpu1.dcache.writebacks::total 120654 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 709063 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 709063 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120669 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28853 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 63613 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 63613 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1047738 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707355 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1773789 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33516936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22861090 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56415418 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499577 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371208 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313508 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463919 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499552 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941324 68.65% 68.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429884 31.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371208 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371519 # Request fanout histogram system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 246641119509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 8b9ee8e26..ce59aa175 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 624db6e54..f25d6db4c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:56:38 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x55e4b00 0x55e4b00 + 0: system.cpu.isa: ISA system set to: 0x5299680 0x5299680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 @@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2783853461500 because m5_exit instruction encountered +Exiting @ tick 2783854177000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e8036ea95..5bbc68c06 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783853 # Number of seconds simulated -sim_ticks 2783853461500 # Number of ticks simulated -final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783854 # Number of seconds simulated +sim_ticks 2783854177000 # Number of ticks simulated +final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1369296 # Simulator instruction rate (inst/s) -host_op_rate 1666897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26699855189 # Simulator tick rate (ticks/s) -host_mem_usage 553552 # Number of bytes of host memory used -host_seconds 104.26 # Real time elapsed on the host -sim_insts 142769281 # Number of instructions simulated -sim_ops 173798567 # Number of ops (including micro ops) simulated +host_inst_rate 1378246 # Simulator instruction rate (inst/s) +host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26874016957 # Simulator tick rate (ticks/s) +host_mem_usage 553624 # Number of bytes of host memory used +host_seconds 103.59 # Real time elapsed on the host +sim_insts 142771179 # Number of instructions simulated +sim_ops 173800939 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory @@ -21,56 +21,56 @@ system.physmem.bytes_read::cpu.data 10345892 # Nu system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8857332 # Number of bytes written to this memory +system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142503 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74236 # Transaction distribution -system.membus.trans_dist::ReadResp 74236 # Transaction distribution +system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74235 # Transaction distribution +system.membus.trans_dist::ReadResp 74235 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101898 # Transaction distribution +system.membus.trans_dist::Writeback 101899 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -79,33 +79,33 @@ system.membus.trans_dist::UpgradeResp 4509 # Tr system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322857 # Request fanout histogram +system.membus.snoop_fanout::samples 322858 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322857 # Request fanout histogram +system.membus.snoop_fanout::total 322858 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -222,9 +222,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525428 # DTB read hits +system.cpu.dtb.read_hits 31525864 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23123837 # DTB write hits +system.cpu.dtb.write_hits 23124034 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -235,12 +235,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534008 # DTB read accesses -system.cpu.dtb.write_accesses 23125285 # DTB write accesses +system.cpu.dtb.read_accesses 31534444 # DTB read accesses +system.cpu.dtb.write_accesses 23125482 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54649265 # DTB hits +system.cpu.dtb.hits 54649898 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54659293 # DTB accesses +system.cpu.dtb.accesses 54659926 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -262,7 +262,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 147035651 # ITB inst hits +system.cpu.itb.inst_hits 147037671 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -279,38 +279,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147040413 # ITB inst accesses -system.cpu.itb.hits 147035651 # DTB hits +system.cpu.itb.inst_accesses 147042433 # ITB inst accesses +system.cpu.itb.hits 147037671 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147040413 # DTB accesses -system.cpu.numCycles 5567710004 # number of cpu cycles simulated +system.cpu.itb.accesses 147042433 # DTB accesses +system.cpu.numCycles 5567711435 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142769281 # Number of instructions committed -system.cpu.committedOps 173798567 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153158502 # Number of integer alu accesses +system.cpu.committedInsts 142771179 # Number of instructions committed +system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730015 # number of instructions that are conditional controls -system.cpu.num_int_insts 153158502 # number of integer instructions +system.cpu.num_func_calls 16873782 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls +system.cpu.num_int_insts 153160639 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285052059 # number of times the integer registers were read -system.cpu.num_int_register_writes 107176408 # number of times the integer registers were written +system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read +system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530840054 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363143 # number of times the CC registers were written -system.cpu.num_mem_refs 55937812 # number of memory refs -system.cpu.num_load_insts 31855061 # Number of load instructions -system.cpu.num_store_insts 24082751 # Number of store instructions -system.cpu.num_idle_cycles 5389631214.604722 # Number of idle cycles -system.cpu.num_busy_cycles 178078789.395278 # Number of busy cycles -system.cpu.not_idle_fraction 0.031984 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.968016 # Percentage of idle cycles -system.cpu.Branches 36396067 # Number of branches fetched +system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written +system.cpu.num_mem_refs 55938446 # number of memory refs +system.cpu.num_load_insts 31855497 # Number of load instructions +system.cpu.num_store_insts 24082949 # Number of store instructions +system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles +system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles +system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.968015 # Percentage of idle cycles +system.cpu.Branches 36396779 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121149664 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116881 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -338,19 +338,19 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855061 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24082751 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177215263 # Class of executed instruction +system.cpu.op_class::total 177217756 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 1698994 # number of replacements +system.cpu.icache.tags.replacements 1699006 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145339246 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy @@ -360,26 +360,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148738270 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148738270 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145339246 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145339246 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145339246 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145339246 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145339246 # number of overall hits -system.cpu.icache.overall_hits::total 145339246 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699512 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699512 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699512 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699512 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699512 # number of overall misses -system.cpu.icache.overall_misses::total 1699512 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147038758 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147038758 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147038758 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits +system.cpu.icache.overall_hits::total 145341254 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses +system.cpu.icache.overall_misses::total 1699524 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -396,16 +396,16 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.315266 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727659 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.559239 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.653997 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309992 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -422,29 +422,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26202376 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26202376 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505491 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2197846 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682038 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682038 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151041 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151041 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681137 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348887 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681137 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348887 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses @@ -468,47 +468,47 @@ system.cpu.l2cache.overall_misses::cpu.data 163398 # system.cpu.l2cache.overall_misses::total 181765 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699495 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521025 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231747 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682038 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298905 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699495 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530652 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699495 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530652 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029814 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494686 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -518,15 +518,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks -system.cpu.l2cache.writebacks::total 101898 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks +system.cpu.l2cache.writebacks::total 101899 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783051 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.595966 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -535,56 +535,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219231854 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219231854 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128262 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128262 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339512 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395063 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395063 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52467774 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52467774 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52862837 # number of overall hits -system.cpu.dcache.overall_hits::total 52862837 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396291 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396291 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301661 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301661 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116123 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116123 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits +system.cpu.dcache.overall_hits::total 52863480 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697952 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697952 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses -system.cpu.dcache.overall_misses::total 814075 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30524553 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641173 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses +system.cpu.dcache.overall_misses::total 814065 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53165726 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53676912 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53676912 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012983 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227164 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227164 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses @@ -601,29 +601,29 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682038 # number of writebacks -system.cpu.dcache.writebacks::total 682038 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks +system.cpu.dcache.writebacks::total 682036 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36632 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram @@ -641,12 +641,12 @@ system.cpu.toL2Bus.snoop_fanout::min_value 5 # system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 1f2cdefde..a40d111c2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 0ab3b3eb3..f808cc158 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:58:33 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x5550b00 0x5550b00 - 0: system.cpu1.isa: ISA system set to: 0x5550b00 0x5550b00 + 0: system.cpu0.isa: ISA system set to: 0x4f96680 0x4f96680 + 0: system.cpu1.isa: ISA system set to: 0x4f96680 0x4f96680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2866929256000 because m5_exit instruction encountered +Exiting @ tick 2866923142000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 391ab3c97..00e66bf9d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,185 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.866929 # Number of seconds simulated -sim_ticks 2866929256000 # Number of ticks simulated -final_tick 2866929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.866923 # Number of seconds simulated +sim_ticks 2866923142000 # Number of ticks simulated +final_tick 2866923142000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 703930 # Simulator instruction rate (inst/s) -host_op_rate 851474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15295798763 # Simulator tick rate (ticks/s) -host_mem_usage 599572 # Number of bytes of host memory used -host_seconds 187.43 # Real time elapsed on the host -sim_insts 131939289 # Number of instructions simulated -sim_ops 159593891 # Number of ops (including micro ops) simulated +host_inst_rate 699616 # Simulator instruction rate (inst/s) +host_op_rate 846245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15203294122 # Simulator tick rate (ticks/s) +host_mem_usage 599680 # Number of bytes of host memory used +host_seconds 188.57 # Real time elapsed on the host +sim_insts 131928295 # Number of instructions simulated +sim_ops 159578500 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 234148 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 830144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9620672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 235364 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 833280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9630848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 440928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365312 # Number of bytes read from this memory -system.physmem.bytes_read::total 12542872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 234148 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 438560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365696 # Number of bytes read from this memory +system.physmem.bytes_read::total 12555416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 235364 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 284024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6392960 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 285240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6390016 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8729040 # Number of bytes written to this memory +system.physmem.bytes_written::total 8726096 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 150323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 13546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 150482 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6913 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 21333 # Number of read requests responded to by this memory -system.physmem.num_reads::total 205140 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 99890 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 6876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 21339 # Number of read requests responded to by this memory +system.physmem.num_reads::total 205336 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 99844 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140550 # Number of write requests responded to by this memory +system.physmem.num_writes::total 140504 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 289559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3355741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 290653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3359298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 153798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 476228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4375020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81672 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 152972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 476363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4379404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82096 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2229898 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 808648 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2228876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 808650 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3044735 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2229898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 808983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3043715 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2228876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 808984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 295734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3355741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 296828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3359298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 153812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 476228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7419755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 205141 # Number of read requests accepted -system.physmem.writeReqs 140550 # Number of write requests accepted -system.physmem.readBursts 205141 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140550 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13114752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14272 # Total number of bytes read from write queue -system.physmem.bytesWritten 8743552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12542936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8729040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 223 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3913 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15151 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12845 # Per bank write bursts -system.physmem.perBankRdBursts::1 12298 # Per bank write bursts -system.physmem.perBankRdBursts::2 13022 # Per bank write bursts -system.physmem.perBankRdBursts::3 12754 # Per bank write bursts -system.physmem.perBankRdBursts::4 21257 # Per bank write bursts -system.physmem.perBankRdBursts::5 12515 # Per bank write bursts -system.physmem.perBankRdBursts::6 12829 # Per bank write bursts -system.physmem.perBankRdBursts::7 12945 # Per bank write bursts -system.physmem.perBankRdBursts::8 12057 # Per bank write bursts +system.physmem.bw_total::cpu1.data 152986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 476363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7423119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 205337 # Number of read requests accepted +system.physmem.writeReqs 140504 # Number of write requests accepted +system.physmem.readBursts 205337 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140504 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13124800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16768 # Total number of bytes read from write queue +system.physmem.bytesWritten 8739776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12555480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8726096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 262 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15133 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12897 # Per bank write bursts +system.physmem.perBankRdBursts::1 12279 # Per bank write bursts +system.physmem.perBankRdBursts::2 13044 # Per bank write bursts +system.physmem.perBankRdBursts::3 12666 # Per bank write bursts +system.physmem.perBankRdBursts::4 21207 # Per bank write bursts +system.physmem.perBankRdBursts::5 12512 # Per bank write bursts +system.physmem.perBankRdBursts::6 12819 # Per bank write bursts +system.physmem.perBankRdBursts::7 13070 # Per bank write bursts +system.physmem.perBankRdBursts::8 12092 # Per bank write bursts system.physmem.perBankRdBursts::9 12100 # Per bank write bursts -system.physmem.perBankRdBursts::10 12212 # Per bank write bursts -system.physmem.perBankRdBursts::11 11004 # Per bank write bursts -system.physmem.perBankRdBursts::12 11810 # Per bank write bursts -system.physmem.perBankRdBursts::13 12145 # Per bank write bursts -system.physmem.perBankRdBursts::14 11734 # Per bank write bursts -system.physmem.perBankRdBursts::15 11391 # Per bank write bursts -system.physmem.perBankWrBursts::0 8757 # Per bank write bursts -system.physmem.perBankWrBursts::1 8655 # Per bank write bursts -system.physmem.perBankWrBursts::2 9184 # Per bank write bursts -system.physmem.perBankWrBursts::3 8823 # Per bank write bursts -system.physmem.perBankWrBursts::4 8606 # Per bank write bursts -system.physmem.perBankWrBursts::5 8736 # Per bank write bursts -system.physmem.perBankWrBursts::6 8840 # Per bank write bursts -system.physmem.perBankWrBursts::7 8881 # Per bank write bursts -system.physmem.perBankWrBursts::8 8404 # Per bank write bursts -system.physmem.perBankWrBursts::9 8549 # Per bank write bursts -system.physmem.perBankWrBursts::10 8595 # Per bank write bursts -system.physmem.perBankWrBursts::11 8133 # Per bank write bursts -system.physmem.perBankWrBursts::12 8369 # Per bank write bursts -system.physmem.perBankWrBursts::13 8306 # Per bank write bursts -system.physmem.perBankWrBursts::14 8199 # Per bank write bursts -system.physmem.perBankWrBursts::15 7581 # Per bank write bursts +system.physmem.perBankRdBursts::10 12291 # Per bank write bursts +system.physmem.perBankRdBursts::11 10982 # Per bank write bursts +system.physmem.perBankRdBursts::12 11837 # Per bank write bursts +system.physmem.perBankRdBursts::13 12135 # Per bank write bursts +system.physmem.perBankRdBursts::14 11741 # Per bank write bursts +system.physmem.perBankRdBursts::15 11403 # Per bank write bursts +system.physmem.perBankWrBursts::0 8736 # Per bank write bursts +system.physmem.perBankWrBursts::1 8619 # Per bank write bursts +system.physmem.perBankWrBursts::2 9216 # Per bank write bursts +system.physmem.perBankWrBursts::3 8724 # Per bank write bursts +system.physmem.perBankWrBursts::4 8630 # Per bank write bursts +system.physmem.perBankWrBursts::5 8715 # Per bank write bursts +system.physmem.perBankWrBursts::6 8820 # Per bank write bursts +system.physmem.perBankWrBursts::7 8946 # Per bank write bursts +system.physmem.perBankWrBursts::8 8394 # Per bank write bursts +system.physmem.perBankWrBursts::9 8545 # Per bank write bursts +system.physmem.perBankWrBursts::10 8627 # Per bank write bursts +system.physmem.perBankWrBursts::11 8114 # Per bank write bursts +system.physmem.perBankWrBursts::12 8397 # Per bank write bursts +system.physmem.perBankWrBursts::13 8288 # Per bank write bursts +system.physmem.perBankWrBursts::14 8182 # Per bank write bursts +system.physmem.perBankWrBursts::15 7606 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2866928814500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 2866922767000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 195371 # Read request sizes (log2) +system.physmem.readPktSize::6 195567 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136114 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 121124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 7040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 501 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136068 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 121119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21791 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 7029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 5390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -209,117 +191,120 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 80974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.941463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.852686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.869933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39277 48.51% 48.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16073 19.85% 68.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6267 7.74% 76.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3406 4.21% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3201 3.95% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1947 2.40% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1140 1.41% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1004 1.24% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8659 10.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 80974 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.475461 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 574.843547 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6723 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.317965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.827449 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.656598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5486 81.59% 81.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 426 6.34% 87.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.22% 89.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 201 2.99% 92.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 197 2.93% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.31% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.28% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.24% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 29 0.43% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.07% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.04% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 175 2.60% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.12% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.10% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 6 0.09% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads -system.physmem.totQLat 5972474500 # Total ticks spent queuing -system.physmem.totMemAccLat 9814687000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1024590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29145.68 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 81121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.529616 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 151.748883 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.565122 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39339 48.49% 48.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16179 19.94% 68.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6333 7.81% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3376 4.16% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3166 3.90% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1954 2.41% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1081 1.33% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1008 1.24% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8685 10.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81121 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.551698 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 544.132444 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6710 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6712 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6712 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.345501 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.833911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.781170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5518 82.21% 82.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 369 5.50% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 92 1.37% 89.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 214 3.19% 92.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 187 2.79% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 23 0.34% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.18% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.25% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 32 0.48% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.09% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 162 2.41% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.13% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.19% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.04% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6712 # Writes before turning the bus around for reads +system.physmem.totQLat 6009454502 # Total ticks spent queuing +system.physmem.totMemAccLat 9854610752 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1025375000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29303.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47895.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 48053.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s @@ -327,584 +312,607 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing -system.physmem.readRowHits 175001 # Number of row buffer hits during reads -system.physmem.writeRowHits 85560 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.62 # Row buffer hit rate for writes -system.physmem.avgGap 8293327.90 # Average gap between requests -system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731384342500 # Time in different power states -system.physmem.memoryStateTime::REF 95733040000 # Time in different power states +system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.49 # Average write queue length when enqueuing +system.physmem.readRowHits 175010 # Number of row buffer hits during reads +system.physmem.writeRowHits 85502 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes +system.physmem.avgGap 8289713.39 # Average gap between requests +system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2731290601750 # Time in different power states +system.physmem.memoryStateTime::REF 95732780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 39811853000 # Time in different power states +system.physmem.memoryStateTime::ACT 39899739250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 323167320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 288996120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 176331375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 157686375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 861627000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 736725600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 456723360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 428561280 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187253826240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187253826240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82374692850 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81185757210 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647898682250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648941608250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919345050395 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1918993161075 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.477790 # Core power per rank (mW) -system.physmem.averagePower::1 669.355049 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 228441 # Transaction distribution -system.membus.trans_dist::ReadResp 228440 # Transaction distribution -system.membus.trans_dist::WriteReq 31177 # Transaction distribution -system.membus.trans_dist::WriteResp 31177 # Transaction distribution -system.membus.trans_dist::Writeback 99890 # Transaction distribution +system.physmem.actEnergy::0 323265600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 290009160 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 176385000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 158239125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 861853200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 737724000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 456230880 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 428671440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 187253317680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 187253317680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82699072155 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81115825050 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1647609467250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1648998280500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1919379591765 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1918982066955 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.491656 # Core power per rank (mW) +system.physmem.averagePower::1 669.352997 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 228669 # Transaction distribution +system.membus.trans_dist::ReadResp 228668 # Transaction distribution +system.membus.trans_dist::WriteReq 31179 # Transaction distribution +system.membus.trans_dist::WriteResp 31179 # Transaction distribution +system.membus.trans_dist::Writeback 99844 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85859 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41212 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15151 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 28398 # Transaction distribution -system.membus.trans_dist::ReadExResp 11478 # Transaction distribution +system.membus.trans_dist::UpgradeReq 85785 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41193 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15133 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 28316 # Transaction distribution +system.membus.trans_dist::ReadExResp 11444 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 800720 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 800908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 873436 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 873624 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18952616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19144659 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19154259 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21463955 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129081 # Total snoops (count) -system.membus.snoop_fanout::samples 475718 # Request fanout histogram +system.membus.pkt_size::total 21473555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 128959 # Total snoops (count) +system.membus.snoop_fanout::samples 475734 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 475718 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 475734 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 475718 # Request fanout histogram -system.membus.reqLayer0.occupancy 88161999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 475734 # Request fanout histogram +system.membus.reqLayer0.occupancy 88166499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 20500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12079498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12097497 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1514580499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1514306999 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1969894164 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1971607923 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38592409 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38585418 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 132728 # number of replacements -system.l2c.tags.tagsinuse 64199.829322 # Cycle average of tags in use -system.l2c.tags.total_refs 489645 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197292 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.481829 # Average number of references to valid blocks. +system.l2c.tags.replacements 132855 # number of replacements +system.l2c.tags.tagsinuse 64219.366353 # Cycle average of tags in use +system.l2c.tags.total_refs 486769 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 197473 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.464990 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12574.713731 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.829645 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043526 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1158.059566 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1408.624866 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38786.462390 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.540569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007801 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 536.338892 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 908.008157 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8820.200180 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.191875 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12668.220978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.836009 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999655 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1159.806509 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1415.804508 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38683.036536 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.697637 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 527.060368 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 909.811701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8848.084656 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.193302 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017671 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021494 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.591834 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000039 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.017697 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.021603 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590256 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000026 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008184 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013855 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134586 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979612 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 44718 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19841 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5098 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39452 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.008042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013883 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.135011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979910 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 45009 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 19601 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5222 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39585 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1574 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18054 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.682343 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.302750 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6148253 # Number of tag accesses -system.l2c.tags.data_accesses 6148253 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 159 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 10419 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 29225 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168428 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 62 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4147 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 10318 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47800 # number of ReadReq hits -system.l2c.ReadReq_hits::total 270735 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 240561 # number of Writeback hits -system.l2c.Writeback_hits::total 240561 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 9666 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1017 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10683 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 240 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 136 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4189 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2493 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6682 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 127 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 159 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 10419 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 33414 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 168428 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 62 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4147 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 47800 # number of demand (read+write) hits -system.l2c.demand_hits::total 277417 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 127 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 159 # number of overall hits -system.l2c.overall_hits::cpu0.inst 10419 # number of overall hits -system.l2c.overall_hits::cpu0.data 33414 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 168428 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 62 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4147 # number of overall hits -system.l2c.overall_hits::cpu1.data 12811 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 47800 # number of overall hits -system.l2c.overall_hits::total 277417 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::3 1500 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 17888 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.686783 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.299088 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6123027 # Number of tag accesses +system.l2c.tags.data_accesses 6123027 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 138 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 10210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 28863 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 166586 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 49 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 4197 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 10271 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47730 # number of ReadReq hits +system.l2c.ReadReq_hits::total 268223 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 239796 # number of Writeback hits +system.l2c.Writeback_hits::total 239796 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 9662 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 934 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10596 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 248 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 151 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 399 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4158 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2526 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6684 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 138 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 10210 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 33021 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 166586 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 4197 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12797 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 47730 # number of demand (read+write) hits +system.l2c.demand_hits::total 274907 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 138 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits +system.l2c.overall_hits::cpu0.inst 10210 # number of overall hits +system.l2c.overall_hits::cpu0.data 33021 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 166586 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits +system.l2c.overall_hits::cpu1.inst 4197 # number of overall hits +system.l2c.overall_hits::cpu1.data 12797 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 47730 # number of overall hits +system.l2c.overall_hits::total 274907 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3095 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6926 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3114 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6976 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 769 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1418 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq misses -system.l2c.ReadReq_misses::total 183878 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8558 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4221 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12779 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 889 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1310 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2199 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 6118 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5533 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 11651 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.data 1415 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq misses +system.l2c.ReadReq_misses::total 184109 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8503 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4264 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 881 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1309 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2190 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 6116 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5504 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 11620 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 3095 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 13044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 150324 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 3114 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 13092 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 769 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6951 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) misses -system.l2c.demand_misses::total 195529 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.demand_misses::cpu1.data 6919 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) misses +system.l2c.demand_misses::total 195729 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3095 # number of overall misses -system.l2c.overall_misses::cpu0.data 13044 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 150324 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 3114 # number of overall misses +system.l2c.overall_misses::cpu0.data 13092 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 150483 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 769 # number of overall misses -system.l2c.overall_misses::cpu1.data 6951 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 21333 # number of overall misses -system.l2c.overall_misses::total 195529 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 510000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.data 6919 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 21339 # number of overall misses +system.l2c.overall_misses::total 195729 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 706500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 268587999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 563686749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 328000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 94250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 70493000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 122227750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18379241574 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8946128 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10070574 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 19016702 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1175950 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2179907 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3355857 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 485246640 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 404862686 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 890109326 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 510000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 269607250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 570989749 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 266750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 88750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 69445999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 122855750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18430164853 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8530144 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 9612086 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 18142230 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1132453 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2244405 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3376858 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 492352141 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 397195181 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 889547322 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 706500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 268587999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1048933389 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 328000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 94250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 70493000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 527090436 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19269350900 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 510000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 269607250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1063341890 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 266750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 88750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 69445999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 520050931 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 19319712175 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 706500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 268587999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1048933389 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 328000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 94250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 70493000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 527090436 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19269350900 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 134 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 160 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 13514 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 36151 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 66 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 4916 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11736 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69133 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 454613 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 240561 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 240561 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 18224 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5238 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 23462 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 269607250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1063341890 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 266750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 88750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 69445999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 520050931 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of overall miss cycles +system.l2c.overall_miss_latency::total 19319712175 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 146 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 134 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 13324 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 35839 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 317069 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 52 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 4966 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 11686 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69069 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 452332 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 239796 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 239796 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 18165 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5198 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 23363 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1129 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1446 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2575 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 10307 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 8026 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 18333 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 134 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 160 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 13514 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 46458 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318752 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 66 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 4916 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19762 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69133 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 472946 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 134 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 160 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 13514 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 46458 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318752 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 66 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 4916 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19762 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69133 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 472946 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.229022 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.191585 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.156428 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.120825 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.404471 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.469601 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805842 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.544668 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787422 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.905947 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.853981 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.593577 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.689385 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.635521 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.006250 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.229022 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.280770 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.156428 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.351736 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.413428 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.006250 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.229022 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.280770 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.156428 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.351736 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.413428 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average ReadReq miss latency +system.l2c.SCUpgradeReq_accesses::cpu1.data 1460 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2589 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 10274 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8030 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 18304 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 146 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 134 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 13324 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 46113 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 317069 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 52 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 4966 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 19716 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69069 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 470636 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 146 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 134 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 13324 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 46113 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 317069 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 52 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 4966 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 19716 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69069 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 470636 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007463 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.233714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.194648 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021277 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.154853 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.121085 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.407022 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.468098 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.820316 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.546462 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.780337 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.896575 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.845886 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.595289 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.685430 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.634834 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.007463 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.233714 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.283911 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.021277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.154853 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.350933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.415882 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.007463 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.233714 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.283911 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.021277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.154853 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.350933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.415882 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86781.259774 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 81387.055876 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 94250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91668.400520 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 86197.284908 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 99953.455954 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1045.352652 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2385.826581 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1488.121293 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1322.778403 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1664.051145 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1526.083220 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79314.586466 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73172.363275 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76397.676251 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86579.078356 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 81850.594753 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90306.890767 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 86823.851590 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 100104.638301 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.192285 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2254.241557 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1421.025300 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1285.417707 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1714.595111 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1541.944292 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80502.312132 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72164.822129 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76553.125818 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 86781.259774 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 80415.009890 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 91668.400520 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75829.439793 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 98549.836086 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 86579.078356 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 81220.737091 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 90306.890767 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75162.730308 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 98706.436834 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 86781.259774 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 80415.009890 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 91668.400520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75829.439793 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 98549.836086 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 86579.078356 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 81220.737091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 90306.890767 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75162.730308 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 98706.436834 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 2 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 99890 # number of writebacks -system.l2c.writebacks::total 99890 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 99844 # number of writebacks +system.l2c.writebacks::total 99844 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 3095 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6926 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 3114 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6976 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 769 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1418 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 183878 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8558 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4221 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12779 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 889 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1310 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2199 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 6118 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5533 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 11651 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1414 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 184108 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8503 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4264 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12767 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 881 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1309 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2190 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 6116 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5504 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 11620 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 3095 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 13044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 3114 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 13092 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 769 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6951 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 195529 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6918 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 195728 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 3095 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 13044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 3114 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 13092 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 769 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6951 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 195529 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 423500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.data 6918 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 195728 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 607500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230146499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 477536249 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 278000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 81250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 60929000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 104521250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 16097880074 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86272013 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42559203 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 128831216 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8927886 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13175305 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 22103191 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 408771858 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 334873814 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 743645672 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 423500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230914750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 484247749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 228750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59892499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105166750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 16146124355 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 85791947 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42794256 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 128586203 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8846879 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13136807 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 21983686 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 415913357 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 327528317 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 743441674 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 607500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 230146499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 886308107 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 278000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 81250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 60929000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 439395064 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16841525746 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 423500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 230914750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 900161106 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 228750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 59892499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 432695067 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16889566029 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 607500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 230146499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 886308107 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 278000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 81250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 60929000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 439395064 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16841525746 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476853500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4797337250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9261250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814340500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6097792500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540127500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712608500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4252736000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476853500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337464750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9261250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526949000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10350528500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191585 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120825 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.404471 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.469601 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.805842 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.544668 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787422 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.905947 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.853981 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.593577 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.689385 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.635521 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.413428 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.413428 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 230914750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 900161106 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 228750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 59892499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 432695067 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16889566029 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796970001 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814272500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6097046501 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540071000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712688499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4252759499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337041001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526960999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10349806000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.194648 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120999 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.407020 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.468098 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.820316 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.546462 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.780337 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.896575 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845886 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595289 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.685430 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.634834 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.415880 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.415880 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68948.346665 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73710.331453 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87546.525816 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10080.861533 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.729922 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.478676 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.616423 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.484733 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10051.473852 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66814.622099 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60523.009940 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63826.767831 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69416.248423 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74375.353607 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87699.200225 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.609197 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.176360 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10071.763374 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10041.860386 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.757830 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10038.212785 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68004.146010 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59507.325036 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63979.490017 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -956,50 +964,50 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 633918 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 633902 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31177 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31177 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 240561 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 96369 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41588 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137957 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39943 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39943 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1258028 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 400059 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1658087 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37640280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8288315 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45928595 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 305065 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1044371 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.034928 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.183598 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 631517 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 631501 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31179 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 239796 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 96205 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41592 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 137797 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 39833 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 39833 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1252484 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399771 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1652255 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37452048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8279747 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45731795 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 304794 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1040942 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.035049 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.183904 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1007893 96.51% 96.51% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36478 3.49% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1004458 96.50% 96.50% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1044371 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1521180751 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1040942 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1516413702 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2136308825 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2125399996 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 850635338 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 850129169 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31019 # Transaction distribution system.iobus.trans_dist::ReadResp 31019 # Transaction distribution -system.iobus.trans_dist::WriteReq 59408 # Transaction distribution +system.iobus.trans_dist::WriteReq 59414 # Transaction distribution system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 32 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 26 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1090,13 +1098,13 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326676322 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 326665578 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36842591 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36844582 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1121,25 +1129,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24353899 # DTB read hits -system.cpu0.dtb.read_misses 6408 # DTB read misses -system.cpu0.dtb.write_hits 18126722 # DTB write hits -system.cpu0.dtb.write_misses 1115 # DTB write misses +system.cpu0.dtb.read_hits 24351510 # DTB read hits +system.cpu0.dtb.read_misses 6410 # DTB read misses +system.cpu0.dtb.write_hits 18124813 # DTB write hits +system.cpu0.dtb.write_misses 1105 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1442 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1454 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24360307 # DTB read accesses -system.cpu0.dtb.write_accesses 18127837 # DTB write accesses +system.cpu0.dtb.read_accesses 24357920 # DTB read accesses +system.cpu0.dtb.write_accesses 18125918 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 42480621 # DTB hits -system.cpu0.dtb.misses 7523 # DTB misses -system.cpu0.dtb.accesses 42488144 # DTB accesses +system.cpu0.dtb.hits 42476323 # DTB hits +system.cpu0.dtb.misses 7515 # DTB misses +system.cpu0.dtb.accesses 42483838 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1161,8 +1169,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 115074724 # ITB inst hits -system.cpu0.itb.inst_misses 3350 # ITB inst misses +system.cpu0.itb.inst_hits 115065468 # ITB inst hits +system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1171,45 +1179,45 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 115078074 # ITB inst accesses -system.cpu0.itb.hits 115074724 # DTB hits -system.cpu0.itb.misses 3350 # DTB misses -system.cpu0.itb.accesses 115078074 # DTB accesses -system.cpu0.numCycles 5733858512 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 115068817 # ITB inst accesses +system.cpu0.itb.hits 115065468 # DTB hits +system.cpu0.itb.misses 3349 # DTB misses +system.cpu0.itb.accesses 115068817 # DTB accesses +system.cpu0.numCycles 5733846284 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 111430460 # Number of instructions committed -system.cpu0.committedOps 134719109 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 119427816 # Number of integer alu accesses +system.cpu0.committedInsts 111421342 # Number of instructions committed +system.cpu0.committedOps 134707084 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 119417138 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 12527987 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14980229 # number of instructions that are conditional controls -system.cpu0.num_int_insts 119427816 # number of integer instructions +system.cpu0.num_func_calls 12527292 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14979198 # number of instructions that are conditional controls +system.cpu0.num_int_insts 119417138 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 220379706 # number of times the integer registers were read -system.cpu0.num_int_register_writes 83050844 # number of times the integer registers were written +system.cpu0.num_int_register_reads 220360477 # number of times the integer registers were read +system.cpu0.num_int_register_writes 83042635 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 488414813 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 49991768 # number of times the CC registers were written -system.cpu0.num_mem_refs 43590115 # number of memory refs -system.cpu0.num_load_insts 24600281 # Number of load instructions -system.cpu0.num_store_insts 18989834 # Number of store instructions -system.cpu0.num_idle_cycles 5477713409.888090 # Number of idle cycles -system.cpu0.num_busy_cycles 256145102.111911 # Number of busy cycles +system.cpu0.num_cc_register_reads 488370374 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 49987740 # number of times the CC registers were written +system.cpu0.num_mem_refs 43585643 # number of memory refs +system.cpu0.num_load_insts 24597805 # Number of load instructions +system.cpu0.num_store_insts 18987838 # Number of store instructions +system.cpu0.num_idle_cycles 5477706580.128089 # Number of idle cycles +system.cpu0.num_busy_cycles 256139703.871911 # Number of busy cycles system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles -system.cpu0.Branches 28216928 # Number of branches fetched +system.cpu0.Branches 28215087 # Number of branches fetched system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 94734127 68.43% 68.43% # Class of executed instruction -system.cpu0.op_class::IntMult 104105 0.08% 68.51% # Class of executed instruction +system.cpu0.op_class::IntAlu 94726294 68.43% 68.43% # Class of executed instruction +system.cpu0.op_class::IntMult 104119 0.08% 68.51% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction @@ -1233,24 +1241,24 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 7379 0.01% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::MemRead 24600281 17.77% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 18989834 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 24597805 17.77% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 18987838 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 138438000 # Class of executed instruction +system.cpu0.op_class::total 138425707 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2074 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1061133 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483144 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 114013070 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1061645 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 107.392838 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12807152500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483144 # Average occupied blocks per requestor +system.cpu0.kern.inst.quiesce 2071 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 1060721 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.483228 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 114004226 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1061233 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 107.426198 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483228 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1258,44 +1266,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 231211102 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 231211102 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 114013070 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 114013070 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 114013070 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 114013070 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 114013070 # number of overall hits -system.cpu0.icache.overall_hits::total 114013070 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1061654 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1061654 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1061654 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1061654 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1061654 # number of overall misses -system.cpu0.icache.overall_misses::total 1061654 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000777256 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9000777256 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9000777256 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9000777256 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9000777256 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9000777256 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 115074724 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115074724 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 115074724 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115074724 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 115074724 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115074724 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.070309 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.070309 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8478.070309 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8478.070309 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 231192178 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 231192178 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 114004226 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 114004226 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 114004226 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 114004226 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 114004226 # number of overall hits +system.cpu0.icache.overall_hits::total 114004226 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1061242 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1061242 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1061242 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1061242 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1061242 # number of overall misses +system.cpu0.icache.overall_misses::total 1061242 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8993016265 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8993016265 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 8993016265 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8993016265 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 8993016265 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8993016265 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065468 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115065468 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 115065468 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115065468 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 115065468 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115065468 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009223 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009223 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009223 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009223 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009223 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009223 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8474.048582 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8474.048582 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8474.048582 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8474.048582 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1304,360 +1312,360 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061654 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1061654 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061654 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1061654 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061654 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1061654 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407609744 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407609744 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407609744 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7407609744 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407609744 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7407609744 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719278000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719278000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719278000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 719278000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.423665 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061242 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1061242 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061242 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1061242 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061242 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1061242 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7400481735 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7400481735 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7400481735 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7400481735 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7400481735 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7400481735 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009223 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009223 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009223 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6973.415804 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923568 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 227909 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9246862 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 529 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9920146 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228501 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9247232 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 457 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 49 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 448219 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778472 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 42 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 443914 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 777982 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 358131 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16113.840521 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1936015 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 374364 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.171477 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6748.405331 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.298352 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.117074 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 799.968206 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1087.232896 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7475.818663 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.411890 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000140 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048826 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.066359 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.456288 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983511 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7939 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8291 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 355628 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16102.172005 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1937789 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 371860 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.211071 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2843494453500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6709.486955 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.515536 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.136878 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 805.451650 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1129.365506 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7457.215481 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.409515 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.049161 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.068931 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455152 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982799 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8004 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8222 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 41 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 127 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1966 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4890 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 915 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1974 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4878 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1002 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2895 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4675 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.484558 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.506042 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 38026831 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 38026831 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 6990 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3189 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045942 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 372788 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428909 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 483936 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 483936 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10087 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 10087 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2033 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2033 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212805 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 212805 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 6990 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3189 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1045942 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 585593 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1641714 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 6990 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3189 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1045942 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 585593 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1641714 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 263 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 219 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15712 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 83577 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 99771 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29878 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 29878 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19321 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19321 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44921 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44921 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 263 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 219 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 15712 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 128498 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 144692 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 263 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 219 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 15712 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 128498 # number of overall misses -system.cpu0.l2cache.overall_misses::total 144692 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6061000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4899500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598206723 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2260687668 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 2869854891 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 524614292 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 524614292 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377658880 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377658880 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1333497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1333497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1506710587 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1506710587 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6061000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4899500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598206723 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 3767398255 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 4376565478 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6061000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4899500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598206723 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 3767398255 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 4376565478 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7253 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3408 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061654 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456365 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1528680 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 483936 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 483936 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39965 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 39965 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21354 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21354 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257726 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 257726 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7253 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3408 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1061654 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 714091 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1786406 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7253 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3408 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1061654 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 714091 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1786406 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064261 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014800 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183136 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.065266 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.747604 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.747604 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.904795 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.904795 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4665 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 528 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.488525 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.501831 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 38047907 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 38047907 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7536 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3405 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045714 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 373715 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1430370 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 484430 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 484430 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10145 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 10145 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2013 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2013 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213040 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 213040 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7536 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3405 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1045714 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 586755 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1643410 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7536 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3405 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1045714 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 586755 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1643410 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 196 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15528 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 83217 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 99215 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29791 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 29791 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19296 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19296 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44826 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44826 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 196 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 15528 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 128043 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 144041 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 196 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 15528 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 128043 # number of overall misses +system.cpu0.l2cache.overall_misses::total 144041 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6536750 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 592785719 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2259626174 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 2863295143 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522985276 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 522985276 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377523884 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377523884 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1293996 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1293996 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513538321 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1513538321 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6536750 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 592785719 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 3773164495 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 4376833464 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6536750 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 592785719 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 3773164495 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 4376833464 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7810 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3601 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061242 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456932 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1529585 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 484430 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 484430 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39936 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 39936 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21309 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21309 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257866 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 257866 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7810 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3601 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1061242 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 714798 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1787451 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7810 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3601 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1061242 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 714798 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1787451 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054429 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014632 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182121 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.064864 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745969 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745969 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905533 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905533 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174298 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174298 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064261 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014800 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179946 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.080996 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064261 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014800 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179946 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.080996 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22372.146119 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38073.238480 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27049.160271 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28764.419430 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17558.547828 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17558.547828 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19546.549350 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.549350 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190499.571429 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190499.571429 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33541.341177 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33541.341177 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 30247.459970 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 30247.459970 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 5815 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173834 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173834 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054429 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014632 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179132 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.080585 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054429 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014632 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179132 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.080585 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22176.020408 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38175.278143 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27153.420263 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28859.498493 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17555.143365 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17555.143365 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19564.877902 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19564.877902 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 161749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 161749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33764.741913 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33764.741913 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 30386.025257 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 30386.025257 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 74 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 76.513158 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 74.675676 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 205462 # number of writebacks -system.cpu0.l2cache.writebacks::total 205462 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2206 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2737 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 4943 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1219 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1219 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2206 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3956 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6162 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2206 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3956 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6162 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 263 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 219 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13506 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80840 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 94828 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 448214 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29878 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29878 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19321 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19321 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43702 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43702 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 263 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 219 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13506 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124542 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 138530 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 263 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 219 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13506 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124542 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 586744 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3366500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457538021 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1656533968 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2121657489 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17785493022 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 490939499 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 490939499 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261550596 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261550596 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1060497 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1060497 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1074359119 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1074359119 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3366500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457538021 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2730893087 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 3196016608 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3366500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457538021 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2730893087 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 20981509630 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647388500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328873750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5976262250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987021005 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987021005 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647388500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315894755 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9963283255 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177139 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062033 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 204753 # number of writebacks +system.cpu0.l2cache.writebacks::total 204753 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2208 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2732 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 4940 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1247 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1247 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2208 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3979 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6187 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2208 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3979 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6187 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 274 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 196 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13320 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80485 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 94275 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 443910 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29791 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29791 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19296 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19296 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43579 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43579 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 274 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 196 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13320 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124064 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 137854 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 274 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 196 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13320 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124064 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 581764 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2974500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 455365525 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1657319721 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2120277496 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17833673651 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489027550 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489027550 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261183602 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261183602 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1027996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1027996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080146893 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080146893 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2974500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 455365525 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2737466614 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 3200424389 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2974500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 455365525 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2737466614 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21034098040 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328493002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975701502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987031009 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987031009 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315524011 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962732511 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176142 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.061634 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.747604 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.747604 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.904795 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.904795 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745969 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745969 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905533 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905533 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169568 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169568 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077547 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.168999 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.168999 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077123 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.328449 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20491.513706 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22373.744980 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39680.806539 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16431.471283 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16431.471283 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13537.114849 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13537.114849 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 151499.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 151499.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24583.751750 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24583.751750 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23070.934873 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35759.223154 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.325471 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20591.659576 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22490.347346 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40174.075040 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16415.278104 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16415.278104 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13535.634432 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13535.634432 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 128499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 128499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24785.949494 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24785.949494 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23216.042980 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36155.723008 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1667,106 +1675,106 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 658799 # number of replacements -system.cpu0.dcache.tags.tagsinuse 485.164758 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41683742 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 659311 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 63.223186 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1016179000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.164758 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947587 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 659666 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.509746 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41678625 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 660178 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 63.132405 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.509746 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946308 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.946308 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 85573160 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 85573160 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23155425 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23155425 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17431620 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17431620 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323179 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 323179 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358328 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 358328 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353864 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 353864 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40587045 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40587045 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40910224 # number of overall hits -system.cpu0.dcache.overall_hits::total 40910224 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 360428 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 360428 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297691 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297691 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106192 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 106192 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21416 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21416 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 658119 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 658119 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 764311 # number of overall misses -system.cpu0.dcache.overall_misses::total 764311 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4473033768 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4473033768 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4445222415 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4445222415 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335592501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 335592501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473344116 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 473344116 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1450500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1450500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8918256183 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8918256183 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8918256183 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8918256183 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23515853 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23515853 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17729311 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17729311 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429371 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 429371 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379744 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 379744 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375234 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 375234 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41245164 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41245164 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 41674535 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 41674535 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015327 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.015327 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016791 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016791 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247320 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247320 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056396 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056396 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056951 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056951 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015956 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.015956 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018340 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018340 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12410.339286 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12410.339286 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14932.337273 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14932.337273 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15670.176550 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15670.176550 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22149.935236 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22149.935236 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 85565275 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 85565275 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23152761 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23152761 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17429713 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17429713 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 322896 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 322896 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358209 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 358209 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353793 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 353793 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 40582474 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 40582474 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 40905370 # number of overall hits +system.cpu0.dcache.overall_hits::total 40905370 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 360920 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 360920 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 297802 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 297802 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106369 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 106369 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21424 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21424 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21331 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21331 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 658722 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 658722 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 765091 # number of overall misses +system.cpu0.dcache.overall_misses::total 765091 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4478152013 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4478152013 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4451575229 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4451575229 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336099252 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336099252 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472564125 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 472564125 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1408000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1408000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8929727242 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8929727242 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8929727242 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8929727242 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513681 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23513681 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727515 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17727515 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429265 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 429265 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379633 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 379633 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375124 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 375124 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 41241196 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 41241196 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 41670461 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 41670461 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015349 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.015349 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016799 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.016799 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247793 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247793 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056433 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056433 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056864 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056864 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015972 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.015972 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018361 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018361 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12407.602829 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12407.602829 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14948.103871 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14948.103871 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15687.978529 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15687.978529 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.866439 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.866439 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13551.130089 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13551.130089 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11668.360370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11668.360370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13556.139376 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13556.139376 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11671.457698 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11671.457698 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1775,82 +1783,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 483937 # number of writebacks -system.cpu0.dcache.writebacks::total 483937 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7364 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7364 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15075 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15075 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 7364 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 7364 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 7364 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 7364 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353064 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 353064 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297691 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297691 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96960 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 96960 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21361 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21361 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 650755 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 650755 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 747715 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 747715 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3674066732 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3674066732 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3839615585 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3839615585 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1190903244 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1190903244 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89864249 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89864249 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429815884 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429815884 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1372500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1372500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7513682317 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7513682317 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8704585561 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8704585561 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564939750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564939750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183945995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183945995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748885745 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748885745 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015014 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015014 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016791 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016791 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225819 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225819 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056927 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056927 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015778 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015778 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017942 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.017942 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10406.234371 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10406.234371 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12897.990148 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12897.990148 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12282.417946 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12282.417946 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14171.936445 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14171.936445 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20121.524460 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20121.524460 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 484431 # number of writebacks +system.cpu0.dcache.writebacks::total 484431 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7369 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15106 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15106 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 7369 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 7369 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 7369 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 7369 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353551 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 353551 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297802 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 297802 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97063 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 97063 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6318 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6318 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 651353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 651353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 748416 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 748416 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3677967737 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3677967737 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3845809771 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3845809771 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1192380739 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1192380739 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89588750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89588750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429129875 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429129875 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1332000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1332000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523777508 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7523777508 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8716158247 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8716158247 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564560247 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564560247 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183952491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183952491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748512738 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748512738 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015036 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015036 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016799 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226114 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226114 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016642 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016642 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056827 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056827 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015794 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015794 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.017960 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10402.934052 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10402.934052 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12913.982347 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12913.982347 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12284.606276 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12284.606276 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14179.922444 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14179.922444 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20130.875592 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20130.875592 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11546.100018 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11546.100018 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11641.582101 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11641.582101 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11550.998472 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11550.998472 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11646.140979 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11646.140979 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1858,57 +1866,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1734717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1628862 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26256 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26256 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 483936 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 598763 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 81012 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43653 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 101651 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 279403 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269117 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141354 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2250253 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9809 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 20976 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4422392 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981948 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80932636 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13632 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29012 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 148957228 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 991588 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3219253 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.272771 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.445384 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1734773 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1628939 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 484430 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 593528 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43635 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 101479 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 279524 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269229 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2140528 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2251817 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10000 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21524 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4423869 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67955576 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 81003288 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14404 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31240 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 149004508 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 985271 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3214597 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.271498 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.444733 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2341135 72.72% 72.72% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 878118 27.28% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2341839 72.85% 72.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 872758 27.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3219253 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1700320883 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3214597 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1701148418 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115643997 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115449999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1603955756 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1603332265 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1150860061 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1151834640 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13723500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13714500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1933,25 +1941,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4827395 # DTB read hits -system.cpu1.dtb.read_misses 2744 # DTB read misses -system.cpu1.dtb.write_hits 4131070 # DTB write hits -system.cpu1.dtb.write_misses 524 # DTB write misses +system.cpu1.dtb.read_hits 4826536 # DTB read hits +system.cpu1.dtb.read_misses 2746 # DTB read misses +system.cpu1.dtb.write_hits 4130096 # DTB write hits +system.cpu1.dtb.write_misses 525 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 441 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4830139 # DTB read accesses -system.cpu1.dtb.write_accesses 4131594 # DTB write accesses +system.cpu1.dtb.read_accesses 4829282 # DTB read accesses +system.cpu1.dtb.write_accesses 4130621 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 8958465 # DTB hits -system.cpu1.dtb.misses 3268 # DTB misses -system.cpu1.dtb.accesses 8961733 # DTB accesses +system.cpu1.dtb.hits 8956632 # DTB hits +system.cpu1.dtb.misses 3271 # DTB misses +system.cpu1.dtb.accesses 8959903 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1973,7 +1981,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20889672 # ITB inst hits +system.cpu1.itb.inst_hits 20887785 # ITB inst hits system.cpu1.itb.inst_misses 1747 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1990,38 +1998,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20891419 # ITB inst accesses -system.cpu1.itb.hits 20889672 # DTB hits +system.cpu1.itb.inst_accesses 20889532 # ITB inst accesses +system.cpu1.itb.hits 20887785 # DTB hits system.cpu1.itb.misses 1747 # DTB misses -system.cpu1.itb.accesses 20891419 # DTB accesses -system.cpu1.numCycles 5732950771 # number of cpu cycles simulated +system.cpu1.itb.accesses 20889532 # DTB accesses +system.cpu1.numCycles 5732937622 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20508829 # Number of instructions committed -system.cpu1.committedOps 24874782 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22190598 # Number of integer alu accesses +system.cpu1.committedInsts 20506953 # Number of instructions committed +system.cpu1.committedOps 24871416 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22187475 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 1209607 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2572400 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22190598 # number of integer instructions +system.cpu1.num_func_calls 1209546 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2572136 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22187475 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 39855869 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15449003 # number of times the integer registers were written +system.cpu1.num_int_register_reads 39849843 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15447126 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 90462747 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 8862782 # number of times the CC registers were written -system.cpu1.num_mem_refs 9247846 # number of memory refs -system.cpu1.num_load_insts 4946569 # Number of load instructions -system.cpu1.num_store_insts 4301277 # Number of store instructions -system.cpu1.num_idle_cycles 5671538888.273010 # Number of idle cycles -system.cpu1.num_busy_cycles 61411882.726990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010712 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989288 # Percentage of idle cycles -system.cpu1.Branches 3892747 # Number of branches fetched +system.cpu1.num_cc_register_reads 90450390 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 8861668 # number of times the CC registers were written +system.cpu1.num_mem_refs 9246104 # number of memory refs +system.cpu1.num_load_insts 4945808 # Number of load instructions +system.cpu1.num_store_insts 4300296 # Number of store instructions +system.cpu1.num_idle_cycles 5671542273.082585 # Number of idle cycles +system.cpu1.num_busy_cycles 61395348.917415 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010709 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989291 # Percentage of idle cycles +system.cpu1.Branches 3892449 # Number of branches fetched system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 16017837 63.30% 63.30% # Class of executed instruction -system.cpu1.op_class::IntMult 33571 0.13% 63.44% # Class of executed instruction +system.cpu1.op_class::IntAlu 16016240 63.31% 63.31% # Class of executed instruction +system.cpu1.op_class::IntMult 33559 0.13% 63.44% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction @@ -2045,69 +2053,69 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4039 0.02% 63.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4035 0.02% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::MemRead 4946569 19.55% 83.00% # Class of executed instruction -system.cpu1.op_class::MemWrite 4301277 17.00% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4945808 19.55% 83.00% # Class of executed instruction +system.cpu1.op_class::MemWrite 4300296 17.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 25303360 # Class of executed instruction +system.cpu1.op_class::total 25300005 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2751 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 565233 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.685358 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20323921 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 565745 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 35.924173 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 115078716000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.685358 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973995 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973995 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 565422 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.690526 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20321845 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 565934 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 35.908507 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 115084597500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690526 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 112 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 42345080 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 42345080 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20323921 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20323921 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20323921 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20323921 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20323921 # number of overall hits -system.cpu1.icache.overall_hits::total 20323921 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 565746 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 565746 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 565746 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 565746 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 565746 # number of overall misses -system.cpu1.icache.overall_misses::total 565746 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4684636281 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4684636281 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4684636281 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4684636281 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4684636281 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4684636281 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20889667 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20889667 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20889667 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20889667 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20889667 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20889667 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027083 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.027083 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027083 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.027083 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027083 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.027083 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8280.458511 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8280.458511 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8280.458511 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8280.458511 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 42341495 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 42341495 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20321845 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20321845 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20321845 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20321845 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20321845 # number of overall hits +system.cpu1.icache.overall_hits::total 20321845 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 565935 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 565935 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 565935 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 565935 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 565935 # number of overall misses +system.cpu1.icache.overall_misses::total 565935 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4686937020 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4686937020 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4686937020 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4686937020 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4686937020 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4686937020 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20887780 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20887780 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20887780 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20887780 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20887780 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20887780 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027094 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.027094 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027094 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.027094 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027094 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.027094 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8281.758541 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8281.758541 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8281.758541 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8281.758541 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2116,356 +2124,356 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565746 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 565746 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 565746 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 565746 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 565746 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 565746 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835844219 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835844219 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835844219 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3835844219 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835844219 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3835844219 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14025750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14025750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14025750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 14025750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027083 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027083 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027083 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6780.152611 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565935 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 565935 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 565935 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 565935 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 565935 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 565935 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3837864980 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3837864980 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3837864980 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3837864980 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3837864980 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3837864980 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027094 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027094 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027094 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6781.458966 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4613211 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23452 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471751 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 253 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4614389 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23334 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471466 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 174 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 21 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 117734 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522133 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 12 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119403 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 521875 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85099 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15602.150946 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 830949 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100297 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.284884 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2855978416500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4730.109881 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.755019 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.314200 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 871.040386 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1529.848587 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8465.082873 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.288703 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000351 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000019 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053164 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.093375 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.516668 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952280 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9308 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5882 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 64 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1130 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8114 # Occupied blocks per task id +system.cpu1.l2cache.tags.replacements 85170 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15608.903517 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 832047 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 100420 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.285670 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4763.037570 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.132590 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.368696 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 855.518210 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1503.059843 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8483.786608 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.290713 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000023 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052217 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091739 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517809 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.952692 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9266 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5973 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 72 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1188 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8006 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1134 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4474 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.568115 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359009 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 16690228 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 16690228 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3013 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1699 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560147 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 123235 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 688094 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 134926 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 134926 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1530 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1530 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 889 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 889 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39290 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 39290 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3013 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1699 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 560147 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 162525 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 727384 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3013 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1699 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 560147 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 162525 # number of overall hits -system.cpu1.l2cache.overall_hits::total 727384 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 347 # number of ReadReq misses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4453 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.565552 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364563 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 16694338 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 16694338 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3134 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1760 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560288 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 123283 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 688465 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 134894 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 134894 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1542 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1542 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 898 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 898 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39293 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 39293 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3134 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1760 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 560288 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 162576 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 727758 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3134 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1760 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 560288 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 162576 # number of overall hits +system.cpu1.l2cache.overall_hits::total 727758 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 333 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 282 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5599 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 70297 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 76525 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29432 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29432 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22334 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22334 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33500 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33500 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 347 # number of demand (read+write) misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5647 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 70211 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 76473 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29395 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29395 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22356 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22356 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33464 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 33464 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 333 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 282 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 5599 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 103797 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 110025 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 347 # number of overall misses +system.cpu1.l2cache.demand_misses::cpu1.inst 5647 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 103675 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 109937 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 333 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 282 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 5599 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 103797 # number of overall misses -system.cpu1.l2cache.overall_misses::total 110025 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7263500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5687750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 191326469 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1549353898 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1753631617 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537113129 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 537113129 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436542574 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436542574 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1696500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1696500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1074535378 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1074535378 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7263500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5687750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 191326469 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2623889276 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2828166995 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7263500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5687750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 191326469 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2623889276 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2828166995 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3360 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565746 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193532 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 764619 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 134926 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 134926 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30962 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30962 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23223 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23223 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72790 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 72790 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3360 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 565746 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 266322 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 837409 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3360 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 565746 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 266322 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 837409 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.142352 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009897 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363232 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.100083 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950585 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950585 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961719 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961719 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.overall_misses::cpu1.inst 5647 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 103675 # number of overall misses +system.cpu1.l2cache.overall_misses::total 109937 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6884250 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5668750 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192294729 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1548076900 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1752924629 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536345651 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 536345651 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436560063 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436560063 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1532500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1532500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1065249640 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1065249640 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6884250 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5668750 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192294729 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2613326540 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2818174269 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6884250 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5668750 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192294729 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2613326540 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2818174269 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3467 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2042 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565935 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193494 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 764938 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 134894 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 134894 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30937 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 30937 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23254 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23254 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72757 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 72757 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3467 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2042 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 565935 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 266251 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 837695 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3467 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2042 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 565935 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 266251 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 837695 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138100 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009978 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.362859 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.099973 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950157 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950157 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961383 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961383 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.460228 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.460228 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.142352 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009897 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389742 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.131387 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.142352 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009897 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389742 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.131387 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.326241 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34171.542954 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22040.114059 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22915.800287 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18249.290874 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18249.290874 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19546.098952 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.098952 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 565500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 565500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32075.682925 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32075.682925 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 25704.767053 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 25704.767053 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 1025 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.459942 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.459942 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138100 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009978 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389388 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.131238 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138100 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009978 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389388 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.131238 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20101.950355 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34052.546308 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22048.922534 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22922.137604 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18246.152441 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18246.152441 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19527.646404 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19527.646404 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 255416.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 255416.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31832.704996 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31832.704996 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 25634.447629 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 25634.447629 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 41 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.285714 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.463415 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 35099 # number of writebacks -system.cpu1.l2cache.writebacks::total 35099 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 685 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 96 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 781 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 214 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 214 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 685 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 310 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 995 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 685 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 310 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 995 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 347 # number of ReadReq MSHR misses +system.cpu1.l2cache.writebacks::writebacks 35043 # number of writebacks +system.cpu1.l2cache.writebacks::total 35043 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 682 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 211 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 211 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 682 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 997 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 682 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 997 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 333 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 282 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4914 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70201 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 75744 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 117733 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29432 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29432 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22334 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22334 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33286 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 33286 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 347 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4965 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70107 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 75687 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 119401 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29395 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29395 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22356 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22356 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33253 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 33253 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 333 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 282 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4914 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103487 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 109030 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 347 # number of overall MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4965 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103360 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 108940 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 333 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 282 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4914 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103487 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 226763 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3713250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143751774 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1055636432 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1207934956 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3298666709 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 431077198 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 431077198 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306544179 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306544179 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1430500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1430500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820609092 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820609092 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3713250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143751774 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1876245524 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2028544048 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3713250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143751774 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1876245524 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 5327210757 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12612250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916010500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928622750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796474001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796474001 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12612250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712484501 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725096751 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362736 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099061 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4965 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103360 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 228341 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3694250 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143766018 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1054723430 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206735448 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3265998125 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430847649 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430847649 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306945673 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306945673 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1280500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1280500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 812696840 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 812696840 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3694250 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143766018 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1867420270 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2019432288 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3694250 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143766018 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1867420270 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 5285430413 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 915969500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928445000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796605001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796605001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712574501 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725050001 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362321 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.098945 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950585 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950585 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961719 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961719 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950157 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950157 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961383 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961383 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457288 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457288 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130199 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457042 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457042 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130047 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.270791 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15037.341804 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15947.599229 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28018.199732 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14646.547907 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14646.547907 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13725.449046 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13725.449046 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 476833.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 476833.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24653.280418 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24653.280418 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18605.375108 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23492.416122 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272583 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15044.481008 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15943.761121 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27353.189044 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14657.174656 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14657.174656 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13729.901279 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13729.901279 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213416.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213416.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24439.805130 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24439.805130 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18537.105636 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23147.093220 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2475,105 +2483,105 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 218932 # number of replacements -system.cpu1.dcache.tags.tagsinuse 479.958616 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8645395 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 219287 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.425023 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104115576500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.958616 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937419 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.937419 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18161929 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18161929 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4463105 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4463105 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3919326 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3919326 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64192 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 64192 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87200 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87200 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79632 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79632 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8382431 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8382431 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8446623 # number of overall hits -system.cpu1.dcache.overall_hits::total 8446623 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 155171 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 155171 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 103752 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 103752 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34196 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 34196 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17931 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17931 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23276 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23276 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 258923 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 258923 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 293119 # number of overall misses -system.cpu1.dcache.overall_misses::total 293119 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2220270266 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2220270266 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2272762314 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2272762314 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325809000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325809000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538454705 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 538454705 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1810500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1810500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4493032580 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4493032580 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4493032580 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4493032580 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4618276 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4618276 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4023078 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4023078 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98388 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 98388 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105131 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105131 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102908 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102908 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8641354 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8641354 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8739742 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8739742 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033599 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.033599 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025789 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025789 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347563 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347563 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170559 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170559 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226183 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226183 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029963 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029963 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033539 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033539 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14308.538748 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14308.538748 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21905.720507 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21905.720507 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18170.152250 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18170.152250 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23133.472461 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23133.472461 # average StoreCondReq miss latency +system.cpu1.dcache.tags.replacements 218971 # number of replacements +system.cpu1.dcache.tags.tagsinuse 479.931321 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8650668 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 219324 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.442414 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104113508000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.931321 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937366 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.937366 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18158178 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18158178 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4462217 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4462217 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3918401 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3918401 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64226 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 64226 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87223 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87223 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79606 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79606 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8380618 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8380618 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8444844 # number of overall hits +system.cpu1.dcache.overall_hits::total 8444844 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 155213 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 155213 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 103694 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 103694 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34142 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 34142 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17915 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17915 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23305 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23305 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 258907 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 258907 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 293049 # number of overall misses +system.cpu1.dcache.overall_misses::total 293049 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2221366762 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2221366762 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2262833509 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2262833509 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325848251 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 325848251 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539203701 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 539203701 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1640500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1640500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4484200271 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4484200271 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4484200271 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4484200271 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4617430 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4617430 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022095 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4022095 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98368 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 98368 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105138 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105138 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102911 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 102911 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8639525 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8639525 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8737893 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8737893 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033615 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.033615 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025781 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.025781 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347084 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347084 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170395 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170395 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226458 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226458 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029968 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033538 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033538 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14311.731376 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14311.731376 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21822.222202 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21822.222202 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18188.571086 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18188.571086 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23136.824759 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23136.824759 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17352.775072 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17352.775072 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15328.356674 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15328.356674 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17319.733615 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17319.733615 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15301.878768 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15301.878768 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2582,82 +2590,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 134926 # number of writebacks -system.cpu1.dcache.writebacks::total 134926 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12328 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12328 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 299 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 299 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154872 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 154872 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103752 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103752 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33057 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 33057 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5603 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5603 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23226 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23226 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 258624 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 258624 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 291681 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 291681 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901749734 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901749734 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2059007686 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2059007686 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496678249 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496678249 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84335500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84335500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490783295 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490783295 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1734500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1734500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3960757420 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3960757420 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4457435669 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4457435669 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961034499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961034499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794416998 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794416998 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025789 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025789 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335986 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335986 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053295 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053295 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225697 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225697 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029929 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029929 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033374 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033374 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12279.493608 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12279.493608 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19845.474651 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19845.474651 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15024.903924 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15024.903924 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15051.847225 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15051.847225 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21130.771334 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21130.771334 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 134894 # number of writebacks +system.cpu1.dcache.writebacks::total 134894 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 307 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12314 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12314 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 307 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 307 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 307 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154906 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 154906 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103694 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103694 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32987 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 32987 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5601 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5601 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23260 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23260 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 258600 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 258600 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 291587 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 291587 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902428238 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902428238 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2049146491 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2049146491 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494497248 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494497248 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84788249 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84788249 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491455299 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491455299 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1568500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1568500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3951574729 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3951574729 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4446071977 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4446071977 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 960995749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 960995749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833535999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833535999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794531748 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794531748 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033548 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033548 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025781 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025781 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335343 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335343 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053273 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053273 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226021 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226021 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033370 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033370 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12281.178508 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12281.178508 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19761.475987 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19761.475987 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14990.670507 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14990.670507 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15138.055526 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15138.055526 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21128.774678 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21128.774678 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15314.732662 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15314.732662 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15281.885584 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15281.885584 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15280.644737 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15280.644737 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15247.840188 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15247.840188 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2665,110 +2673,110 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1206103 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 816776 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 134926 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 169865 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 86284 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42512 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89712 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 91056 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 78188 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131848 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880488 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9281 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2026923 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36208456 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28775795 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13440 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 65005615 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 818131 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1761210 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.414931 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.492710 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1203948 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 816897 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 134894 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 171563 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 86145 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89650 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 90932 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 78151 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1132224 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880229 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5367 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9390 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2027210 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36220548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28766783 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8168 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13868 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 65009367 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 817024 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1760474 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.414632 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.492658 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1030430 58.51% 58.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 730780 41.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1030526 58.54% 58.54% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 729948 41.46% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1761210 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 658102724 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1760474 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 658123967 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89600499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 89509999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 848922781 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 849202770 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 438669538 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 438590477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5921500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5923750 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36443 # number of replacements -system.iocache.tags.tagsinuse 14.446814 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277160524000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.446814 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902926 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902926 # Average percentage of cache occupancy +system.iocache.tags.replacements 36427 # number of replacements +system.iocache.tags.tagsinuse 14.452095 # Cycle average of tags in use +system.iocache.tags.total_refs 16 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36443 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 277168075000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.452095 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.903256 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.903256 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328549 # Number of tag accesses -system.iocache.tags.data_accesses 328549 # Number of data accesses +system.iocache.tags.tag_accesses 328485 # Number of tag accesses +system.iocache.tags.data_accesses 328485 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses system.iocache.ReadReq_misses::total 253 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 32 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 32 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 26 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 26 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses system.iocache.demand_misses::total 253 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 253 # number of overall misses system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31613377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31613377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31613377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31613377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31613377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31613377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36256 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36256 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36250 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36250 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000883 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000883 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000717 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000717 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124954.059289 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124954.059289 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124954.059289 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124954.059289 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2783,28 +2791,28 @@ system.iocache.demand_mshr_misses::realview.ide 253 system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2247085536 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2247085536 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18456377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18456377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2245537783 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2245537783 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18456377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18456377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18456377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18456377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72950.106719 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72950.106719 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index f074dc56c..0ae66cc7f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 7ca64b9c1..ce3f5bea6 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:58:15 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x56b5b00 0x56b5b00 + 0: system.cpu.isa: ISA system set to: 0x44d4680 0x44d4680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index f83b43588..c670f647a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.902619 # Nu sim_ticks 2902619131000 # Number of ticks simulated final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744858 # Simulator instruction rate (inst/s) -host_op_rate 898074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19216925045 # Simulator tick rate (ticks/s) -host_mem_usage 553548 # Number of bytes of host memory used -host_seconds 151.05 # Real time elapsed on the host -sim_insts 112506996 # Number of instructions simulated -sim_ops 135649573 # Number of ops (including micro ops) simulated +host_inst_rate 756630 # Simulator instruction rate (inst/s) +host_op_rate 912268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19520630002 # Simulator tick rate (ticks/s) +host_mem_usage 553652 # Number of bytes of host memory used +host_seconds 148.70 # Real time elapsed on the host +sim_insts 112506995 # Number of instructions simulated +sim_ops 135649572 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory @@ -100,7 +100,7 @@ system.physmem.perBankWrBursts::14 7284 # Pe system.physmem.perBankWrBursts::15 7101 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2902618699500 # Total gap between requests +system.physmem.totGap 2902618754500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) @@ -211,20 +211,20 @@ system.physmem.wrQLenPdf::60 13 # Wh system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes @@ -268,12 +268,12 @@ system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads -system.physmem.totQLat 1491787750 # Total ticks spent queuing -system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1492072500 # Total ticks spent queuing +system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -284,49 +284,49 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing -system.physmem.readRowHits 138438 # Number of row buffer hits during reads +system.physmem.readRowHits 138435 # Number of row buffer hits during reads system.physmem.writeRowHits 90000 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes -system.physmem.avgGap 9972509.98 # Average gap between requests +system.physmem.avgGap 9972510.17 # Average gap between requests system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states system.physmem.memoryStateTime::REF 96924620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states +system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ) +system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.480430 # Core power per rank (mW) -system.physmem.averagePower::1 669.392372 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 70650 # Transaction distribution -system.membus.trans_dist::ReadResp 70650 # Transaction distribution +system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.480439 # Core power per rank (mW) +system.physmem.averagePower::1 669.392466 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 70649 # Transaction distribution +system.membus.trans_dist::ReadResp 70649 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution system.membus.trans_dist::Writeback 82180 # Transaction distribution @@ -338,21 +338,21 @@ system.membus.trans_dist::UpgradeResp 4505 # Tr system.membus.trans_dist::ReadExReq 128451 # Transaction distribution system.membus.trans_dist::ReadExResp 128451 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 219 # Total snoops (count) system.membus.snoop_fanout::samples 281834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram @@ -367,13 +367,13 @@ system.membus.snoop_fanout::max_value 1 # Re system.membus.snoop_fanout::total 281834 # Request fanout histogram system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) @@ -604,20 +604,20 @@ system.cpu.itb.accesses 115610659 # DT system.cpu.numCycles 5805238262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112506996 # Number of instructions committed -system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses +system.cpu.committedInsts 112506995 # Number of instructions committed +system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses system.cpu.num_func_calls 9898964 # number of times a function call or return occured system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls -system.cpu.num_int_insts 119948924 # number of integer instructions +system.cpu.num_int_insts 119948923 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read -system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written +system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read +system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written +system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written system.cpu.num_mem_refs 45428231 # number of memory refs system.cpu.num_load_insts 24855392 # Number of load instructions system.cpu.num_store_insts 20572839 # Number of store instructions @@ -627,7 +627,7 @@ system.cpu.not_idle_fraction 0.072139 # Pe system.cpu.idle_fraction 0.927861 # Percentage of idle cycles system.cpu.Branches 25929456 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction @@ -660,7 +660,7 @@ system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Cl system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138771626 # Class of executed instruction +system.cpu.op_class::total 138771625 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed system.cpu.icache.tags.replacements 1699818 # number of replacements @@ -736,10 +736,10 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses @@ -837,18 +837,18 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses) @@ -902,18 +902,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -954,26 +954,26 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses @@ -1004,18 +1004,18 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1072,16 +1072,16 @@ system.cpu.dcache.overall_misses::cpu.data 820348 # system.cpu.dcache.overall_misses::total 820348 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses) @@ -1112,16 +1112,16 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -1156,24 +1156,24 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 817570 system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses @@ -1190,18 +1190,18 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1209,8 +1209,8 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution @@ -1220,16 +1220,16 @@ system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 52963 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram @@ -1246,13 +1246,13 @@ system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index c44b0a7f7..72e487329 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -37,13 +37,13 @@ load_offset=2147483648 machine_type=VExpress_EMM mem_mode=atomic mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram +memories=system.realview.nvmem system.physmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr index cf30e237d..6291714a8 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr @@ -38,7 +38,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index 0605672c9..4a0c68df7 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 16:00:04 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:27:15 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x50c1b00 0x50c1b00 - 0: system.cpu1.isa: ISA system set to: 0x50c1b00 0x50c1b00 + 0: system.cpu0.isa: ISA system set to: 0x4171680 0x4171680 + 0: system.cpu1.isa: ISA system set to: 0x4171680 0x4171680 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 863689702..b1c7d16c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,93 +1,93 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783853 # Number of seconds simulated -sim_ticks 2783853461500 # Number of ticks simulated -final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783854 # Number of seconds simulated +sim_ticks 2783854177000 # Number of ticks simulated +final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1402368 # Simulator instruction rate (inst/s) -host_op_rate 1707157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27344724772 # Simulator tick rate (ticks/s) -host_mem_usage 555568 # Number of bytes of host memory used -host_seconds 101.81 # Real time elapsed on the host -sim_insts 142769281 # Number of instructions simulated -sim_ops 173798567 # Number of ops (including micro ops) simulated +host_inst_rate 1241693 # Simulator instruction rate (inst/s) +host_op_rate 1511561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24211403286 # Simulator tick rate (ticks/s) +host_mem_usage 555676 # Number of bytes of host memory used +host_seconds 114.98 # Real time elapsed on the host +sim_insts 142771179 # Number of instructions simulated +sim_ops 173800939 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 727076 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4668128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 726948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4668448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 483904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5677444 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 484032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5677124 # Number of bytes read from this memory system.physmem.bytes_read::total 11558024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 727076 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 483904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 726948 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 484032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521088 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6521152 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8856948 # Number of bytes written to this memory +system.physmem.bytes_written::total 8857012 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19812 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73463 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7561 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88706 # Number of read requests responded to by this memory system.physmem.num_reads::total 189567 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101892 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 101893 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142497 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142498 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 261176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1676858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 261130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1676973 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 173825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2039419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 261176 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 173825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 173871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2039304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4151807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 261130 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 173871 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342468 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2342491 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2342491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 261176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1683150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 261130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1683265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 173825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2039422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333350 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74230 # Transaction distribution -system.membus.trans_dist::ReadResp 74230 # Transaction distribution +system.physmem.bw_total::cpu1.inst 173871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2039307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333371 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74229 # Transaction distribution +system.membus.trans_dist::ReadResp 74229 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101892 # Transaction distribution +system.membus.trans_dist::Writeback 101893 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -96,48 +96,48 @@ system.membus.trans_dist::UpgradeResp 4509 # Tr system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498777 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 606179 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679107 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258695 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18258755 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20592391 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20592451 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322845 # Request fanout histogram +system.membus.snoop_fanout::samples 322846 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322845 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 322846 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322845 # Request fanout histogram +system.membus.snoop_fanout::total 322846 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 110021 # number of replacements -system.l2c.tags.tagsinuse 65155.315266 # Cycle average of tags in use -system.l2c.tags.total_refs 2731077 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65155.315046 # Cycle average of tags in use +system.l2c.tags.total_refs 2731069 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.579269 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 15.579223 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.451407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48893.450806 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.249806 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.238472 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5044.246169 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.238625 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4020.297746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.174711 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4020.301933 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2464.174390 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -157,143 +157,143 @@ system.l2c.tags.age_task_id_blocks_1024::3 10700 # system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26229754 # Number of tag accesses -system.l2c.tags.data_accesses 26229754 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4715 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2286 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833389 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4988 # number of ReadReq hits +system.l2c.tags.tag_accesses 26229699 # Number of tag accesses +system.l2c.tags.data_accesses 26229699 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4718 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 833258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 246713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4981 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 258725 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201051 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682262 # number of Writeback hits -system.l2c.Writeback_hits::total 682262 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 847891 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 258771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2201046 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682259 # number of Writeback hits +system.l2c.Writeback_hits::total 682259 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72309 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78732 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151041 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4715 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319080 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4988 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::cpu0.data 72299 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151042 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4718 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2285 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 319012 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4981 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847748 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337457 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352092 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4715 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2286 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833389 # number of overall hits -system.l2c.overall_hits::cpu0.data 319080 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4988 # number of overall hits +system.l2c.demand_hits::cpu1.inst 847891 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337514 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352088 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4718 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2285 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833258 # number of overall hits +system.l2c.overall_hits::cpu0.data 319012 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4981 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847748 # number of overall hits -system.l2c.overall_hits::cpu1.data 337457 # number of overall hits -system.l2c.overall_hits::total 2352092 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847891 # number of overall hits +system.l2c.overall_hits::cpu1.data 337514 # number of overall hits +system.l2c.overall_hits::total 2352088 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10797 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9751 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10795 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9750 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7561 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5778 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 7563 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5779 # number of ReadReq misses system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1248 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1480 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63966 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83898 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63973 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83891 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10797 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73717 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10795 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73723 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89676 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89670 # number of demand (read+write) misses system.l2c.demand_misses::total 181759 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10797 # number of overall misses -system.l2c.overall_misses::cpu0.data 73717 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10795 # number of overall misses +system.l2c.overall_misses::cpu0.data 73723 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7561 # number of overall misses -system.l2c.overall_misses::cpu1.data 89676 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7563 # number of overall misses +system.l2c.overall_misses::cpu1.data 89670 # number of overall misses system.l2c.overall_misses::total 181759 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4720 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2287 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844186 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256522 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4990 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4723 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2286 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844053 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 256463 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4983 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855309 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264503 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2234946 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682262 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682262 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1260 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1496 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 855454 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 264550 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2234941 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682259 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682259 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1261 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136275 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162630 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4720 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2287 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844186 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392797 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4990 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 136272 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162634 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4723 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2286 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844053 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392735 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4983 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855309 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427133 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533851 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4720 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2287 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844186 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392797 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4990 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855454 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427184 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533847 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4723 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2286 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844053 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392735 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4983 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855309 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427133 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533851 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855454 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427184 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533847 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.012790 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038012 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.012789 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038017 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008841 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.021845 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989305 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989298 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469389 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515883 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469451 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515827 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012790 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187672 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012789 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187717 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008840 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209949 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008841 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209910 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012790 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187672 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012789 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187717 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008840 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209949 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008841 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209910 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -303,8 +303,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101892 # number of writebacks -system.l2c.writebacks::total 101892 # number of writebacks +system.l2c.writebacks::writebacks 101893 # number of writebacks +system.l2c.writebacks::total 101893 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -343,28 +343,28 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2291806 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291806 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2291797 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291797 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682262 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682259 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417070 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444902 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20772 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41576 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924320 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323083 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41544 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205252639 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417092 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41564 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5924301 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96322187 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205252475 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36632 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272100 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3272090 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -373,12 +373,12 @@ system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3235636 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3235626 98.89% 98.89% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272100 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3272090 # Request fanout histogram system.iobus.trans_dist::ReadReq 30171 # Transaction distribution system.iobus.trans_dist::ReadResp 30171 # Transaction distribution system.iobus.trans_dist::WriteReq 59016 # Transaction distribution @@ -457,25 +457,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997245 # DTB read hits -system.cpu0.dtb.read_misses 4798 # DTB read misses -system.cpu0.dtb.write_hits 11281299 # DTB write hits -system.cpu0.dtb.write_misses 897 # DTB write misses -system.cpu0.dtb.flush_tlb 2812 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 15997157 # DTB read hits +system.cpu0.dtb.read_misses 4809 # DTB read misses +system.cpu0.dtb.write_hits 11281332 # DTB write hits +system.cpu0.dtb.write_misses 894 # DTB write misses +system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3224 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 779 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16002043 # DTB read accesses -system.cpu0.dtb.write_accesses 11282196 # DTB write accesses +system.cpu0.dtb.read_accesses 16001966 # DTB read accesses +system.cpu0.dtb.write_accesses 11282226 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278544 # DTB hits -system.cpu0.dtb.misses 5695 # DTB misses -system.cpu0.dtb.accesses 27284239 # DTB accesses +system.cpu0.dtb.hits 27278489 # DTB hits +system.cpu0.dtb.misses 5703 # DTB misses +system.cpu0.dtb.accesses 27284192 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -497,55 +497,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 74797989 # ITB inst hits +system.cpu0.itb.inst_hits 74798311 # ITB inst hits system.cpu0.itb.inst_misses 2590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2812 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1905 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74800579 # ITB inst accesses -system.cpu0.itb.hits 74797989 # DTB hits +system.cpu0.itb.inst_accesses 74800901 # ITB inst accesses +system.cpu0.itb.hits 74798311 # DTB hits system.cpu0.itb.misses 2590 # DTB misses -system.cpu0.itb.accesses 74800579 # DTB accesses -system.cpu0.numCycles 5536445370 # number of cpu cycles simulated +system.cpu0.itb.accesses 74800901 # DTB accesses +system.cpu0.numCycles 5536444793 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72639024 # Number of instructions committed -system.cpu0.committedOps 87981151 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77491342 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses -system.cpu0.num_func_calls 8694279 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9459647 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77491342 # number of integer instructions -system.cpu0.num_fp_insts 5273 # number of float instructions -system.cpu0.num_int_register_reads 144069707 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447285 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read +system.cpu0.committedInsts 72639683 # Number of instructions committed +system.cpu0.committedOps 87981695 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77491900 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses +system.cpu0.num_func_calls 8694354 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9459791 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77491900 # number of integer instructions +system.cpu0.num_fp_insts 5289 # number of float instructions +system.cpu0.num_int_register_reads 144070444 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54447556 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268877072 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31833969 # number of times the CC registers were written -system.cpu0.num_mem_refs 27909499 # number of memory refs -system.cpu0.num_load_insts 16164843 # Number of load instructions -system.cpu0.num_store_insts 11744656 # Number of store instructions -system.cpu0.num_idle_cycles 5353619097.982533 # Number of idle cycles -system.cpu0.num_busy_cycles 182826272.017466 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles -system.cpu0.Branches 18600717 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2187 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61776214 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59687 0.07% 68.90% # Class of executed instruction +system.cpu0.num_cc_register_reads 268879109 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31834194 # number of times the CC registers were written +system.cpu0.num_mem_refs 27909453 # number of memory refs +system.cpu0.num_load_insts 16164742 # Number of load instructions +system.cpu0.num_store_insts 11744711 # Number of store instructions +system.cpu0.num_idle_cycles 5353616970.490369 # Number of idle cycles +system.cpu0.num_busy_cycles 182827822.509631 # Number of busy cycles +system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles +system.cpu0.Branches 18600859 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61776837 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction @@ -569,27 +569,27 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16164843 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11744656 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16164742 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11744711 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89752000 # Class of executed instruction +system.cpu0.op_class::total 89752572 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1698994 # number of replacements +system.cpu0.icache.tags.replacements 1699006 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145339246 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.122338 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.541342 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888911 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110432 # Average percentage of cache occupancy +system.cpu0.icache.tags.total_refs 145341254 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121642 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542037 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -597,43 +597,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148738270 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148738270 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73955669 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71383577 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145339246 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73955669 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71383577 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145339246 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73955669 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71383577 # number of overall hits -system.cpu0.icache.overall_hits::total 145339246 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844195 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855317 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699512 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844195 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855317 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699512 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844195 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855317 # number of overall misses -system.cpu0.icache.overall_misses::total 1699512 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799864 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72238894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74799864 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72238894 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74799864 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72238894 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011286 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011840 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 148740302 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148740302 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73956125 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71385129 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145341254 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73956125 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71385129 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145341254 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73956125 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71385129 # number of overall hits +system.cpu0.icache.overall_hits::total 145341254 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844062 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855462 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699524 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844062 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855462 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699524 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844062 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855462 # number of overall misses +system.cpu0.icache.overall_misses::total 1699524 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74800187 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72240591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74800187 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72240591 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74800187 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72240591 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011286 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011840 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011286 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011840 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -644,105 +644,105 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 819402 # number of replacements +system.cpu0.dcache.tags.replacements 819391 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53782968 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.595865 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.832873 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.164301 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929361 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070633 # Average percentage of cache occupancy +system.cpu0.dcache.tags.total_refs 53783615 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819903 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597534 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830642 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219231522 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219231522 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305372 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14822853 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128225 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894245 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445267 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185732 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209303 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395035 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234999 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222317 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219234055 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219234055 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305331 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14823339 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128670 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10894284 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445424 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185757 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209284 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395041 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234994 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222322 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236700 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223422 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236693 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223429 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26199617 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26268120 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52467737 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385349 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26477423 # number of overall hits -system.cpu0.dcache.overall_hits::total 52862772 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197486 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198842 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396328 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137535 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164126 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301661 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54372 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61696 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116068 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4664 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3965 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26199615 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26268763 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468378 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385372 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26478047 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863419 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197455 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198864 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396319 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137533 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164129 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301662 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61720 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116065 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4663 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362968 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697989 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389393 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424664 # number of overall misses -system.cpu0.dcache.overall_misses::total 814057 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502858 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021695 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609393 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270999 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511103 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239663 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 334988 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 362993 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697981 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389333 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424713 # number of overall misses +system.cpu0.dcache.overall_misses::total 814046 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502786 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022203 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031817 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609553 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240102 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511106 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239657 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226288 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236700 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223424 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236693 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223431 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26534638 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631088 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26774742 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26902087 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53676829 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012739 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013237 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.012984 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26534603 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631756 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26774705 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26902760 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677465 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012737 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012467 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014137 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226452 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227661 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227093 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019461 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017522 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226341 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227746 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227086 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012626 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.013129 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014543 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013630 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014541 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015787 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -752,8 +752,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682262 # number of writebacks -system.cpu0.dcache.writebacks::total 682262 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682259 # number of writebacks +system.cpu0.dcache.writebacks::total 682259 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -778,25 +778,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15526476 # DTB read hits -system.cpu1.dtb.read_misses 5406 # DTB read misses -system.cpu1.dtb.write_hits 11842298 # DTB write hits -system.cpu1.dtb.write_misses 791 # DTB write misses -system.cpu1.dtb.flush_tlb 2818 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 15527003 # DTB read hits +system.cpu1.dtb.read_misses 5395 # DTB read misses +system.cpu1.dtb.write_hits 11842462 # DTB write hits +system.cpu1.dtb.write_misses 794 # DTB write misses +system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3194 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 923 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15531882 # DTB read accesses -system.cpu1.dtb.write_accesses 11843089 # DTB write accesses +system.cpu1.dtb.read_accesses 15532398 # DTB read accesses +system.cpu1.dtb.write_accesses 11843256 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27368774 # DTB hits -system.cpu1.dtb.misses 6197 # DTB misses -system.cpu1.dtb.accesses 27374971 # DTB accesses +system.cpu1.dtb.hits 27369465 # DTB hits +system.cpu1.dtb.misses 6189 # DTB misses +system.cpu1.dtb.accesses 27375654 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -818,55 +818,55 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 72236782 # ITB inst hits -system.cpu1.itb.inst_misses 3052 # ITB inst misses +system.cpu1.itb.inst_hits 72238481 # ITB inst hits +system.cpu1.itb.inst_misses 3051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2818 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2023 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72239834 # ITB inst accesses -system.cpu1.itb.hits 72236782 # DTB hits -system.cpu1.itb.misses 3052 # DTB misses -system.cpu1.itb.accesses 72239834 # DTB accesses -system.cpu1.numCycles 88012648 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72241532 # ITB inst accesses +system.cpu1.itb.hits 72238481 # DTB hits +system.cpu1.itb.misses 3051 # DTB misses +system.cpu1.itb.accesses 72241532 # DTB accesses +system.cpu1.numCycles 88014935 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 70130257 # Number of instructions committed -system.cpu1.committedOps 85817416 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75667160 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses -system.cpu1.num_func_calls 8179026 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9270368 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75667160 # number of integer instructions -system.cpu1.num_fp_insts 6211 # number of float instructions -system.cpu1.num_int_register_reads 140982352 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52729123 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read +system.cpu1.committedInsts 70131496 # Number of instructions committed +system.cpu1.committedOps 85819244 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75668739 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses +system.cpu1.num_func_calls 8179428 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9270456 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75668739 # number of integer instructions +system.cpu1.num_fp_insts 6195 # number of float instructions +system.cpu1.num_int_register_reads 140985899 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52730443 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261962982 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30529174 # number of times the CC registers were written -system.cpu1.num_mem_refs 28028313 # number of memory refs -system.cpu1.num_load_insts 15690218 # Number of load instructions -system.cpu1.num_store_insts 12338095 # Number of store instructions -system.cpu1.num_idle_cycles 85358107.940046 # Number of idle cycles -system.cpu1.num_busy_cycles 2654540.059954 # Number of busy cycles +system.cpu1.num_cc_register_reads 261968424 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30529611 # number of times the CC registers were written +system.cpu1.num_mem_refs 28028993 # number of memory refs +system.cpu1.num_load_insts 15690755 # Number of load instructions +system.cpu1.num_store_insts 12338238 # Number of store instructions +system.cpu1.num_idle_cycles 85360290.427990 # Number of idle cycles +system.cpu1.num_busy_cycles 2654644.572010 # Number of busy cycles system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles -system.cpu1.Branches 17795350 # Number of branches fetched -system.cpu1.op_class::No_OpClass 150 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59373450 67.88% 67.88% # Class of executed instruction -system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction +system.cpu1.Branches 17795920 # Number of branches fetched +system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59374689 67.88% 67.88% # Class of executed instruction +system.cpu1.op_class::IntMult 57198 0.07% 67.95% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction @@ -890,24 +890,24 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::MemRead 15690218 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12338095 14.11% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15690755 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12338238 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87463263 # Class of executed instruction +system.cpu1.op_class::total 87465184 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |