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authorSteve Reinhardt <steve.reinhardt@amd.com>2009-05-11 10:38:46 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2009-05-11 10:38:46 -0700
commitb174ec065e2b9f8ffa68c350b2563819eef5e9b1 (patch)
tree247eaf664b887559a1575d0733daa2179741bcd2 /tests/quick
parent6df61e1f2409e336dc4ae68eaeae7d0638e65a9d (diff)
downloadgem5-b174ec065e2b9f8ffa68c350b2563819eef5e9b1.tar.xz
ruby: Initial references for ruby regressions
Diffstat (limited to 'tests/quick')
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/config.ini98
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/ruby.stats795
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simout24
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/stats.txt50
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini95
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats823
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout24
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt50
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/config.ini98
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/ruby.stats795
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simerr5
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simout24
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/stats.txt50
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini95
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats823
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr5
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout24
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt50
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/config.ini152
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout24
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt36
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini149
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout24
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt36
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/config.ini98
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/ruby.stats795
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simout22
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini95
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats823
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr3
-rwxr-xr-xtests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout22
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini98
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats795
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr7
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout23
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini95
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats823
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr7
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout23
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt18
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/config.ini218
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/ruby.stats930
-rwxr-xr-xtests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simerr3
-rwxr-xr-xtests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simout94
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/stats.txt33
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini206
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats1004
-rwxr-xr-xtests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr3
-rwxr-xr-xtests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout94
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt33
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini169
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats1315
-rwxr-xr-xtests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr74
-rwxr-xr-xtests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout22
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt34
63 files changed, 12397 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/config.ini
new file mode 100644
index 000000000..5222463dc
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/config.ini
@@ -0,0 +1,98 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/ruby.stats
new file mode 100644
index 000000000..b0c4de63b
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/ruby.stats
@@ -0,0 +1,795 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:51:11, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 1
+g_NUM_CHIP_BITS: 0
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 0
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 0
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 26
+g_MEMORY_MODULE_BLOCKS: 67108864
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 1
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 26
+ module_size_lines: 67108864
+ module_size_bytes: 4294967296
+ module_size_Kbytes: 4.1943e+06
+ module_size_Mbytes: 4096
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> Directory-0 net_lat: 5
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 5
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:03
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.15
+Virtual_time_in_minutes: 0.0025
+Virtual_time_in_hours: 4.16667e-05
+Virtual_time_in_days: 4.16667e-05
+
+Ruby_current_time: 3215001
+Ruby_start_time: 1
+Ruby_cycles: 3215000
+
+mbytes_resident: 34.6523
+mbytes_total: 195.43
+resident_ratio: 0.177334
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+instruction_executed: 1 [ 1 ]
+cycles_executed: 1 [ 1 ]
+cycles_per_instruction: 3.215e+06 [ 3.215e+06 ]
+misses_per_thousand_instructions: 0 [ 0 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+instructions_per_transaction: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 0
+ L1D_cache_total_demand_misses: 0
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 0
+ L1D_cache_misses_per_instruction: 0
+ L1D_cache_instructions_per_misses: NaN
+
+ L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 0
+ L1I_cache_total_demand_misses: 0
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 0
+ L1I_cache_misses_per_instruction: 0
+ L1I_cache_instructions_per_misses: NaN
+
+ L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 0
+ L2_cache_total_demand_misses: 0
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 0
+ L2_cache_misses_per_instruction: 0
+ L2_cache_instructions_per_misses: NaN
+
+ L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 9071
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 56
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0
+ links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0
+ links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0
+ links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
+
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 0
+Ifetch 0
+Store 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+L2_Replacement 0
+Own_GETS 0
+Own_GET_INSTR 0
+Own_GETX 0
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 0
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 0 <--
+IS_AD Own_GET_INSTR 0 <--
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 0 <--
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 0 <--
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 0 <--
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 0 <--
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 0 <--
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 0
+GET_INSTR 0
+GETX 0
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 0 <--
+C GET_INSTR 0 <--
+C GETX 0 <--
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 0 <--
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simout
new file mode 100755
index 000000000..c41d11015
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simout
@@ -0,0 +1,24 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:03
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 3215000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/stats.txt
new file mode 100644
index 000000000..217e6b915
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/stats.txt
@@ -0,0 +1,50 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 94038 # Simulator instruction rate (inst/s)
+host_mem_usage 200124 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 47099326 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 6404 # Number of instructions simulated
+sim_seconds 0.000003 # Number of seconds simulated
+sim_ticks 3215000 # Number of ticks simulated
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 6431 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 6414 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 6431 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
new file mode 100644
index 000000000..03c3b0b9d
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -0,0 +1,95 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
new file mode 100644
index 000000000..e9a5bcf83
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -0,0 +1,823 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:51:11, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 1
+g_NUM_CHIP_BITS: 0
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 0
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 0
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 26
+g_MEMORY_MODULE_BLOCKS: 67108864
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 1
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 26
+ module_size_lines: 67108864
+ module_size_bytes: 4294967296
+ module_size_Kbytes: 4.1943e+06
+ module_size_Mbytes: 4096
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> Directory-0 net_lat: 5
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 5
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:03
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.63
+Virtual_time_in_minutes: 0.0105
+Virtual_time_in_hours: 0.000175
+Virtual_time_in_days: 0.000175
+
+Ruby_current_time: 25390001
+Ruby_start_time: 1
+Ruby_cycles: 25390000
+
+mbytes_resident: 34.8633
+mbytes_total: 195.445
+resident_ratio: 0.178399
+
+Total_misses: 460
+total_misses: 460 [ 460 ]
+user_misses: 460 [ 460 ]
+supervisor_misses: 0 [ 0 ]
+
+instruction_executed: 1 [ 1 ]
+cycles_executed: 1 [ 1 ]
+cycles_per_instruction: 2.539e+07 [ 2.539e+07 ]
+misses_per_thousand_instructions: 460000 [ 460000 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+instructions_per_transaction: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 182
+ L1D_cache_total_demand_misses: 182
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 182
+ L1D_cache_misses_per_instruction: 182
+ L1D_cache_instructions_per_misses: 0.00549451
+
+ L1D_cache_request_type_LD: 52.1978%
+ L1D_cache_request_type_ST: 47.8022%
+
+ L1D_cache_access_mode_type_UserMode: 182 100%
+ L1D_cache_request_size: [binsize: log2 max: 8 count: 182 average: 7.58242 | standard deviation: 1.22812 | 0 0 0 19 163 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 279
+ L1I_cache_total_demand_misses: 279
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 279
+ L1I_cache_misses_per_instruction: 279
+ L1I_cache_instructions_per_misses: 0.00358423
+
+ L1I_cache_request_type_IFETCH: 100%
+
+ L1I_cache_access_mode_type_UserMode: 279 100%
+ L1I_cache_request_size: [binsize: log2 max: 4 count: 279 average: 4 | standard deviation: 0 | 0 0 0 279 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 460
+ L2_cache_total_demand_misses: 460
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 460
+ L2_cache_misses_per_instruction: 460
+ L2_cache_instructions_per_misses: 0.00217391
+
+ L2_cache_request_type_LD: 20.6522%
+ L2_cache_request_type_ST: 18.913%
+ L2_cache_request_type_IFETCH: 60.4348%
+
+ L2_cache_access_mode_type_UserMode: 460 100%
+ L2_cache_request_size: [binsize: log2 max: 8 count: 460 average: 5.41739 | standard deviation: 1.91542 | 0 0 0 297 163 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 460 average: 0 | standard deviation: 0 | 460 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 461 average: 1 | standard deviation: 0 | 0 461 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 176 count: 461 average: 173.761 | standard deviation: 8.04822 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 88 93 94 106 ]
+miss_latency_LD: [binsize: 1 max: 176 count: 95 average: 173.747 | standard deviation: 1.40667 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 22 17 18 14 ]
+miss_latency_ST: [binsize: 1 max: 176 count: 87 average: 174.069 | standard deviation: 1.38093 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 19 19 17 18 ]
+miss_latency_IFETCH: [binsize: 1 max: 176 count: 279 average: 173.67 | standard deviation: 10.29 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 47 57 59 74 ]
+miss_latency_NULL: [binsize: 1 max: 176 count: 461 average: 173.761 | standard deviation: 8.04822 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 88 93 94 106 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+conflicting_histogram: [binsize: log2 max: 25263004 count: 460 average: 1.08573e+07 | standard deviation: 1.22406e+07 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 2 4 4 12 8 10 39 75 48 123 133 ]
+conflicting_histogram_percent: [binsize: log2 max: 25263004 count: 460 average: 1.08573e+07 | standard deviation: 1.22406e+07 | 0 0 0 0.217391 0 0 0 0 0 0 0 0 0 0 0.217391 0.434783 0.869565 0.869565 2.6087 1.73913 2.17391 8.47826 16.3043 10.4348 26.7391 28.913 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+ NP C GETS 95 20.6522
+ NP C GETX 73 15.8696
+ NP C GET_INSTR 278 60.4348
+ S S GETX 14 3.04348
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 9125
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 64
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:461 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0.00144939
+ links_utilized_percent_switch_0_link_0: 0.00144939 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Control: 460 3680 [ 460 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0.0130445
+ links_utilized_percent_switch_1_link_0: 0.0130445 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Data: 460 33120 [ 0 460 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.00797164
+ links_utilized_percent_switch_2_link_0: 0.0144939 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.00144939 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 460 3680 [ 460 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Data: 460 33120 [ 0 460 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 460 3680 [ 460 0 0 0 ] base_latency: 1
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 95
+Ifetch 279
+Store 87
+L1_to_L2 1
+L2_to_L1D 0
+L2_to_L1I 1
+L2_Replacement 0
+Own_GETS 95
+Own_GET_INSTR 278
+Own_GETX 87
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 460
+
+ - Transitions -
+NP Load 95
+NP Ifetch 278
+NP Store 73
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 1
+S Store 14
+S L1_to_L2 1
+S L2_to_L1D 0 <--
+S L2_to_L1I 1
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 95
+IS_AD Own_GET_INSTR 278
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 73
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 14
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 373
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 73
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 14
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 95
+GET_INSTR 278
+GETX 87
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 95
+C GET_INSTR 278
+C GETX 73
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 14
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
new file mode 100755
index 000000000..c0ccb0caf
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -0,0 +1,24 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:03
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 25390000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
new file mode 100644
index 000000000..8021d3d79
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -0,0 +1,50 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 9868 # Simulator instruction rate (inst/s)
+host_mem_usage 200140 # Number of bytes of host memory used
+host_seconds 0.65 # Real time elapsed on the host
+host_tick_rate 39112264 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 6404 # Number of instructions simulated
+sim_seconds 0.000025 # Number of seconds simulated
+sim_ticks 25390000 # Number of ticks simulated
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 6432 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 6415 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 50780 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/config.ini
new file mode 100644
index 000000000..68be6a6d7
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/config.ini
@@ -0,0 +1,98 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/ruby.stats
new file mode 100644
index 000000000..b21a503a5
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/ruby.stats
@@ -0,0 +1,795 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:51:11, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 1
+g_NUM_CHIP_BITS: 0
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 0
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 0
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 26
+g_MEMORY_MODULE_BLOCKS: 67108864
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 1
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 26
+ module_size_lines: 67108864
+ module_size_bytes: 4294967296
+ module_size_Kbytes: 4.1943e+06
+ module_size_Mbytes: 4096
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> Directory-0 net_lat: 5
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 5
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:03
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.13
+Virtual_time_in_minutes: 0.00216667
+Virtual_time_in_hours: 3.61111e-05
+Virtual_time_in_days: 3.61111e-05
+
+Ruby_current_time: 1297501
+Ruby_start_time: 1
+Ruby_cycles: 1297500
+
+mbytes_resident: 33.3828
+mbytes_total: 194.5
+resident_ratio: 0.171654
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+instruction_executed: 1 [ 1 ]
+cycles_executed: 1 [ 1 ]
+cycles_per_instruction: 1.2975e+06 [ 1.2975e+06 ]
+misses_per_thousand_instructions: 0 [ 0 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+instructions_per_transaction: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 0
+ L1D_cache_total_demand_misses: 0
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 0
+ L1D_cache_misses_per_instruction: 0
+ L1D_cache_instructions_per_misses: NaN
+
+ L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 0
+ L1I_cache_total_demand_misses: 0
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 0
+ L1I_cache_misses_per_instruction: 0
+ L1I_cache_instructions_per_misses: NaN
+
+ L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 0
+ L2_cache_total_demand_misses: 0
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 0
+ L2_cache_misses_per_instruction: 0
+ L2_cache_instructions_per_misses: NaN
+
+ L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 8746
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 56
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0
+ links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0
+ links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0
+ links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
+
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 0
+Ifetch 0
+Store 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+L2_Replacement 0
+Own_GETS 0
+Own_GET_INSTR 0
+Own_GETX 0
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 0
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 0 <--
+IS_AD Own_GET_INSTR 0 <--
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 0 <--
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 0 <--
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 0 <--
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 0 <--
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 0 <--
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 0
+GET_INSTR 0
+GETX 0
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 0 <--
+C GET_INSTR 0 <--
+C GETX 0 <--
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 0 <--
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simerr
new file mode 100755
index 000000000..bb8489f81
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simerr
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simout
new file mode 100755
index 000000000..c9e547b05
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simout
@@ -0,0 +1,24 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:03
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 1297500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/stats.txt
new file mode 100644
index 000000000..e3f2255fa
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/stats.txt
@@ -0,0 +1,50 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 44606 # Simulator instruction rate (inst/s)
+host_mem_usage 199172 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 22395015 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2577 # Number of instructions simulated
+sim_seconds 0.000001 # Number of seconds simulated
+sim_ticks 1297500 # Number of ticks simulated
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2596 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2585 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 2596 # number of cpu cycles simulated
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_refs 717 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
new file mode 100644
index 000000000..ec68a9659
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -0,0 +1,95 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
new file mode 100644
index 000000000..c0e81e6d5
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -0,0 +1,823 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:51:11, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 1
+g_NUM_CHIP_BITS: 0
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 0
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 0
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 26
+g_MEMORY_MODULE_BLOCKS: 67108864
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 1
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 26
+ module_size_lines: 67108864
+ module_size_bytes: 4294967296
+ module_size_Kbytes: 4.1943e+06
+ module_size_Mbytes: 4096
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> Directory-0 net_lat: 5
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 5
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:03
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.27
+Virtual_time_in_minutes: 0.0045
+Virtual_time_in_hours: 7.5e-05
+Virtual_time_in_days: 7.5e-05
+
+Ruby_current_time: 9880001
+Ruby_start_time: 1
+Ruby_cycles: 9880000
+
+mbytes_resident: 33.5469
+mbytes_total: 194.562
+resident_ratio: 0.172442
+
+Total_misses: 256
+total_misses: 256 [ 256 ]
+user_misses: 256 [ 256 ]
+supervisor_misses: 0 [ 0 ]
+
+instruction_executed: 1 [ 1 ]
+cycles_executed: 1 [ 1 ]
+cycles_per_instruction: 9.88e+06 [ 9.88e+06 ]
+misses_per_thousand_instructions: 256000 [ 256000 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+instructions_per_transaction: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 93
+ L1D_cache_total_demand_misses: 93
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 93
+ L1D_cache_misses_per_instruction: 93
+ L1D_cache_instructions_per_misses: 0.0107527
+
+ L1D_cache_request_type_LD: 59.1398%
+ L1D_cache_request_type_ST: 40.8602%
+
+ L1D_cache_access_mode_type_UserMode: 93 100%
+ L1D_cache_request_size: [binsize: log2 max: 8 count: 93 average: 7.39785 | standard deviation: 1.44086 | 0 0 0 14 79 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 163
+ L1I_cache_total_demand_misses: 163
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 163
+ L1I_cache_misses_per_instruction: 163
+ L1I_cache_instructions_per_misses: 0.00613497
+
+ L1I_cache_request_type_IFETCH: 100%
+
+ L1I_cache_access_mode_type_UserMode: 163 100%
+ L1I_cache_request_size: [binsize: log2 max: 4 count: 163 average: 4 | standard deviation: 0 | 0 0 0 163 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 256
+ L2_cache_total_demand_misses: 256
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 256
+ L2_cache_misses_per_instruction: 256
+ L2_cache_instructions_per_misses: 0.00390625
+
+ L2_cache_request_type_LD: 21.4844%
+ L2_cache_request_type_ST: 14.8438%
+ L2_cache_request_type_IFETCH: 63.6719%
+
+ L2_cache_access_mode_type_UserMode: 256 100%
+ L2_cache_request_size: [binsize: log2 max: 8 count: 256 average: 5.23438 | standard deviation: 1.85134 | 0 0 0 177 79 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 256 average: 0 | standard deviation: 0 | 256 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 256 average: 1 | standard deviation: 0 | 0 256 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 176 count: 256 average: 173.977 | standard deviation: 1.39185 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 58 56 44 51 ]
+miss_latency_LD: [binsize: 1 max: 176 count: 55 average: 173.945 | standard deviation: 1.36761 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 12 14 9 10 ]
+miss_latency_ST: [binsize: 1 max: 176 count: 38 average: 174.105 | standard deviation: 1.33558 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 9 8 9 7 ]
+miss_latency_IFETCH: [binsize: 1 max: 176 count: 163 average: 173.957 | standard deviation: 1.42075 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 37 34 26 34 ]
+miss_latency_NULL: [binsize: 1 max: 176 count: 256 average: 173.977 | standard deviation: 1.39185 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 58 56 44 51 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+conflicting_histogram: [binsize: log2 max: 9843004 count: 256 average: 3.88873e+06 | standard deviation: 2.83442e+06 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 2 2 10 13 18 30 72 82 24 ]
+conflicting_histogram_percent: [binsize: log2 max: 9843004 count: 256 average: 3.88873e+06 | standard deviation: 2.83442e+06 | 0 0 0 0.390625 0 0 0 0 0 0 0 0 0 0 0.390625 0.390625 0.78125 0.78125 3.90625 5.07812 7.03125 11.7188 28.125 32.0312 9.375 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+ NP C GETS 55 21.4844
+ NP C GETX 27 10.5469
+ NP C GET_INSTR 163 63.6719
+ S S GETX 11 4.29688
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 8788
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 64
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:256 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0.00207287
+ links_utilized_percent_switch_0_link_0: 0.00207287 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Control: 256 2048 [ 256 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0.0186559
+ links_utilized_percent_switch_1_link_0: 0.0186559 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.0114008
+ links_utilized_percent_switch_2_link_0: 0.0207287 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.00207287 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 256 2048 [ 256 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 256 2048 [ 256 0 0 0 ] base_latency: 1
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 55
+Ifetch 163
+Store 38
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+L2_Replacement 0
+Own_GETS 55
+Own_GET_INSTR 163
+Own_GETX 38
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 256
+
+ - Transitions -
+NP Load 55
+NP Ifetch 163
+NP Store 27
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 11
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 55
+IS_AD Own_GET_INSTR 163
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 27
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 11
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 218
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 27
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 11
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 55
+GET_INSTR 163
+GETX 38
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 55
+C GET_INSTR 163
+C GETX 27
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 11
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
new file mode 100755
index 000000000..bb8489f81
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -0,0 +1,5 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
new file mode 100755
index 000000000..f8e31d27c
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -0,0 +1,24 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:03
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 9880000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
new file mode 100644
index 000000000..3fec94126
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -0,0 +1,50 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 6475 # Simulator instruction rate (inst/s)
+host_mem_usage 199236 # Number of bytes of host memory used
+host_seconds 0.40 # Real time elapsed on the host
+host_tick_rate 24815516 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2577 # Number of instructions simulated
+sim_seconds 0.000010 # Number of seconds simulated
+sim_ticks 9880000 # Number of ticks simulated
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 2586 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 19760 # number of cpu cycles simulated
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_refs 717 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/config.ini
new file mode 100644
index 000000000..5efc6e80b
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/config.ini
@@ -0,0 +1,152 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+CP0_Config=0
+CP0_Config1=0
+CP0_Config1_C2=false
+CP0_Config1_CA=false
+CP0_Config1_DA=0
+CP0_Config1_DL=0
+CP0_Config1_DS=0
+CP0_Config1_EP=false
+CP0_Config1_FP=false
+CP0_Config1_IA=0
+CP0_Config1_IL=0
+CP0_Config1_IS=0
+CP0_Config1_M=0
+CP0_Config1_MD=false
+CP0_Config1_MMU=0
+CP0_Config1_PC=false
+CP0_Config1_WR=false
+CP0_Config2=0
+CP0_Config2_M=false
+CP0_Config2_SA=0
+CP0_Config2_SL=0
+CP0_Config2_SS=0
+CP0_Config2_SU=0
+CP0_Config2_TA=0
+CP0_Config2_TL=0
+CP0_Config2_TS=0
+CP0_Config2_TU=0
+CP0_Config3=0
+CP0_Config3_DSPP=false
+CP0_Config3_LPA=false
+CP0_Config3_M=false
+CP0_Config3_MT=false
+CP0_Config3_SM=false
+CP0_Config3_SP=false
+CP0_Config3_TL=false
+CP0_Config3_VEIC=false
+CP0_Config3_VInt=false
+CP0_Config_AR=0
+CP0_Config_AT=0
+CP0_Config_BE=0
+CP0_Config_MT=0
+CP0_Config_VI=0
+CP0_EBase_CPUNum=0
+CP0_IntCtl_IPPCI=0
+CP0_IntCtl_IPTI=0
+CP0_PRId=0
+CP0_PRId_CompanyID=0
+CP0_PRId_CompanyOptions=0
+CP0_PRId_ProcessorID=1
+CP0_PRId_Revision=0
+CP0_PerfCtr_M=false
+CP0_PerfCtr_W=false
+CP0_SrsCtl_HSS=0
+CP0_WatchHi_M=false
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=MipsTLB
+size=64
+
+[system.cpu.itb]
+type=MipsTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout
new file mode 100755
index 000000000..f3f24cc9d
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout
@@ -0,0 +1,24 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:02
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/MIPS_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello World!
+Exiting @ tick 2828000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt
new file mode 100644
index 000000000..5eb6c9aa1
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt
@@ -0,0 +1,36 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 15454 # Simulator instruction rate (inst/s)
+host_mem_usage 201224 # Number of bytes of host memory used
+host_seconds 0.37 # Real time elapsed on the host
+host_tick_rate 7721818 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5656 # Number of instructions simulated
+sim_seconds 0.000003 # Number of seconds simulated
+sim_ticks 2828000 # Number of ticks simulated
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 5657 # number of cpu cycles simulated
+system.cpu.num_insts 5656 # Number of instructions executed
+system.cpu.num_refs 2055 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
new file mode 100644
index 000000000..66ce03a9c
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -0,0 +1,149 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+CP0_Config=0
+CP0_Config1=0
+CP0_Config1_C2=false
+CP0_Config1_CA=false
+CP0_Config1_DA=0
+CP0_Config1_DL=0
+CP0_Config1_DS=0
+CP0_Config1_EP=false
+CP0_Config1_FP=false
+CP0_Config1_IA=0
+CP0_Config1_IL=0
+CP0_Config1_IS=0
+CP0_Config1_M=0
+CP0_Config1_MD=false
+CP0_Config1_MMU=0
+CP0_Config1_PC=false
+CP0_Config1_WR=false
+CP0_Config2=0
+CP0_Config2_M=false
+CP0_Config2_SA=0
+CP0_Config2_SL=0
+CP0_Config2_SS=0
+CP0_Config2_SU=0
+CP0_Config2_TA=0
+CP0_Config2_TL=0
+CP0_Config2_TS=0
+CP0_Config2_TU=0
+CP0_Config3=0
+CP0_Config3_DSPP=false
+CP0_Config3_LPA=false
+CP0_Config3_M=false
+CP0_Config3_MT=false
+CP0_Config3_SM=false
+CP0_Config3_SP=false
+CP0_Config3_TL=false
+CP0_Config3_VEIC=false
+CP0_Config3_VInt=false
+CP0_Config_AR=0
+CP0_Config_AT=0
+CP0_Config_BE=0
+CP0_Config_MT=0
+CP0_Config_VI=0
+CP0_EBase_CPUNum=0
+CP0_IntCtl_IPPCI=0
+CP0_IntCtl_IPTI=0
+CP0_PRId=0
+CP0_PRId_CompanyID=0
+CP0_PRId_CompanyOptions=0
+CP0_PRId_ProcessorID=1
+CP0_PRId_Revision=0
+CP0_PerfCtr_M=false
+CP0_PerfCtr_W=false
+CP0_SrsCtl_HSS=0
+CP0_WatchHi_M=false
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=MipsTLB
+size=64
+
+[system.cpu.itb]
+type=MipsTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
new file mode 100755
index 000000000..ff72f5189
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -0,0 +1,24 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:02
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/MIPS_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello World!
+Exiting @ tick 23131000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
new file mode 100644
index 000000000..05c9c2369
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -0,0 +1,36 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 10877 # Simulator instruction rate (inst/s)
+host_mem_usage 201300 # Number of bytes of host memory used
+host_seconds 0.52 # Real time elapsed on the host
+host_tick_rate 44468411 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5656 # Number of instructions simulated
+sim_seconds 0.000023 # Number of seconds simulated
+sim_ticks 23131000 # Number of ticks simulated
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 46262 # number of cpu cycles simulated
+system.cpu.num_insts 5656 # Number of instructions executed
+system.cpu.num_refs 2055 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/config.ini
new file mode 100644
index 000000000..e429a4f85
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/config.ini
@@ -0,0 +1,98 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/ruby.stats
new file mode 100644
index 000000000..20bce2784
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/ruby.stats
@@ -0,0 +1,795 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:54:24, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 1
+g_NUM_CHIP_BITS: 0
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 0
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 0
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 26
+g_MEMORY_MODULE_BLOCKS: 67108864
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 1
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 26
+ module_size_lines: 67108864
+ module_size_bytes: 4294967296
+ module_size_Kbytes: 4.1943e+06
+ module_size_Mbytes: 4096
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> Directory-0 net_lat: 5
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 5
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:03
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
+
+Virtual_time_in_seconds: 0.17
+Virtual_time_in_minutes: 0.00283333
+Virtual_time_in_hours: 4.72222e-05
+Virtual_time_in_days: 4.72222e-05
+
+Ruby_current_time: 2701001
+Ruby_start_time: 1
+Ruby_cycles: 2701000
+
+mbytes_resident: 34.9023
+mbytes_total: 196.324
+resident_ratio: 0.177799
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+instruction_executed: 1 [ 1 ]
+cycles_executed: 1 [ 1 ]
+cycles_per_instruction: 2.701e+06 [ 2.701e+06 ]
+misses_per_thousand_instructions: 0 [ 0 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+instructions_per_transaction: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 0
+ L1D_cache_total_demand_misses: 0
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 0
+ L1D_cache_misses_per_instruction: 0
+ L1D_cache_instructions_per_misses: NaN
+
+ L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 0
+ L1I_cache_total_demand_misses: 0
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 0
+ L1I_cache_misses_per_instruction: 0
+ L1I_cache_instructions_per_misses: NaN
+
+ L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 0
+ L2_cache_total_demand_misses: 0
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 0
+ L2_cache_misses_per_instruction: 0
+ L2_cache_instructions_per_misses: NaN
+
+ L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 9143
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 56
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0
+ links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0
+ links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0
+ links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
+
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 0
+Ifetch 0
+Store 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+L2_Replacement 0
+Own_GETS 0
+Own_GET_INSTR 0
+Own_GETX 0
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 0
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 0 <--
+IS_AD Own_GET_INSTR 0 <--
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 0 <--
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 0 <--
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 0 <--
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 0 <--
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 0 <--
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 0
+GET_INSTR 0
+GETX 0
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 0 <--
+C GET_INSTR 0 <--
+C GETX 0 <--
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 0 <--
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simout
new file mode 100755
index 000000000..462034fac
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simout
@@ -0,0 +1,22 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:02
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+Hello World!Exiting @ tick 2701000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/stats.txt
new file mode 100644
index 000000000..8137d6a2a
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 49084 # Simulator instruction rate (inst/s)
+host_mem_usage 201040 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
+host_tick_rate 24773225 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5340 # Number of instructions simulated
+sim_seconds 0.000003 # Number of seconds simulated
+sim_ticks 2701000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 5403 # number of cpu cycles simulated
+system.cpu.num_insts 5340 # Number of instructions executed
+system.cpu.num_refs 1402 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
new file mode 100644
index 000000000..4d7c09664
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -0,0 +1,95 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
new file mode 100644
index 000000000..9fe86b6fb
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -0,0 +1,823 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:54:24, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 1
+g_NUM_CHIP_BITS: 0
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 0
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 0
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 26
+g_MEMORY_MODULE_BLOCKS: 67108864
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 1
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 26
+ module_size_lines: 67108864
+ module_size_bytes: 4294967296
+ module_size_Kbytes: 4.1943e+06
+ module_size_Mbytes: 4096
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> Directory-0 net_lat: 5
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 5
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:03
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
+
+Virtual_time_in_seconds: 0.53
+Virtual_time_in_minutes: 0.00883333
+Virtual_time_in_hours: 0.000147222
+Virtual_time_in_days: 0.000147222
+
+Ruby_current_time: 20314001
+Ruby_start_time: 1
+Ruby_cycles: 20314000
+
+mbytes_resident: 35.0898
+mbytes_total: 196.461
+resident_ratio: 0.17863
+
+Total_misses: 404
+total_misses: 404 [ 404 ]
+user_misses: 404 [ 404 ]
+supervisor_misses: 0 [ 0 ]
+
+instruction_executed: 1 [ 1 ]
+cycles_executed: 1 [ 1 ]
+cycles_per_instruction: 2.0314e+07 [ 2.0314e+07 ]
+misses_per_thousand_instructions: 404000 [ 404000 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+instructions_per_transaction: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 150
+ L1D_cache_total_demand_misses: 150
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 150
+ L1D_cache_misses_per_instruction: 150
+ L1D_cache_instructions_per_misses: 0.00666667
+
+ L1D_cache_request_type_LD: 36%
+ L1D_cache_request_type_ST: 64%
+
+ L1D_cache_access_mode_type_UserMode: 150 100%
+ L1D_cache_request_size: [binsize: log2 max: 8 count: 150 average: 6.96 | standard deviation: 2.0067 | 0 6 1 27 116 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 257
+ L1I_cache_total_demand_misses: 257
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 257
+ L1I_cache_misses_per_instruction: 257
+ L1I_cache_instructions_per_misses: 0.00389105
+
+ L1I_cache_request_type_IFETCH: 100%
+
+ L1I_cache_access_mode_type_UserMode: 257 100%
+ L1I_cache_request_size: [binsize: log2 max: 4 count: 257 average: 4 | standard deviation: 0 | 0 0 0 257 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 404
+ L2_cache_total_demand_misses: 404
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 404
+ L2_cache_misses_per_instruction: 404
+ L2_cache_instructions_per_misses: 0.00247525
+
+ L2_cache_request_type_LD: 13.1188%
+ L2_cache_request_type_ST: 23.7624%
+ L2_cache_request_type_IFETCH: 63.1188%
+
+ L2_cache_access_mode_type_UserMode: 404 100%
+ L2_cache_request_size: [binsize: log2 max: 8 count: 404 average: 5.09901 | standard deviation: 1.88174 | 0 6 1 281 116 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 404 average: 0 | standard deviation: 0 | 404 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 407 average: 1 | standard deviation: 0 | 0 407 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 176 count: 407 average: 172.84 | standard deviation: 14.6349 | 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 82 83 78 91 ]
+miss_latency_LD: [binsize: 1 max: 176 count: 54 average: 170.907 | standard deviation: 23.1838 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 7 13 12 10 ]
+miss_latency_ST: [binsize: 1 max: 176 count: 96 average: 173.948 | standard deviation: 1.42533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 26 20 11 22 ]
+miss_latency_IFETCH: [binsize: 1 max: 176 count: 257 average: 172.833 | standard deviation: 15.0465 | 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42 49 50 55 59 ]
+miss_latency_NULL: [binsize: 1 max: 176 count: 407 average: 172.84 | standard deviation: 14.6349 | 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 82 83 78 91 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+conflicting_histogram: [binsize: log2 max: 20310004 count: 404 average: 9.51695e+06 | standard deviation: 1.23775e+07 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 5 7 4 10 30 62 66 156 61 ]
+conflicting_histogram_percent: [binsize: log2 max: 20310004 count: 404 average: 9.51695e+06 | standard deviation: 1.23775e+07 | 0 0 0 0.247525 0 0 0 0 0 0 0 0 0 0 0.247525 0 0.247525 1.23762 1.73267 0.990099 2.47525 7.42574 15.3465 16.3366 38.6139 15.099 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+ NP C GETS 53 13.1188
+ NP C GETX 81 20.0495
+ NP C GET_INSTR 255 63.1188
+ S S GETX 15 3.71287
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 9192
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 64
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:407 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0.00159102
+ links_utilized_percent_switch_0_link_0: 0.00159102 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Control: 404 3232 [ 404 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0.0143192
+ links_utilized_percent_switch_1_link_0: 0.0143192 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Data: 404 29088 [ 0 404 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.00875062
+ links_utilized_percent_switch_2_link_0: 0.0159102 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.00159102 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 404 3232 [ 404 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Data: 404 29088 [ 0 404 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 404 3232 [ 404 0 0 0 ] base_latency: 1
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 54
+Ifetch 257
+Store 96
+L1_to_L2 3
+L2_to_L1D 1
+L2_to_L1I 2
+L2_Replacement 0
+Own_GETS 53
+Own_GET_INSTR 255
+Own_GETX 96
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 404
+
+ - Transitions -
+NP Load 53
+NP Ifetch 255
+NP Store 81
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 1
+S Ifetch 2
+S Store 15
+S L1_to_L2 3
+S L2_to_L1D 1
+S L2_to_L1I 2
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 53
+IS_AD Own_GET_INSTR 255
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 81
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 15
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 308
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 81
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 15
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 53
+GET_INSTR 255
+GETX 96
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 53
+C GET_INSTR 255
+C GETX 81
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 15
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
new file mode 100755
index 000000000..d86f8a670
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -0,0 +1,22 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:02
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+Hello World!Exiting @ tick 20314000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
new file mode 100644
index 000000000..11c0e1cfa
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 11636 # Simulator instruction rate (inst/s)
+host_mem_usage 201180 # Number of bytes of host memory used
+host_seconds 0.46 # Real time elapsed on the host
+host_tick_rate 44246862 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5340 # Number of instructions simulated
+sim_seconds 0.000020 # Number of seconds simulated
+sim_ticks 20314000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 40628 # number of cpu cycles simulated
+system.cpu.num_insts 5340 # Number of instructions executed
+system.cpu.num_refs 1402 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini
new file mode 100644
index 000000000..15433dc70
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini
@@ -0,0 +1,98 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats
new file mode 100644
index 000000000..2d4628d32
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats
@@ -0,0 +1,795 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:56:05, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 1
+g_NUM_CHIP_BITS: 0
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 0
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 0
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 26
+g_MEMORY_MODULE_BLOCKS: 67108864
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 1
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 26
+ module_size_lines: 67108864
+ module_size_bytes: 4294967296
+ module_size_Kbytes: 4.1943e+06
+ module_size_Mbytes: 4096
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> Directory-0 net_lat: 5
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 5
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:04
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
+
+Virtual_time_in_seconds: 0.24
+Virtual_time_in_minutes: 0.004
+Virtual_time_in_hours: 6.66667e-05
+Virtual_time_in_days: 6.66667e-05
+
+Ruby_current_time: 5491501
+Ruby_start_time: 1
+Ruby_cycles: 5491500
+
+mbytes_resident: 34.8438
+mbytes_total: 196.57
+resident_ratio: 0.177278
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+instruction_executed: 1 [ 1 ]
+cycles_executed: 1 [ 1 ]
+cycles_per_instruction: 5.4915e+06 [ 5.4915e+06 ]
+misses_per_thousand_instructions: 0 [ 0 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+instructions_per_transaction: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 0
+ L1D_cache_total_demand_misses: 0
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 0
+ L1D_cache_misses_per_instruction: 0
+ L1D_cache_instructions_per_misses: NaN
+
+ L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 0
+ L1I_cache_total_demand_misses: 0
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 0
+ L1I_cache_misses_per_instruction: 0
+ L1I_cache_instructions_per_misses: NaN
+
+ L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 0
+ L2_cache_total_demand_misses: 0
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 0
+ L2_cache_misses_per_instruction: 0
+ L2_cache_instructions_per_misses: NaN
+
+ L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 9117
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 56
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0
+ links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0
+ links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0
+ links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
+
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 0
+Ifetch 0
+Store 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+L2_Replacement 0
+Own_GETS 0
+Own_GET_INSTR 0
+Own_GETX 0
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 0
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 0 <--
+IS_AD Own_GET_INSTR 0 <--
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 0 <--
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 0 <--
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 0 <--
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 0 <--
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 0 <--
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 0
+GET_INSTR 0
+GETX 0
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 0 <--
+C GET_INSTR 0 <--
+C GETX 0 <--
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 0 <--
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr
new file mode 100755
index 000000000..94d399eab
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr
@@ -0,0 +1,7 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: instruction 'fnstcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+warn: instruction 'fldcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout
new file mode 100755
index 000000000..4af11d154
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout
@@ -0,0 +1,23 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:01
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:03
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/X86_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 5491500 because target called exit()
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt
new file mode 100644
index 000000000..e7781d22f
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 67050 # Simulator instruction rate (inst/s)
+host_mem_usage 201292 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
+host_tick_rate 38741287 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 9494 # Number of instructions simulated
+sim_seconds 0.000005 # Number of seconds simulated
+sim_ticks 5491500 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 10984 # number of cpu cycles simulated
+system.cpu.num_insts 9494 # Number of instructions executed
+system.cpu.num_refs 1987 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
new file mode 100644
index 000000000..40ba46c85
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -0,0 +1,95 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=1
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
new file mode 100644
index 000000000..73b9cd0eb
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -0,0 +1,823 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:56:05, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 1
+g_NUM_CHIP_BITS: 0
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 0
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 0
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 26
+g_MEMORY_MODULE_BLOCKS: 67108864
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 1
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 26
+ module_size_lines: 67108864
+ module_size_bytes: 4294967296
+ module_size_Kbytes: 4.1943e+06
+ module_size_Mbytes: 4096
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> Directory-0 net_lat: 5
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 5
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:04
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
+
+Virtual_time_in_seconds: 0.54
+Virtual_time_in_minutes: 0.009
+Virtual_time_in_hours: 0.00015
+Virtual_time_in_days: 0.00015
+
+Ruby_current_time: 26617001
+Ruby_start_time: 1
+Ruby_cycles: 26617000
+
+mbytes_resident: 35.0547
+mbytes_total: 196.652
+resident_ratio: 0.178277
+
+Total_misses: 379
+total_misses: 379 [ 379 ]
+user_misses: 379 [ 379 ]
+supervisor_misses: 0 [ 0 ]
+
+instruction_executed: 1 [ 1 ]
+cycles_executed: 1 [ 1 ]
+cycles_per_instruction: 2.6617e+07 [ 2.6617e+07 ]
+misses_per_thousand_instructions: 379000 [ 379000 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+instructions_per_transaction: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 152
+ L1D_cache_total_demand_misses: 152
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 152
+ L1D_cache_misses_per_instruction: 152
+ L1D_cache_instructions_per_misses: 0.00657895
+
+ L1D_cache_request_type_LD: 35.5263%
+ L1D_cache_request_type_ST: 64.4737%
+
+ L1D_cache_access_mode_type_UserMode: 152 100%
+ L1D_cache_request_size: [binsize: log2 max: 8 count: 152 average: 7.09868 | standard deviation: 1.89457 | 0 5 1 24 122 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 228
+ L1I_cache_total_demand_misses: 228
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 228
+ L1I_cache_misses_per_instruction: 228
+ L1I_cache_instructions_per_misses: 0.00438596
+
+ L1I_cache_request_type_IFETCH: 100%
+
+ L1I_cache_access_mode_type_UserMode: 228 100%
+ L1I_cache_request_size: [binsize: log2 max: 8 count: 228 average: 8 | standard deviation: 0 | 0 0 0 0 228 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 379
+ L2_cache_total_demand_misses: 379
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 379
+ L2_cache_misses_per_instruction: 379
+ L2_cache_instructions_per_misses: 0.00263852
+
+ L2_cache_request_type_LD: 14.248%
+ L2_cache_request_type_ST: 25.8575%
+ L2_cache_request_type_IFETCH: 59.8945%
+
+ L2_cache_access_mode_type_UserMode: 379 100%
+ L2_cache_request_size: [binsize: log2 max: 8 count: 379 average: 7.63852 | standard deviation: 1.27657 | 0 5 1 24 349 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0
+Directory-0:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 379 average: 0 | standard deviation: 0 | 379 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 380 average: 1 | standard deviation: 0 | 0 380 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 176 count: 380 average: 173.629 | standard deviation: 8.8352 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 80 80 73 82 ]
+miss_latency_LD: [binsize: 1 max: 176 count: 54 average: 174.241 | standard deviation: 1.30312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 10 15 11 12 ]
+miss_latency_ST: [binsize: 1 max: 176 count: 98 average: 174.102 | standard deviation: 1.52302 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 22 16 12 29 ]
+miss_latency_IFETCH: [binsize: 1 max: 176 count: 228 average: 173.281 | standard deviation: 11.3419 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39 48 49 50 41 ]
+miss_latency_NULL: [binsize: 1 max: 176 count: 380 average: 173.629 | standard deviation: 8.8352 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 80 80 73 82 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+conflicting_histogram: [binsize: log2 max: 26583004 count: 379 average: 1.21441e+07 | standard deviation: 1.42032e+07 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 2 8 10 9 22 55 62 52 155 ]
+conflicting_histogram_percent: [binsize: log2 max: 26583004 count: 379 average: 1.21441e+07 | standard deviation: 1.42032e+07 | 0 0 0 0.263852 0 0 0 0 0 0 0 0 0 0 0.263852 0.263852 0.263852 0.527704 2.11082 2.63852 2.37467 5.80475 14.5119 16.3588 13.7203 40.8971 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+ NP C GETS 54 14.248
+ NP C GETX 79 20.8443
+ NP C GET_INSTR 227 59.8945
+ S S GETX 19 5.01319
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 0
+system_time: 0
+page_reclaims: 9171
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 64
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:380 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0.00113912
+ links_utilized_percent_switch_0_link_0: 0.00113912 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Control: 379 3032 [ 379 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0.0102521
+ links_utilized_percent_switch_1_link_0: 0.0102521 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Data: 379 27288 [ 0 379 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 0.00626517
+ links_utilized_percent_switch_2_link_0: 0.0113912 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.00113912 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 379 3032 [ 379 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Data: 379 27288 [ 0 379 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 379 3032 [ 379 0 0 0 ] base_latency: 1
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 54
+Ifetch 228
+Store 98
+L1_to_L2 1
+L2_to_L1D 0
+L2_to_L1I 1
+L2_Replacement 0
+Own_GETS 54
+Own_GET_INSTR 227
+Own_GETX 98
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 379
+
+ - Transitions -
+NP Load 54
+NP Ifetch 227
+NP Store 79
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 1
+S Store 19
+S L1_to_L2 1
+S L2_to_L1D 0 <--
+S L2_to_L1I 1
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 54
+IS_AD Own_GET_INSTR 227
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 79
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 19
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 281
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 79
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 19
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 54
+GET_INSTR 227
+GETX 98
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 54
+C GET_INSTR 227
+C GETX 79
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 19
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
new file mode 100755
index 000000000..94d399eab
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
@@ -0,0 +1,7 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: instruction 'fnstcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+warn: instruction 'fldcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
new file mode 100755
index 000000000..458aad3f6
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -0,0 +1,23 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:01
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:03
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/X86_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 1
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 26617000 because target called exit()
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
new file mode 100644
index 000000000..65764b562
--- /dev/null
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 19555 # Simulator instruction rate (inst/s)
+host_mem_usage 201376 # Number of bytes of host memory used
+host_seconds 0.49 # Real time elapsed on the host
+host_tick_rate 54805154 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 9494 # Number of instructions simulated
+sim_seconds 0.000027 # Number of seconds simulated
+sim_ticks 26617000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 53234 # number of cpu cycles simulated
+system.cpu.num_insts 9494 # Number of instructions executed
+system.cpu.num_refs 1987 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/config.ini
new file mode 100644
index 000000000..2c754d8d5
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/config.ini
@@ -0,0 +1,218 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.membus.port[1]
+icache_port=system.membus.port[0]
+
+[system.cpu0.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu0.itb]
+type=SparcTLB
+size=64
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu0.workload]
+type=LiveProcess
+cmd=test_atomic 4
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu1.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu1.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu1.itb]
+type=SparcTLB
+size=64
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu2]
+type=AtomicSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=2
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu2.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.membus.port[5]
+icache_port=system.membus.port[4]
+
+[system.cpu2.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu2.itb]
+type=SparcTLB
+size=64
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.cpu3]
+type=AtomicSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=3
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu3.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu3.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu3.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.membus.port[7]
+icache_port=system.membus.port[6]
+
+[system.cpu3.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu3.itb]
+type=SparcTLB
+size=64
+
+[system.cpu3.tracer]
+type=ExeTracer
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0]
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=4
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[8]
+
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/ruby.stats b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/ruby.stats
new file mode 100644
index 000000000..2f903fa47
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/ruby.stats
@@ -0,0 +1,930 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:54:24, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 4
+g_NUM_L2_BANKS: 4
+g_NUM_MEMORIES: 4
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 4
+g_NUM_CHIP_BITS: 2
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 2
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 2
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 2
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 24
+g_MEMORY_MODULE_BLOCKS: 16777216
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 4
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 24
+ module_size_lines: 16777216
+ module_size_bytes: 1073741824
+ module_size_Kbytes: 1.04858e+06
+ module_size_Mbytes: 1024
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> L1Cache-1 net_lat: 9
+ L1Cache-0 -> L1Cache-2 net_lat: 9
+ L1Cache-0 -> L1Cache-3 net_lat: 9
+ L1Cache-0 -> Directory-0 net_lat: 9
+ L1Cache-0 -> Directory-1 net_lat: 9
+ L1Cache-0 -> Directory-2 net_lat: 9
+ L1Cache-0 -> Directory-3 net_lat: 9
+
+L1Cache-1 Network Latencies
+ L1Cache-1 -> L1Cache-0 net_lat: 9
+ L1Cache-1 -> L1Cache-2 net_lat: 9
+ L1Cache-1 -> L1Cache-3 net_lat: 9
+ L1Cache-1 -> Directory-0 net_lat: 9
+ L1Cache-1 -> Directory-1 net_lat: 9
+ L1Cache-1 -> Directory-2 net_lat: 9
+ L1Cache-1 -> Directory-3 net_lat: 9
+
+L1Cache-2 Network Latencies
+ L1Cache-2 -> L1Cache-0 net_lat: 9
+ L1Cache-2 -> L1Cache-1 net_lat: 9
+ L1Cache-2 -> L1Cache-3 net_lat: 9
+ L1Cache-2 -> Directory-0 net_lat: 9
+ L1Cache-2 -> Directory-1 net_lat: 9
+ L1Cache-2 -> Directory-2 net_lat: 9
+ L1Cache-2 -> Directory-3 net_lat: 9
+
+L1Cache-3 Network Latencies
+ L1Cache-3 -> L1Cache-0 net_lat: 9
+ L1Cache-3 -> L1Cache-1 net_lat: 9
+ L1Cache-3 -> L1Cache-2 net_lat: 9
+ L1Cache-3 -> Directory-0 net_lat: 9
+ L1Cache-3 -> Directory-1 net_lat: 9
+ L1Cache-3 -> Directory-2 net_lat: 9
+ L1Cache-3 -> Directory-3 net_lat: 9
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 9
+ Directory-0 -> L1Cache-1 net_lat: 9
+ Directory-0 -> L1Cache-2 net_lat: 9
+ Directory-0 -> L1Cache-3 net_lat: 9
+ Directory-0 -> Directory-1 net_lat: 9
+ Directory-0 -> Directory-2 net_lat: 9
+ Directory-0 -> Directory-3 net_lat: 9
+
+Directory-1 Network Latencies
+ Directory-1 -> L1Cache-0 net_lat: 9
+ Directory-1 -> L1Cache-1 net_lat: 9
+ Directory-1 -> L1Cache-2 net_lat: 9
+ Directory-1 -> L1Cache-3 net_lat: 9
+ Directory-1 -> Directory-0 net_lat: 9
+ Directory-1 -> Directory-2 net_lat: 9
+ Directory-1 -> Directory-3 net_lat: 9
+
+Directory-2 Network Latencies
+ Directory-2 -> L1Cache-0 net_lat: 9
+ Directory-2 -> L1Cache-1 net_lat: 9
+ Directory-2 -> L1Cache-2 net_lat: 9
+ Directory-2 -> L1Cache-3 net_lat: 9
+ Directory-2 -> Directory-0 net_lat: 9
+ Directory-2 -> Directory-1 net_lat: 9
+ Directory-2 -> Directory-3 net_lat: 9
+
+Directory-3 Network Latencies
+ Directory-3 -> L1Cache-0 net_lat: 9
+ Directory-3 -> L1Cache-1 net_lat: 9
+ Directory-3 -> L1Cache-2 net_lat: 9
+ Directory-3 -> L1Cache-3 net_lat: 9
+ Directory-3 -> Directory-0 net_lat: 9
+ Directory-3 -> Directory-1 net_lat: 9
+ Directory-3 -> Directory-2 net_lat: 9
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:05
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 3
+Elapsed_time_in_minutes: 0.05
+Elapsed_time_in_hours: 0.000833333
+Elapsed_time_in_days: 3.47222e-05
+
+Virtual_time_in_seconds: 1.88
+Virtual_time_in_minutes: 0.0313333
+Virtual_time_in_hours: 0.000522222
+Virtual_time_in_days: 0.000522222
+
+Ruby_current_time: 87713501
+Ruby_start_time: 1
+Ruby_cycles: 87713500
+
+mbytes_resident: 90.4062
+mbytes_total: 251.832
+resident_ratio: 0.35901
+
+Total_misses: 0
+total_misses: 0 [ 0 0 0 0 ]
+user_misses: 0 [ 0 0 0 0 ]
+supervisor_misses: 0 [ 0 0 0 0 ]
+
+instruction_executed: 4 [ 1 1 1 1 ]
+cycles_executed: 4 [ 1 1 1 1 ]
+cycles_per_instruction: 8.77135e+07 [ 8.77135e+07 8.77135e+07 8.77135e+07 8.77135e+07 ]
+misses_per_thousand_instructions: 0 [ 0 0 0 0 ]
+
+transactions_started: 0 [ 0 0 0 0 ]
+transactions_ended: 0 [ 0 0 0 0 ]
+instructions_per_transaction: 0 [ 0 0 0 0 ]
+cycles_per_transaction: 0 [ 0 0 0 0 ]
+misses_per_transaction: 0 [ 0 0 0 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 0
+ L1D_cache_total_demand_misses: 0
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 0
+ L1D_cache_misses_per_instruction: 0
+ L1D_cache_instructions_per_misses: NaN
+
+ L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 0
+ L1I_cache_total_demand_misses: 0
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 0
+ L1I_cache_misses_per_instruction: 0
+ L1I_cache_instructions_per_misses: NaN
+
+ L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 0
+ L2_cache_total_demand_misses: 0
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 0
+ L2_cache_misses_per_instruction: 0
+ L2_cache_instructions_per_misses: NaN
+
+ L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0
+Directory-0:0 Directory-1:0 Directory-2:0 Directory-3:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 1
+system_time: 0
+page_reclaims: 23338
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 640
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
+MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
+MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
+MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 0
+ links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 0
+ links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_2_inlinks: 1
+switch_2_outlinks: 1
+links_utilized_percent_switch_2: 0
+ links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_3_inlinks: 1
+switch_3_outlinks: 1
+links_utilized_percent_switch_3: 0
+ links_utilized_percent_switch_3_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_4_inlinks: 1
+switch_4_outlinks: 1
+links_utilized_percent_switch_4: 0
+ links_utilized_percent_switch_4_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_5_inlinks: 1
+switch_5_outlinks: 1
+links_utilized_percent_switch_5: 0
+ links_utilized_percent_switch_5_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_6_inlinks: 1
+switch_6_outlinks: 1
+links_utilized_percent_switch_6: 0
+ links_utilized_percent_switch_6_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_7_inlinks: 1
+switch_7_outlinks: 1
+links_utilized_percent_switch_7: 0
+ links_utilized_percent_switch_7_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_8_inlinks: 4
+switch_8_outlinks: 1
+links_utilized_percent_switch_8: 0
+ links_utilized_percent_switch_8_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_9_inlinks: 4
+switch_9_outlinks: 1
+links_utilized_percent_switch_9: 0
+ links_utilized_percent_switch_9_link_0: 0 bw: 10000 base_latency: 1
+
+
+switch_10_inlinks: 2
+switch_10_outlinks: 2
+links_utilized_percent_switch_10: 0
+ links_utilized_percent_switch_10_link_0: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_10_link_1: 0 bw: 10000 base_latency: 1
+
+
+switch_11_inlinks: 1
+switch_11_outlinks: 4
+links_utilized_percent_switch_11: 0
+ links_utilized_percent_switch_11_link_0: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_11_link_1: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_11_link_2: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_11_link_3: 0 bw: 10000 base_latency: 1
+
+
+switch_12_inlinks: 1
+switch_12_outlinks: 4
+links_utilized_percent_switch_12: 0
+ links_utilized_percent_switch_12_link_0: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_12_link_1: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_12_link_2: 0 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_12_link_3: 0 bw: 10000 base_latency: 1
+
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 0
+Ifetch 0
+Store 0
+L1_to_L2 0
+L2_to_L1D 0
+L2_to_L1I 0
+L2_Replacement 0
+Own_GETS 0
+Own_GET_INSTR 0
+Own_GETX 0
+Own_PUTX 0
+Other_GETS 0
+Other_GET_INSTR 0
+Other_GETX 0
+Other_PUTX 0
+Data 0
+
+ - Transitions -
+NP Load 0 <--
+NP Ifetch 0 <--
+NP Store 0 <--
+NP Other_GETS 0 <--
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 0 <--
+NP Other_PUTX 0 <--
+
+I Load 0 <--
+I Ifetch 0 <--
+I Store 0 <--
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 0 <--
+I Other_GET_INSTR 0 <--
+I Other_GETX 0 <--
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 0 <--
+S Store 0 <--
+S L1_to_L2 0 <--
+S L2_to_L1D 0 <--
+S L2_to_L1I 0 <--
+S L2_Replacement 0 <--
+S Other_GETS 0 <--
+S Other_GET_INSTR 0 <--
+S Other_GETX 0 <--
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 0 <--
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 0 <--
+O Other_GET_INSTR 0 <--
+O Other_GETX 0 <--
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 0 <--
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 0 <--
+M Other_GET_INSTR 0 <--
+M Other_GETX 0 <--
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 0 <--
+IS_AD Own_GET_INSTR 0 <--
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 0 <--
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 0 <--
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 0 <--
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 0 <--
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 0 <--
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 0 <--
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 0
+GET_INSTR 0
+GETX 0
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 0 <--
+C GET_INSTR 0 <--
+C GETX 0 <--
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 0 <--
+S GET_INSTR 0 <--
+S GETX 0 <--
+S PUTX_NotOwner 0 <--
+
+SS GETS 0 <--
+SS GET_INSTR 0 <--
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 0 <--
+OS GET_INSTR 0 <--
+OS GETX 0 <--
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 0 <--
+OSS GET_INSTR 0 <--
+OSS GETX 0 <--
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 0 <--
+M GET_INSTR 0 <--
+M GETX 0 <--
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simout
new file mode 100755
index 000000000..93719d3b2
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simout
@@ -0,0 +1,94 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:02
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 4
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+Init done
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 1 completed
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 2 completed
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 3 completed
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
+Iteration 4 completed
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 5 completed
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 6 completed
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 7 completed
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 8 completed
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 9 completed
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 10 completed
+PASSED :-)
+Exiting @ tick 87713500 because target called exit()
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/stats.txt
new file mode 100644
index 000000000..0b12f069c
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/stats.txt
@@ -0,0 +1,33 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 286405 # Simulator instruction rate (inst/s)
+host_mem_usage 257880 # Number of bytes of host memory used
+host_seconds 2.37 # Real time elapsed on the host
+host_tick_rate 37086106 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 677340 # Number of instructions simulated
+sim_seconds 0.000088 # Number of seconds simulated
+sim_ticks 87713500 # Number of ticks simulated
+system.cpu0.idle_fraction 0.045871 # Percentage of idle cycles
+system.cpu0.not_idle_fraction 0.954129 # Percentage of non-idle cycles
+system.cpu0.numCycles 173308 # number of cpu cycles simulated
+system.cpu0.num_insts 167334 # Number of instructions executed
+system.cpu0.num_refs 58537 # Number of memory references
+system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
+system.cpu1.idle_fraction 0.046241 # Percentage of idle cycles
+system.cpu1.not_idle_fraction 0.953759 # Percentage of non-idle cycles
+system.cpu1.numCycles 173307 # number of cpu cycles simulated
+system.cpu1.num_insts 167269 # Number of instructions executed
+system.cpu1.num_refs 55900 # Number of memory references
+system.cpu2.idle_fraction 0 # Percentage of idle cycles
+system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu2.numCycles 175428 # number of cpu cycles simulated
+system.cpu2.num_insts 175339 # Number of instructions executed
+system.cpu2.num_refs 82398 # Number of memory references
+system.cpu3.idle_fraction 0.045506 # Percentage of idle cycles
+system.cpu3.not_idle_fraction 0.954494 # Percentage of non-idle cycles
+system.cpu3.numCycles 173308 # number of cpu cycles simulated
+system.cpu3.num_insts 167398 # Number of instructions executed
+system.cpu3.num_refs 53394 # Number of memory references
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
new file mode 100644
index 000000000..bbd5c6af7
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
@@ -0,0 +1,206 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 membus physmem
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu0.tracer
+workload=system.cpu0.workload
+dcache_port=system.membus.port[1]
+icache_port=system.membus.port[0]
+
+[system.cpu0.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu0.itb]
+type=SparcTLB
+size=64
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu0.workload]
+type=LiveProcess
+cmd=test_atomic 4
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu1.tracer
+workload=system.cpu0.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu1.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu1.itb]
+type=SparcTLB
+size=64
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu2]
+type=TimingSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=2
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu2.tracer
+workload=system.cpu0.workload
+dcache_port=system.membus.port[5]
+icache_port=system.membus.port[4]
+
+[system.cpu2.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu2.itb]
+type=SparcTLB
+size=64
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.cpu3]
+type=TimingSimpleCPU
+children=dtb itb tracer
+checker=Null
+clock=500
+cpu_id=3
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu3.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu3.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu3.tracer
+workload=system.cpu0.workload
+dcache_port=system.membus.port[7]
+icache_port=system.membus.port[6]
+
+[system.cpu3.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu3.itb]
+type=SparcTLB
+size=64
+
+[system.cpu3.tracer]
+type=ExeTracer
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0]
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=4
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[8]
+
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
new file mode 100644
index 000000000..5758c154e
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
@@ -0,0 +1,1004 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:54:24, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 4
+g_NUM_L2_BANKS: 4
+g_NUM_MEMORIES: 4
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 4
+g_NUM_CHIP_BITS: 2
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 2
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 2
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 2
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 24
+g_MEMORY_MODULE_BLOCKS: 16777216
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 4
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 24
+ module_size_lines: 16777216
+ module_size_bytes: 1073741824
+ module_size_Kbytes: 1.04858e+06
+ module_size_Mbytes: 1024
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> L1Cache-1 net_lat: 9
+ L1Cache-0 -> L1Cache-2 net_lat: 9
+ L1Cache-0 -> L1Cache-3 net_lat: 9
+ L1Cache-0 -> Directory-0 net_lat: 9
+ L1Cache-0 -> Directory-1 net_lat: 9
+ L1Cache-0 -> Directory-2 net_lat: 9
+ L1Cache-0 -> Directory-3 net_lat: 9
+
+L1Cache-1 Network Latencies
+ L1Cache-1 -> L1Cache-0 net_lat: 9
+ L1Cache-1 -> L1Cache-2 net_lat: 9
+ L1Cache-1 -> L1Cache-3 net_lat: 9
+ L1Cache-1 -> Directory-0 net_lat: 9
+ L1Cache-1 -> Directory-1 net_lat: 9
+ L1Cache-1 -> Directory-2 net_lat: 9
+ L1Cache-1 -> Directory-3 net_lat: 9
+
+L1Cache-2 Network Latencies
+ L1Cache-2 -> L1Cache-0 net_lat: 9
+ L1Cache-2 -> L1Cache-1 net_lat: 9
+ L1Cache-2 -> L1Cache-3 net_lat: 9
+ L1Cache-2 -> Directory-0 net_lat: 9
+ L1Cache-2 -> Directory-1 net_lat: 9
+ L1Cache-2 -> Directory-2 net_lat: 9
+ L1Cache-2 -> Directory-3 net_lat: 9
+
+L1Cache-3 Network Latencies
+ L1Cache-3 -> L1Cache-0 net_lat: 9
+ L1Cache-3 -> L1Cache-1 net_lat: 9
+ L1Cache-3 -> L1Cache-2 net_lat: 9
+ L1Cache-3 -> Directory-0 net_lat: 9
+ L1Cache-3 -> Directory-1 net_lat: 9
+ L1Cache-3 -> Directory-2 net_lat: 9
+ L1Cache-3 -> Directory-3 net_lat: 9
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 9
+ Directory-0 -> L1Cache-1 net_lat: 9
+ Directory-0 -> L1Cache-2 net_lat: 9
+ Directory-0 -> L1Cache-3 net_lat: 9
+ Directory-0 -> Directory-1 net_lat: 9
+ Directory-0 -> Directory-2 net_lat: 9
+ Directory-0 -> Directory-3 net_lat: 9
+
+Directory-1 Network Latencies
+ Directory-1 -> L1Cache-0 net_lat: 9
+ Directory-1 -> L1Cache-1 net_lat: 9
+ Directory-1 -> L1Cache-2 net_lat: 9
+ Directory-1 -> L1Cache-3 net_lat: 9
+ Directory-1 -> Directory-0 net_lat: 9
+ Directory-1 -> Directory-2 net_lat: 9
+ Directory-1 -> Directory-3 net_lat: 9
+
+Directory-2 Network Latencies
+ Directory-2 -> L1Cache-0 net_lat: 9
+ Directory-2 -> L1Cache-1 net_lat: 9
+ Directory-2 -> L1Cache-2 net_lat: 9
+ Directory-2 -> L1Cache-3 net_lat: 9
+ Directory-2 -> Directory-0 net_lat: 9
+ Directory-2 -> Directory-1 net_lat: 9
+ Directory-2 -> Directory-3 net_lat: 9
+
+Directory-3 Network Latencies
+ Directory-3 -> L1Cache-0 net_lat: 9
+ Directory-3 -> L1Cache-1 net_lat: 9
+ Directory-3 -> L1Cache-2 net_lat: 9
+ Directory-3 -> L1Cache-3 net_lat: 9
+ Directory-3 -> Directory-0 net_lat: 9
+ Directory-3 -> Directory-1 net_lat: 9
+ Directory-3 -> Directory-2 net_lat: 9
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:34:42
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 40
+Elapsed_time_in_minutes: 0.666667
+Elapsed_time_in_hours: 0.0111111
+Elapsed_time_in_days: 0.000462963
+
+Virtual_time_in_seconds: 37.33
+Virtual_time_in_minutes: 0.622167
+Virtual_time_in_hours: 0.0103694
+Virtual_time_in_days: 0.0103694
+
+Ruby_current_time: 2480212001
+Ruby_start_time: 1
+Ruby_cycles: 2480212000
+
+mbytes_resident: 90.6484
+mbytes_total: 252.043
+resident_ratio: 0.35967
+
+Total_misses: 1949
+total_misses: 1949 [ 424 409 702 414 ]
+user_misses: 1949 [ 424 409 702 414 ]
+supervisor_misses: 0 [ 0 0 0 0 ]
+
+instruction_executed: 4 [ 1 1 1 1 ]
+cycles_executed: 4 [ 1 1 1 1 ]
+cycles_per_instruction: 2.48021e+09 [ 2.48021e+09 2.48021e+09 2.48021e+09 2.48021e+09 ]
+misses_per_thousand_instructions: 487250 [ 424000 409000 702000 414000 ]
+
+transactions_started: 0 [ 0 0 0 0 ]
+transactions_ended: 0 [ 0 0 0 0 ]
+instructions_per_transaction: 0 [ 0 0 0 0 ]
+cycles_per_transaction: 0 [ 0 0 0 0 ]
+misses_per_transaction: 0 [ 0 0 0 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 1340
+ L1D_cache_total_demand_misses: 1340
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 1340
+ L1D_cache_misses_per_instruction: 1340
+ L1D_cache_instructions_per_misses: 0.000746269
+
+ L1D_cache_request_type_LD: 47.4627%
+ L1D_cache_request_type_ST: 38.0597%
+ L1D_cache_request_type_ATOMIC: 14.4776%
+
+ L1D_cache_access_mode_type_UserMode: 1340 100%
+ L1D_cache_request_size: [binsize: log2 max: 8 count: 1340 average: 3.48881 | standard deviation: 2.44812 | 0 527 4 583 226 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 610
+ L1I_cache_total_demand_misses: 610
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 610
+ L1I_cache_misses_per_instruction: 610
+ L1I_cache_instructions_per_misses: 0.00163934
+
+ L1I_cache_request_type_IFETCH: 100%
+
+ L1I_cache_access_mode_type_UserMode: 610 100%
+ L1I_cache_request_size: [binsize: log2 max: 4 count: 610 average: 4 | standard deviation: 0 | 0 0 0 610 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 1949
+ L2_cache_total_demand_misses: 1949
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 1949
+ L2_cache_misses_per_instruction: 1949
+ L2_cache_instructions_per_misses: 0.000513084
+
+ L2_cache_request_type_LD: 32.6321%
+ L2_cache_request_type_ST: 26.1673%
+ L2_cache_request_type_ATOMIC: 9.95382%
+ L2_cache_request_type_IFETCH: 31.2468%
+
+ L2_cache_access_mode_type_UserMode: 1949 100%
+ L2_cache_request_size: [binsize: log2 max: 8 count: 1949 average: 3.64854 | standard deviation: 2.04355 | 0 527 4 1192 226 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0
+Directory-0:0 Directory-1:0 Directory-2:0 Directory-3:0
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 0 count: 1949 average: 0 | standard deviation: 0 | 1949 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 1950 average: 1 | standard deviation: 0 | 0 1950 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ]
+miss_latency_LD: [binsize: 1 max: 184 count: 636 average: 57.2925 | standard deviation: 53.9711 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 536 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 19 26 17 23 ]
+miss_latency_ST: [binsize: 1 max: 184 count: 510 average: 73.749 | standard deviation: 69.6824 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34 27 26 19 42 ]
+miss_latency_ATOMIC: [binsize: 1 max: 183 count: 194 average: 37.7887 | standard deviation: 23.3543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 0 1 ]
+miss_latency_IFETCH: [binsize: 1 max: 184 count: 610 average: 181.728 | standard deviation: 7.34165 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 113 125 131 117 123 ]
+miss_latency_NULL: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+conflicting_histogram: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 6 7 6 10 37 57 33 164 243 38 123 210 142 218 449 203 ]
+conflicting_histogram_percent: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 0.0513084 0 0 0 0 0 0 0 0 0 0 0.0513084 0 0.0513084 0.30785 0.359159 0.30785 0.513084 1.89841 2.92458 1.69318 8.41457 12.4679 1.94972 6.31093 10.7748 7.28579 11.1852 23.0375 10.4156 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+ I M GETS 310 15.9056
+ I M GETX 216 11.0826
+ I OS GETS 142 7.28579
+ I OS GETX 33 1.69318
+ I OSS GETS 54 2.77065
+ I OSS GETX 15 0.769625
+ NP C GETS 75 3.84813
+ NP C GETX 136 6.97794
+ NP C GET_INSTR 348 17.8553
+ NP M GETS 17 0.872242
+ NP M GETX 11 0.564392
+ NP OS GETS 6 0.30785
+ NP OSS GETS 7 0.359159
+ NP S GETS 9 0.461775
+ NP S GET_INSTR 93 4.77168
+ NP SS GETS 16 0.820934
+ NP SS GET_INSTR 168 8.61981
+ O OS GETX 22 1.12878
+ O OSS GETX 60 3.0785
+ S OS GETX 124 6.36224
+ S OSS GETX 70 3.59159
+ S S GETX 17 0.872242
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 37
+system_time: 0
+page_reclaims: 23404
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 656
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:424 full:0
+MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:409 full:0
+MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:703 full:0
+MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:414 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 8.82828e-05
+ links_utilized_percent_switch_0_link_0: 8.82828e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Control: 424 3392 [ 424 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Data: 257 18504 [ 0 257 0 0 ] base_latency: 1
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 8.92504e-05
+ links_utilized_percent_switch_1_link_0: 8.92504e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Control: 409 3272 [ 409 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Data: 262 18864 [ 0 262 0 0 ] base_latency: 1
+
+switch_2_inlinks: 1
+switch_2_outlinks: 1
+links_utilized_percent_switch_2: 8.94117e-05
+ links_utilized_percent_switch_2_link_0: 8.94117e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 702 5616 [ 702 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Data: 230 16560 [ 0 230 0 0 ] base_latency: 1
+
+switch_3_inlinks: 1
+switch_3_outlinks: 1
+links_utilized_percent_switch_3: 8.76699e-05
+ links_utilized_percent_switch_3_link_0: 8.76699e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Control: 414 3312 [ 414 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1
+
+switch_4_inlinks: 1
+switch_4_outlinks: 1
+links_utilized_percent_switch_4: 6.76394e-05
+ links_utilized_percent_switch_4_link_0: 6.76394e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_4_link_0_Data: 233 16776 [ 0 233 0 0 ] base_latency: 1
+
+switch_5_inlinks: 1
+switch_5_outlinks: 1
+links_utilized_percent_switch_5: 6.21237e-05
+ links_utilized_percent_switch_5_link_0: 6.21237e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_5_link_0_Data: 214 15408 [ 0 214 0 0 ] base_latency: 1
+
+switch_6_inlinks: 1
+switch_6_outlinks: 1
+links_utilized_percent_switch_6: 5.9511e-05
+ links_utilized_percent_switch_6_link_0: 5.9511e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_6_link_0_Data: 205 14760 [ 0 205 0 0 ] base_latency: 1
+
+switch_7_inlinks: 1
+switch_7_outlinks: 1
+links_utilized_percent_switch_7: 6.09625e-05
+ links_utilized_percent_switch_7_link_0: 6.09625e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_7_link_0_Data: 210 15120 [ 0 210 0 0 ] base_latency: 1
+
+switch_8_inlinks: 4
+switch_8_outlinks: 1
+links_utilized_percent_switch_8: 0.000354615
+ links_utilized_percent_switch_8_link_0: 0.000354615 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_8_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_8_link_0_Data: 1005 72360 [ 0 1005 0 0 ] base_latency: 1
+
+switch_9_inlinks: 4
+switch_9_outlinks: 1
+links_utilized_percent_switch_9: 0.000250237
+ links_utilized_percent_switch_9_link_0: 0.000250237 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_9_link_0_Data: 862 62064 [ 0 862 0 0 ] base_latency: 1
+
+switch_10_inlinks: 2
+switch_10_outlinks: 2
+links_utilized_percent_switch_10: 0.000333859
+ links_utilized_percent_switch_10_link_0: 0.000604852 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_10_link_1: 6.28656e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_10_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_0_Data: 1867 134424 [ 0 1867 0 0 ] base_latency: 1
+ outgoing_messages_switch_10_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+
+switch_11_inlinks: 1
+switch_11_outlinks: 4
+links_utilized_percent_switch_11: 0.000198362
+ links_utilized_percent_switch_11_link_0: 0.000181597 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_11_link_1: 0.000176082 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_11_link_2: 0.000257655 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_11_link_3: 0.000178114 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_11_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_11_link_0_Data: 409 29448 [ 0 409 0 0 ] base_latency: 1
+ outgoing_messages_switch_11_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_11_link_1_Data: 390 28080 [ 0 390 0 0 ] base_latency: 1
+ outgoing_messages_switch_11_link_2_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_11_link_2_Data: 671 48312 [ 0 671 0 0 ] base_latency: 1
+ outgoing_messages_switch_11_link_3_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_11_link_3_Data: 397 28584 [ 0 397 0 0 ] base_latency: 1
+
+switch_12_inlinks: 1
+switch_12_outlinks: 4
+links_utilized_percent_switch_12: 1.57164e-05
+ links_utilized_percent_switch_12_link_0: 2.37399e-05 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_12_link_1: 1.05475e-05 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_12_link_2: 6.87038e-06 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_12_link_3: 2.17078e-05 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_12_link_0_Control: 736 5888 [ 736 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_12_link_1_Control: 327 2616 [ 327 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_12_link_2_Control: 213 1704 [ 213 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_12_link_3_Control: 673 5384 [ 673 0 0 0 ] base_latency: 1
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 636
+Ifetch 610
+Store 704
+L1_to_L2 3
+L2_to_L1D 0
+L2_to_L1I 1
+L2_Replacement 0
+Own_GETS 636
+Own_GET_INSTR 609
+Own_GETX 704
+Own_PUTX 0
+Other_GETS 1908
+Other_GET_INSTR 1827
+Other_GETX 2112
+Other_PUTX 0
+Data 1867
+
+ - Transitions -
+NP Load 130
+NP Ifetch 609
+NP Store 147
+NP Other_GETS 289
+NP Other_GET_INSTR 1323
+NP Other_GETX 514
+NP Other_PUTX 0 <--
+
+I Load 506
+I Ifetch 0 <--
+I Store 264
+I L1_to_L2 0 <--
+I L2_to_L1D 0 <--
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 765
+I Other_GET_INSTR 0 <--
+I Other_GETX 796
+I Other_PUTX 0 <--
+
+S Load 0 <--
+S Ifetch 1
+S Store 211
+S L1_to_L2 2
+S L2_to_L1D 0 <--
+S L2_to_L1I 1
+S L2_Replacement 0 <--
+S Other_GETS 318
+S Other_GET_INSTR 504
+S Other_GETX 333
+S Other_PUTX 0 <--
+
+O Load 0 <--
+O Ifetch 0 <--
+O Store 82
+O L1_to_L2 0 <--
+O L2_to_L1D 0 <--
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 209
+O Other_GET_INSTR 0 <--
+O Other_GETX 242
+O Other_PUTX 0 <--
+
+M Load 0 <--
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 1
+M L2_to_L1D 0 <--
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 327
+M Other_GET_INSTR 0 <--
+M Other_GETX 227
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 636
+IS_AD Own_GET_INSTR 609
+IS_AD Other_GETS 0 <--
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 0 <--
+IS_AD Other_PUTX 0 <--
+IS_AD Data 0 <--
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 411
+IM_AD Other_GETS 0 <--
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 0 <--
+IM_AD Other_PUTX 0 <--
+IM_AD Data 0 <--
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 211
+SM_AD Other_GETS 0 <--
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 0 <--
+SM_AD Other_PUTX 0 <--
+SM_AD Data 0 <--
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 82
+OM_A Other_GETS 0 <--
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 0 <--
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 0 <--
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 0 <--
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 0 <--
+IM_A Other_GETS 0 <--
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 0 <--
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 0 <--
+SM_A Other_GETS 0 <--
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 0 <--
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 0 <--
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 0 <--
+IS_D Other_PUTX 0 <--
+IS_D Data 1245
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 0 <--
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 0 <--
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 0 <--
+IM_D Other_PUTX 0 <--
+IM_D Data 411
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 0 <--
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 0 <--
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 0 <--
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 0 <--
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 0 <--
+SM_D Other_PUTX 0 <--
+SM_D Data 211
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 0 <--
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 636
+GET_INSTR 609
+GETX 704
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 75
+C GET_INSTR 348
+C GETX 136
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 9
+S GET_INSTR 93
+S GETX 17
+S PUTX_NotOwner 0 <--
+
+SS GETS 16
+SS GET_INSTR 168
+SS GETX 0 <--
+SS PUTX_NotOwner 0 <--
+
+OS GETS 148
+OS GET_INSTR 0 <--
+OS GETX 179
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 61
+OSS GET_INSTR 0 <--
+OSS GETX 145
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 327
+M GET_INSTR 0 <--
+M GETX 227
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
new file mode 100755
index 000000000..24f1aa5ae
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
@@ -0,0 +1,94 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:02
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 4
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+Init done
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 1 completed
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
+Iteration 2 completed
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 3 completed
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
+Iteration 4 completed
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 5 completed
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 6 completed
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 7 completed
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+Iteration 8 completed
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 9 completed
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 10 completed
+PASSED :-)
+Exiting @ tick 2480212000 because target called exit()
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
new file mode 100644
index 000000000..977b2c7d7
--- /dev/null
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
@@ -0,0 +1,33 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 15492 # Simulator instruction rate (inst/s)
+host_mem_usage 258096 # Number of bytes of host memory used
+host_seconds 39.33 # Real time elapsed on the host
+host_tick_rate 63054672 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 609352 # Number of instructions simulated
+sim_seconds 0.002480 # Number of seconds simulated
+sim_ticks 2480212000 # Number of ticks simulated
+system.cpu0.idle_fraction 0.011975 # Percentage of idle cycles
+system.cpu0.not_idle_fraction 0.988025 # Percentage of non-idle cycles
+system.cpu0.numCycles 4944742 # number of cpu cycles simulated
+system.cpu0.num_insts 156931 # Number of instructions executed
+system.cpu0.num_refs 47256 # Number of memory references
+system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
+system.cpu1.idle_fraction 0.012259 # Percentage of idle cycles
+system.cpu1.not_idle_fraction 0.987741 # Percentage of non-idle cycles
+system.cpu1.numCycles 4944666 # number of cpu cycles simulated
+system.cpu1.num_insts 152657 # Number of instructions executed
+system.cpu1.num_refs 51452 # Number of memory references
+system.cpu2.idle_fraction 0 # Percentage of idle cycles
+system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu2.numCycles 4960424 # number of cpu cycles simulated
+system.cpu2.num_insts 146173 # Number of instructions executed
+system.cpu2.num_refs 67815 # Number of memory references
+system.cpu3.idle_fraction 0.011794 # Percentage of idle cycles
+system.cpu3.not_idle_fraction 0.988206 # Percentage of non-idle cycles
+system.cpu3.numCycles 4944758 # number of cpu cycles simulated
+system.cpu3.num_insts 153591 # Number of instructions executed
+system.cpu3.num_refs 50671 # Number of memory references
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
new file mode 100644
index 000000000..2c57f204c
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -0,0 +1,169 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem membus physmem
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu0]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.membus.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.membus.port[1]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.membus.port[2]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.membus.port[3]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.membus.port[4]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.membus.port[5]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.membus.port[6]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.membus.port[7]
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=2
+header_cycles=1
+responder_set=false
+width=16
+port=system.cpu0.test system.cpu1.test system.cpu2.test system.cpu3.test system.cpu4.test system.cpu5.test system.cpu6.test system.cpu7.test system.physmem.port[0]
+
+[system.physmem]
+type=RubyMemory
+clock=1
+config_file=
+config_options=
+debug=false
+debug_file=
+file=
+latency=30000
+latency_var=0
+null=false
+num_cpus=8
+phase=0
+range=0:134217727
+stats_file=ruby.stats
+zero=false
+port=system.membus.port[8]
+
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
new file mode 100644
index 000000000..a3c4dfb4e
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -0,0 +1,1315 @@
+
+================ Begin RubySystem Configuration Print ================
+
+Ruby Configuration
+------------------
+protocol: MOSI_SMP_bcast
+compiled_at: 22:51:11, May 4 2009
+RUBY_DEBUG: false
+hostname: piton
+g_RANDOM_SEED: 1
+g_DEADLOCK_THRESHOLD: 500000
+RANDOMIZATION: false
+g_SYNTHETIC_DRIVER: false
+g_DETERMINISTIC_DRIVER: false
+g_FILTERING_ENABLED: false
+g_DISTRIBUTED_PERSISTENT_ENABLED: true
+g_DYNAMIC_TIMEOUT_ENABLED: true
+g_RETRY_THRESHOLD: 1
+g_FIXED_TIMEOUT_LATENCY: 300
+g_trace_warmup_length: 1000000
+g_bash_bandwidth_adaptive_threshold: 0.75
+g_tester_length: 0
+g_synthetic_locks: 2048
+g_deterministic_addrs: 1
+g_SpecifiedGenerator: DetermInvGenerator
+g_callback_counter: 0
+g_NUM_COMPLETIONS_BEFORE_PASS: 0
+g_NUM_SMT_THREADS: 1
+g_think_time: 5
+g_hold_time: 5
+g_wait_time: 5
+PROTOCOL_DEBUG_TRACE: true
+DEBUG_FILTER_STRING: none
+DEBUG_VERBOSITY_STRING: none
+DEBUG_START_TIME: 0
+DEBUG_OUTPUT_FILENAME: none
+SIMICS_RUBY_MULTIPLIER: 4
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+BLOCK_STC: false
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 8
+L2_CACHE_ASSOC: 4
+L2_CACHE_NUM_SETS_BITS: 16
+g_MEMORY_SIZE_BYTES: 4294967296
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 4096
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+g_NUM_PROCESSORS: 8
+g_NUM_L2_BANKS: 8
+g_NUM_MEMORIES: 8
+g_PROCS_PER_CHIP: 1
+g_NUM_CHIPS: 8
+g_NUM_CHIP_BITS: 3
+g_MEMORY_SIZE_BITS: 32
+g_DATA_BLOCK_BITS: 6
+g_PAGE_SIZE_BITS: 12
+g_NUM_PROCESSORS_BITS: 3
+g_PROCS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_BITS: 3
+g_NUM_L2_BANKS_PER_CHIP_BITS: 0
+g_NUM_L2_BANKS_PER_CHIP: 1
+g_NUM_MEMORIES_BITS: 3
+g_NUM_MEMORIES_PER_CHIP: 1
+g_MEMORY_MODULE_BITS: 23
+g_MEMORY_MODULE_BLOCKS: 8388608
+MAP_L2BANKS_TO_LOWEST_BITS: false
+DIRECTORY_CACHE_LATENCY: 6
+NULL_LATENCY: 1
+ISSUE_LATENCY: 2
+CACHE_RESPONSE_LATENCY: 12
+L2_RESPONSE_LATENCY: 6
+L2_TAG_LATENCY: 6
+L1_RESPONSE_LATENCY: 3
+MEMORY_RESPONSE_LATENCY_MINUS_2: 158
+DIRECTORY_LATENCY: 80
+NETWORK_LINK_LATENCY: 1
+COPY_HEAD_LATENCY: 4
+ON_CHIP_LINK_LATENCY: 1
+RECYCLE_LATENCY: 10
+L2_RECYCLE_LATENCY: 5
+TIMER_LATENCY: 10000
+TBE_RESPONSE_LATENCY: 1
+PERIODIC_TIMER_WAKEUPS: true
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: true
+PROFILE_NONXACT: false
+XACT_DEBUG: true
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_VISUALIZER: false
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 256
+XACT_STORE_PREDICTOR_ENTRIES: 256
+XACT_STORE_PREDICTOR_THRESHOLD: 4
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 32
+ATMTP_DEBUG_LEVEL: 0
+L1_REQUEST_LATENCY: 2
+L2_REQUEST_LATENCY: 4
+SINGLE_ACCESS_L2_BANKS: true
+SEQUENCER_TO_CONTROLLER_LATENCY: 4
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+NUMBER_OF_L2_TBES: 32
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
+g_CACHE_DESIGN: NUCA
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 4
+FAN_OUT_DEGREE: 4
+g_PRINT_TOPOLOGY: true
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+g_GARNET_NETWORK: false
+g_DETAIL_NETWORK: false
+g_NETWORK_TESTING: false
+g_FLIT_SIZE: 16
+g_NUM_PIPE_STAGES: 4
+g_VCS_PER_CLASS: 4
+g_BUFFER_SIZE: 4
+MEM_BUS_CYCLE_MULTIPLIER: 10
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 11
+RANK_RANK_DELAY: 1
+READ_WRITE_DELAY: 2
+BASIC_BUS_BUSY_TIME: 2
+MEM_CTL_LATENCY: 12
+REFRESH_PERIOD: 1560
+TFAW: 0
+MEM_RANDOM_ARBITRATE: 0
+MEM_FIXED_DELAY: 0
+
+Chip Config
+-----------
+Total_Chips: 8
+
+L1Cache_TBEs numberPerChip: 1
+TBEs_per_TBETable: 128
+
+L1Cache_L1IcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1I
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L1DcacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L1D
+ cache_associativity: 4
+ num_cache_sets_bits: 8
+ num_cache_sets: 256
+ cache_set_size_bytes: 16384
+ cache_set_size_Kbytes: 16
+ cache_set_size_Mbytes: 0.015625
+ cache_size_bytes: 65536
+ cache_size_Kbytes: 64
+ cache_size_Mbytes: 0.0625
+
+L1Cache_L2cacheMemory numberPerChip: 1
+Cache config: L1Cache_0_L2
+ cache_associativity: 4
+ num_cache_sets_bits: 16
+ num_cache_sets: 65536
+ cache_set_size_bytes: 4194304
+ cache_set_size_Kbytes: 4096
+ cache_set_size_Mbytes: 4
+ cache_size_bytes: 16777216
+ cache_size_Kbytes: 16384
+ cache_size_Mbytes: 16
+
+L1Cache_mandatoryQueue numberPerChip: 1
+
+L1Cache_sequencer numberPerChip: 1
+sequencer: Sequencer - SC
+ max_outstanding_requests: 16
+
+L1Cache_storeBuffer numberPerChip: 1
+Store buffer entries: 128 (Only valid if TSO is enabled)
+
+Directory_directory numberPerChip: 1
+Memory config:
+ memory_bits: 32
+ memory_size_bytes: 4294967296
+ memory_size_Kbytes: 4.1943e+06
+ memory_size_Mbytes: 4096
+ memory_size_Gbytes: 4
+ module_bits: 23
+ module_size_lines: 8388608
+ module_size_bytes: 536870912
+ module_size_Kbytes: 524288
+ module_size_Mbytes: 512
+
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: HIERARCHICAL_SWITCH
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: inactive
+virtual_net_3: inactive
+
+--- Begin Topology Print ---
+
+Topology print ONLY indicates the _NETWORK_ latency between two machines
+It does NOT include the latency within the machines
+
+L1Cache-0 Network Latencies
+ L1Cache-0 -> L1Cache-1 net_lat: 9
+ L1Cache-0 -> L1Cache-2 net_lat: 9
+ L1Cache-0 -> L1Cache-3 net_lat: 9
+ L1Cache-0 -> L1Cache-4 net_lat: 9
+ L1Cache-0 -> L1Cache-5 net_lat: 9
+ L1Cache-0 -> L1Cache-6 net_lat: 9
+ L1Cache-0 -> L1Cache-7 net_lat: 9
+ L1Cache-0 -> Directory-0 net_lat: 9
+ L1Cache-0 -> Directory-1 net_lat: 9
+ L1Cache-0 -> Directory-2 net_lat: 9
+ L1Cache-0 -> Directory-3 net_lat: 9
+ L1Cache-0 -> Directory-4 net_lat: 9
+ L1Cache-0 -> Directory-5 net_lat: 9
+ L1Cache-0 -> Directory-6 net_lat: 9
+ L1Cache-0 -> Directory-7 net_lat: 9
+
+L1Cache-1 Network Latencies
+ L1Cache-1 -> L1Cache-0 net_lat: 9
+ L1Cache-1 -> L1Cache-2 net_lat: 9
+ L1Cache-1 -> L1Cache-3 net_lat: 9
+ L1Cache-1 -> L1Cache-4 net_lat: 9
+ L1Cache-1 -> L1Cache-5 net_lat: 9
+ L1Cache-1 -> L1Cache-6 net_lat: 9
+ L1Cache-1 -> L1Cache-7 net_lat: 9
+ L1Cache-1 -> Directory-0 net_lat: 9
+ L1Cache-1 -> Directory-1 net_lat: 9
+ L1Cache-1 -> Directory-2 net_lat: 9
+ L1Cache-1 -> Directory-3 net_lat: 9
+ L1Cache-1 -> Directory-4 net_lat: 9
+ L1Cache-1 -> Directory-5 net_lat: 9
+ L1Cache-1 -> Directory-6 net_lat: 9
+ L1Cache-1 -> Directory-7 net_lat: 9
+
+L1Cache-2 Network Latencies
+ L1Cache-2 -> L1Cache-0 net_lat: 9
+ L1Cache-2 -> L1Cache-1 net_lat: 9
+ L1Cache-2 -> L1Cache-3 net_lat: 9
+ L1Cache-2 -> L1Cache-4 net_lat: 9
+ L1Cache-2 -> L1Cache-5 net_lat: 9
+ L1Cache-2 -> L1Cache-6 net_lat: 9
+ L1Cache-2 -> L1Cache-7 net_lat: 9
+ L1Cache-2 -> Directory-0 net_lat: 9
+ L1Cache-2 -> Directory-1 net_lat: 9
+ L1Cache-2 -> Directory-2 net_lat: 9
+ L1Cache-2 -> Directory-3 net_lat: 9
+ L1Cache-2 -> Directory-4 net_lat: 9
+ L1Cache-2 -> Directory-5 net_lat: 9
+ L1Cache-2 -> Directory-6 net_lat: 9
+ L1Cache-2 -> Directory-7 net_lat: 9
+
+L1Cache-3 Network Latencies
+ L1Cache-3 -> L1Cache-0 net_lat: 9
+ L1Cache-3 -> L1Cache-1 net_lat: 9
+ L1Cache-3 -> L1Cache-2 net_lat: 9
+ L1Cache-3 -> L1Cache-4 net_lat: 9
+ L1Cache-3 -> L1Cache-5 net_lat: 9
+ L1Cache-3 -> L1Cache-6 net_lat: 9
+ L1Cache-3 -> L1Cache-7 net_lat: 9
+ L1Cache-3 -> Directory-0 net_lat: 9
+ L1Cache-3 -> Directory-1 net_lat: 9
+ L1Cache-3 -> Directory-2 net_lat: 9
+ L1Cache-3 -> Directory-3 net_lat: 9
+ L1Cache-3 -> Directory-4 net_lat: 9
+ L1Cache-3 -> Directory-5 net_lat: 9
+ L1Cache-3 -> Directory-6 net_lat: 9
+ L1Cache-3 -> Directory-7 net_lat: 9
+
+L1Cache-4 Network Latencies
+ L1Cache-4 -> L1Cache-0 net_lat: 9
+ L1Cache-4 -> L1Cache-1 net_lat: 9
+ L1Cache-4 -> L1Cache-2 net_lat: 9
+ L1Cache-4 -> L1Cache-3 net_lat: 9
+ L1Cache-4 -> L1Cache-5 net_lat: 9
+ L1Cache-4 -> L1Cache-6 net_lat: 9
+ L1Cache-4 -> L1Cache-7 net_lat: 9
+ L1Cache-4 -> Directory-0 net_lat: 9
+ L1Cache-4 -> Directory-1 net_lat: 9
+ L1Cache-4 -> Directory-2 net_lat: 9
+ L1Cache-4 -> Directory-3 net_lat: 9
+ L1Cache-4 -> Directory-4 net_lat: 9
+ L1Cache-4 -> Directory-5 net_lat: 9
+ L1Cache-4 -> Directory-6 net_lat: 9
+ L1Cache-4 -> Directory-7 net_lat: 9
+
+L1Cache-5 Network Latencies
+ L1Cache-5 -> L1Cache-0 net_lat: 9
+ L1Cache-5 -> L1Cache-1 net_lat: 9
+ L1Cache-5 -> L1Cache-2 net_lat: 9
+ L1Cache-5 -> L1Cache-3 net_lat: 9
+ L1Cache-5 -> L1Cache-4 net_lat: 9
+ L1Cache-5 -> L1Cache-6 net_lat: 9
+ L1Cache-5 -> L1Cache-7 net_lat: 9
+ L1Cache-5 -> Directory-0 net_lat: 9
+ L1Cache-5 -> Directory-1 net_lat: 9
+ L1Cache-5 -> Directory-2 net_lat: 9
+ L1Cache-5 -> Directory-3 net_lat: 9
+ L1Cache-5 -> Directory-4 net_lat: 9
+ L1Cache-5 -> Directory-5 net_lat: 9
+ L1Cache-5 -> Directory-6 net_lat: 9
+ L1Cache-5 -> Directory-7 net_lat: 9
+
+L1Cache-6 Network Latencies
+ L1Cache-6 -> L1Cache-0 net_lat: 9
+ L1Cache-6 -> L1Cache-1 net_lat: 9
+ L1Cache-6 -> L1Cache-2 net_lat: 9
+ L1Cache-6 -> L1Cache-3 net_lat: 9
+ L1Cache-6 -> L1Cache-4 net_lat: 9
+ L1Cache-6 -> L1Cache-5 net_lat: 9
+ L1Cache-6 -> L1Cache-7 net_lat: 9
+ L1Cache-6 -> Directory-0 net_lat: 9
+ L1Cache-6 -> Directory-1 net_lat: 9
+ L1Cache-6 -> Directory-2 net_lat: 9
+ L1Cache-6 -> Directory-3 net_lat: 9
+ L1Cache-6 -> Directory-4 net_lat: 9
+ L1Cache-6 -> Directory-5 net_lat: 9
+ L1Cache-6 -> Directory-6 net_lat: 9
+ L1Cache-6 -> Directory-7 net_lat: 9
+
+L1Cache-7 Network Latencies
+ L1Cache-7 -> L1Cache-0 net_lat: 9
+ L1Cache-7 -> L1Cache-1 net_lat: 9
+ L1Cache-7 -> L1Cache-2 net_lat: 9
+ L1Cache-7 -> L1Cache-3 net_lat: 9
+ L1Cache-7 -> L1Cache-4 net_lat: 9
+ L1Cache-7 -> L1Cache-5 net_lat: 9
+ L1Cache-7 -> L1Cache-6 net_lat: 9
+ L1Cache-7 -> Directory-0 net_lat: 9
+ L1Cache-7 -> Directory-1 net_lat: 9
+ L1Cache-7 -> Directory-2 net_lat: 9
+ L1Cache-7 -> Directory-3 net_lat: 9
+ L1Cache-7 -> Directory-4 net_lat: 9
+ L1Cache-7 -> Directory-5 net_lat: 9
+ L1Cache-7 -> Directory-6 net_lat: 9
+ L1Cache-7 -> Directory-7 net_lat: 9
+
+Directory-0 Network Latencies
+ Directory-0 -> L1Cache-0 net_lat: 9
+ Directory-0 -> L1Cache-1 net_lat: 9
+ Directory-0 -> L1Cache-2 net_lat: 9
+ Directory-0 -> L1Cache-3 net_lat: 9
+ Directory-0 -> L1Cache-4 net_lat: 9
+ Directory-0 -> L1Cache-5 net_lat: 9
+ Directory-0 -> L1Cache-6 net_lat: 9
+ Directory-0 -> L1Cache-7 net_lat: 9
+ Directory-0 -> Directory-1 net_lat: 9
+ Directory-0 -> Directory-2 net_lat: 9
+ Directory-0 -> Directory-3 net_lat: 9
+ Directory-0 -> Directory-4 net_lat: 9
+ Directory-0 -> Directory-5 net_lat: 9
+ Directory-0 -> Directory-6 net_lat: 9
+ Directory-0 -> Directory-7 net_lat: 9
+
+Directory-1 Network Latencies
+ Directory-1 -> L1Cache-0 net_lat: 9
+ Directory-1 -> L1Cache-1 net_lat: 9
+ Directory-1 -> L1Cache-2 net_lat: 9
+ Directory-1 -> L1Cache-3 net_lat: 9
+ Directory-1 -> L1Cache-4 net_lat: 9
+ Directory-1 -> L1Cache-5 net_lat: 9
+ Directory-1 -> L1Cache-6 net_lat: 9
+ Directory-1 -> L1Cache-7 net_lat: 9
+ Directory-1 -> Directory-0 net_lat: 9
+ Directory-1 -> Directory-2 net_lat: 9
+ Directory-1 -> Directory-3 net_lat: 9
+ Directory-1 -> Directory-4 net_lat: 9
+ Directory-1 -> Directory-5 net_lat: 9
+ Directory-1 -> Directory-6 net_lat: 9
+ Directory-1 -> Directory-7 net_lat: 9
+
+Directory-2 Network Latencies
+ Directory-2 -> L1Cache-0 net_lat: 9
+ Directory-2 -> L1Cache-1 net_lat: 9
+ Directory-2 -> L1Cache-2 net_lat: 9
+ Directory-2 -> L1Cache-3 net_lat: 9
+ Directory-2 -> L1Cache-4 net_lat: 9
+ Directory-2 -> L1Cache-5 net_lat: 9
+ Directory-2 -> L1Cache-6 net_lat: 9
+ Directory-2 -> L1Cache-7 net_lat: 9
+ Directory-2 -> Directory-0 net_lat: 9
+ Directory-2 -> Directory-1 net_lat: 9
+ Directory-2 -> Directory-3 net_lat: 9
+ Directory-2 -> Directory-4 net_lat: 9
+ Directory-2 -> Directory-5 net_lat: 9
+ Directory-2 -> Directory-6 net_lat: 9
+ Directory-2 -> Directory-7 net_lat: 9
+
+Directory-3 Network Latencies
+ Directory-3 -> L1Cache-0 net_lat: 9
+ Directory-3 -> L1Cache-1 net_lat: 9
+ Directory-3 -> L1Cache-2 net_lat: 9
+ Directory-3 -> L1Cache-3 net_lat: 9
+ Directory-3 -> L1Cache-4 net_lat: 9
+ Directory-3 -> L1Cache-5 net_lat: 9
+ Directory-3 -> L1Cache-6 net_lat: 9
+ Directory-3 -> L1Cache-7 net_lat: 9
+ Directory-3 -> Directory-0 net_lat: 9
+ Directory-3 -> Directory-1 net_lat: 9
+ Directory-3 -> Directory-2 net_lat: 9
+ Directory-3 -> Directory-4 net_lat: 9
+ Directory-3 -> Directory-5 net_lat: 9
+ Directory-3 -> Directory-6 net_lat: 9
+ Directory-3 -> Directory-7 net_lat: 9
+
+Directory-4 Network Latencies
+ Directory-4 -> L1Cache-0 net_lat: 9
+ Directory-4 -> L1Cache-1 net_lat: 9
+ Directory-4 -> L1Cache-2 net_lat: 9
+ Directory-4 -> L1Cache-3 net_lat: 9
+ Directory-4 -> L1Cache-4 net_lat: 9
+ Directory-4 -> L1Cache-5 net_lat: 9
+ Directory-4 -> L1Cache-6 net_lat: 9
+ Directory-4 -> L1Cache-7 net_lat: 9
+ Directory-4 -> Directory-0 net_lat: 9
+ Directory-4 -> Directory-1 net_lat: 9
+ Directory-4 -> Directory-2 net_lat: 9
+ Directory-4 -> Directory-3 net_lat: 9
+ Directory-4 -> Directory-5 net_lat: 9
+ Directory-4 -> Directory-6 net_lat: 9
+ Directory-4 -> Directory-7 net_lat: 9
+
+Directory-5 Network Latencies
+ Directory-5 -> L1Cache-0 net_lat: 9
+ Directory-5 -> L1Cache-1 net_lat: 9
+ Directory-5 -> L1Cache-2 net_lat: 9
+ Directory-5 -> L1Cache-3 net_lat: 9
+ Directory-5 -> L1Cache-4 net_lat: 9
+ Directory-5 -> L1Cache-5 net_lat: 9
+ Directory-5 -> L1Cache-6 net_lat: 9
+ Directory-5 -> L1Cache-7 net_lat: 9
+ Directory-5 -> Directory-0 net_lat: 9
+ Directory-5 -> Directory-1 net_lat: 9
+ Directory-5 -> Directory-2 net_lat: 9
+ Directory-5 -> Directory-3 net_lat: 9
+ Directory-5 -> Directory-4 net_lat: 9
+ Directory-5 -> Directory-6 net_lat: 9
+ Directory-5 -> Directory-7 net_lat: 9
+
+Directory-6 Network Latencies
+ Directory-6 -> L1Cache-0 net_lat: 9
+ Directory-6 -> L1Cache-1 net_lat: 9
+ Directory-6 -> L1Cache-2 net_lat: 9
+ Directory-6 -> L1Cache-3 net_lat: 9
+ Directory-6 -> L1Cache-4 net_lat: 9
+ Directory-6 -> L1Cache-5 net_lat: 9
+ Directory-6 -> L1Cache-6 net_lat: 9
+ Directory-6 -> L1Cache-7 net_lat: 9
+ Directory-6 -> Directory-0 net_lat: 9
+ Directory-6 -> Directory-1 net_lat: 9
+ Directory-6 -> Directory-2 net_lat: 9
+ Directory-6 -> Directory-3 net_lat: 9
+ Directory-6 -> Directory-4 net_lat: 9
+ Directory-6 -> Directory-5 net_lat: 9
+ Directory-6 -> Directory-7 net_lat: 9
+
+Directory-7 Network Latencies
+ Directory-7 -> L1Cache-0 net_lat: 9
+ Directory-7 -> L1Cache-1 net_lat: 9
+ Directory-7 -> L1Cache-2 net_lat: 9
+ Directory-7 -> L1Cache-3 net_lat: 9
+ Directory-7 -> L1Cache-4 net_lat: 9
+ Directory-7 -> L1Cache-5 net_lat: 9
+ Directory-7 -> L1Cache-6 net_lat: 9
+ Directory-7 -> L1Cache-7 net_lat: 9
+ Directory-7 -> Directory-0 net_lat: 9
+ Directory-7 -> Directory-1 net_lat: 9
+ Directory-7 -> Directory-2 net_lat: 9
+ Directory-7 -> Directory-3 net_lat: 9
+ Directory-7 -> Directory-4 net_lat: 9
+ Directory-7 -> Directory-5 net_lat: 9
+ Directory-7 -> Directory-6 net_lat: 9
+
+--- End Topology Print ---
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: May/05/2009 07:44:03
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 600
+Elapsed_time_in_minutes: 10
+Elapsed_time_in_hours: 0.166667
+Elapsed_time_in_days: 0.00694444
+
+Virtual_time_in_seconds: 600.33
+Virtual_time_in_minutes: 10.0055
+Virtual_time_in_hours: 0.166758
+Virtual_time_in_days: 0.166758
+
+Ruby_current_time: 4446777
+Ruby_start_time: 1
+Ruby_cycles: 4446776
+
+mbytes_resident: 168.625
+mbytes_total: 457.891
+resident_ratio: 0.368273
+
+Total_misses: 721271
+total_misses: 721271 [ 90191 90177 90170 90159 90144 90184 90135 90111 ]
+user_misses: 721271 [ 90191 90177 90170 90159 90144 90184 90135 90111 ]
+supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
+
+instruction_executed: 8 [ 1 1 1 1 1 1 1 1 ]
+cycles_executed: 8 [ 1 1 1 1 1 1 1 1 ]
+cycles_per_instruction: 4.44678e+06 [ 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 ]
+misses_per_thousand_instructions: 9.01589e+07 [ 9.0191e+07 9.0177e+07 9.017e+07 9.0159e+07 9.0144e+07 9.0184e+07 9.0135e+07 9.0111e+07 ]
+
+transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
+transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
+instructions_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
+
+L1D_cache cache stats:
+ L1D_cache_total_misses: 745688
+ L1D_cache_total_demand_misses: 745688
+ L1D_cache_total_prefetches: 0
+ L1D_cache_total_sw_prefetches: 0
+ L1D_cache_total_hw_prefetches: 0
+ L1D_cache_misses_per_transaction: 745688
+ L1D_cache_misses_per_instruction: 745688
+ L1D_cache_instructions_per_misses: 1.34104e-06
+
+ L1D_cache_request_type_LD: 65.1516%
+ L1D_cache_request_type_ST: 34.8484%
+
+ L1D_cache_access_mode_type_UserMode: 745688 100%
+ L1D_cache_request_size: [binsize: log2 max: 1 count: 745688 average: 1 | standard deviation: 0 | 0 745688 ]
+
+L1I_cache cache stats:
+ L1I_cache_total_misses: 0
+ L1I_cache_total_demand_misses: 0
+ L1I_cache_total_prefetches: 0
+ L1I_cache_total_sw_prefetches: 0
+ L1I_cache_total_hw_prefetches: 0
+ L1I_cache_misses_per_transaction: 0
+ L1I_cache_misses_per_instruction: 0
+ L1I_cache_instructions_per_misses: NaN
+
+ L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+L2_cache cache stats:
+ L2_cache_total_misses: 721271
+ L2_cache_total_demand_misses: 721271
+ L2_cache_total_prefetches: 0
+ L2_cache_total_sw_prefetches: 0
+ L2_cache_total_hw_prefetches: 0
+ L2_cache_misses_per_transaction: 721271
+ L2_cache_misses_per_instruction: 721271
+ L2_cache_instructions_per_misses: 1.38644e-06
+
+ L2_cache_request_type_LD: 63.9719%
+ L2_cache_request_type_ST: 36.0281%
+
+ L2_cache_access_mode_type_UserMode: 721271 100%
+ L2_cache_request_size: [binsize: log2 max: 1 count: 721271 average: 1 | standard deviation: 0 | 0 721271 ]
+
+
+Busy Controller Counts:
+L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
+
+Directory-0:0 Directory-1:0 Directory-2:0 Directory-3:0 Directory-4:0 Directory-5:0 Directory-6:0 Directory-7:0
+
+
+Busy Bank Count:0
+
+L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+L2TBE_usage: [binsize: 1 max: 15 count: 721271 average: 2.03629 | standard deviation: 2.34771 | 143227 223076 166564 88859 41156 18332 8540 4969 3538 3168 3367 3419 3399 3457 3198 3002 ]
+StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 745688 average: 3.10967 | standard deviation: 2.34747 | 0 135014 224824 178310 98438 46220 20718 9529 5314 3675 3215 3360 3521 3368 3500 3258 3424 ]
+store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 8 max: 1116 count: 745669 average: 106.682 | standard deviation: 99.0818 | 24417 622 615 521 35683 54628 61710 64752 61426 56993 50743 43645 37419 32707 28113 24160 20402 17446 15135 13054 11166 9337 8153 7202 6087 5203 4349 3878 3227 2804 2344 2092 1784 1513 1405 1207 1044 926 815 785 646 657 585 540 532 530 552 516 525 517 552 512 548 540 592 609 634 610 628 609 600 596 622 617 575 568 506 532 504 535 484 441 430 386 424 360 346 330 303 267 268 265 243 208 204 186 194 183 190 188 161 169 164 165 153 148 142 133 136 123 117 101 109 110 96 102 94 82 115 83 80 67 72 56 43 50 40 32 28 26 27 20 15 15 11 11 8 10 12 7 4 6 9 3 4 2 3 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 8 max: 1116 count: 485819 average: 105.451 | standard deviation: 99.9404 | 24417 0 0 0 22626 34580 39558 41559 39317 36732 32549 27946 23929 21013 18042 15529 13125 11165 9814 8327 7126 6019 5331 4661 3925 3326 2749 2527 2019 1814 1505 1387 1182 973 911 794 687 625 536 526 404 426 376 345 350 349 371 328 352 345 353 330 353 341 365 373 403 402 406 367 392 370 393 397 366 372 322 330 327 364 310 288 280 251 285 249 233 209 206 172 189 178 161 142 134 117 126 110 124 129 101 113 109 109 99 97 84 90 82 76 72 71 78 70 69 70 73 53 82 57 56 45 47 39 27 29 27 24 23 20 17 12 7 10 8 7 6 8 10 4 3 3 6 1 3 1 2 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 8 max: 1112 count: 259850 average: 108.983 | standard deviation: 97.4146 | 0 622 615 521 13057 20048 22152 23193 22109 20261 18194 15699 13490 11694 10071 8631 7277 6281 5321 4727 4040 3318 2822 2541 2162 1877 1600 1351 1208 990 839 705 602 540 494 413 357 301 279 259 242 231 209 195 182 181 181 188 173 172 199 182 195 199 227 236 231 208 222 242 208 226 229 220 209 196 184 202 177 171 174 153 150 135 139 111 113 121 97 95 79 87 82 66 70 69 68 73 66 59 60 56 55 56 54 51 58 43 54 47 45 30 31 40 27 32 21 29 33 26 24 22 25 17 16 21 13 8 5 6 10 8 8 5 3 4 2 2 2 3 1 3 3 2 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 8 max: 1116 count: 745669 average: 106.682 | standard deviation: 99.0818 | 24417 622 615 521 35683 54628 61710 64752 61426 56993 50743 43645 37419 32707 28113 24160 20402 17446 15135 13054 11166 9337 8153 7202 6087 5203 4349 3878 3227 2804 2344 2092 1784 1513 1405 1207 1044 926 815 785 646 657 585 540 532 530 552 516 525 517 552 512 548 540 592 609 634 610 628 609 600 596 622 617 575 568 506 532 504 535 484 441 430 386 424 360 346 330 303 267 268 265 243 208 204 186 194 183 190 188 161 169 164 165 153 148 142 133 136 123 117 101 109 110 96 102 94 82 115 83 80 67 72 56 43 50 40 32 28 26 27 20 15 15 11 11 8 10 12 7 4 6 9 3 4 2 3 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+conflicting_histogram: [binsize: log2 max: 4446776 count: 721271 average: 2.2084e+06 | standard deviation: 2.55884e+06 | 0 0 0 1 2 6 10 24 46 86 63 240 490 927 1836 3670 6574 12027 21272 42384 84410 168738 337705 40760 ]
+conflicting_histogram_percent: [binsize: log2 max: 4446776 count: 721271 average: 2.2084e+06 | standard deviation: 2.55884e+06 | 0 0 0 0.000138644 0.000277288 0.000831865 0.00138644 0.00332746 0.00637763 0.0119234 0.00873458 0.0332746 0.0679356 0.128523 0.254551 0.508824 0.911447 1.66747 2.94924 5.87629 11.703 23.3945 46.8208 5.65114 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+ I M GETS 163897 22.7234
+ I M GETX 87421 12.1204
+ I OS GETS 106703 14.7938
+ I OS GETX 57217 7.93282
+ I OSS GETS 174691 24.22
+ I OSS GETX 93632 12.9816
+ NP C GETS 2027 0.281032
+ NP C GETX 1045 0.144884
+ NP M GETS 4871 0.675337
+ NP M GETX 2611 0.362001
+ NP OS GETS 2755 0.381966
+ NP OS GETX 1417 0.196459
+ NP OSS GETS 3034 0.420647
+ NP OSS GETX 1534 0.212681
+ NP S GETS 1318 0.182733
+ NP S GETX 704 0.0976057
+ NP SS GETS 2114 0.293095
+ NP SS GETX 1146 0.158887
+ O OS GETX 11 0.00152509
+ O OSS GETX 4695 0.650936
+ S M GETX 9 0.0012478
+ S OS GETX 1 0.000138645
+ S OSS GETX 8239 1.14229
+ S S GETX 5 0.000693223
+ S SS GETX 172 0.0238469
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 599
+system_time: 1
+page_reclaims: 43363
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 160
+MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:93207 full:0
+MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:93229 full:0
+MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:93192 full:0
+MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:93200 full:0
+MessageBuffer: [Chip 4 0, L1Cache, mandatoryQueue_in] stats - msgs:93207 full:0
+MessageBuffer: [Chip 5 0, L1Cache, mandatoryQueue_in] stats - msgs:93210 full:0
+MessageBuffer: [Chip 6 0, L1Cache, mandatoryQueue_in] stats - msgs:93209 full:0
+MessageBuffer: [Chip 7 0, L1Cache, mandatoryQueue_in] stats - msgs:93234 full:0
+
+Network Stats
+-------------
+
+switch_0_inlinks: 1
+switch_0_outlinks: 1
+links_utilized_percent_switch_0: 15.85
+ links_utilized_percent_switch_0_link_0: 15.85 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Control: 90191 721528 [ 90191 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Data: 87870 6326640 [ 0 87870 0 0 ] base_latency: 1
+
+switch_1_inlinks: 1
+switch_1_outlinks: 1
+links_utilized_percent_switch_1: 16.1391
+ links_utilized_percent_switch_1_link_0: 16.1391 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Control: 90177 721416 [ 90177 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Data: 89657 6455304 [ 0 89657 0 0 ] base_latency: 1
+
+switch_2_inlinks: 1
+switch_2_outlinks: 1
+links_utilized_percent_switch_2: 15.956
+ links_utilized_percent_switch_2_link_0: 15.956 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 90169 721352 [ 90169 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Data: 88527 6373944 [ 0 88527 0 0 ] base_latency: 1
+
+switch_3_inlinks: 1
+switch_3_outlinks: 1
+links_utilized_percent_switch_3: 15.9235
+ links_utilized_percent_switch_3_link_0: 15.9235 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Control: 90158 721264 [ 90158 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Data: 88327 6359544 [ 0 88327 0 0 ] base_latency: 1
+
+switch_4_inlinks: 1
+switch_4_outlinks: 1
+links_utilized_percent_switch_4: 15.9062
+ links_utilized_percent_switch_4_link_0: 15.9062 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_4_link_0_Control: 90144 721152 [ 90144 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_4_link_0_Data: 88222 6351984 [ 0 88222 0 0 ] base_latency: 1
+
+switch_5_inlinks: 1
+switch_5_outlinks: 1
+links_utilized_percent_switch_5: 15.8852
+ links_utilized_percent_switch_5_link_0: 15.8852 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_5_link_0_Control: 90184 721472 [ 90184 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Data: 88088 6342336 [ 0 88088 0 0 ] base_latency: 1
+
+switch_6_inlinks: 1
+switch_6_outlinks: 1
+links_utilized_percent_switch_6: 15.8419
+ links_utilized_percent_switch_6_link_0: 15.8419 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_6_link_0_Control: 90135 721080 [ 90135 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_6_link_0_Data: 87826 6323472 [ 0 87826 0 0 ] base_latency: 1
+
+switch_7_inlinks: 1
+switch_7_outlinks: 1
+links_utilized_percent_switch_7: 16.1135
+ links_utilized_percent_switch_7_link_0: 16.1135 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_7_link_0_Control: 90111 720888 [ 90111 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_7_link_0_Data: 89506 6444432 [ 0 89506 0 0 ] base_latency: 1
+
+switch_8_inlinks: 1
+switch_8_outlinks: 1
+links_utilized_percent_switch_8: 0.167582
+ links_utilized_percent_switch_8_link_0: 0.167582 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_8_link_0_Data: 1035 74520 [ 0 1035 0 0 ] base_latency: 1
+
+switch_9_inlinks: 1
+switch_9_outlinks: 1
+links_utilized_percent_switch_9: 0.165477
+ links_utilized_percent_switch_9_link_0: 0.165477 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_9_link_0_Data: 1022 73584 [ 0 1022 0 0 ] base_latency: 1
+
+switch_10_inlinks: 1
+switch_10_outlinks: 1
+links_utilized_percent_switch_10: 0.167258
+ links_utilized_percent_switch_10_link_0: 0.167258 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_10_link_0_Data: 1033 74376 [ 0 1033 0 0 ] base_latency: 1
+
+switch_11_inlinks: 1
+switch_11_outlinks: 1
+links_utilized_percent_switch_11: 0.173735
+ links_utilized_percent_switch_11_link_0: 0.173735 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_11_link_0_Data: 1073 77256 [ 0 1073 0 0 ] base_latency: 1
+
+switch_12_inlinks: 1
+switch_12_outlinks: 1
+links_utilized_percent_switch_12: 0.181507
+ links_utilized_percent_switch_12_link_0: 0.181507 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_12_link_0_Data: 1121 80712 [ 0 1121 0 0 ] base_latency: 1
+
+switch_13_inlinks: 1
+switch_13_outlinks: 1
+links_utilized_percent_switch_13: 0.184097
+ links_utilized_percent_switch_13_link_0: 0.184097 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_13_link_0_Data: 1137 81864 [ 0 1137 0 0 ] base_latency: 1
+
+switch_14_inlinks: 1
+switch_14_outlinks: 1
+links_utilized_percent_switch_14: 0.170011
+ links_utilized_percent_switch_14_link_0: 0.170011 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_14_link_0_Data: 1050 75600 [ 0 1050 0 0 ] base_latency: 1
+
+switch_15_inlinks: 1
+switch_15_outlinks: 1
+links_utilized_percent_switch_15: 0.17163
+ links_utilized_percent_switch_15_link_0: 0.17163 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_15_link_0_Data: 1060 76320 [ 0 1060 0 0 ] base_latency: 1
+
+switch_16_inlinks: 4
+switch_16_outlinks: 1
+links_utilized_percent_switch_16: 63.8683
+ links_utilized_percent_switch_16_link_0: 63.8683 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_16_link_0_Control: 360695 2885560 [ 360695 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_16_link_0_Data: 354379 25515288 [ 0 354379 0 0 ] base_latency: 1
+
+switch_17_inlinks: 4
+switch_17_outlinks: 1
+links_utilized_percent_switch_17: 63.7469
+ links_utilized_percent_switch_17_link_0: 63.7469 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_17_link_0_Control: 360574 2884592 [ 360574 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_17_link_0_Data: 353642 25462224 [ 0 353642 0 0 ] base_latency: 1
+
+switch_18_inlinks: 4
+switch_18_outlinks: 1
+links_utilized_percent_switch_18: 0.674052
+ links_utilized_percent_switch_18_link_0: 0.674052 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_18_link_0_Data: 4163 299736 [ 0 4163 0 0 ] base_latency: 1
+
+switch_19_inlinks: 4
+switch_19_outlinks: 1
+links_utilized_percent_switch_19: 0.707245
+ links_utilized_percent_switch_19_link_0: 0.707245 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_19_link_0_Data: 4368 314496 [ 0 4368 0 0 ] base_latency: 1
+
+switch_20_inlinks: 4
+switch_20_outlinks: 4
+links_utilized_percent_switch_20: 38.737
+ links_utilized_percent_switch_20_link_0: 71.0033 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_20_link_1: 70.9688 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_20_link_2: 6.48531 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_20_link_3: 6.49072 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_20_link_0_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_20_link_0_Data: 358382 25803504 [ 0 358382 0 0 ] base_latency: 1
+ outgoing_messages_switch_20_link_1_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_20_link_1_Data: 358170 25788240 [ 0 358170 0 0 ] base_latency: 1
+ outgoing_messages_switch_20_link_2_Control: 360484 2883872 [ 360484 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_20_link_3_Control: 360785 2886280 [ 360785 0 0 0 ] base_latency: 1
+
+switch_21_inlinks: 1
+switch_21_outlinks: 4
+links_utilized_percent_switch_21: 27.4829
+ links_utilized_percent_switch_21_link_0: 27.4857 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_21_link_1: 27.4791 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_21_link_2: 27.4873 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_21_link_3: 27.4793 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_21_link_0_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_21_link_0_Data: 89613 6452136 [ 0 89613 0 0 ] base_latency: 1
+ outgoing_messages_switch_21_link_1_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_21_link_1_Data: 89572 6449184 [ 0 89572 0 0 ] base_latency: 1
+ outgoing_messages_switch_21_link_2_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_21_link_2_Data: 89623 6452856 [ 0 89623 0 0 ] base_latency: 1
+ outgoing_messages_switch_21_link_3_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_21_link_3_Data: 89573 6449256 [ 0 89573 0 0 ] base_latency: 1
+
+switch_22_inlinks: 1
+switch_22_outlinks: 4
+links_utilized_percent_switch_22: 27.474
+ links_utilized_percent_switch_22_link_0: 27.4713 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_22_link_1: 27.4807 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_22_link_2: 27.4725 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_22_link_3: 27.4715 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_22_link_0_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_22_link_0_Data: 89526 6445872 [ 0 89526 0 0 ] base_latency: 1
+ outgoing_messages_switch_22_link_1_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_22_link_1_Data: 89584 6450048 [ 0 89584 0 0 ] base_latency: 1
+ outgoing_messages_switch_22_link_2_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_22_link_2_Data: 89533 6446376 [ 0 89533 0 0 ] base_latency: 1
+ outgoing_messages_switch_22_link_3_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_22_link_3_Data: 89527 6445944 [ 0 89527 0 0 ] base_latency: 1
+
+switch_23_inlinks: 1
+switch_23_outlinks: 4
+links_utilized_percent_switch_23: 1.62133
+ links_utilized_percent_switch_23_link_0: 1.6212 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_23_link_1: 1.62023 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_23_link_2: 1.62027 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_23_link_3: 1.62361 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_23_link_0_Control: 90114 720912 [ 90114 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_23_link_1_Control: 90060 720480 [ 90060 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_23_link_2_Control: 90062 720496 [ 90062 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_23_link_3_Control: 90248 721984 [ 90248 0 0 0 ] base_latency: 1
+
+switch_24_inlinks: 1
+switch_24_outlinks: 4
+links_utilized_percent_switch_24: 1.62268
+ links_utilized_percent_switch_24_link_0: 1.62295 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_24_link_1: 1.62417 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_24_link_2: 1.62052 bw: 10000 base_latency: 1
+ links_utilized_percent_switch_24_link_3: 1.62309 bw: 10000 base_latency: 1
+
+ outgoing_messages_switch_24_link_0_Control: 90211 721688 [ 90211 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_24_link_1_Control: 90279 722232 [ 90279 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_24_link_2_Control: 90076 720608 [ 90076 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_24_link_3_Control: 90219 721752 [ 90219 0 0 0 ] base_latency: 1
+
+
+Chip Stats
+----------
+
+ --- L1Cache ---
+ - Event Counts -
+Load 485828
+Ifetch 0
+Store 259860
+L1_to_L2 737242
+L2_to_L1D 720852
+L2_to_L1I 0
+L2_Replacement 0
+Own_GETS 461405
+Own_GET_INSTR 0
+Own_GETX 259855
+Own_PUTX 0
+Other_GETS 3229843
+Other_GET_INSTR 0
+Other_GETX 1818981
+Other_PUTX 0
+Data 716551
+
+ - Transitions -
+NP Load 16119
+NP Ifetch 0 <--
+NP Store 8457
+NP Other_GETS 58716
+NP Other_GET_INSTR 0 <--
+NP Other_GETX 31715
+NP Other_PUTX 0 <--
+
+I Load 445292
+I Ifetch 0 <--
+I Store 238271
+I L1_to_L2 409661
+I L2_to_L1D 683358
+I L2_to_L1I 0 <--
+I L2_Replacement 0 <--
+I Other_GETS 2030822
+I Other_GET_INSTR 0 <--
+I Other_GETX 1087031
+I Other_PUTX 0 <--
+
+S Load 15687
+S Ifetch 0 <--
+S Store 8426
+S L1_to_L2 209306
+S L2_to_L1D 24075
+S L2_to_L1I 0 <--
+S L2_Replacement 0 <--
+S Other_GETS 682440
+S Other_GET_INSTR 0 <--
+S Other_GETX 447103
+S Other_PUTX 0 <--
+
+O Load 8725
+O Ifetch 0 <--
+O Store 4706
+O L1_to_L2 89987
+O L2_to_L1D 13414
+O L2_to_L1I 0 <--
+O L2_Replacement 0 <--
+O Other_GETS 287176
+O Other_GET_INSTR 0 <--
+O Other_GETX 162038
+O Other_PUTX 0 <--
+
+M Load 5
+M Ifetch 0 <--
+M Store 0 <--
+M L1_to_L2 28282
+M L2_to_L1D 5
+M L2_to_L1I 0 <--
+M L2_Replacement 0 <--
+M Other_GETS 168458
+M Other_GET_INSTR 0 <--
+M Other_GETX 89842
+M Other_PUTX 0 <--
+
+IS_AD Load 0 <--
+IS_AD Ifetch 0 <--
+IS_AD Store 0 <--
+IS_AD L1_to_L2 0 <--
+IS_AD L2_to_L1D 0 <--
+IS_AD L2_to_L1I 0 <--
+IS_AD L2_Replacement 0 <--
+IS_AD Own_GETS 408918
+IS_AD Own_GET_INSTR 0 <--
+IS_AD Other_GETS 753
+IS_AD Other_GET_INSTR 0 <--
+IS_AD Other_GETX 445
+IS_AD Other_PUTX 0 <--
+IS_AD Data 52490
+
+IM_AD Load 0 <--
+IM_AD Ifetch 0 <--
+IM_AD Store 0 <--
+IM_AD L1_to_L2 0 <--
+IM_AD L2_to_L1D 0 <--
+IM_AD L2_to_L1I 0 <--
+IM_AD L2_Replacement 0 <--
+IM_AD Own_GETX 218774
+IM_AD Other_GETS 401
+IM_AD Other_GET_INSTR 0 <--
+IM_AD Other_GETX 262
+IM_AD Other_PUTX 0 <--
+IM_AD Data 27960
+
+SM_AD Load 0 <--
+SM_AD Ifetch 0 <--
+SM_AD Store 0 <--
+SM_AD L1_to_L2 0 <--
+SM_AD L2_to_L1D 0 <--
+SM_AD L2_to_L1I 0 <--
+SM_AD L2_Replacement 0 <--
+SM_AD Own_GETX 7503
+SM_AD Other_GETS 2
+SM_AD Other_GET_INSTR 0 <--
+SM_AD Other_GETX 9
+SM_AD Other_PUTX 0 <--
+SM_AD Data 914
+
+OM_A Load 0 <--
+OM_A Ifetch 0 <--
+OM_A Store 0 <--
+OM_A L1_to_L2 0 <--
+OM_A L2_to_L1D 0 <--
+OM_A L2_to_L1I 0 <--
+OM_A L2_Replacement 0 <--
+OM_A Own_GETX 4705
+OM_A Other_GETS 4
+OM_A Other_GET_INSTR 0 <--
+OM_A Other_GETX 0 <--
+OM_A Other_PUTX 0 <--
+OM_A Data 0 <--
+
+IS_A Load 0 <--
+IS_A Ifetch 0 <--
+IS_A Store 0 <--
+IS_A L1_to_L2 0 <--
+IS_A L2_to_L1D 0 <--
+IS_A L2_to_L1I 0 <--
+IS_A L2_Replacement 0 <--
+IS_A Own_GETS 52487
+IS_A Own_GET_INSTR 0 <--
+IS_A Other_GETS 95
+IS_A Other_GET_INSTR 0 <--
+IS_A Other_GETX 14
+IS_A Other_PUTX 0 <--
+
+IM_A Load 0 <--
+IM_A Ifetch 0 <--
+IM_A Store 0 <--
+IM_A L1_to_L2 0 <--
+IM_A L2_to_L1D 0 <--
+IM_A L2_to_L1I 0 <--
+IM_A L2_Replacement 0 <--
+IM_A Own_GETX 27959
+IM_A Other_GETS 53
+IM_A Other_GET_INSTR 0 <--
+IM_A Other_GETX 12
+IM_A Other_PUTX 0 <--
+
+SM_A Load 0 <--
+SM_A Ifetch 0 <--
+SM_A Store 0 <--
+SM_A L1_to_L2 0 <--
+SM_A L2_to_L1D 0 <--
+SM_A L2_to_L1I 0 <--
+SM_A L2_Replacement 0 <--
+SM_A Own_GETX 914
+SM_A Other_GETS 2
+SM_A Other_GET_INSTR 0 <--
+SM_A Other_GETX 0 <--
+SM_A Other_PUTX 0 <--
+
+MI_A Load 0 <--
+MI_A Ifetch 0 <--
+MI_A Store 0 <--
+MI_A L1_to_L2 0 <--
+MI_A L2_to_L1D 0 <--
+MI_A L2_to_L1I 0 <--
+MI_A L2_Replacement 0 <--
+MI_A Own_PUTX 0 <--
+MI_A Other_GETS 0 <--
+MI_A Other_GET_INSTR 0 <--
+MI_A Other_GETX 0 <--
+MI_A Other_PUTX 0 <--
+
+OI_A Load 0 <--
+OI_A Ifetch 0 <--
+OI_A Store 0 <--
+OI_A L1_to_L2 0 <--
+OI_A L2_to_L1D 0 <--
+OI_A L2_to_L1I 0 <--
+OI_A L2_Replacement 0 <--
+OI_A Own_PUTX 0 <--
+OI_A Other_GETS 0 <--
+OI_A Other_GET_INSTR 0 <--
+OI_A Other_GETX 0 <--
+OI_A Other_PUTX 0 <--
+
+II_A Load 0 <--
+II_A Ifetch 0 <--
+II_A Store 0 <--
+II_A L1_to_L2 0 <--
+II_A L2_to_L1D 0 <--
+II_A L2_to_L1I 0 <--
+II_A L2_Replacement 0 <--
+II_A Own_PUTX 0 <--
+II_A Other_GETS 0 <--
+II_A Other_GET_INSTR 0 <--
+II_A Other_GETX 0 <--
+II_A Other_PUTX 0 <--
+
+IS_D Load 0 <--
+IS_D Ifetch 0 <--
+IS_D Store 0 <--
+IS_D L1_to_L2 6
+IS_D L2_to_L1D 0 <--
+IS_D L2_to_L1I 0 <--
+IS_D L2_Replacement 0 <--
+IS_D Other_GETS 611
+IS_D Other_GET_INSTR 0 <--
+IS_D Other_GETX 314
+IS_D Other_PUTX 0 <--
+IS_D Data 408601
+
+IS_D_I Load 0 <--
+IS_D_I Ifetch 0 <--
+IS_D_I Store 0 <--
+IS_D_I L1_to_L2 0 <--
+IS_D_I L2_to_L1D 0 <--
+IS_D_I L2_to_L1I 0 <--
+IS_D_I L2_Replacement 0 <--
+IS_D_I Other_GETS 0 <--
+IS_D_I Other_GET_INSTR 0 <--
+IS_D_I Other_GETX 0 <--
+IS_D_I Other_PUTX 0 <--
+IS_D_I Data 314
+
+IM_D Load 0 <--
+IM_D Ifetch 0 <--
+IM_D Store 0 <--
+IM_D L1_to_L2 0 <--
+IM_D L2_to_L1D 0 <--
+IM_D L2_to_L1I 0 <--
+IM_D L2_Replacement 0 <--
+IM_D Other_GETS 302
+IM_D Other_GET_INSTR 0 <--
+IM_D Other_GETX 188
+IM_D Other_PUTX 0 <--
+IM_D Data 218279
+
+IM_D_O Load 0 <--
+IM_D_O Ifetch 0 <--
+IM_D_O Store 0 <--
+IM_D_O L1_to_L2 0 <--
+IM_D_O L2_to_L1D 0 <--
+IM_D_O L2_to_L1I 0 <--
+IM_D_O L2_Replacement 0 <--
+IM_D_O Other_GETS 0 <--
+IM_D_O Other_GET_INSTR 0 <--
+IM_D_O Other_GETX 0 <--
+IM_D_O Other_PUTX 0 <--
+IM_D_O Data 302
+
+IM_D_I Load 0 <--
+IM_D_I Ifetch 0 <--
+IM_D_I Store 0 <--
+IM_D_I L1_to_L2 0 <--
+IM_D_I L2_to_L1D 0 <--
+IM_D_I L2_to_L1I 0 <--
+IM_D_I L2_Replacement 0 <--
+IM_D_I Other_GETS 1
+IM_D_I Other_GET_INSTR 0 <--
+IM_D_I Other_GETX 0 <--
+IM_D_I Other_PUTX 0 <--
+IM_D_I Data 196
+
+IM_D_OI Load 0 <--
+IM_D_OI Ifetch 0 <--
+IM_D_OI Store 0 <--
+IM_D_OI L1_to_L2 0 <--
+IM_D_OI L2_to_L1D 0 <--
+IM_D_OI L2_to_L1I 0 <--
+IM_D_OI L2_Replacement 0 <--
+IM_D_OI Other_GETS 0 <--
+IM_D_OI Other_GET_INSTR 0 <--
+IM_D_OI Other_GETX 0 <--
+IM_D_OI Other_PUTX 0 <--
+IM_D_OI Data 0 <--
+
+SM_D Load 0 <--
+SM_D Ifetch 0 <--
+SM_D Store 0 <--
+SM_D L1_to_L2 0 <--
+SM_D L2_to_L1D 0 <--
+SM_D L2_to_L1I 0 <--
+SM_D L2_Replacement 0 <--
+SM_D Other_GETS 7
+SM_D Other_GET_INSTR 0 <--
+SM_D Other_GETX 8
+SM_D Other_PUTX 0 <--
+SM_D Data 7488
+
+SM_D_O Load 0 <--
+SM_D_O Ifetch 0 <--
+SM_D_O Store 0 <--
+SM_D_O L1_to_L2 0 <--
+SM_D_O L2_to_L1D 0 <--
+SM_D_O L2_to_L1I 0 <--
+SM_D_O L2_Replacement 0 <--
+SM_D_O Other_GETS 0 <--
+SM_D_O Other_GET_INSTR 0 <--
+SM_D_O Other_GETX 0 <--
+SM_D_O Other_PUTX 0 <--
+SM_D_O Data 7
+
+ --- Directory ---
+ - Event Counts -
+OtherAddress 0
+GETS 461410
+GET_INSTR 0
+GETX 259859
+PUTX_Owner 0
+PUTX_NotOwner 0
+
+ - Transitions -
+C OtherAddress 0 <--
+C GETS 2027
+C GET_INSTR 0 <--
+C GETX 1045
+
+I GETS 0 <--
+I GET_INSTR 0 <--
+I GETX 0 <--
+I PUTX_NotOwner 0 <--
+
+S GETS 1318
+S GET_INSTR 0 <--
+S GETX 709
+S PUTX_NotOwner 0 <--
+
+SS GETS 2114
+SS GET_INSTR 0 <--
+SS GETX 1318
+SS PUTX_NotOwner 0 <--
+
+OS GETS 109458
+OS GET_INSTR 0 <--
+OS GETX 58646
+OS PUTX_Owner 0 <--
+OS PUTX_NotOwner 0 <--
+
+OSS GETS 177725
+OSS GET_INSTR 0 <--
+OSS GETX 108100
+OSS PUTX_Owner 0 <--
+OSS PUTX_NotOwner 0 <--
+
+M GETS 168768
+M GET_INSTR 0 <--
+M GETX 90041
+M PUTX_Owner 0 <--
+M PUTX_NotOwner 0 <--
+
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
new file mode 100755
index 000000000..328821d4a
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -0,0 +1,74 @@
+system.cpu7: completed 10000 read accesses @483405
+system.cpu1: completed 10000 read accesses @489648
+system.cpu2: completed 10000 read accesses @489706
+system.cpu5: completed 10000 read accesses @490354
+system.cpu0: completed 10000 read accesses @492776
+system.cpu4: completed 10000 read accesses @495396
+system.cpu6: completed 10000 read accesses @497104
+system.cpu3: completed 10000 read accesses @497952
+system.cpu7: completed 20000 read accesses @923382
+system.cpu5: completed 20000 read accesses @926026
+system.cpu1: completed 20000 read accesses @927265
+system.cpu2: completed 20000 read accesses @930725
+system.cpu3: completed 20000 read accesses @933398
+system.cpu6: completed 20000 read accesses @936538
+system.cpu0: completed 20000 read accesses @938376
+system.cpu4: completed 20000 read accesses @941944
+system.cpu5: completed 30000 read accesses @1362075
+system.cpu1: completed 30000 read accesses @1364620
+system.cpu7: completed 30000 read accesses @1365206
+system.cpu2: completed 30000 read accesses @1372346
+system.cpu3: completed 30000 read accesses @1372730
+system.cpu6: completed 30000 read accesses @1377457
+system.cpu0: completed 30000 read accesses @1377608
+system.cpu4: completed 30000 read accesses @1384598
+system.cpu7: completed 40000 read accesses @1798226
+system.cpu1: completed 40000 read accesses @1802550
+system.cpu5: completed 40000 read accesses @1803508
+system.cpu2: completed 40000 read accesses @1813044
+system.cpu0: completed 40000 read accesses @1813249
+system.cpu6: completed 40000 read accesses @1814460
+system.cpu3: completed 40000 read accesses @1816124
+system.cpu4: completed 40000 read accesses @1829214
+system.cpu7: completed 50000 read accesses @2240501
+system.cpu0: completed 50000 read accesses @2243543
+system.cpu1: completed 50000 read accesses @2245806
+system.cpu5: completed 50000 read accesses @2246126
+system.cpu2: completed 50000 read accesses @2254021
+system.cpu3: completed 50000 read accesses @2256564
+system.cpu6: completed 50000 read accesses @2258894
+system.cpu4: completed 50000 read accesses @2271354
+system.cpu7: completed 60000 read accesses @2684820
+system.cpu5: completed 60000 read accesses @2685946
+system.cpu0: completed 60000 read accesses @2687254
+system.cpu1: completed 60000 read accesses @2688183
+system.cpu6: completed 60000 read accesses @2690040
+system.cpu2: completed 60000 read accesses @2690996
+system.cpu3: completed 60000 read accesses @2703034
+system.cpu4: completed 60000 read accesses @2716020
+system.cpu7: completed 70000 read accesses @3125991
+system.cpu0: completed 70000 read accesses @3129042
+system.cpu1: completed 70000 read accesses @3129110
+system.cpu6: completed 70000 read accesses @3130362
+system.cpu5: completed 70000 read accesses @3131396
+system.cpu2: completed 70000 read accesses @3139286
+system.cpu3: completed 70000 read accesses @3141858
+system.cpu4: completed 70000 read accesses @3162690
+system.cpu0: completed 80000 read accesses @3563564
+system.cpu1: completed 80000 read accesses @3566188
+system.cpu7: completed 80000 read accesses @3566291
+system.cpu6: completed 80000 read accesses @3571624
+system.cpu5: completed 80000 read accesses @3574146
+system.cpu3: completed 80000 read accesses @3580572
+system.cpu2: completed 80000 read accesses @3586246
+system.cpu4: completed 80000 read accesses @3599364
+system.cpu0: completed 90000 read accesses @4000938
+system.cpu7: completed 90000 read accesses @4005441
+system.cpu1: completed 90000 read accesses @4006993
+system.cpu5: completed 90000 read accesses @4009374
+system.cpu6: completed 90000 read accesses @4017392
+system.cpu3: completed 90000 read accesses @4018754
+system.cpu2: completed 90000 read accesses @4031534
+system.cpu4: completed 90000 read accesses @4042150
+system.cpu1: completed 100000 read accesses @4446776
+hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
new file mode 100755
index 000000000..02f5b1fde
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -0,0 +1,22 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 5 2009 07:34:00
+M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
+M5 started May 5 2009 07:34:03
+M5 executing on piton
+command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
+Global frequency set at 1000000000000 ticks per second
+Ruby Timing Mode
+Creating event queue...
+Creating event queue done
+Creating system...
+ Processors: 8
+Creating system done
+Ruby initialization complete
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 4446776 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
new file mode 100644
index 000000000..d6d174c7f
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -0,0 +1,34 @@
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 468884 # Number of bytes of host memory used
+host_seconds 600.21 # Real time elapsed on the host
+host_tick_rate 7409 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_seconds 0.000004 # Number of seconds simulated
+sim_ticks 4446776 # Number of ticks simulated
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 99923 # number of read accesses completed
+system.cpu0.num_writes 53542 # number of write accesses completed
+system.cpu1.num_copies 0 # number of copy accesses completed
+system.cpu1.num_reads 100000 # number of read accesses completed
+system.cpu1.num_writes 53649 # number of write accesses completed
+system.cpu2.num_copies 0 # number of copy accesses completed
+system.cpu2.num_reads 99460 # number of read accesses completed
+system.cpu2.num_writes 53552 # number of write accesses completed
+system.cpu3.num_copies 0 # number of copy accesses completed
+system.cpu3.num_reads 99751 # number of read accesses completed
+system.cpu3.num_writes 53614 # number of write accesses completed
+system.cpu4.num_copies 0 # number of copy accesses completed
+system.cpu4.num_reads 99278 # number of read accesses completed
+system.cpu4.num_writes 53437 # number of write accesses completed
+system.cpu5.num_copies 0 # number of copy accesses completed
+system.cpu5.num_reads 99949 # number of read accesses completed
+system.cpu5.num_writes 53857 # number of write accesses completed
+system.cpu6.num_copies 0 # number of copy accesses completed
+system.cpu6.num_reads 99812 # number of read accesses completed
+system.cpu6.num_writes 53539 # number of write accesses completed
+system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu7.num_reads 99962 # number of read accesses completed
+system.cpu7.num_writes 53947 # number of write accesses completed
+
+---------- End Simulation Statistics ----------
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 19:11:44 +0000