diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
| commit | b85690e239616b703881b7734b0559f61f9eb75e (patch) | |
| tree | f144325bc982177a8ff0d87ba87cc9e840bfb301 /tests/quick | |
| parent | c30e615689148c6e5ecd06e86069cba716dec5e0 (diff) | |
| download | gem5-b85690e239616b703881b7734b0559f61f9eb75e.tar.xz | |
update all the regresstion tests for release
--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
Diffstat (limited to 'tests/quick')
95 files changed, 6204 insertions, 3271 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 2a139492e..882c78529 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 8155faf63..701034053 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 86aa4129f..c07021f5a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 606 # Number of BTB hits -global.BPredUnit.BTBLookups 1858 # Number of BTB lookups -global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted -global.BPredUnit.lookups 2195 # Number of BP lookups -global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -host_inst_rate 22780 # Simulator instruction rate (inst/s) +global.BPredUnit.BTBHits 524 # Number of BTB hits +global.BPredUnit.BTBLookups 1590 # Number of BTB lookups +global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted +global.BPredUnit.lookups 1843 # Number of BP lookups +global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target. +host_inst_rate 54565 # Simulator instruction rate (inst/s) host_mem_usage 154084 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host -host_tick_rate 14337041 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit. +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 44392410 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 127 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1144 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 3543500 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4588000 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6315 +system.cpu.commit.COM:committed_per_cycle.samples 8514 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 4255 6737.93% - 1 915 1448.93% - 2 408 646.08% - 3 162 256.53% - 4 140 221.69% - 5 91 144.10% - 6 121 191.61% - 7 102 161.52% - 8 121 191.61% + 0 6195 7276.25% + 1 1158 1360.11% + 2 469 550.86% + 3 176 206.72% + 4 131 153.86% + 5 99 116.28% + 6 109 128.02% + 7 73 85.74% + 8 104 122.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3588 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses +system.cpu.cpi 1.635604 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.635604 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5928.571429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5385 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1342 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.090169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 538500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.067797 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 4501.457726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1544000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.468208 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses -system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2287 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1811 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2332500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208133 # miss rate for demand accesses +system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 912000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2287 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1857 # number of overall hits -system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses -system.cpu.dcache.overall_misses 471 # number of overall misses -system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 1811 # number of overall hits +system.cpu.dcache.overall_miss_latency 2332500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208133 # miss rate for overall accesses +system.cpu.dcache.overall_misses 476 # number of overall misses +system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 912000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use -system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 112.670676 # Cycle average of tags in use +system.cpu.dcache.total_refs 1811 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched -system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 144 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10499 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1848 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 1843 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1471 # Number of cache lines fetched +system.cpu.fetch.Cycles 3451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11450 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.200391 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 765 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.244971 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 7088 +system.cpu.fetch.rateDist.samples 9197 system.cpu.fetch.rateDist.min_value 0 - 0 4755 6708.52% - 1 197 277.93% - 2 177 249.72% - 3 163 229.97% - 4 234 330.14% - 5 170 239.84% - 6 198 279.35% - 7 114 160.84% - 8 1080 1523.70% + 0 7219 7849.30% + 1 167 181.58% + 2 147 159.83% + 3 129 140.26% + 4 200 217.46% + 5 139 151.14% + 6 181 196.80% + 7 99 107.64% + 8 916 995.98% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1471 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5375.757576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4524.038462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1141 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1774000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.224337 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1411500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.212101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.657051 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency -system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses -system.cpu.icache.demand_misses 328 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1471 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency +system.cpu.icache.demand_hits 1141 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1774000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.224337 # miss rate for demand accesses +system.cpu.icache.demand_misses 330 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1411500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.212101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1471 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1288 # number of overall hits -system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses -system.cpu.icache.overall_misses 328 # number of overall misses -system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses +system.cpu.icache.overall_hits 1141 # number of overall hits +system.cpu.icache.overall_miss_latency 1774000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.224337 # miss rate for overall accesses +system.cpu.icache.overall_misses 330 # number of overall misses +system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1411500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.212101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use -system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.938349 # Cycle average of tags in use +system.cpu.icache.total_refs 1141 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1203 # Number of branches executed -system.cpu.iew.EXEC:nop 41 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate -system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.idleCycles 2475 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1148 # Number of branches executed +system.cpu.iew.EXEC:nop 40 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.837338 # Inst execution rate +system.cpu.iew.EXEC:refs 2524 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 977 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5598 # num instructions consuming a value -system.cpu.iew.WB:count 7767 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back +system.cpu.iew.WB:consumers 5205 # num instructions consuming a value +system.cpu.iew.WB:count 7402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.742747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4153 # num instructions producing a value -system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle -system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions +system.cpu.iew.WB:producers 3866 # num instructions producing a value +system.cpu.iew.WB:rate 0.804828 # insts written-back per cycle +system.cpu.iew.WB:sent 7467 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1876 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1144 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9245 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1547 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 280 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 682 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 897 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 332 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.611395 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5713 66.97% # Type of FU issued + (null) 2 0.03% # Type of FU issued + IntAlu 5322 66.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued + FloatAdd 2 0.03% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1773 20.78% # Type of FU issued - MemWrite 1040 12.19% # Type of FU issued + MemRead 1662 20.82% # Type of FU issued + MemWrite 992 12.43% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 7 5.47% # attempts to use FU when none available + IntAlu 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 78 60.94% # attempts to use FU when none available - MemWrite 43 33.59% # attempts to use FU when none available + MemRead 71 66.98% # attempts to use FU when none available + MemWrite 35 33.02% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 7088 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9197 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 4068 5739.28% - 1 771 1087.75% - 2 763 1076.47% - 3 485 684.26% - 4 504 711.06% - 5 295 416.20% - 6 144 203.16% - 7 40 56.43% - 8 18 25.40% + 0 5952 6471.68% + 1 1107 1203.65% + 2 919 999.24% + 3 442 480.59% + 4 375 407.74% + 5 250 271.83% + 6 115 125.04% + 7 26 28.27% + 8 11 11.96% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate -system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.867783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 7981 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2045 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4639.751553 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2463.768116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2241000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1190000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2241000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1190000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2241000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 485 # number of overall misses +system.cpu.l2cache.overall_misses 483 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1190000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,28 +380,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 278.222582 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 7088 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking +system.cpu.numCycles 9197 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IdleCycles 6383 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 12854 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 7485 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1746 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3434 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 25 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index eeba3846f..3ab3ef422 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:06 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:39 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 3543500 because target called exit() +Exiting @ tick 4588000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 26009ca4f..bf00075ce 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index f8e40871a..117159126 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 0f64469e9..4e1bd9447 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 357156 # Simulator instruction rate (inst/s) -host_mem_usage 148180 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 171417285 # Simulator tick rate (ticks/s) +host_inst_rate 576538 # Simulator instruction rate (inst/s) +host_mem_usage 148208 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 276546720 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 5acc408a3..6848303a8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:08 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:40 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 025531062..6daf0bd85 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index fa1054e9e..7041702bf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index afdac247d..ad908bf47 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 215467 # Simulator instruction rate (inst/s) -host_mem_usage 153656 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 193088667 # Simulator tick rate (ticks/s) +host_inst_rate 280990 # Simulator instruction rate (inst/s) +host_mem_usage 153668 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 642654954 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5135000 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13168000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3750 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1288000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 253000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1196000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3582.191781 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2582.191781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 261500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1022000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 949000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3675.757576 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 606500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2310000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 441500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2145000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3675.757576 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 606500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2310000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 441500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2145000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 105.359700 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.640117 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3729.241877 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2729.241877 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13960.288809 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12960.288809 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1033000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3867000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3590000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3729.241877 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1033000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3867000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3590000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3729.241877 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 1033000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3867000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 756000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3590000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 131.245403 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.241810 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2712.018141 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1711.018141 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1196000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 754559 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4851000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2712.018141 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1196000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5733000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 754559 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2712.018141 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1196000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5733000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 754559 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 236.577060 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 232.802947 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5135000 # number of cpu cycles simulated +system.cpu.numCycles 13168000 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index a79e87c66..3fc11f801 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:09 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:40 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5135000 because target called exit() +Exiting @ tick 13168000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 1e3b2746e..40a8f1a84 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 5df02e4ff..46dc2c36a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index d3074bcf9..c1b1b7625 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 162 # Number of BTB hits -global.BPredUnit.BTBLookups 671 # Number of BTB lookups -global.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 427 # Number of conditional branches predicted -global.BPredUnit.lookups 860 # Number of BP lookups -global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -host_inst_rate 31252 # Simulator instruction rate (inst/s) +global.BPredUnit.BTBHits 132 # Number of BTB hits +global.BPredUnit.BTBLookups 584 # Number of BTB lookups +global.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 208 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 376 # Number of conditional branches predicted +global.BPredUnit.lookups 738 # Number of BP lookups +global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target. +host_inst_rate 54176 # Simulator instruction rate (inst/s) host_mem_usage 153592 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 21107113 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 46286693 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 385 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 357 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1619000 # Number of ticks simulated +sim_ticks 2053000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 2977 +system.cpu.commit.COM:committed_per_cycle.samples 3906 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 2102 7060.80% - 1 212 712.13% - 2 297 997.65% - 3 114 382.94% - 4 83 278.80% - 5 58 194.83% - 6 30 100.77% - 7 22 73.90% - 8 59 198.19% + 0 2949 7549.92% + 1 266 681.00% + 2 333 852.53% + 3 131 335.38% + 4 74 189.45% + 5 64 163.85% + 6 29 74.24% + 7 19 48.64% + 8 41 104.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 128 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 465 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 333000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.134078 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 232500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.113594 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.cpi 1.721408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.721408 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5456.521739 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4737.288136 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5013.888889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4520.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 361000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 108500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 5669.014085 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5020 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 223 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 402500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.241497 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 71 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.085034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 25 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.082353 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.952381 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 831 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4819.444444 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_hits 687 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 694000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.173285 # miss rate for demand accesses -system.cpu.dcache.demand_misses 144 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102286 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 779000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses +system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 405000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 831 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4819.444444 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 687 # number of overall hits -system.cpu.dcache.overall_miss_latency 694000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.173285 # miss rate for overall accesses -system.cpu.dcache.overall_misses 144 # number of overall misses -system.cpu.dcache.overall_mshr_hits 59 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102286 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses +system.cpu.dcache.overall_hits 668 # number of overall hits +system.cpu.dcache.overall_miss_latency 779000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses +system.cpu.dcache.overall_misses 140 # number of overall misses +system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 405000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,90 +119,89 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 50.824604 # Cycle average of tags in use -system.cpu.dcache.total_refs 687 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 51.851940 # Cycle average of tags in use +system.cpu.dcache.total_refs 668 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 83 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4642 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 2009 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 261 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 313 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 860 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 736 # Number of cache lines fetched -system.cpu.fetch.Cycles 1668 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 78 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5463 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.265514 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 736 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 336 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.686632 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 95 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 767 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.fetch.Branches 738 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 654 # Number of cache lines fetched +system.cpu.fetch.Cycles 1440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.179606 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.140180 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 3239 +system.cpu.fetch.rateDist.samples 4109 system.cpu.fetch.rateDist.min_value 0 - 0 2309 7128.74% - 1 47 145.11% - 2 82 253.16% - 3 70 216.12% - 4 128 395.18% - 5 58 179.07% - 6 37 114.23% - 7 46 142.02% - 8 462 1426.37% + 0 3325 8091.99% + 1 32 77.88% + 2 74 180.09% + 3 53 128.99% + 4 99 240.93% + 5 49 119.25% + 6 38 92.48% + 7 35 85.18% + 8 404 983.21% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4129.533679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3209.677419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 543 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 797000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.262228 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 193 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 597000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.252717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5296.019900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4553.763441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1064500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 847000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.919355 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.435484 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 736 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4129.533679 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency -system.cpu.icache.demand_hits 543 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 797000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.262228 # miss rate for demand accesses -system.cpu.icache.demand_misses 193 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 597000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.252717 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency +system.cpu.icache.demand_hits 453 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1064500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses +system.cpu.icache.demand_misses 201 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 847000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 736 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4129.533679 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency +system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 543 # number of overall hits -system.cpu.icache.overall_miss_latency 797000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.262228 # miss rate for overall accesses -system.cpu.icache.overall_misses 193 # number of overall misses -system.cpu.icache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 597000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.252717 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 453 # number of overall hits +system.cpu.icache.overall_miss_latency 1064500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses +system.cpu.icache.overall_misses 201 # number of overall misses +system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 847000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -218,58 +217,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 104.079729 # Cycle average of tags in use -system.cpu.icache.total_refs 543 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 106.237740 # Cycle average of tags in use +system.cpu.icache.total_refs 453 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 535 # Number of branches executed -system.cpu.iew.EXEC:nop 256 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.978388 # Inst execution rate -system.cpu.iew.EXEC:refs 913 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 339 # Number of stores executed +system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 501 # Number of branches executed +system.cpu.iew.EXEC:nop 234 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.727184 # Inst execution rate +system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 333 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1857 # num instructions consuming a value -system.cpu.iew.WB:count 3126 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.787291 # average fanout of values written-back +system.cpu.iew.WB:consumers 1652 # num instructions consuming a value +system.cpu.iew.WB:count 2914 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.799637 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1462 # num instructions producing a value -system.cpu.iew.WB:rate 0.965113 # insts written-back per cycle -system.cpu.iew.WB:sent 3139 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 156 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1321 # num instructions producing a value +system.cpu.iew.WB:rate 0.709175 # insts written-back per cycle +system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 692 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 99 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 385 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4013 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 208 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3169 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 608 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 357 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 3571 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 545 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 87 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2988 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 261 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 202 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 22 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 277 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 91 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 193 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 63 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued +system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.580920 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2413 71.45% # Type of FU issued + IntAlu 2178 70.83% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 617 18.27% # Type of FU issued - MemWrite 346 10.25% # Type of FU issued + MemRead 561 18.24% # Type of FU issued + MemWrite 335 10.89% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 37 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010956 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 2.70% # attempts to use FU when none available + IntAlu 2 5.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +296,42 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 14 37.84% # attempts to use FU when none available - MemWrite 22 59.46% # attempts to use FU when none available + MemRead 12 34.29% # attempts to use FU when none available + MemWrite 21 60.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 3239 +system.cpu.iq.ISSUE:issued_per_cycle.samples 4109 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2006 6193.27% - 1 362 1117.63% - 2 258 796.54% - 3 236 728.62% - 4 193 595.86% - 5 111 342.70% - 6 53 163.63% - 7 14 43.22% - 8 6 18.52% + 0 2849 6933.56% + 1 475 1156.00% + 2 270 657.09% + 3 217 528.11% + 4 159 386.96% + 5 86 209.30% + 6 34 82.75% + 7 13 31.64% + 8 6 14.60% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.042606 # Inst issue rate -system.cpu.iq.iqInstsAdded 3751 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3377 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 564 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 271 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3298.892989 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1993.811808 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 894000 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.748357 # Inst issue rate +system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 790 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4522.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1221000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 271 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 540323 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 270 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +340,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3298.892989 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 894000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1221000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 540323 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 645000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3298.892989 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 894000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1221000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 271 # number of overall misses +system.cpu.l2cache.overall_misses 270 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 540323 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 645000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,27 +378,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 271 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 155.098898 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 158.236294 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 3239 # number of cpu cycles simulated +system.cpu.numCycles 4109 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 2100 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5014 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4443 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3193 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 795 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 261 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1425 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 76 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 696 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 89 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 9 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 55 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 7 # count of temporary serializing insts renamed +system.cpu.timesIdled 8 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index e582c15a8..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 835f03aa2..587034bb2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:10 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:41 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1619000 because target called exit() +Exiting @ tick 2053000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 3e6a662e6..20dfddd0a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index a2be80e9b..acc734991 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 16257c237..e82d837af 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 254768 # Simulator instruction rate (inst/s) -host_mem_usage 147764 # Number of bytes of host memory used +host_inst_rate 484860 # Simulator instruction rate (inst/s) +host_mem_usage 147796 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 121316260 # Simulator tick rate (ticks/s) +host_tick_rate 225459318 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index ddbbe3d32..3b5348194 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:10 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 52183bdb1..1c1daa355 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 05d289a63..45a8521ac 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 8671d784f..756244d02 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 125225 # Simulator instruction rate (inst/s) +host_inst_rate 228404 # Simulator instruction rate (inst/s) host_mem_usage 153176 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 116347710 # Simulator tick rate (ticks/s) +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 552831639 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2444000 # Number of ticks simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 6472000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3890.909091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2890.909091 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 770000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 159000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 715000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3722.222222 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 100500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 378000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 73500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 351000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3835.365854 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 314500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1148000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 232500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1066000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3835.365854 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.overall_miss_latency 314500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1148000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 232500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1066000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 51.430454 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 50.002941 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3733.128834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2733.128834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 608500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2282000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 445500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2119000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3733.128834 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 608500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2282000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 445500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2119000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3733.128834 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2416 # number of overall hits -system.cpu.icache.overall_miss_latency 608500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2282000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 445500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2119000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 89.421061 # Cycle average of tags in use +system.cpu.icache.tagsinuse 86.067224 # Cycle average of tags in use system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2767.346939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1766.346939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 678000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 3185000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 432755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 2695000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2767.346939 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3185000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 432755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2767.346939 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3185000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 432755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 140.951761 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.108021 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2444000 # number of cpu cycles simulated +system.cpu.numCycles 6472000 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index d2bc8bfb7..f5e3a6008 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:11 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2444000 because target called exit() +Exiting @ tick 6472000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 80ef56747..ea3ba751b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 9f8b84468..06a3d271d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index daf99515d..6a0c251b5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 7127 # Simulator instruction rate (inst/s) -host_mem_usage 148488 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host -host_tick_rate 3561193 # Simulator tick rate (ticks/s) +host_inst_rate 535701 # Simulator instruction rate (inst/s) +host_mem_usage 148368 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 257653061 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index b975f8f18..7fb23e5a5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:47:32 -M5 started Sun Apr 22 20:47:35 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 29fcae5de..a5d4e6583 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index d5d160f1e..3f8a51cf4 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index 71b0896dd..41bb7c8b7 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 224031 # Simulator instruction rate (inst/s) -host_mem_usage 153864 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 205051803 # Simulator tick rate (ticks/s) +host_inst_rate 273338 # Simulator instruction rate (inst/s) +host_mem_usage 153844 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 633390216 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5264500 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13362000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3762.195122 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2762.195122 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 308500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1148000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1066000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3690 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2690 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 184500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 700000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 134500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 650000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3734.848485 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 493000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1848000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 361000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1716000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3734.848485 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1922 # number of overall hits -system.cpu.dcache.overall_miss_latency 493000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1848000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 361000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1716000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 86.050916 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 85.283494 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3740.924092 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2740.924092 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13986.798680 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12986.798680 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1133500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 4238000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 830500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3935000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3740.924092 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1133500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 4238000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 830500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3935000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3740.924092 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 1133500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 4238000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 830500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3935000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 137.160443 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.309471 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2743.648961 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1742.648961 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1188000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 5629000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 754567 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4763000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2743.648961 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1188000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5629000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 754567 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2743.648961 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1188000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5629000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 754567 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 224.535228 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.872415 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5264500 # number of cpu cycles simulated +system.cpu.numCycles 13362000 # number of cpu cycles simulated system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 1cc143ec3..6b688641a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:47:32 -M5 started Sun Apr 22 20:47:36 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5264500 because target called exit() +Exiting @ tick 13362000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 5d4dafee7..0e142e6ce 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index 1a521c678..1666790d0 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index bbc3d0e4f..8e0baaf8b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 16183 # Simulator instruction rate (inst/s) -host_mem_usage 149132 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 8071210 # Simulator tick rate (ticks/s) +host_inst_rate 439375 # Simulator instruction rate (inst/s) +host_mem_usage 149124 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 211870315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 84e837005..9e1770f92 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:04 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2431000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 4371849c9..fdb2bc3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out index b02683337..89910d3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index c6b55a6f2..839307810 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 189060 # Simulator instruction rate (inst/s) -host_mem_usage 154496 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 164285984 # Simulator tick rate (ticks/s) +host_inst_rate 239687 # Simulator instruction rate (inst/s) +host_mem_usage 154512 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 542234464 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 4347500 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11221000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3740.740741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2740.740741 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13796.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12796.296296 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 202000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 745000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 148000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 691000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 304500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1176000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 220500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1092000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3670.289855 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 506500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1921000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 368500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1783000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3670.289855 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1131 # number of overall hits -system.cpu.dcache.overall_miss_latency 506500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1921000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 368500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1783000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.314216 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.705022 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3796.875000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2796.875000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13914.062500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12914.062500 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 972000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3562000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 716000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3306000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3796.875000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 972000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3562000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 716000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3306000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3796.875000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4608 # number of overall hits -system.cpu.icache.overall_miss_latency 972000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3562000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 716000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3306000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.238100 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.172725 # Cycle average of tags in use system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2760.869565 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1759.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5083000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 688109 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4301000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2760.869565 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5083000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 688109 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4301000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2760.869565 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5083000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 688109 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4301000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 197.030867 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.304892 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4347500 # number of cpu cycles simulated +system.cpu.numCycles 11221000 # number of cpu cycles simulated system.cpu.num_insts 4863 # Number of instructions executed system.cpu.num_refs 1269 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 6a58f8e2a..65bf4abca 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:05 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4347500 because target called exit() +Exiting @ tick 11221000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5e1ced152..5380fc831 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -379,6 +377,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index f04ad4ffd..c8129d10d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload0] type=LiveProcess @@ -265,7 +266,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -296,14 +297,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -334,14 +334,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -372,7 +371,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -380,4 +378,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index b44194dff..484bdcca9 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 687 # Number of BTB hits -global.BPredUnit.BTBLookups 3480 # Number of BTB lookups -global.BPredUnit.RASInCorrect 113 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1086 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2328 # Number of conditional branches predicted -global.BPredUnit.lookups 4062 # Number of BP lookups -global.BPredUnit.usedRAS 562 # Number of times the RAS was used to get a target. -host_inst_rate 49679 # Simulator instruction rate (inst/s) -host_mem_usage 154724 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -host_tick_rate 20293608 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +global.BPredUnit.BTBHits 674 # Number of BTB hits +global.BPredUnit.BTBLookups 3410 # Number of BTB lookups +global.BPredUnit.RASInCorrect 118 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1115 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2318 # Number of conditional branches predicted +global.BPredUnit.lookups 3964 # Number of BP lookups +global.BPredUnit.usedRAS 532 # Number of times the RAS was used to get a target. +host_inst_rate 56668 # Simulator instruction rate (inst/s) +host_mem_usage 154692 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 27618195 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1911 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1079 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1058 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1898 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1088 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1090 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4600500 # Number of ticks simulated +sim_ticks 5490000 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 179 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 165 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9158 +system.cpu.commit.COM:committed_per_cycle.samples 10929 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 4902 5352.70% - 1 1725 1883.60% - 2 937 1023.15% - 3 472 515.40% - 4 355 387.64% - 5 234 255.51% - 6 234 255.51% - 7 120 131.03% - 8 179 195.46% + 0 6410 5865.13% + 1 2019 1847.38% + 2 999 914.08% + 3 454 415.41% + 4 300 274.50% + 5 246 225.09% + 6 200 183.00% + 7 136 124.44% + 8 165 150.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -61,141 +61,133 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 843 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 874 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 7371 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7769 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.636671 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.636380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.818263 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2909 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2909 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6520.912548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 6520.912548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6121.212121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6121.212121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2646 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2646 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1715000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 1715000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.090409 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.090409 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 263 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 263 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 1212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.068065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses +system.cpu.cpi_0 1.952516 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.952169 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976171 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 7072.992701 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6972.361809 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.092287 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067026 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4509.846827 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 4509.846827 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4681.506849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 4681.506849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1167 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1167 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2061000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 2061000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.281404 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.281404 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 457 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 457 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 683500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 683500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency_0 5352.409639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 5859.589041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.306650 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 855500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 855500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.084302 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.075362 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4533 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4533 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4593 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4593 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5244.444444 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 5244.444444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3821 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3821 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3776000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 3776000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 4603500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 4603500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.158835 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.158835 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.168082 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 720 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 720 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 772 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 772 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 427 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1895500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 1895500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2243000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 2243000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.075888 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.075888 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075114 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 345 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4533 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4533 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4593 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4593 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5244.444444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 5244.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3813 # number of overall hits -system.cpu.dcache.overall_hits_0 3813 # number of overall hits +system.cpu.dcache.overall_hits 3821 # number of overall hits +system.cpu.dcache.overall_hits_0 3821 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 3776000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 3776000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 4603500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 4603500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.158835 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.158835 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.168082 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 720 # number of overall misses -system.cpu.dcache.overall_misses_0 720 # number of overall misses +system.cpu.dcache.overall_misses 772 # number of overall misses +system.cpu.dcache.overall_misses_0 772 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 427 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1895500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 1895500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2243000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 2243000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.075888 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.075888 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075114 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +207,149 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 345 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 218.590181 # Cycle average of tags in use -system.cpu.dcache.total_refs 3813 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.724795 # Cycle average of tags in use +system.cpu.dcache.total_refs 3821 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1876 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 260 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22033 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 11054 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3598 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1407 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 337 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 284 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4062 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2946 # Number of cache lines fetched -system.cpu.fetch.Cycles 6973 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 24430 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1145 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.441378 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2946 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1249 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.654569 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1857 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 251 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 21806 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 14535 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3658 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1498 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 351 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 145 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 3964 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2983 # Number of cache lines fetched +system.cpu.fetch.Cycles 6940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24033 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1178 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.361053 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2983 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1206 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.188997 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 9203 +system.cpu.fetch.rateDist.samples 10979 system.cpu.fetch.rateDist.min_value 0 - 0 5177 5625.34% - 1 291 316.20% - 2 234 254.26% - 3 263 285.78% - 4 314 341.19% - 5 294 319.46% - 6 311 337.93% - 7 262 284.69% - 8 2057 2235.14% + 0 7023 6396.76% + 1 285 259.59% + 2 224 204.03% + 3 248 225.89% + 4 335 305.13% + 5 281 255.94% + 6 301 274.16% + 7 251 228.62% + 8 2031 1849.90% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 2946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4950.682853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 4950.682853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4079.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 4079.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2287 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2287 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 3262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.223693 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.223693 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 659 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 659 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 39 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2529500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 2529500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.210455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.210455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 5910.313901 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5152.173913 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.224271 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 669 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 669 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208180 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 621 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.688710 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.726248 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2946 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 2946 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2983 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2983 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4950.682853 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 4950.682853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2287 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2287 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2314 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2314 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3262500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 3262500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3954000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 3954000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.223693 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.223693 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.224271 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 659 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 659 # number of demand (read+write) misses +system.cpu.icache.demand_misses 669 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 669 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 39 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 48 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2529500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 2529500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3199500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 3199500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.210455 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.210455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.208180 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 621 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2946 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 2946 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2983 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2983 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4950.682853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 4950.682853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2287 # number of overall hits -system.cpu.icache.overall_hits_0 2287 # number of overall hits +system.cpu.icache.overall_hits 2314 # number of overall hits +system.cpu.icache.overall_hits_0 2314 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 3262500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 3262500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3954000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 3954000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.223693 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.223693 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.224271 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 659 # number of overall misses -system.cpu.icache.overall_misses_0 659 # number of overall misses +system.cpu.icache.overall_misses 669 # number of overall misses +system.cpu.icache.overall_misses_0 669 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 39 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 39 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 48 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2529500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 2529500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3199500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 3199500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.210455 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.210455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.208180 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 621 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -381,104 +369,104 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9 # number of replacements system.cpu.icache.replacements_0 9 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 621 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 315.428279 # Cycle average of tags in use -system.cpu.icache.total_refs 2287 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 322.894952 # Cycle average of tags in use +system.cpu.icache.total_refs 2314 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles -1 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2339 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1175 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1164 # Number of branches executed -system.cpu.iew.EXEC:nop 72 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed +system.cpu.idleCycles 1998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2367 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1185 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1182 # Number of branches executed +system.cpu.iew.EXEC:nop 73 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 37 # number of nop insts executed system.cpu.iew.EXEC:nop_1 36 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.666196 # Inst execution rate -system.cpu.iew.EXEC:refs 4928 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2490 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2438 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1865 # Number of stores executed +system.cpu.iew.EXEC:rate 1.416158 # Inst execution rate +system.cpu.iew.EXEC:refs 4978 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2514 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2464 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1867 # Number of stores executed system.cpu.iew.EXEC:stores_0 938 # Number of stores executed -system.cpu.iew.EXEC:stores_1 927 # Number of stores executed +system.cpu.iew.EXEC:stores_1 929 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10157 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5143 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5014 # num instructions consuming a value -system.cpu.iew.WB:count 14949 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7544 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7405 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.769912 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.768229 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.771639 # average fanout of values written-back +system.cpu.iew.WB:consumers 10219 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5113 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5106 # num instructions consuming a value +system.cpu.iew.WB:count 14974 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7532 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7442 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.526960 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.762957 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.764003 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7820 # num instructions producing a value -system.cpu.iew.WB:producers_0 3951 # num instructions producing a value -system.cpu.iew.WB:producers_1 3869 # num instructions producing a value -system.cpu.iew.WB:rate 1.624362 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.819733 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.804629 # insts written-back per cycle -system.cpu.iew.WB:sent 15070 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7606 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7464 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3744 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2137 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 18669 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3063 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1552 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1511 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15334 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7802 # num instructions producing a value +system.cpu.iew.WB:producers_0 3901 # num instructions producing a value +system.cpu.iew.WB:producers_1 3901 # num instructions producing a value +system.cpu.iew.WB:rate 1.363876 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.686037 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.677840 # insts written-back per cycle +system.cpu.iew.WB:sent 15105 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7590 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7515 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 7 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3823 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 501 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2178 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19078 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3111 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1576 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1535 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 864 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15548 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1407 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1498 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 42 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 56 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 932 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 267 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 946 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 276 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 49 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 38 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 57 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 54 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 246 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 113 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 753 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 174 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.610996 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.611105 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.222101 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8271 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 919 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 278 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 117 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 761 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 180 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.512160 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.512251 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024410 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8232 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5600 67.71% # Type of FU issued + IntAlu 5551 67.43% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +475,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1701 20.57% # Type of FU issued - MemWrite 965 11.67% # Type of FU issued + MemRead 1704 20.70% # Type of FU issued + MemWrite 972 11.81% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8071 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8180 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5485 67.96% # Type of FU issued + IntAlu 5536 67.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +492,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1640 20.32% # Type of FU issued - MemWrite 941 11.66% # Type of FU issued + MemRead 1681 20.55% # Type of FU issued + MemWrite 958 11.71% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16342 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16412 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 11085 67.83% # Type of FU issued + IntAlu 11087 67.55% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +509,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3341 20.44% # Type of FU issued - MemWrite 1906 11.66% # Type of FU issued + MemRead 3385 20.63% # Type of FU issued + MemWrite 1930 11.76% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 89 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011259 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.005813 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005446 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010968 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005606 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005362 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 11 5.98% # attempts to use FU when none available + IntAlu 16 8.89% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,108 +531,104 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 108 58.70% # attempts to use FU when none available - MemWrite 65 35.33% # attempts to use FU when none available + MemRead 97 53.89% # attempts to use FU when none available + MemWrite 67 37.22% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 9203 +system.cpu.iq.ISSUE:issued_per_cycle.samples 10979 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3452 3750.95% - 1 1399 1520.16% - 2 1479 1607.08% - 3 1070 1162.66% - 4 845 918.18% - 5 528 573.73% - 6 290 315.11% - 7 105 114.09% - 8 35 38.03% + 0 4788 4361.05% + 1 1816 1654.07% + 2 1657 1509.24% + 3 1039 946.35% + 4 774 704.98% + 5 501 456.33% + 6 289 263.23% + 7 90 81.97% + 8 25 22.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.775725 # Inst issue rate -system.cpu.iq.iqInstsAdded 18557 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16342 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 6288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4143.899896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 4143.899896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2323.820647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2323.820647 # average ReadReq mshr miss latency +system.cpu.iq.ISSUE:rate 1.494854 # Inst issue rate +system.cpu.iq.iqInstsAdded 18963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16412 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 5220.374220 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2725.051975 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits_0 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 3974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.998958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 0.998958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2228544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2228544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.998958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.998962 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998962 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 962 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.001043 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.001040 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 960 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 963 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 963 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4143.899896 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 4143.899896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 3974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5022000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 5022000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.998958 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.998958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.998962 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 959 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 962 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2228544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 2228544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2621500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2621500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.998958 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.998958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.998962 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 962 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 960 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 963 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 963 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4143.899896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 4143.899896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency @@ -652,26 +636,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_hits_0 1 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3974000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 3974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5022000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 5022000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.998958 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.998958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.998962 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 959 # number of overall misses -system.cpu.l2cache.overall_misses_0 959 # number of overall misses +system.cpu.l2cache.overall_misses 962 # number of overall misses +system.cpu.l2cache.overall_misses_0 962 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2228544 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 2228544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2621500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2621500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.998958 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.998958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.998962 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -691,33 +675,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 959 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 962 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 534.228654 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 545.133409 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 9203 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 514 # Number of cycles rename is blocking +system.cpu.numCycles 10979 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 614 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 11467 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26335 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 20742 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15622 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3447 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1407 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 876 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7520 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 14840 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 684 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26359 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 20748 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15612 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3480 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1498 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 744 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7510 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 517 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2622 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 2147 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index ea08dc448..ef617d5ef 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:11 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4600500 because target called exit() +Exiting @ tick 5490000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 1f1e7a355..61102139c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out index ac1dcb9ba..70564f749 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 8359db0f2..7859d5c2b 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 3154 # Number of BTB hits -global.BPredUnit.BTBLookups 9574 # Number of BTB lookups +global.BPredUnit.BTBHits 2726 # Number of BTB hits +global.BPredUnit.BTBLookups 7230 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2047 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10459 # Number of conditional branches predicted -global.BPredUnit.lookups 10459 # Number of BP lookups +global.BPredUnit.condIncorrect 2062 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 7954 # Number of conditional branches predicted +global.BPredUnit.lookups 7954 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 26468 # Simulator instruction rate (inst/s) -host_mem_usage 154944 # Number of bytes of host memory used -host_seconds 0.41 # Real time elapsed on the host -host_tick_rate 32157366 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. +host_inst_rate 37089 # Simulator instruction rate (inst/s) +host_mem_usage 154932 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 53780846 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3573 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 3440 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 3198 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2970 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13345500 # Number of ticks simulated +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 15931500 # Number of ticks simulated system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 164 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 146 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 23147 +system.cpu.commit.COM:committed_per_cycle.samples 28801 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 17950 7754.78% - 1 2912 1258.05% - 2 993 429.00% - 3 424 183.18% - 4 287 123.99% - 5 235 101.53% - 6 103 44.50% - 7 79 34.13% - 8 164 70.85% + 0 23411 8128.54% + 1 2862 993.72% + 2 1174 407.62% + 3 608 211.10% + 4 359 124.65% + 5 123 42.71% + 6 103 35.76% + 7 15 5.21% + 8 146 50.69% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2760 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2047 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 18321 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14297 # The number of squashed insts skipped by commit system.cpu.committedInsts 10976 # Number of Instructions Simulated system.cpu.committedInsts_total 10976 # Number of Instructions Simulated -system.cpu.cpi 2.431851 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.431851 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2813 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4311.764706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3546.153846 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2728 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 366500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.030217 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 85 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 230500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses +system.cpu.cpi 2.903061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.903061 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2743 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5392.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4696.969697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2659 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 453000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.030623 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 84 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 310000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.024061 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4645.408163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3470.930233 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1096 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 910500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.151703 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 196 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 110 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 298500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 5505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4802.325581 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1092 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1101000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.154799 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 200 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 114 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 413000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 25.364238 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 24.717105 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4105 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4544.483986 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3824 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1277000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.068453 # miss rate for demand accesses -system.cpu.dcache.demand_misses 281 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.036784 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 4035 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5471.830986 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3751 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1554000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.070384 # miss rate for demand accesses +system.cpu.dcache.demand_misses 284 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.037670 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4105 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4544.483986 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 4035 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5471.830986 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3824 # number of overall hits -system.cpu.dcache.overall_miss_latency 1277000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.068453 # miss rate for overall accesses -system.cpu.dcache.overall_misses 281 # number of overall misses -system.cpu.dcache.overall_mshr_hits 130 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 529000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.036784 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses +system.cpu.dcache.overall_hits 3751 # number of overall hits +system.cpu.dcache.overall_miss_latency 1554000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.070384 # miss rate for overall accesses +system.cpu.dcache.overall_misses 284 # number of overall misses +system.cpu.dcache.overall_mshr_hits 132 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 723000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.037670 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.362185 # Cycle average of tags in use -system.cpu.dcache.total_refs 3830 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 113.439038 # Cycle average of tags in use +system.cpu.dcache.total_refs 3757 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4942 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 48420 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8618 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 9347 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 3545 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 240 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 10459 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 5440 # Number of cache lines fetched -system.cpu.fetch.Cycles 16262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 55152 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2110 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.391840 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 5440 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 3154 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.066237 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 4602 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 38937 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 16098 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 7883 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 3063 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 218 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 7954 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4933 # Number of cache lines fetched +system.cpu.fetch.Cycles 14166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 44421 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2121 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.249623 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2726 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.394081 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 26692 +system.cpu.fetch.rateDist.samples 31864 system.cpu.fetch.rateDist.min_value 0 - 0 15871 5945.98% - 1 2250 842.95% - 2 637 238.65% - 3 971 363.78% - 4 550 206.05% - 5 848 317.70% - 6 962 360.41% - 7 321 120.26% - 8 4282 1604.23% + 0 22632 7102.69% + 1 2187 686.35% + 2 562 176.37% + 3 869 272.72% + 4 521 163.51% + 5 770 241.65% + 6 886 278.06% + 7 243 76.26% + 8 3194 1002.39% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 5440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3939.473684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2944.591029 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5060 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1497000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.069853 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 380 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1116000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.069669 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 4933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5310.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4396.174863 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 4558 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1991500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.076019 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 375 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.074194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 13.350923 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.453552 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5440 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3939.473684 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency -system.cpu.icache.demand_hits 5060 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1497000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.069853 # miss rate for demand accesses -system.cpu.icache.demand_misses 380 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1116000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.069669 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 379 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 4933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5310.666667 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency +system.cpu.icache.demand_hits 4558 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1991500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.076019 # miss rate for demand accesses +system.cpu.icache.demand_misses 375 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.074194 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5440 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3939.473684 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency +system.cpu.icache.overall_accesses 4933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5310.666667 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5060 # number of overall hits -system.cpu.icache.overall_miss_latency 1497000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.069853 # miss rate for overall accesses -system.cpu.icache.overall_misses 380 # number of overall misses -system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1116000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.069669 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 379 # number of overall MSHR misses +system.cpu.icache.overall_hits 4558 # number of overall hits +system.cpu.icache.overall_miss_latency 1991500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.076019 # miss rate for overall accesses +system.cpu.icache.overall_misses 375 # number of overall misses +system.cpu.icache.overall_mshr_hits 9 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.074194 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 366 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,60 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 379 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 242.916499 # Cycle average of tags in use -system.cpu.icache.total_refs 5060 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 233.760012 # Cycle average of tags in use +system.cpu.icache.total_refs 4558 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 3713 # Number of branches executed +system.cpu.idleCycles 499 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3548 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.830061 # Inst execution rate -system.cpu.iew.EXEC:refs 5553 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2589 # Number of stores executed +system.cpu.iew.EXEC:rate 0.670318 # Inst execution rate +system.cpu.iew.EXEC:refs 5385 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2502 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10966 # num instructions consuming a value -system.cpu.iew.WB:count 21367 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.799836 # average fanout of values written-back +system.cpu.iew.WB:consumers 10159 # num instructions consuming a value +system.cpu.iew.WB:count 20199 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790629 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8771 # num instructions producing a value -system.cpu.iew.WB:rate 0.800502 # insts written-back per cycle -system.cpu.iew.WB:sent 21712 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2654 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 8032 # num instructions producing a value +system.cpu.iew.WB:rate 0.633913 # insts written-back per cycle +system.cpu.iew.WB:sent 20448 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2568 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3573 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 630 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1509 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 3440 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 29298 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2964 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3437 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 22156 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 3198 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 610 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2750 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2970 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 25274 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2883 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 21359 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 3545 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 3063 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 75 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2111 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2142 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 75 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1624 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.411209 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.411209 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 25593 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 52 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1736 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1672 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 52 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1610 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.344464 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.344464 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 22822 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 1919 7.50% # Type of FU issued - IntAlu 17231 67.33% # Type of FU issued + (null) 1826 8.00% # Type of FU issued + IntAlu 15247 66.81% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -277,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3429 13.40% # Type of FU issued - MemWrite 3014 11.78% # Type of FU issued + MemRead 3042 13.33% # Type of FU issued + MemWrite 2707 11.86% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 238 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009299 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 99 41.60% # attempts to use FU when none available + IntAlu 50 26.32% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -295,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 22 9.24% # attempts to use FU when none available - MemWrite 117 49.16% # attempts to use FU when none available + MemRead 25 13.16% # attempts to use FU when none available + MemWrite 115 60.53% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 26692 +system.cpu.iq.ISSUE:issued_per_cycle.samples 31864 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 17644 6610.22% - 1 3262 1222.09% - 2 1371 513.64% - 3 1071 401.24% - 4 1568 587.44% - 5 925 346.55% - 6 579 216.92% - 7 171 64.06% - 8 101 37.84% + 0 22879 7180.20% + 1 3824 1200.10% + 2 1304 409.24% + 3 1251 392.61% + 4 1252 392.92% + 5 751 235.69% + 6 414 129.93% + 7 122 38.29% + 8 67 21.03% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.958827 # Inst issue rate -system.cpu.iq.iqInstsAdded 28668 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 25593 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 630 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 15737 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 303 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 526 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3018.060837 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1812.857414 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1587500 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.716231 # Inst issue rate +system.cpu.iq.iqInstsAdded 24664 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 22822 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 610 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 11119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5685 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4458.171206 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2373.540856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2291500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 526 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 953563 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 514 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1220000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 526 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -340,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 526 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3018.060837 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 514 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4458.171206 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1587500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2291500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 526 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 514 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 953563 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1220000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 526 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 514 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 526 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3018.060837 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 514 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4458.171206 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1587500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2291500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 526 # number of overall misses +system.cpu.l2cache.overall_misses 514 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 953563 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1220000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 526 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 514 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -378,28 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 526 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 514 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 353.661697 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 345.564898 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 26692 # number of cpu cycles simulated +system.cpu.numCycles 31864 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 8631 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 59097 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 39751 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 31999 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 9086 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 3545 # Number of cycles rename is squashing -system.cpu.rename.RENAME:SquashedInsts 8167 # Number of squashed instructions processed by rename -system.cpu.rename.RENAME:UnblockCycles 716 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 22131 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4224 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 665 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4954 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 658 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IdleCycles 16082 # Number of cycles rename is idle +system.cpu.rename.RENAME:RenameLookups 44650 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 29655 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 24195 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 7618 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 3063 # Number of cycles rename is squashing +system.cpu.rename.RENAME:SquashedInsts 8815 # Number of squashed instructions processed by rename +system.cpu.rename.RENAME:UnblockCycles 684 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 14327 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 3915 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 631 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4702 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 623 # count of temporary serializing insts renamed +system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index 0bb67880e..0b6e54449 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:05 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:06 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 13345500 because target called exit() +Exiting @ tick 15931500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 7e9c12db2..5493b952f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out index 29915233b..c1a77ba0d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 22ea72ebd..468b3f0a1 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 430012 # Simulator instruction rate (inst/s) -host_mem_usage 149064 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 207711772 # Simulator tick rate (ticks/s) +host_inst_rate 563720 # Simulator instruction rate (inst/s) +host_mem_usage 149048 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 276035132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 66bfb4931..01c59e833 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:06 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 5500000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 394f564a5..2e2789f26 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out index 9d999c4c3..df1a9c852 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index aef9433e6..33502bf5c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 285170 # Simulator instruction rate (inst/s) -host_mem_usage 154424 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 211576923 # Simulator tick rate (ticks/s) +host_inst_rate 346412 # Simulator instruction rate (inst/s) +host_mem_usage 154396 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 598818775 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 8251500 # Number of ticks simulated +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 19264000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3712.962963 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 200500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 756000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 146500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 702000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3676.136364 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2676.136364 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1204 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 323500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1232000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.068111 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 88 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1144000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.068111 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 88 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3690.140845 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 2612 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 524000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1988000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.051561 # miss rate for demand accesses system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1846000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.051561 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3690.140845 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 2612 # number of overall hits -system.cpu.dcache.overall_miss_latency 524000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1988000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.051561 # miss rate for overall accesses system.cpu.dcache.overall_misses 142 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 382000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1846000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.051561 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 106.692969 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.809387 # Cycle average of tags in use system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3743.816254 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2743.816254 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13922.261484 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12922.261484 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3940000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 776500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3657000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3743.816254 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13922.261484 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3940000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses system.cpu.icache.demand_misses 283 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 776500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3657000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3743.816254 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13922.261484 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 10719 # number of overall hits -system.cpu.icache.overall_miss_latency 1059500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3940000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses system.cpu.icache.overall_misses 283 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 776500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3657000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,18 +140,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 170.449932 # Cycle average of tags in use +system.cpu.icache.tagsinuse 163.879834 # Cycle average of tags in use system.cpu.icache.total_refs 10719 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 423 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2730.496454 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1729.496454 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5499000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 423 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 731577 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4653000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -163,29 +163,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 423 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2730.496454 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1155000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5499000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 731577 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 423 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2730.496454 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1155000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5499000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 423 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 731577 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -202,12 +202,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 423 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 276.385948 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 266.922506 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 8251500 # number of cpu cycles simulated +system.cpu.numCycles 19264000 # number of cpu cycles simulated system.cpu.num_insts 11001 # Number of instructions executed system.cpu.num_refs 2760 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index dd4d8d282..c2d31ed8f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:07 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 8251500 because target called exit() +Exiting @ tick 19264000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 8145ecdc4..6e38281a1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -5,8 +5,8 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -21,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -51,21 +56,109 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -85,13 +178,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -99,7 +280,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -118,7 +299,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -140,27 +321,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -200,6 +421,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -209,7 +457,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -220,7 +468,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -235,7 +483,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -245,19 +493,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -302,7 +552,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -318,7 +568,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -334,7 +584,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -350,7 +600,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -366,7 +616,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -382,7 +632,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -398,7 +648,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -414,7 +664,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -430,7 +680,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -446,7 +696,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -462,7 +712,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -478,7 +728,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -494,7 +744,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -510,7 +760,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -526,7 +776,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -542,7 +792,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -558,7 +808,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -574,7 +824,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -590,7 +840,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -607,7 +857,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -615,13 +865,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -665,9 +917,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -678,7 +930,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -696,7 +948,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index e0c23706f..324ede6b4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -11,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -27,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -43,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -55,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -78,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -96,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -121,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -129,6 +172,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -152,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -160,6 +287,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img @@ -173,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -188,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -203,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -218,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -233,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -248,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -256,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -288,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -308,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -323,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -331,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -346,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -361,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -376,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -391,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -406,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -421,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -436,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -451,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -469,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -510,12 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -524,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -543,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -558,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -566,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -581,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -632,18 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 2a3b3163d..7765c2852 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,89 +1,256 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 674184 # Simulator instruction rate (inst/s) -host_mem_usage 251408 # Number of bytes of host memory used -host_seconds 93.63 # Real time elapsed on the host -host_tick_rate 39952215 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 63122441 # Number of instructions simulated -sim_seconds 1.870326 # Number of seconds simulated -sim_ticks 3740651174 # Number of ticks simulated +host_inst_rate 607412 # Simulator instruction rate (inst/s) +host_mem_usage 245896 # Number of bytes of host memory used +host_seconds 103.93 # Real time elapsed on the host +host_tick_rate 17996726251 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63125943 # Number of instructions simulated +sim_seconds 1.870335 # Number of seconds simulated +sim_ticks 1870335097000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7464208 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.185481 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1699733 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5646723 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 286673 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.625609 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13110931 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.131573 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1986406 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13110931 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.131573 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1986406 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1699733 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 122 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 282337 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks +system.cpu0.dcache.replacements 1978969 # number of replacements +system.cpu0.dcache.sampled_refs 1979481 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115267 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 0 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15071957 # DTB hits +system.cpu0.dtb.hits 15082969 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9142249 # DTB read hits +system.cpu0.dtb.read_hits 9148390 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5929708 # DTB write hits +system.cpu0.dtb.write_hits 5934579 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.idle_fraction 0.984720 # Percentage of idle cycles -system.cpu0.itb.accesses 3857497 # ITB accesses +system.cpu0.icache.ReadReq_accesses 57190172 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56305300 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 884872 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 63.637052 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57190172 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_hits 56305300 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses +system.cpu0.icache.demand_misses 884872 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57190172 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56305300 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses +system.cpu0.icache.overall_misses 884872 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 25821 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 884276 # number of replacements +system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use +system.cpu0.icache.total_refs 56305300 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles +system.cpu0.itb.accesses 3858835 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3854012 # ITB hits +system.cpu0.itb.hits 3855350 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183119 # number of callpals executed +system.cpu0.kern.callpal 183272 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 111 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3759 2.05% 2.12% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 167881 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal_rdps 6134 3.35% 97.17% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168017 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 196948 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174714 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70932 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 197101 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174850 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101623 58.17% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141281 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69565 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101695 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69557 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3740650759 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3706243742 99.08% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 40220 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 164088 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1899 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 34200810 0.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808642 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.980728 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1870334889500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125118000 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106668000 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684461 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.684606 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good_kernel 1155 system.cpu0.kern.mode_good_user 1156 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7088 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.280325 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.162951 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3738736759 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 1913998 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869377889500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3760 # number of times the context was actually changed +system.cpu0.kern.swap_context 3762 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed @@ -115,82 +282,249 @@ system.cpu0.kern.syscall_98 2 0.88% 97.35% # nu system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015280 # Percentage of non-idle cycles -system.cpu0.numCycles 57155598 # number of cpu cycles simulated -system.cpu0.num_insts 57151986 # Number of instructions executed -system.cpu0.num_refs 15311384 # Number of memory references +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.numCycles 57193784 # number of cpu cycles simulated +system.cpu0.num_insts 57190172 # Number of instructions executed +system.cpu0.num_refs 15322419 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1847506 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 69527 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 61769 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks +system.cpu1.dcache.replacements 62341 # number of replacements +system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851266669500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 0 # number of writebacks system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations -system.cpu1.dtb.hits 1925043 # DTB hits +system.cpu1.dtb.hits 1914885 # DTB hits system.cpu1.dtb.misses 3692 # DTB misses system.cpu1.dtb.read_accesses 220342 # DTB read accesses system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_hits 1169160 # DTB read hits +system.cpu1.dtb.read_hits 1163439 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.write_accesses 103280 # DTB write accesses system.cpu1.dtb.write_acv 58 # DTB write access violations -system.cpu1.dtb.write_hits 755883 # DTB write hits +system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles -system.cpu1.itb.accesses 1471216 # ITB accesses +system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5832135 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103636 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 17328 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 103097 # number of replacements +system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868932665500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.itb.accesses 1469938 # ITB accesses system.cpu1.itb.acv 57 # ITB acv -system.cpu1.itb.hits 1469677 # ITB hits +system.cpu1.itb.hits 1468399 # ITB hits system.cpu1.itb.misses 1539 # ITB misses -system.cpu1.kern.callpal 32267 # number of callpals executed +system.cpu1.kern.callpal 32131 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 472 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal_swpipl 26358 81.69% 83.25% # number of callpals executed -system.cpu1.kern.callpal_rdps 2589 8.02% 91.28% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 91.28% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 91.29% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 91.30% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 91.31% # number of callpals executed -system.cpu1.kern.callpal_rti 2608 8.08% 99.39% # number of callpals executed +system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed +system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed +system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 30985 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 10388 33.53% 33.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1907 6.15% 39.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 111 0.36% 40.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 18579 59.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 22663 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3740237191 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3718224753 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 164002 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 28353 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21820083 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.731418 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.999037 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1870124001500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859122583000 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.552613 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 613 +system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 612 system.cpu1.kern.mode_good_user 580 -system.cpu1.kern.mode_good_idle 33 -system.cpu1.kern.mode_switch_kernel 1034 # number of protection mode switches +system.cpu1.kern.mode_good_idle 32 +system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches system.cpu1.kern.mode_switch_user 580 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2048 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.334790 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.592843 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.016113 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 2786521 0.07% 0.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1016578 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3735960321 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 473 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 1373909500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002152500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 471 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed @@ -209,10 +543,10 @@ system.cpu1.kern.syscall_71 24 24.00% 89.00% # nu system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles -system.cpu1.numCycles 5972051 # number of cpu cycles simulated -system.cpu1.num_insts 5970455 # Number of instructions executed -system.cpu1.num_refs 1936828 # Number of memory references +system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles +system.cpu1.numCycles 5937367 # number of cpu cycles simulated +system.cpu1.num_insts 5935771 # Number of instructions executed +system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -225,6 +559,68 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306245 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 181107 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.408621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1782852 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.345539 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941303 # number of ReadReq misses +system.l2c.Writeback_accesses 427632 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427632 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.242866 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2724155 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1782852 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.345539 # miss rate for demand accesses +system.l2c.demand_misses 941303 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3151787 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2210484 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.298657 # miss rate for overall accesses +system.l2c.overall_misses 941303 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 1000779 # number of replacements +system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.575355 # Cycle average of tags in use +system.l2c.total_refs 2391252 # Total number of references to valid blocks. +system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 111ccf4f1..563ca3160 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,7 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 195723: Trying to launch CPU number 1! +warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 9ec0f1c3f..6afe2cfa0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:53:05 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3740651174 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1870335097000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 26242f3b3..791200f9a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -5,8 +5,8 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -21,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -51,13 +56,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -65,7 +158,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -84,7 +177,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -106,27 +199,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -166,6 +299,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -175,7 +335,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -186,7 +346,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -201,7 +361,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -211,19 +371,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -268,7 +430,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -284,7 +446,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -300,7 +462,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -316,7 +478,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -332,7 +494,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -348,7 +510,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -364,7 +526,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -380,7 +542,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -396,7 +558,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -412,7 +574,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -428,7 +590,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -444,7 +606,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -460,7 +622,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -476,7 +638,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -492,7 +654,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -508,7 +670,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -524,7 +686,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -540,7 +702,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -556,7 +718,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -573,7 +735,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -581,13 +743,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -631,9 +795,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -644,7 +808,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -662,7 +826,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index 7a0f99013..94cc53f32 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -11,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -27,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -43,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -55,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -78,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -96,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage @@ -111,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -126,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -141,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -156,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -171,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -186,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -194,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -241,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -257,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -277,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -292,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -300,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -315,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -330,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -345,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -360,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -375,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -390,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -405,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -420,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -438,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -479,12 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -493,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -512,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -527,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -535,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -550,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -601,18 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index de848de68..aaa6c0c86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,31 +1,199 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1069072 # Simulator instruction rate (inst/s) -host_mem_usage 251484 # Number of bytes of host memory used -host_seconds 56.13 # Real time elapsed on the host -host_tick_rate 65146530 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60007301 # Number of instructions simulated -sim_seconds 1.828354 # Number of seconds simulated -sim_ticks 3656708271 # Number of ticks simulated +host_inst_rate 577751 # Simulator instruction rate (inst/s) +host_mem_usage 244724 # Number of bytes of host memory used +host_seconds 103.86 # Real time elapsed on the host +host_tick_rate 17603359253 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60007317 # Number of instructions simulated +sim_seconds 1.828355 # Number of seconds simulated +sim_ticks 1828355481500 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7984499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1738834 # number of ReadReq misses +system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.866570 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_hits 14029592 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2043188 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14029592 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2043188 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1738834 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2042663 # number of replacements +system.cpu.dcache.sampled_refs 2043175 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029604 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053817 # DTB hits +system.cpu.dtb.hits 16053818 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703849 # DTB read hits +system.cpu.dtb.read_hits 9703850 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses +system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59087263 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses +system.cpu.icache.overall_misses 920054 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 919427 # number of replacements +system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use +system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979206 # ITB accesses +system.cpu.itb.accesses 4979217 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974200 # ITB hits +system.cpu.itb.hits 4974211 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192138 # number of callpals executed +system.cpu.kern.callpal 192139 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -33,7 +201,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175209 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -43,41 +211,40 @@ system.cpu.kern.callpal_rti 5202 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211276 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182520 # number of times we switched to this ipl +system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105597 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3656707856 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3622172407 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 40220 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 160390 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34334839 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.816371 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks 1828355274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087543000 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695550 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1907 -system.cpu.kern.mode_good_user 1736 +system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1908 +system.cpu.kern.mode_good_user 1737 system.cpu.kern.mode_good_idle 171 system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch_user 1736 # number of protection mode switches +system.cpu.kern.mode_switch_user 1737 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389940 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320612 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 53668047 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 2930128 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3600109679 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056177500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -111,9 +278,9 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 60012491 # number of cpu cycles simulated -system.cpu.num_insts 60007301 # Number of instructions executed -system.cpu.num_refs 16302128 # Number of memory references +system.cpu.numCycles 60012507 # number of cpu cycles simulated +system.cpu.num_insts 60007317 # Number of instructions executed +system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -126,6 +293,68 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658871 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1717827 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941044 # number of ReadReq misses +system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.205900 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2658871 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1717827 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses +system.l2c.demand_misses 941044 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3087756 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2146712 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses +system.l2c.overall_misses 941044 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992432 # number of replacements +system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use +system.l2c.total_refs 2333445 # Total number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 969291745..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,5 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index c3a1cb464..e47b6f226 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:52:08 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3656708271 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1828355481500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 8e1ba179d..7bcdbdb71 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -5,14 +5,14 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/Users/ali/work/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/Users/ali/work/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/Users/ali/work/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -21,10 +21,10 @@ system_type=34 [system.bridge] type=Bridge -delay=0 +delay=50000 fix_partial_write_a=false fix_partial_write_b=true -nack_delay=0 +nack_delay=4000 req_size_a=16 req_size_b=16 resp_size_a=16 @@ -35,8 +35,8 @@ side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -54,21 +54,109 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -86,13 +174,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -100,7 +276,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -113,13 +289,13 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -132,7 +308,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -143,27 +319,65 @@ sys=system type=Bus block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -200,9 +414,36 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -212,7 +453,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -223,7 +464,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -238,7 +479,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -248,21 +489,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 -max_backoff_delay=20000 -min_backoff_delay=8 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -307,7 +548,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -323,7 +564,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -339,7 +580,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -355,7 +596,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -371,7 +612,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -387,7 +628,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -403,7 +644,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -419,7 +660,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -435,7 +676,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -451,7 +692,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -467,7 +708,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -483,7 +724,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -499,7 +740,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -515,7 +756,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -531,7 +772,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -547,7 +788,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -563,7 +804,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -579,7 +820,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -595,7 +836,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -612,7 +853,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -620,15 +861,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 -max_backoff_delay=20000 -min_backoff_delay=8 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -672,9 +913,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -685,7 +926,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -703,7 +944,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index 890030c19..68698cf83 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -11,12 +11,12 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing -kernel=/Users/ali/work/system/binaries/vmlinux -console=/Users/ali/work/system/binaries/console -pal=/Users/ali/work/system/binaries/ts_osfpal +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -27,7 +27,7 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false block_size=64 @@ -44,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -56,21 +56,58 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge req_size_a=16 req_size_b=16 resp_size_a=16 resp_size_b=16 -delay=0 -nack_delay=0 +delay=50000 +nack_delay=4000 write_ack=false fix_partial_write_a=false fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -84,11 +121,11 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -102,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -127,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -135,6 +172,90 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -158,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -166,9 +287,93 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -179,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -194,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -209,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -224,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -239,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -254,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -262,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -294,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -314,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -329,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -337,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -352,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -367,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -382,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -397,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -412,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -427,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -442,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -457,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -475,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -516,14 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -532,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -551,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -566,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -574,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -589,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -640,21 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true block_size=64 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index e808b031d..83bb77f93 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,221 +1,604 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 159511 # Simulator instruction rate (inst/s) -host_seconds 408.44 # Real time elapsed on the host -host_tick_rate 9737848 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 65151264 # Number of instructions simulated -sim_seconds 1.988681 # Number of seconds simulated -sim_ticks 3977362808 # Number of ticks simulated -system.cpu0.dtb.accesses 676531 # DTB accesses -system.cpu0.dtb.acv 306 # DTB access violations -system.cpu0.dtb.hits 12726999 # DTB hits -system.cpu0.dtb.misses 8261 # DTB misses -system.cpu0.dtb.read_accesses 494241 # DTB read accesses -system.cpu0.dtb.read_acv 184 # DTB read access violations -system.cpu0.dtb.read_hits 7906690 # DTB read hits -system.cpu0.dtb.read_misses 7534 # DTB read misses -system.cpu0.dtb.write_accesses 182290 # DTB write accesses -system.cpu0.dtb.write_acv 122 # DTB write access violations -system.cpu0.dtb.write_hits 4820309 # DTB write hits -system.cpu0.dtb.write_misses 727 # DTB write misses -system.cpu0.idle_fraction 0.930953 # Percentage of idle cycles -system.cpu0.itb.accesses 3412195 # ITB accesses -system.cpu0.itb.acv 161 # ITB acv -system.cpu0.itb.hits 3408362 # ITB hits -system.cpu0.itb.misses 3833 # ITB misses -system.cpu0.kern.callpal 142550 # number of callpals executed +host_inst_rate 213082 # Simulator instruction rate (inst/s) +host_mem_usage 203724 # Number of bytes of host memory used +host_seconds 296.83 # Real time elapsed on the host +host_tick_rate 6573231278 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63248814 # Number of instructions simulated +sim_seconds 1.951129 # Number of seconds simulated +sim_ticks 1951129131000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9299202 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 13073.177688 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12073.152824 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7589849 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 22346675500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.183817 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1709353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 20637280000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.183817 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1709353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable 6873 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu0.dcache.ReadResp_mshr_uncacheable_latency 841915000 # number of ReadResp MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_accesses 6016348 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 12644.438594 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 11630.972878 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 5727689 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 3649931000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.047979 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 288659 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 3357385000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.047979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 288659 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable 9698 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu0.dcache.WriteResp_mshr_uncacheable_latency 1186164500 # number of WriteResp MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.687909 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15315550 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13317538 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 25996606500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.130456 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1998012 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 23994665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.130456 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1998012 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15315550 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13317538 # number of overall hits +system.cpu0.dcache.overall_miss_latency 25996606500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.130456 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1998012 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 23994665000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.130456 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1998012 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 16571 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1709421 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 908 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 3762 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 72 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2297 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 235 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 207 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 15 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 7 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1074 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 726 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 284810 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2533 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1354 # write misses to shared blocks +system.cpu0.dcache.replacements 1991354 # number of replacements +system.cpu0.dcache.sampled_refs 1991866 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 503.775443 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13321418 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 57953000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 401606 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses +system.cpu0.dtb.acv 289 # DTB access violations +system.cpu0.dtb.hits 15299767 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses +system.cpu0.dtb.read_acv 174 # DTB read access violations +system.cpu0.dtb.read_hits 9282693 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses +system.cpu0.dtb.write_accesses 195659 # DTB write accesses +system.cpu0.dtb.write_acv 115 # DTB write access violations +system.cpu0.dtb.write_hits 6017074 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses +system.cpu0.icache.ReadReq_accesses 57872551 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 12029.752588 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11029.000057 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 56957639 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 11006165000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.015809 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 914912 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10090564500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.015809 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 914912 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 62.632934 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57872551 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.demand_hits 56957639 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 11006165000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015809 # miss rate for demand accesses +system.cpu0.icache.demand_misses 914912 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10090564500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.015809 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 914912 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57872551 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56957639 # number of overall hits +system.cpu0.icache.overall_miss_latency 11006165000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015809 # miss rate for overall accesses +system.cpu0.icache.overall_misses 914912 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10090564500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.015809 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 914912 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 915158 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 4652 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 8768 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 121 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 908876 # number of replacements +system.cpu0.icache.sampled_refs 909388 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 508.806183 # Cycle average of tags in use +system.cpu0.icache.total_refs 56957639 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 34906249000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.943968 # Percentage of idle cycles +system.cpu0.itb.accesses 3944641 # ITB accesses +system.cpu0.itb.acv 143 # ITB acv +system.cpu0.itb.hits 3940800 # ITB hits +system.cpu0.itb.misses 3841 # ITB misses +system.cpu0.kern.callpal 187118 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 572 0.40% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2878 2.02% 2.42% # number of callpals executed -system.cpu0.kern.callpal_tbi 47 0.03% 2.46% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal_swpipl 127700 89.58% 92.04% # number of callpals executed -system.cpu0.kern.callpal_rdps 6611 4.64% 96.68% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_rdusp 8 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal_rti 4215 2.96% 99.65% # number of callpals executed -system.cpu0.kern.callpal_callsys 355 0.25% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 96 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3865 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.15% # number of callpals executed +system.cpu0.kern.callpal_swpipl 171254 91.52% 93.67% # number of callpals executed +system.cpu0.kern.callpal_rdps 6635 3.55% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rti 4694 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 157735 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6620 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 134538 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 53716 39.93% 39.93% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.10% 40.02% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 2009 1.49% 41.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 482 0.36% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78200 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 108740 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 53300 49.02% 49.02% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 131 0.12% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 2009 1.85% 50.98% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 482 0.44% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 52818 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3976579702 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3843619308 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 123584 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1873872 0.05% 96.71% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 129761186 3.26% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808247 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992256 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 201983 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6162 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178054 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72322 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1968 1.11% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 103627 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144005 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 70953 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1968 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 70947 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1951128432000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1894864204500 97.12% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 72482500 0.00% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 564462000 0.03% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 4114000 0.00% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 55623169000 2.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981071 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.675422 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1193 -system.cpu0.kern.mode_good_user 1193 +system.cpu0.kern.ipl_used_31 0.684638 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1230 +system.cpu0.kern.mode_good_user 1231 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6700 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7215 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1231 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.302293 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.178060 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170478 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3965295376 99.76% 99.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 9600934 0.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1947973402000 99.84% 99.84% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3155028000 0.16% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2879 # number of times the context was actually changed -system.cpu0.kern.syscall 216 # number of syscalls executed -system.cpu0.kern.syscall_2 7 3.24% 3.24% # number of syscalls executed -system.cpu0.kern.syscall_3 18 8.33% 11.57% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.39% 12.96% # number of syscalls executed -system.cpu0.kern.syscall_6 30 13.89% 26.85% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.46% 27.31% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.46% 27.78% # number of syscalls executed -system.cpu0.kern.syscall_17 9 4.17% 31.94% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.78% 34.72% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.85% 36.57% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.93% 37.50% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.85% 39.35% # number of syscalls executed -system.cpu0.kern.syscall_33 7 3.24% 42.59% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.93% 43.52% # number of syscalls executed -system.cpu0.kern.syscall_45 36 16.67% 60.19% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.85% 62.04% # number of syscalls executed -system.cpu0.kern.syscall_48 8 3.70% 65.74% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.17% 69.91% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.46% 70.37% # number of syscalls executed -system.cpu0.kern.syscall_59 6 2.78% 73.15% # number of syscalls executed -system.cpu0.kern.syscall_71 28 12.96% 86.11% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.39% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_74 8 3.70% 91.20% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.46% 91.67% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.93% 92.59% # number of syscalls executed -system.cpu0.kern.syscall_92 7 3.24% 95.83% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.93% 96.76% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.93% 97.69% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.93% 98.61% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.46% 99.07% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.069047 # Percentage of non-idle cycles -system.cpu0.numCycles 3976579942 # number of cpu cycles simulated -system.cpu0.num_insts 50252314 # Number of instructions executed -system.cpu0.num_refs 12958725 # Number of memory references -system.cpu1.dtb.accesses 346252 # DTB accesses -system.cpu1.dtb.acv 67 # DTB access violations -system.cpu1.dtb.hits 4740996 # DTB hits -system.cpu1.dtb.misses 3345 # DTB misses -system.cpu1.dtb.read_accesses 235843 # DTB read accesses -system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_hits 2707487 # DTB read hits -system.cpu1.dtb.read_misses 2918 # DTB read misses -system.cpu1.dtb.write_accesses 110409 # DTB write accesses -system.cpu1.dtb.write_acv 41 # DTB write access violations -system.cpu1.dtb.write_hits 2033509 # DTB write hits -system.cpu1.dtb.write_misses 427 # DTB write misses -system.cpu1.idle_fraction 0.974578 # Percentage of idle cycles -system.cpu1.itb.accesses 2097175 # ITB accesses -system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 2095903 # ITB hits -system.cpu1.itb.misses 1272 # ITB misses -system.cpu1.kern.callpal 80960 # number of callpals executed +system.cpu0.kern.swap_context 3866 # number of times the context was actually changed +system.cpu0.kern.syscall 224 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed +system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed +system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed +system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed +system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed +system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed +system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed +system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed +system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed +system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed +system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed +system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed +system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed +system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed +system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.056032 # Percentage of non-idle cycles +system.cpu0.numCycles 1951129131000 # number of cpu cycles simulated +system.cpu0.num_insts 57872550 # Number of instructions executed +system.cpu0.num_refs 15541096 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1052558 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 11119.734481 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10119.576119 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 1014670 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 421304500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035996 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 37888 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 383410500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035996 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 37888 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable 120 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu1.dcache.ReadResp_mshr_uncacheable_latency 14641500 # number of ReadResp MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_accesses 677186 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 11920.138166 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 10843.231096 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 653157 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 286429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.035484 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 24029 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 260552000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.035484 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 24029 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable 2496 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu1.dcache.WriteResp_mshr_uncacheable_latency 304596500 # number of WriteResp MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.876823 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1729744 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1667827 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 707733500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.035795 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 61917 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 643962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.035795 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 61917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1729744 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1667827 # number of overall hits +system.cpu1.dcache.overall_miss_latency 707733500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.035795 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 61917 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 643962500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.035795 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 61917 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 2616 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 37951 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 906 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 1965 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 254 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 65869 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 191 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 198 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 48 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 42 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1132 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2716 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 22206 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 601 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1247 # write misses to shared blocks +system.cpu1.dcache.replacements 55360 # number of replacements +system.cpu1.dcache.sampled_refs 55749 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 388.749341 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1665603 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1935095598000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 27663 # number of writebacks +system.cpu1.dtb.accesses 302878 # DTB accesses +system.cpu1.dtb.acv 84 # DTB access violations +system.cpu1.dtb.hits 1728432 # DTB hits +system.cpu1.dtb.misses 3106 # DTB misses +system.cpu1.dtb.read_accesses 205838 # DTB read accesses +system.cpu1.dtb.read_acv 36 # DTB read access violations +system.cpu1.dtb.read_hits 1049360 # DTB read hits +system.cpu1.dtb.read_misses 2750 # DTB read misses +system.cpu1.dtb.write_accesses 97040 # DTB write accesses +system.cpu1.dtb.write_acv 48 # DTB write access violations +system.cpu1.dtb.write_hits 679072 # DTB write hits +system.cpu1.dtb.write_misses 356 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5376264 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 12045.939531 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11045.466957 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5281041 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1147050500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.017712 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 95223 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1051782500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.017712 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 95223 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 57.662729 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5376264 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5281041 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1147050500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017712 # miss rate for demand accesses +system.cpu1.icache.demand_misses 95223 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 1051782500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.017712 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 95223 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5376264 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5281041 # number of overall hits +system.cpu1.icache.overall_miss_latency 1147050500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017712 # miss rate for overall accesses +system.cpu1.icache.overall_misses 95223 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 1051782500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.017712 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 95223 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 97341 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 39627 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 214588 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 26 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 91073 # number of replacements +system.cpu1.icache.sampled_refs 91585 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 420.500398 # Cycle average of tags in use +system.cpu1.icache.total_refs 5281041 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1947911714000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.995322 # Percentage of idle cycles +system.cpu1.itb.accesses 1399877 # ITB accesses +system.cpu1.itb.acv 41 # ITB acv +system.cpu1.itb.hits 1398631 # ITB hits +system.cpu1.itb.misses 1246 # ITB misses +system.cpu1.kern.callpal 29847 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 482 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2289 2.83% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71572 88.40% 91.85% # number of callpals executed -system.cpu1.kern.callpal_rdps 2303 2.84% 94.69% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_rti 4092 5.05% 99.76% # number of callpals executed -system.cpu1.kern.callpal_callsys 162 0.20% 99.96% # number of callpals executed -system.cpu1.kern.callpal_imb 33 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_swpctx 375 1.26% 1.29% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.32% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24461 81.95% 83.30% # number of callpals executed +system.cpu1.kern.callpal_rdps 2201 7.37% 90.67% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.68% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.70% # number of callpals executed +system.cpu1.kern.callpal_rti 2582 8.65% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 88242 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2815 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 78238 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30461 38.93% 38.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 2001 2.56% 41.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 572 0.73% 42.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45204 57.78% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 61001 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29500 48.36% 48.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 2001 3.28% 51.64% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 572 0.94% 52.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28928 47.42% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3977361024 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3855399740 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1871566 0.05% 96.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 1461344 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118628374 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.779685 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968451 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 36385 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2332 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 29103 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9344 32.11% 32.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1963 6.75% 38.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 96 0.33% 39.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17700 60.82% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20635 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9336 45.24% 45.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1963 9.51% 54.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 96 0.47% 55.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9240 44.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1950372731000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1911409272000 98.00% 98.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 494740000 0.03% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 52316000 0.00% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 38416403000 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999144 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.639943 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1058 -system.cpu1.kern.mode_good_user 562 -system.cpu1.kern.mode_good_idle 496 -system.cpu1.kern.mode_switch_kernel 2397 # number of protection mode switches -system.cpu1.kern.mode_switch_user 562 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 3035 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.353020 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.441385 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.522034 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 538 +system.cpu1.kern.mode_good_user 517 +system.cpu1.kern.mode_good_idle 21 +system.cpu1.kern.mode_switch_kernel 884 # number of protection mode switches +system.cpu1.kern.mode_switch_user 517 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2075 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.618718 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.608597 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.163427 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 64032120 1.61% 1.61% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5754658 0.14% 1.75% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3907574238 98.25% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2290 # number of times the context was actually changed -system.cpu1.kern.syscall 110 # number of syscalls executed -system.cpu1.kern.syscall_2 1 0.91% 0.91% # number of syscalls executed -system.cpu1.kern.syscall_3 12 10.91% 11.82% # number of syscalls executed -system.cpu1.kern.syscall_4 1 0.91% 12.73% # number of syscalls executed -system.cpu1.kern.syscall_6 12 10.91% 23.64% # number of syscalls executed -system.cpu1.kern.syscall_17 6 5.45% 29.09% # number of syscalls executed -system.cpu1.kern.syscall_19 4 3.64% 32.73% # number of syscalls executed -system.cpu1.kern.syscall_20 2 1.82% 34.55% # number of syscalls executed -system.cpu1.kern.syscall_23 2 1.82% 36.36% # number of syscalls executed -system.cpu1.kern.syscall_24 2 1.82% 38.18% # number of syscalls executed -system.cpu1.kern.syscall_33 4 3.64% 41.82% # number of syscalls executed -system.cpu1.kern.syscall_45 18 16.36% 58.18% # number of syscalls executed -system.cpu1.kern.syscall_47 2 1.82% 60.00% # number of syscalls executed -system.cpu1.kern.syscall_48 2 1.82% 61.82% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.91% 62.73% # number of syscalls executed -system.cpu1.kern.syscall_59 1 0.91% 63.64% # number of syscalls executed -system.cpu1.kern.syscall_71 26 23.64% 87.27% # number of syscalls executed -system.cpu1.kern.syscall_74 8 7.27% 94.55% # number of syscalls executed -system.cpu1.kern.syscall_90 1 0.91% 95.45% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.82% 97.27% # number of syscalls executed -system.cpu1.kern.syscall_132 2 1.82% 99.09% # number of syscalls executed -system.cpu1.kern.syscall_144 1 0.91% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025422 # Percentage of non-idle cycles -system.cpu1.numCycles 3977362808 # number of cpu cycles simulated -system.cpu1.num_insts 14898950 # Number of instructions executed -system.cpu1.num_refs 4770935 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.010120 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 3563216000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1513259000 0.08% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1945257297000 99.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 376 # number of times the context was actually changed +system.cpu1.kern.syscall 102 # number of syscalls executed +system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed +system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed +system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed +system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed +system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed +system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed +system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed +system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed +system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed +system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed +system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed +system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed +system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed +system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed +system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed +system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed +system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed +system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed +system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed +system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed +system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.004678 # Percentage of non-idle cycles +system.cpu1.numCycles 1950372761000 # number of cpu cycles simulated +system.cpu1.num_insts 5376264 # Number of instructions executed +system.cpu1.num_refs 1738417 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -228,6 +611,91 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306499 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 12998.029396 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 10997.988681 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 183694 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1596223000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.400670 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 122805 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1350608000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.400670 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 122805 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2751323 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 12999.901707 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 10999.990968 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1810263 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12233687500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.342039 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941060 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 10351530500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.342035 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 941049 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6993 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 779629500 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 12194 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1356619000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429269 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429256 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.000030 # miss rate for Writeback accesses +system.l2c.Writeback_misses 13 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.000030 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 13 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.277768 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2751323 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 12999.901707 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.demand_hits 1810263 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12233687500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.342039 # miss rate for demand accesses +system.l2c.demand_misses 941060 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10351530500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.342035 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 941049 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3180592 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 12999.722126 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2239519 # number of overall hits +system.l2c.overall_miss_latency 12233687500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.295880 # miss rate for overall accesses +system.l2c.overall_misses 941073 # number of overall misses +system.l2c.overall_mshr_hits 11 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10351530500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.295872 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 941049 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 19187 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 998318 # number of replacements +system.l2c.sampled_refs 1063854 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65469.787238 # Cycle average of tags in use +system.l2c.total_refs 2423213 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3064127000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 79556 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 9d86a655e..dc84ff88b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,7 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 1082476: Trying to launch CPU number 1! +warn: 423901000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index ebf8b13c8..a3bd937f6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:57:20 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3977364868 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:07:53 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1951129131000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 65aa9c7e6..ded525737 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -5,14 +5,14 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/Users/ali/work/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/Users/ali/work/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/Users/ali/work/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -21,10 +21,10 @@ system_type=34 [system.bridge] type=Bridge -delay=0 +delay=50000 fix_partial_write_a=false fix_partial_write_b=true -nack_delay=0 +nack_delay=4000 req_size_a=16 req_size_b=16 resp_size_a=16 @@ -35,8 +35,8 @@ side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -54,13 +54,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -68,7 +156,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -81,13 +169,13 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -100,7 +188,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -111,27 +199,65 @@ sys=system type=Bus block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -168,9 +294,36 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -180,7 +333,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -191,7 +344,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -206,7 +359,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -216,21 +369,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 -max_backoff_delay=20000 -min_backoff_delay=8 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -275,7 +428,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -291,7 +444,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -307,7 +460,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -323,7 +476,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -339,7 +492,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -355,7 +508,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -371,7 +524,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -387,7 +540,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -403,7 +556,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -419,7 +572,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -435,7 +588,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -451,7 +604,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -467,7 +620,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -483,7 +636,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -499,7 +652,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -515,7 +668,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -531,7 +684,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -547,7 +700,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -563,7 +716,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -580,7 +733,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -588,15 +741,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 -max_backoff_delay=20000 -min_backoff_delay=8 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -640,9 +793,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -653,7 +806,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -671,7 +824,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index 1034abd0e..b51eb234e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -11,12 +11,12 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing -kernel=/Users/ali/work/system/binaries/vmlinux -console=/Users/ali/work/system/binaries/console -pal=/Users/ali/work/system/binaries/ts_osfpal +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -27,7 +27,7 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false block_size=64 @@ -44,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -56,21 +56,58 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge req_size_a=16 req_size_b=16 resp_size_a=16 resp_size_b=16 -delay=0 -nack_delay=0 +delay=50000 +nack_delay=4000 write_ack=false fix_partial_write_a=false fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -84,11 +121,11 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -102,11 +139,11 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -117,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -132,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -147,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -162,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -177,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -192,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -200,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -247,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -263,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -283,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -298,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -306,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -321,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -336,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -351,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -366,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -381,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -396,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -411,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -426,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -444,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -485,14 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -501,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -520,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -535,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -543,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -558,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -609,21 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true block_size=64 +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 466fb2d27..d9f42b16b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,83 +1,275 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 233672 # Simulator instruction rate (inst/s) -host_seconds 257.14 # Real time elapsed on the host -host_tick_rate 15108417 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60085488 # Number of instructions simulated -sim_seconds 1.942464 # Number of seconds simulated -sim_ticks 3884928812 # Number of ticks simulated -system.cpu.dtb.accesses 1020784 # DTB accesses +host_inst_rate 212380 # Simulator instruction rate (inst/s) +host_mem_usage 201984 # Number of bytes of host memory used +host_seconds 282.69 # Real time elapsed on the host +host_tick_rate 6746442466 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60037406 # Number of instructions simulated +sim_seconds 1.907146 # Number of seconds simulated +sim_ticks 1907146437000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9726331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13065.219101 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12065.192690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7984648 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22755470000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.179069 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1741683 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 21013741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.179069 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1741683 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu.dcache.ReadResp_mshr_uncacheable_latency 824099000 # number of ReadResp MSHR uncacheable cycles +system.cpu.dcache.WriteReq_accesses 6350552 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 12768.106941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11768.067509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6046235 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3885552000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.047920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304317 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3581223000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.047920 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 304317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu.dcache.WriteResp_mshr_uncacheable_latency 1154484000 # number of WriteResp MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.857760 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16076883 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.demand_hits 14030883 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26641022000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127263 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2046000 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 24594964000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.127263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2046000 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16076883 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14030883 # number of overall hits +system.cpu.dcache.overall_miss_latency 26641022000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127263 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2046000 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 24594964000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.127263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2046000 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1741683 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 9 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 4 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 92 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304305 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2045476 # number of replacements +system.cpu.dcache.sampled_refs 2045988 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.987904 # Cycle average of tags in use +system.cpu.dcache.total_refs 14030895 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 57945000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 429989 # number of writebacks +system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16070353 # DTB hits -system.cpu.dtb.misses 11466 # DTB misses -system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.hits 16057425 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9714571 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9706740 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6355782 # DTB write hits +system.cpu.dtb.write_hits 6350685 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.idle_fraction 0.921526 # Percentage of idle cycles -system.cpu.itb.accesses 4985698 # ITB accesses +system.cpu.icache.ReadReq_accesses 60037407 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12029.456206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11028.713640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 59110217 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11153591500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.015444 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 927190 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10225713000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.015444 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 927190 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 63.763003 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60037407 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.demand_hits 59110217 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11153591500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015444 # miss rate for demand accesses +system.cpu.icache.demand_misses 927190 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10225713000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.015444 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 927190 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60037407 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59110217 # number of overall hits +system.cpu.icache.overall_miss_latency 11153591500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015444 # miss rate for overall accesses +system.cpu.icache.overall_misses 927190 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10225713000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.015444 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 927190 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 927190 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 644 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1040 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 146 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 2 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 926519 # number of replacements +system.cpu.icache.sampled_refs 927030 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 508.761542 # Cycle average of tags in use +system.cpu.icache.total_refs 59110217 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 34634685000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.940784 # Percentage of idle cycles +system.cpu.itb.accesses 4977586 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4980688 # ITB hits -system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193483 # number of callpals executed +system.cpu.itb.hits 4972580 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192752 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4144 2.14% 2.14% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.17% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.18% # number of callpals executed -system.cpu.kern.callpal_swpipl 176511 91.23% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6861 3.55% 96.95% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.95% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rti 5187 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 175824 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal_rdps 6824 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal_rti 5148 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212605 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6153 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183792 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75069 40.84% 40.84% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1962 1.07% 41.98% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106630 58.02% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149497 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73702 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1962 1.31% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73702 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3884927028 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3757863794 96.73% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 112456 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 918216 0.02% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126032562 3.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.813403 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981790 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211836 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183027 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74862 40.90% 40.90% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1923 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106111 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149044 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73495 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1923 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73495 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1907145727000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1851261210000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 73754500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 531976500 0.03% 97.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 55278786000 2.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981740 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691194 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1895 -system.cpu.kern.mode_good_user 1742 -system.cpu.kern.mode_good_idle 153 -system.cpu.kern.mode_switch_kernel 5935 # number of protection mode switches -system.cpu.kern.mode_switch_user 1742 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2062 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389157 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319292 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.692624 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1740 +system.cpu.kern.mode_good_idle 170 +system.cpu.kern.mode_switch_kernel 5894 # number of protection mode switches +system.cpu.kern.mode_switch_user 1740 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.405165 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.324058 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.074200 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 112890486 2.91% 2.91% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 15209884 0.39% 3.30% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3756826650 96.70% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4145 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 42657550000 2.24% 2.24% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4648649000 0.24% 2.48% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1859839526000 97.52% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -109,10 +301,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.078474 # Percentage of non-idle cycles -system.cpu.numCycles 3884928812 # number of cpu cycles simulated -system.cpu.num_insts 60085488 # Number of instructions executed -system.cpu.num_refs 16318244 # Number of memory references +system.cpu.not_idle_fraction 0.059216 # Percentage of non-idle cycles +system.cpu.numCycles 1907146437000 # number of cpu cycles simulated +system.cpu.num_insts 60037406 # Number of instructions executed +system.cpu.num_refs 16305563 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -125,6 +317,86 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304305 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 13000.153945 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11000.153945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 187380 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1520043000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.384236 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116925 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1286193000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.384236 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 116925 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2668854 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 13000.065889 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11000.065889 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1727874 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12232802000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.352578 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 940980 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 10350842000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.352578 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 940980 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 750102000 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1050666000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429989 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429989 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.216875 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2668854 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.demand_hits 1727874 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12232802000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.352578 # miss rate for demand accesses +system.l2c.demand_misses 940980 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10350842000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.352578 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 940980 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3098843 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2157863 # number of overall hits +system.l2c.overall_miss_latency 12232802000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.303655 # miss rate for overall accesses +system.l2c.overall_misses 940980 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10350842000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.303655 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 940980 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992369 # number of replacements +system.l2c.sampled_refs 1057905 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65468.856552 # Cycle average of tags in use +system.l2c.total_refs 2345243 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3045832000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 74072 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 969291745..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,5 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 427d90ea3..b8196fe27 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:54:39 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3883112324 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:07:53 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1907146437000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 0c1dbb0ba..0431dd3db 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -39,6 +39,7 @@ system=system [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 5e988f3f9..73c363bc4 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=EioProcess diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index bc0a96087..7380e419f 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 689098 # Simulator instruction rate (inst/s) -host_mem_usage 147724 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -host_tick_rate 344128671 # Simulator tick rate (ticks/s) +host_inst_rate 819297 # Simulator instruction rate (inst/s) +host_mem_usage 147636 # Number of bytes of host memory used +host_seconds 0.61 # Real time elapsed on the host +host_tick_rate 409362131 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 47ee09274..c8bcb5723 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:12 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:43 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 249999500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index eef4c0a1a..c05a66f9d 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -162,6 +160,7 @@ system=system [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index e897b733f..570ef7de8 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=EioProcess @@ -52,13 +53,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -89,14 +91,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -127,14 +128,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -165,5 +165,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index a6caa5891..be87d3617 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 518674 # Simulator instruction rate (inst/s) -host_mem_usage 153108 # Number of bytes of host memory used -host_seconds 0.96 # Real time elapsed on the host -host_tick_rate 355827019 # Simulator tick rate (ticks/s) +host_inst_rate 392036 # Simulator instruction rate (inst/s) +host_mem_usage 153128 # Number of bytes of host memory used +host_seconds 1.28 # Real time elapsed on the host +host_tick_rate 542334315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000343 # Number of seconds simulated -sim_ticks 343161000 # Number of ticks simulated +sim_seconds 0.000692 # Number of seconds simulated +sim_ticks 691915000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3793.650794 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2793.650794 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1195000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4410000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 880000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4095000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3600.719424 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2600.719424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 500500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1946000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 361500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1807000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3734.581498 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1695500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 6356000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1241500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5902000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3734.581498 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 1695500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 6356000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1241500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5902000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 291.533202 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 290.922203 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3739.454094 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2739.454094 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1507000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 5642000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1104000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 5239000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3739.454094 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1507000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 5642000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1104000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 5239000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3739.454094 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits -system.cpu.icache.overall_miss_latency 1507000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 5642000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1104000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 5239000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 268.106513 # Cycle average of tags in use +system.cpu.icache.tagsinuse 267.665433 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2736.872812 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1735.872812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2345500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 11141000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1487643 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 9427000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2736.872812 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2345500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 11141000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1487643 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9427000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2736.872812 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2345500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 11141000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1487643 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9427000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 559.642213 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 558.588875 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 343161000 # number of cpu cycles simulated +system.cpu.numCycles 691915000 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 8126fb0fb..83f216de6 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:14 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:44 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 343161000 because a thread reached the max instruction count +Exiting @ tick 691915000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 363cb64d4..bf66a6947 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -34,8 +34,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -95,8 +94,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -156,8 +154,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -217,8 +214,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -278,8 +274,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -339,8 +334,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -400,8 +394,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -461,8 +454,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -514,8 +506,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=10 +latency=10000 lifo=false max_miss_count=0 mshrs=92 @@ -547,6 +538,7 @@ mem_side=system.membus.port[0] [system.membus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=false @@ -563,6 +555,7 @@ port=system.membus.port[1] [system.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=false diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out index b3f4ec871..53f718c0d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -20,13 +20,14 @@ bus_id=0 clock=2 width=16 responder_set=false +block_size=64 [system.l2c] type=BaseCache size=65536 assoc=8 block_size=64 -latency=10 +latency=10000 mshrs=92 tgts_per_mshr=16 write_buffers=8 @@ -57,7 +58,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu6] type=MemTest @@ -82,7 +82,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -113,7 +113,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu4] type=MemTest @@ -138,7 +137,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -169,7 +168,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu5] type=MemTest @@ -194,7 +192,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -225,7 +223,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu2] type=MemTest @@ -250,7 +247,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -281,7 +278,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu3] type=MemTest @@ -306,7 +302,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -337,7 +333,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu0] type=MemTest @@ -362,7 +357,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -393,7 +388,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu1] type=MemTest @@ -418,7 +412,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -449,7 +443,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.funcmem] type=PhysicalMemory @@ -481,7 +474,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -512,7 +505,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.toL2Bus] type=Bus @@ -520,4 +512,5 @@ bus_id=0 clock=2 width=16 responder_set=false +block_size=64 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index 285ab3702..2617dd49e 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 303680 # Number of bytes of host memory used -host_seconds 32.50 # Real time elapsed on the host -host_tick_rate 177110 # Simulator tick rate (ticks/s) +host_mem_usage 1265676 # Number of bytes of host memory used +host_seconds 390.60 # Real time elapsed on the host +host_tick_rate 215953 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5755736 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 45048 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 959.688548 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 884.132516 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_hits 7543 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 35993119 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.832556 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37505 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 33159390 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832556 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37505 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable 9815 # number of ReadReq MSHR uncacheable +sim_seconds 0.000084 # Number of seconds simulated +sim_ticks 84350509 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44421 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 14010.391786 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 12986.475734 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7291 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 520205847 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.835866 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37130 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 482187844 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835866 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37130 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable 9916 # number of ReadReq MSHR uncacheable system.cpu0.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 17521633 # number of ReadResp MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24308 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 862.246942 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 778.821396 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_hits 1173 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 19948083 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.951744 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23135 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 18018033 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.951744 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23135 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable 5428 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 255520881 # number of ReadResp MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 23898 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 12904.605270 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 11399.917485 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_hits 1090 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 294328237 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.954389 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 22808 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 260009318 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.954389 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 22808 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable 5184 # number of WriteReq MSHR uncacheable system.cpu0.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 10755873 # number of WriteResp MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 81.366905 # average number of cycles each access was blocked +system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 154702333 # number of WriteResp MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1194.948852 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.417208 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69811 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.407238 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69093 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 5680305 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 82562601 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69356 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 922.513226 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8716 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 55941202 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.874330 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60640 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68319 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 13589.610664 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8381 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 814534084 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.877325 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 59938 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 51177423 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.874330 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60640 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 742197162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.877325 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 59938 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 69356 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 922.513226 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 68319 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 13589.610664 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8716 # number of overall hits -system.cpu0.l1c.overall_miss_latency 55941202 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.874330 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60640 # number of overall misses +system.cpu0.l1c.overall_hits 8381 # number of overall hits +system.cpu0.l1c.overall_miss_latency 814534084 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.877325 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 59938 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 51177423 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.874330 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60640 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_miss_latency 742197162 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.877325 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 59938 # number of overall MSHR misses system.cpu0.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_misses 15243 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses 15100 # number of overall MSHR uncacheable misses system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -78,103 +78,103 @@ system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.l1c.protocol.read_invalid 109554 # read misses to invalid blocks +system.cpu0.l1c.protocol.read_invalid 1761660 # read misses to invalid blocks system.cpu0.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu0.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu0.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu0.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu0.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.l1c.protocol.snoop_read_exclusive 2807 # read snoops on exclusive blocks -system.cpu0.l1c.protocol.snoop_read_modified 12380 # read snoops on modified blocks -system.cpu0.l1c.protocol.snoop_read_owned 7157 # read snoops on owned blocks -system.cpu0.l1c.protocol.snoop_read_shared 22767 # read snoops on shared blocks -system.cpu0.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks -system.cpu0.l1c.protocol.snoop_readex_modified 6851 # readEx snoops on modified blocks -system.cpu0.l1c.protocol.snoop_readex_owned 3877 # readEx snoops on owned blocks -system.cpu0.l1c.protocol.snoop_readex_shared 12465 # readEx snoops on shared blocks -system.cpu0.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks -system.cpu0.l1c.protocol.snoop_upgrade_shared 2994 # upgradee snoops on shared blocks +system.cpu0.l1c.protocol.snoop_read_exclusive 2836 # read snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_read_modified 12378 # read snoops on modified blocks +system.cpu0.l1c.protocol.snoop_read_owned 7300 # read snoops on owned blocks +system.cpu0.l1c.protocol.snoop_read_shared 1749577 # read snoops on shared blocks +system.cpu0.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_readex_modified 6692 # readEx snoops on modified blocks +system.cpu0.l1c.protocol.snoop_readex_owned 4009 # readEx snoops on owned blocks +system.cpu0.l1c.protocol.snoop_readex_shared 12550 # readEx snoops on shared blocks +system.cpu0.l1c.protocol.snoop_upgrade_owned 790 # upgrade snoops on owned blocks +system.cpu0.l1c.protocol.snoop_upgrade_shared 3004 # upgradee snoops on shared blocks system.cpu0.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu0.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu0.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu0.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu0.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu0.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.l1c.protocol.write_invalid 60706 # write misses to invalid blocks -system.cpu0.l1c.protocol.write_owned 1361 # write misses to owned blocks -system.cpu0.l1c.protocol.write_shared 4416 # write misses to shared blocks -system.cpu0.l1c.replacements 27529 # number of replacements -system.cpu0.l1c.sampled_refs 27883 # Sample count of references to valid blocks. +system.cpu0.l1c.protocol.write_invalid 940728 # write misses to invalid blocks +system.cpu0.l1c.protocol.write_owned 1344 # write misses to owned blocks +system.cpu0.l1c.protocol.write_shared 4484 # write misses to shared blocks +system.cpu0.l1c.replacements 27160 # number of replacements +system.cpu0.l1c.sampled_refs 27495 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 342.460043 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11633 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 342.709273 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11197 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 10915 # number of writebacks +system.cpu0.l1c.writebacks 10716 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99586 # number of read accesses completed -system.cpu0.num_writes 53803 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44416 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 969.343786 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 893.327484 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_hits 7486 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 35797866 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.831457 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 36930 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 32990584 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831457 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 36930 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable 9894 # number of ReadReq MSHR uncacheable +system.cpu0.num_reads 98012 # number of read accesses completed +system.cpu0.num_writes 53207 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44893 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 13909.754864 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 12900.185775 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7579 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 519028593 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.831176 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37314 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 481357532 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831176 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37314 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable 9811 # number of ReadReq MSHR uncacheable system.cpu1.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 17663360 # number of ReadResp MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24084 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 871.179293 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 786.258930 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_hits 1155 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 19975270 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.952043 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 22929 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 18028131 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.952043 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 22929 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable 5271 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 251708747 # number of ReadResp MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24614 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 12788.679753 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 11344.205121 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_hits 1257 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 298705193 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.948932 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23357 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 264966599 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.948932 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23357 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable 5453 # number of WriteReq MSHR uncacheable system.cpu1.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 10523322 # number of WriteResp MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 82.260179 # average number of cycles each access was blocked +system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 163813954 # number of WriteResp MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1183.149435 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.414867 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 68941 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.414323 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69763 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 5671099 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 82540054 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 68500 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 931.741860 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8641 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 55773136 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.873854 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 59859 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 69507 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 13478.165615 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8836 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 817733786 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.872876 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60671 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 51018715 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.873854 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 59859 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 746324131 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.872876 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60671 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 68500 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 931.741860 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 69507 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 13478.165615 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8641 # number of overall hits -system.cpu1.l1c.overall_miss_latency 55773136 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.873854 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 59859 # number of overall misses +system.cpu1.l1c.overall_hits 8836 # number of overall hits +system.cpu1.l1c.overall_miss_latency 817733786 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.872876 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60671 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 51018715 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.873854 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 59859 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_miss_latency 746324131 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.872876 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60671 # number of overall MSHR misses system.cpu1.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_misses 15165 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses 15264 # number of overall MSHR uncacheable misses system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -185,103 +185,103 @@ system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu1.l1c.protocol.read_invalid 114228 # read misses to invalid blocks +system.cpu1.l1c.protocol.read_invalid 1717891 # read misses to invalid blocks system.cpu1.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu1.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu1.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu1.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu1.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.l1c.protocol.snoop_read_exclusive 2718 # read snoops on exclusive blocks -system.cpu1.l1c.protocol.snoop_read_modified 12396 # read snoops on modified blocks -system.cpu1.l1c.protocol.snoop_read_owned 7348 # read snoops on owned blocks -system.cpu1.l1c.protocol.snoop_read_shared 23222 # read snoops on shared blocks -system.cpu1.l1c.protocol.snoop_readex_exclusive 1497 # readEx snoops on exclusive blocks -system.cpu1.l1c.protocol.snoop_readex_modified 6706 # readEx snoops on modified blocks -system.cpu1.l1c.protocol.snoop_readex_owned 3865 # readEx snoops on owned blocks -system.cpu1.l1c.protocol.snoop_readex_shared 12512 # readEx snoops on shared blocks -system.cpu1.l1c.protocol.snoop_upgrade_owned 852 # upgrade snoops on owned blocks -system.cpu1.l1c.protocol.snoop_upgrade_shared 2973 # upgradee snoops on shared blocks +system.cpu1.l1c.protocol.snoop_read_exclusive 2925 # read snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_read_modified 12701 # read snoops on modified blocks +system.cpu1.l1c.protocol.snoop_read_owned 7436 # read snoops on owned blocks +system.cpu1.l1c.protocol.snoop_read_shared 1669937 # read snoops on shared blocks +system.cpu1.l1c.protocol.snoop_readex_exclusive 1611 # readEx snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_readex_modified 6726 # readEx snoops on modified blocks +system.cpu1.l1c.protocol.snoop_readex_owned 3965 # readEx snoops on owned blocks +system.cpu1.l1c.protocol.snoop_readex_shared 12596 # readEx snoops on shared blocks +system.cpu1.l1c.protocol.snoop_upgrade_owned 860 # upgrade snoops on owned blocks +system.cpu1.l1c.protocol.snoop_upgrade_shared 2979 # upgradee snoops on shared blocks system.cpu1.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu1.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu1.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu1.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu1.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu1.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu1.l1c.protocol.write_invalid 61595 # write misses to invalid blocks -system.cpu1.l1c.protocol.write_owned 1320 # write misses to owned blocks -system.cpu1.l1c.protocol.write_shared 4183 # write misses to shared blocks -system.cpu1.l1c.replacements 27139 # number of replacements -system.cpu1.l1c.sampled_refs 27498 # Sample count of references to valid blocks. +system.cpu1.l1c.protocol.write_invalid 914774 # write misses to invalid blocks +system.cpu1.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu1.l1c.protocol.write_shared 4382 # write misses to shared blocks +system.cpu1.l1c.replacements 27806 # number of replacements +system.cpu1.l1c.sampled_refs 28164 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 341.113569 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11408 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 345.545872 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11669 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10884 # number of writebacks +system.cpu1.l1c.writebacks 11204 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98821 # number of read accesses completed -system.cpu1.num_writes 53366 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 45016 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 956.031371 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 880.781951 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_hits 7529 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 35838748 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832748 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37487 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 33017873 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832748 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable 9887 # number of ReadReq MSHR uncacheable +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 54335 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44489 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 14018.031231 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 12993.788573 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7507 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 518414831 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.831262 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 36982 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 480536289 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.831262 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 36982 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable system.cpu2.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 17582637 # number of ReadResp MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24456 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 859.707355 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 777.777296 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_hits 1165 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 20023444 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.952363 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23291 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 18115211 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.952363 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23291 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable 5362 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 253484666 # number of ReadResp MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24340 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 12765.385606 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 11318.971789 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_hits 1122 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 296386723 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.953903 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23218 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 262803887 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.953903 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23218 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable 5480 # number of WriteReq MSHR uncacheable system.cpu2.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 10583136 # number of WriteResp MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 81.152375 # average number of cycles each access was blocked +system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 165110755 # number of WriteResp MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1190.317505 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.404365 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69867 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.414721 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69202 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 5669873 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 82372352 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 69472 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 919.118628 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8694 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 55862192 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.874856 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60778 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68829 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 13534.909535 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8629 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 814801554 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.874631 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60200 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 51133084 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.874856 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60778 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 743340176 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.874631 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60200 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 69472 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 919.118628 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 68829 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 13534.909535 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8694 # number of overall hits -system.cpu2.l1c.overall_miss_latency 55862192 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.874856 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60778 # number of overall misses +system.cpu2.l1c.overall_hits 8629 # number of overall hits +system.cpu2.l1c.overall_miss_latency 814801554 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.874631 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60200 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 51133084 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.874856 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60778 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_miss_latency 743340176 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.874631 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60200 # number of overall MSHR misses system.cpu2.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_misses 15249 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses 15341 # number of overall MSHR uncacheable misses system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -292,103 +292,103 @@ system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu2.l1c.protocol.read_invalid 111528 # read misses to invalid blocks +system.cpu2.l1c.protocol.read_invalid 1818161 # read misses to invalid blocks system.cpu2.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu2.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu2.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu2.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu2.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu2.l1c.protocol.snoop_read_exclusive 2757 # read snoops on exclusive blocks -system.cpu2.l1c.protocol.snoop_read_modified 12587 # read snoops on modified blocks -system.cpu2.l1c.protocol.snoop_read_owned 7252 # read snoops on owned blocks -system.cpu2.l1c.protocol.snoop_read_shared 22967 # read snoops on shared blocks -system.cpu2.l1c.protocol.snoop_readex_exclusive 1579 # readEx snoops on exclusive blocks -system.cpu2.l1c.protocol.snoop_readex_modified 6680 # readEx snoops on modified blocks -system.cpu2.l1c.protocol.snoop_readex_owned 3891 # readEx snoops on owned blocks -system.cpu2.l1c.protocol.snoop_readex_shared 12468 # readEx snoops on shared blocks -system.cpu2.l1c.protocol.snoop_upgrade_owned 850 # upgrade snoops on owned blocks -system.cpu2.l1c.protocol.snoop_upgrade_shared 2951 # upgradee snoops on shared blocks +system.cpu2.l1c.protocol.snoop_read_exclusive 2846 # read snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_read_modified 12505 # read snoops on modified blocks +system.cpu2.l1c.protocol.snoop_read_owned 7354 # read snoops on owned blocks +system.cpu2.l1c.protocol.snoop_read_shared 1719896 # read snoops on shared blocks +system.cpu2.l1c.protocol.snoop_readex_exclusive 1512 # readEx snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_readex_modified 6836 # readEx snoops on modified blocks +system.cpu2.l1c.protocol.snoop_readex_owned 4066 # readEx snoops on owned blocks +system.cpu2.l1c.protocol.snoop_readex_shared 12494 # readEx snoops on shared blocks +system.cpu2.l1c.protocol.snoop_upgrade_owned 828 # upgrade snoops on owned blocks +system.cpu2.l1c.protocol.snoop_upgrade_shared 2975 # upgradee snoops on shared blocks system.cpu2.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu2.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu2.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu2.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu2.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu2.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu2.l1c.protocol.write_invalid 57618 # write misses to invalid blocks -system.cpu2.l1c.protocol.write_owned 1263 # write misses to owned blocks -system.cpu2.l1c.protocol.write_shared 4251 # write misses to shared blocks -system.cpu2.l1c.replacements 28062 # number of replacements -system.cpu2.l1c.sampled_refs 28405 # Sample count of references to valid blocks. +system.cpu2.l1c.protocol.write_invalid 1061132 # write misses to invalid blocks +system.cpu2.l1c.protocol.write_owned 1410 # write misses to owned blocks +system.cpu2.l1c.protocol.write_shared 4436 # write misses to shared blocks +system.cpu2.l1c.replacements 27337 # number of replacements +system.cpu2.l1c.sampled_refs 27674 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 344.040679 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11486 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 343.290844 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11477 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 11295 # number of writebacks +system.cpu2.l1c.writebacks 10872 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 54133 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44504 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 968.772953 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 892.914985 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_hits 7428 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 35918226 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.833094 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37076 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 33105716 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833094 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37076 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable 9876 # number of ReadReq MSHR uncacheable +system.cpu2.num_reads 98887 # number of read accesses completed +system.cpu2.num_writes 53640 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44566 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 14066.553951 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 13052.525235 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7375 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 523149208 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.834515 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37191 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 485436466 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.834515 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable system.cpu3.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 17594905 # number of ReadResp MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24087 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 868.499565 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 784.537397 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_hits 1117 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 19949435 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.953626 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 22970 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 18020824 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.953626 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 22970 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable 5355 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 252799971 # number of ReadResp MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24030 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 12807.474484 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 11345.837164 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_hits 1142 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 293137476 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.952476 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 22888 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 259683521 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.952476 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 22888 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable 5294 # number of WriteReq MSHR uncacheable system.cpu3.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 10637792 # number of WriteResp MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 82.097897 # average number of cycles each access was blocked +system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 159218905 # number of WriteResp MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1193.729049 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.411489 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69124 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.411345 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69160 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 5674935 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 82558301 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 68591 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 930.414366 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8545 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 55867661 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.875421 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60046 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68596 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 13586.888663 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8517 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 816286684 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.875838 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60079 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 51126540 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.875421 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60046 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 745119987 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.875838 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60079 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 68591 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 930.414366 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 68596 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 13586.888663 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8545 # number of overall hits -system.cpu3.l1c.overall_miss_latency 55867661 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.875421 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60046 # number of overall misses +system.cpu3.l1c.overall_hits 8517 # number of overall hits +system.cpu3.l1c.overall_miss_latency 816286684 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.875838 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60079 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 51126540 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.875421 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60046 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_miss_latency 745119987 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.875838 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60079 # number of overall MSHR misses system.cpu3.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_misses 15231 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses 15114 # number of overall MSHR uncacheable misses system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -399,103 +399,103 @@ system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu3.l1c.protocol.read_invalid 110901 # read misses to invalid blocks +system.cpu3.l1c.protocol.read_invalid 1894373 # read misses to invalid blocks system.cpu3.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu3.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu3.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu3.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu3.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu3.l1c.protocol.snoop_read_exclusive 2843 # read snoops on exclusive blocks -system.cpu3.l1c.protocol.snoop_read_modified 12490 # read snoops on modified blocks -system.cpu3.l1c.protocol.snoop_read_owned 7235 # read snoops on owned blocks -system.cpu3.l1c.protocol.snoop_read_shared 23011 # read snoops on shared blocks -system.cpu3.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks -system.cpu3.l1c.protocol.snoop_readex_modified 6732 # readEx snoops on modified blocks -system.cpu3.l1c.protocol.snoop_readex_owned 3954 # readEx snoops on owned blocks -system.cpu3.l1c.protocol.snoop_readex_shared 12354 # readEx snoops on shared blocks -system.cpu3.l1c.protocol.snoop_upgrade_owned 858 # upgrade snoops on owned blocks -system.cpu3.l1c.protocol.snoop_upgrade_shared 3087 # upgradee snoops on shared blocks +system.cpu3.l1c.protocol.snoop_read_exclusive 2902 # read snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_read_modified 12291 # read snoops on modified blocks +system.cpu3.l1c.protocol.snoop_read_owned 7221 # read snoops on owned blocks +system.cpu3.l1c.protocol.snoop_read_shared 1743434 # read snoops on shared blocks +system.cpu3.l1c.protocol.snoop_readex_exclusive 1553 # readEx snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_readex_modified 6822 # readEx snoops on modified blocks +system.cpu3.l1c.protocol.snoop_readex_owned 3914 # readEx snoops on owned blocks +system.cpu3.l1c.protocol.snoop_readex_shared 12477 # readEx snoops on shared blocks +system.cpu3.l1c.protocol.snoop_upgrade_owned 867 # upgrade snoops on owned blocks +system.cpu3.l1c.protocol.snoop_upgrade_shared 3008 # upgradee snoops on shared blocks system.cpu3.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu3.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu3.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu3.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu3.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu3.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu3.l1c.protocol.write_invalid 59061 # write misses to invalid blocks -system.cpu3.l1c.protocol.write_owned 1261 # write misses to owned blocks -system.cpu3.l1c.protocol.write_shared 4235 # write misses to shared blocks -system.cpu3.l1c.replacements 27216 # number of replacements -system.cpu3.l1c.sampled_refs 27556 # Sample count of references to valid blocks. +system.cpu3.l1c.protocol.write_invalid 1046634 # write misses to invalid blocks +system.cpu3.l1c.protocol.write_owned 1364 # write misses to owned blocks +system.cpu3.l1c.protocol.write_shared 4484 # write misses to shared blocks +system.cpu3.l1c.replacements 27286 # number of replacements +system.cpu3.l1c.sampled_refs 27624 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 341.602377 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11339 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 342.290575 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11363 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10831 # number of writebacks +system.cpu3.l1c.writebacks 10681 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98893 # number of read accesses completed -system.cpu3.num_writes 53654 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44272 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 976.655364 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 901.292278 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_hits 7468 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 35944824 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.831316 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 36804 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 33171161 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831316 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 36804 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable 9822 # number of ReadReq MSHR uncacheable +system.cpu3.num_reads 99322 # number of read accesses completed +system.cpu3.num_writes 53280 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 13943.186039 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 12937.718615 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7581 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 521335726 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.831425 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37390 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 483741299 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831425 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable 9931 # number of ReadReq MSHR uncacheable system.cpu4.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 17532387 # number of ReadResp MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 23994 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 874.063859 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 788.017488 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_hits 1178 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 19942641 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.950904 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 22816 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 17979407 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.950904 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 22816 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable 5315 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 254015216 # number of ReadResp MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24134 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 12764.573629 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 11273.971841 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_hits 1086 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 294197893 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.955001 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23048 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 259842503 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.955001 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23048 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable 5390 # number of WriteReq MSHR uncacheable system.cpu4.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 10563676 # number of WriteResp MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 82.703233 # average number of cycles each access was blocked +system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 161643344 # number of WriteResp MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1186.636056 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.416368 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 68707 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.410931 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69637 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 5682291 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 82633775 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68266 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 937.394582 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8646 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 55887465 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.873348 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 59620 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 69105 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 13493.722807 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8667 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 815533619 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.874582 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60438 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 51150568 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.873348 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 59620 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 743583802 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.874582 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60438 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68266 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 937.394582 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 69105 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 13493.722807 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8646 # number of overall hits -system.cpu4.l1c.overall_miss_latency 55887465 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.873348 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 59620 # number of overall misses +system.cpu4.l1c.overall_hits 8667 # number of overall hits +system.cpu4.l1c.overall_miss_latency 815533619 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.874582 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60438 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 51150568 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.873348 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 59620 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_miss_latency 743583802 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.874582 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60438 # number of overall MSHR misses system.cpu4.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_misses 15137 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses 15321 # number of overall MSHR uncacheable misses system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -506,103 +506,103 @@ system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu4.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu4.l1c.protocol.read_invalid 113154 # read misses to invalid blocks +system.cpu4.l1c.protocol.read_invalid 1830675 # read misses to invalid blocks system.cpu4.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu4.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu4.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu4.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu4.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu4.l1c.protocol.snoop_read_exclusive 2804 # read snoops on exclusive blocks -system.cpu4.l1c.protocol.snoop_read_modified 12453 # read snoops on modified blocks -system.cpu4.l1c.protocol.snoop_read_owned 7418 # read snoops on owned blocks -system.cpu4.l1c.protocol.snoop_read_shared 23136 # read snoops on shared blocks -system.cpu4.l1c.protocol.snoop_readex_exclusive 1528 # readEx snoops on exclusive blocks -system.cpu4.l1c.protocol.snoop_readex_modified 6607 # readEx snoops on modified blocks -system.cpu4.l1c.protocol.snoop_readex_owned 3922 # readEx snoops on owned blocks -system.cpu4.l1c.protocol.snoop_readex_shared 12524 # readEx snoops on shared blocks -system.cpu4.l1c.protocol.snoop_upgrade_owned 843 # upgrade snoops on owned blocks -system.cpu4.l1c.protocol.snoop_upgrade_shared 2904 # upgradee snoops on shared blocks +system.cpu4.l1c.protocol.snoop_read_exclusive 2847 # read snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_read_modified 12499 # read snoops on modified blocks +system.cpu4.l1c.protocol.snoop_read_owned 7458 # read snoops on owned blocks +system.cpu4.l1c.protocol.snoop_read_shared 1765770 # read snoops on shared blocks +system.cpu4.l1c.protocol.snoop_readex_exclusive 1560 # readEx snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_readex_modified 6711 # readEx snoops on modified blocks +system.cpu4.l1c.protocol.snoop_readex_owned 3919 # readEx snoops on owned blocks +system.cpu4.l1c.protocol.snoop_readex_shared 12526 # readEx snoops on shared blocks +system.cpu4.l1c.protocol.snoop_upgrade_owned 902 # upgrade snoops on owned blocks +system.cpu4.l1c.protocol.snoop_upgrade_shared 3023 # upgradee snoops on shared blocks system.cpu4.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu4.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu4.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu4.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu4.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu4.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu4.l1c.protocol.write_invalid 59622 # write misses to invalid blocks -system.cpu4.l1c.protocol.write_owned 1265 # write misses to owned blocks -system.cpu4.l1c.protocol.write_shared 4187 # write misses to shared blocks -system.cpu4.l1c.replacements 27000 # number of replacements -system.cpu4.l1c.sampled_refs 27346 # Sample count of references to valid blocks. +system.cpu4.l1c.protocol.write_invalid 854606 # write misses to invalid blocks +system.cpu4.l1c.protocol.write_owned 1318 # write misses to owned blocks +system.cpu4.l1c.protocol.write_shared 4519 # write misses to shared blocks +system.cpu4.l1c.replacements 27664 # number of replacements +system.cpu4.l1c.sampled_refs 28012 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 342.121323 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11386 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 344.185288 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11511 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10847 # number of writebacks +system.cpu4.l1c.writebacks 10935 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98882 # number of read accesses completed -system.cpu4.num_writes 53288 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44218 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 975.652027 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 898.818359 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_hits 7310 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 36009365 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.834683 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 36908 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 33173588 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.834683 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 36908 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable 9866 # number of ReadReq MSHR uncacheable +system.cpu4.num_reads 99841 # number of read accesses completed +system.cpu4.num_writes 54005 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 45075 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 13980.675167 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 12974.186518 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7588 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 524093570 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.831658 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37487 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 486363330 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831658 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable 9769 # number of ReadReq MSHR uncacheable system.cpu5.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 17625443 # number of ReadResp MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 23923 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 873.308611 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 788.173188 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_hits 1150 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 19887857 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.951929 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 22773 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 17949068 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.951929 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 22773 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable 5207 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 252483534 # number of ReadResp MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24120 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 12733.111936 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 11249.826210 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_hits 1098 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 293141703 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.954478 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23022 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 258993499 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.954478 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23022 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable 5232 # number of WriteReq MSHR uncacheable system.cpu5.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 10374807 # number of WriteResp MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 82.590363 # average number of cycles each access was blocked +system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 155064988 # number of WriteResp MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1188.349008 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.413664 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 68944 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.414917 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 5694110 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 82634225 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 68141 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 936.599956 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8460 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 55897222 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.875846 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 59681 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 69195 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 13506.011883 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8686 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 817235273 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.874471 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60509 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 51122656 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.875846 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 59681 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 745356829 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.874471 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60509 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 68141 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 936.599956 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 69195 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 13506.011883 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8460 # number of overall hits -system.cpu5.l1c.overall_miss_latency 55897222 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.875846 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 59681 # number of overall misses +system.cpu5.l1c.overall_hits 8686 # number of overall hits +system.cpu5.l1c.overall_miss_latency 817235273 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.874471 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60509 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 51122656 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.875846 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 59681 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_miss_latency 745356829 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.874471 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60509 # number of overall MSHR misses system.cpu5.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_misses 15073 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses 15001 # number of overall MSHR uncacheable misses system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -613,103 +613,103 @@ system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu5.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu5.l1c.protocol.read_invalid 114279 # read misses to invalid blocks +system.cpu5.l1c.protocol.read_invalid 1718821 # read misses to invalid blocks system.cpu5.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu5.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu5.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu5.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu5.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu5.l1c.protocol.snoop_read_exclusive 2860 # read snoops on exclusive blocks -system.cpu5.l1c.protocol.snoop_read_modified 12253 # read snoops on modified blocks -system.cpu5.l1c.protocol.snoop_read_owned 7231 # read snoops on owned blocks -system.cpu5.l1c.protocol.snoop_read_shared 23182 # read snoops on shared blocks -system.cpu5.l1c.protocol.snoop_readex_exclusive 1499 # readEx snoops on exclusive blocks -system.cpu5.l1c.protocol.snoop_readex_modified 6757 # readEx snoops on modified blocks -system.cpu5.l1c.protocol.snoop_readex_owned 3896 # readEx snoops on owned blocks -system.cpu5.l1c.protocol.snoop_readex_shared 12461 # readEx snoops on shared blocks -system.cpu5.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks -system.cpu5.l1c.protocol.snoop_upgrade_shared 3020 # upgradee snoops on shared blocks +system.cpu5.l1c.protocol.snoop_read_exclusive 2926 # read snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_read_modified 12465 # read snoops on modified blocks +system.cpu5.l1c.protocol.snoop_read_owned 7201 # read snoops on owned blocks +system.cpu5.l1c.protocol.snoop_read_shared 1810557 # read snoops on shared blocks +system.cpu5.l1c.protocol.snoop_readex_exclusive 1622 # readEx snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_readex_modified 6690 # readEx snoops on modified blocks +system.cpu5.l1c.protocol.snoop_readex_owned 3947 # readEx snoops on owned blocks +system.cpu5.l1c.protocol.snoop_readex_shared 12574 # readEx snoops on shared blocks +system.cpu5.l1c.protocol.snoop_upgrade_owned 818 # upgrade snoops on owned blocks +system.cpu5.l1c.protocol.snoop_upgrade_shared 3092 # upgradee snoops on shared blocks system.cpu5.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu5.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu5.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu5.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu5.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu5.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu5.l1c.protocol.write_invalid 60969 # write misses to invalid blocks -system.cpu5.l1c.protocol.write_owned 1349 # write misses to owned blocks -system.cpu5.l1c.protocol.write_shared 4191 # write misses to shared blocks -system.cpu5.l1c.replacements 26828 # number of replacements -system.cpu5.l1c.sampled_refs 27196 # Sample count of references to valid blocks. +system.cpu5.l1c.protocol.write_invalid 914561 # write misses to invalid blocks +system.cpu5.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu5.l1c.protocol.write_shared 4534 # write misses to shared blocks +system.cpu5.l1c.replacements 27551 # number of replacements +system.cpu5.l1c.sampled_refs 27914 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 340.865502 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11250 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 344.440637 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11582 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10567 # number of writebacks +system.cpu5.l1c.writebacks 10931 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97882 # number of read accesses completed -system.cpu5.num_writes 52965 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 967.006541 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 890.563660 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_hits 7514 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 36221164 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.832915 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37457 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 33357843 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37457 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable 9684 # number of ReadReq MSHR uncacheable +system.cpu5.num_reads 99674 # number of read accesses completed +system.cpu5.num_writes 53393 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44595 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 14001.082353 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 12995.526917 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7462 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 519902191 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.832672 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37133 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 482562901 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832672 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37133 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable system.cpu6.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 17275344 # number of ReadResp MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 23996 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 873.777515 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 790.631514 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_hits 1181 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 19935234 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.950783 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 22815 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 18038258 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.950783 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 22815 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable 5345 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 251671127 # number of ReadResp MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24364 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 12854.640783 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 11385.598176 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_hits 1222 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 297482097 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.949844 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23142 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 263485513 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.949844 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23142 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable 5447 # number of WriteReq MSHR uncacheable system.cpu6.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 10602140 # number of WriteResp MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 82.071085 # average number of cycles each access was blocked +system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 163399316 # number of WriteResp MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1189.328084 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.412251 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69157 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.411043 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69345 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 5675790 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 82473956 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 68967 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 931.716187 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8695 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 56156398 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.873925 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60272 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68959 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 13560.917263 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8684 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 817384288 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.874070 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60275 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 51396101 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.873925 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60272 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 746048414 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.874070 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60275 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 68967 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 931.716187 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 68959 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 13560.917263 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8695 # number of overall hits -system.cpu6.l1c.overall_miss_latency 56156398 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.873925 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60272 # number of overall misses +system.cpu6.l1c.overall_hits 8684 # number of overall hits +system.cpu6.l1c.overall_miss_latency 817384288 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.874070 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60275 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 51396101 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.873925 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60272 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_miss_latency 746048414 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.874070 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60275 # number of overall MSHR misses system.cpu6.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_misses 15029 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses 15267 # number of overall MSHR uncacheable misses system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -720,103 +720,103 @@ system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu6.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu6.l1c.protocol.read_invalid 114488 # read misses to invalid blocks +system.cpu6.l1c.protocol.read_invalid 1894590 # read misses to invalid blocks system.cpu6.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu6.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu6.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu6.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu6.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu6.l1c.protocol.snoop_read_exclusive 2876 # read snoops on exclusive blocks -system.cpu6.l1c.protocol.snoop_read_modified 12371 # read snoops on modified blocks -system.cpu6.l1c.protocol.snoop_read_owned 7223 # read snoops on owned blocks -system.cpu6.l1c.protocol.snoop_read_shared 23305 # read snoops on shared blocks -system.cpu6.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks -system.cpu6.l1c.protocol.snoop_readex_modified 6693 # readEx snoops on modified blocks -system.cpu6.l1c.protocol.snoop_readex_owned 3909 # readEx snoops on owned blocks -system.cpu6.l1c.protocol.snoop_readex_shared 12446 # readEx snoops on shared blocks -system.cpu6.l1c.protocol.snoop_upgrade_owned 833 # upgrade snoops on owned blocks -system.cpu6.l1c.protocol.snoop_upgrade_shared 2948 # upgradee snoops on shared blocks +system.cpu6.l1c.protocol.snoop_read_exclusive 2887 # read snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_read_modified 12551 # read snoops on modified blocks +system.cpu6.l1c.protocol.snoop_read_owned 7188 # read snoops on owned blocks +system.cpu6.l1c.protocol.snoop_read_shared 1703425 # read snoops on shared blocks +system.cpu6.l1c.protocol.snoop_readex_exclusive 1550 # readEx snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_readex_modified 6733 # readEx snoops on modified blocks +system.cpu6.l1c.protocol.snoop_readex_owned 3926 # readEx snoops on owned blocks +system.cpu6.l1c.protocol.snoop_readex_shared 12456 # readEx snoops on shared blocks +system.cpu6.l1c.protocol.snoop_upgrade_owned 800 # upgrade snoops on owned blocks +system.cpu6.l1c.protocol.snoop_upgrade_shared 3156 # upgradee snoops on shared blocks system.cpu6.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu6.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu6.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu6.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu6.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu6.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu6.l1c.protocol.write_invalid 58413 # write misses to invalid blocks -system.cpu6.l1c.protocol.write_owned 1374 # write misses to owned blocks -system.cpu6.l1c.protocol.write_shared 4109 # write misses to shared blocks -system.cpu6.l1c.replacements 27477 # number of replacements -system.cpu6.l1c.sampled_refs 27835 # Sample count of references to valid blocks. +system.cpu6.l1c.protocol.write_invalid 987928 # write misses to invalid blocks +system.cpu6.l1c.protocol.write_owned 1405 # write misses to owned blocks +system.cpu6.l1c.protocol.write_shared 4406 # write misses to shared blocks +system.cpu6.l1c.replacements 27613 # number of replacements +system.cpu6.l1c.sampled_refs 27946 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 342.134742 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11475 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 344.860122 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11487 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 10759 # number of writebacks +system.cpu6.l1c.writebacks 11073 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99303 # number of read accesses completed -system.cpu6.num_writes 53385 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44438 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 975.306986 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 899.340271 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_hits 7394 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 36129272 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.833611 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37044 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 33315161 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833611 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37044 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable +system.cpu6.num_reads 98723 # number of read accesses completed +system.cpu6.num_writes 53876 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44990 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 13952.283047 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 12937.789329 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7505 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 523001330 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.833185 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37485 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 484973033 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833185 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37485 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable 10001 # number of ReadReq MSHR uncacheable system.cpu7.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 17576395 # number of ReadResp MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 23999 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 861.568979 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 776.580264 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_hits 1137 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 19697190 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.952623 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 22862 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 17754178 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.952623 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 22862 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable 5386 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 257188342 # number of ReadResp MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 12615.682417 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 11155.458639 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_hits 1163 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 289151441 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.951709 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 22920 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 255683112 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.951709 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 22920 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable 5323 # number of WriteReq MSHR uncacheable system.cpu7.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 10720857 # number of WriteResp MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 82.167211 # average number of cycles each access was blocked +system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 159397105 # number of WriteResp MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1185.864523 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.419292 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 68907 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.413879 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69665 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 5661896 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 82613252 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 68437 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 931.901012 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8531 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 55826462 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.875345 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 59906 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 69073 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 13445.124923 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8668 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 812152771 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.874510 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60405 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 51069339 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.875345 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 59906 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 740656145 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.874510 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60405 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 68437 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 931.901012 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 69073 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 13445.124923 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8531 # number of overall hits -system.cpu7.l1c.overall_miss_latency 55826462 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.875345 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 59906 # number of overall misses +system.cpu7.l1c.overall_hits 8668 # number of overall hits +system.cpu7.l1c.overall_miss_latency 812152771 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.874510 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60405 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 51069339 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.875345 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 59906 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_miss_latency 740656145 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.874510 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60405 # number of overall MSHR misses system.cpu7.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_misses 15247 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses 15324 # number of overall MSHR uncacheable misses system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -827,111 +827,111 @@ system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu7.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu7.l1c.protocol.read_invalid 115064 # read misses to invalid blocks +system.cpu7.l1c.protocol.read_invalid 1929884 # read misses to invalid blocks system.cpu7.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu7.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu7.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu7.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu7.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu7.l1c.protocol.snoop_read_exclusive 2793 # read snoops on exclusive blocks -system.cpu7.l1c.protocol.snoop_read_modified 12588 # read snoops on modified blocks -system.cpu7.l1c.protocol.snoop_read_owned 7412 # read snoops on owned blocks -system.cpu7.l1c.protocol.snoop_read_shared 23048 # read snoops on shared blocks -system.cpu7.l1c.protocol.snoop_readex_exclusive 1548 # readEx snoops on exclusive blocks -system.cpu7.l1c.protocol.snoop_readex_modified 6593 # readEx snoops on modified blocks -system.cpu7.l1c.protocol.snoop_readex_owned 3944 # readEx snoops on owned blocks -system.cpu7.l1c.protocol.snoop_readex_shared 12404 # readEx snoops on shared blocks -system.cpu7.l1c.protocol.snoop_upgrade_owned 919 # upgrade snoops on owned blocks -system.cpu7.l1c.protocol.snoop_upgrade_shared 2959 # upgradee snoops on shared blocks +system.cpu7.l1c.protocol.snoop_read_exclusive 2904 # read snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_read_modified 12387 # read snoops on modified blocks +system.cpu7.l1c.protocol.snoop_read_owned 7174 # read snoops on owned blocks +system.cpu7.l1c.protocol.snoop_read_shared 1782059 # read snoops on shared blocks +system.cpu7.l1c.protocol.snoop_readex_exclusive 1587 # readEx snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_readex_modified 6687 # readEx snoops on modified blocks +system.cpu7.l1c.protocol.snoop_readex_owned 3842 # readEx snoops on owned blocks +system.cpu7.l1c.protocol.snoop_readex_shared 12759 # readEx snoops on shared blocks +system.cpu7.l1c.protocol.snoop_upgrade_owned 792 # upgrade snoops on owned blocks +system.cpu7.l1c.protocol.snoop_upgrade_shared 3085 # upgradee snoops on shared blocks system.cpu7.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu7.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu7.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu7.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu7.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu7.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu7.l1c.protocol.write_invalid 58173 # write misses to invalid blocks -system.cpu7.l1c.protocol.write_owned 1351 # write misses to owned blocks -system.cpu7.l1c.protocol.write_shared 4494 # write misses to shared blocks -system.cpu7.l1c.replacements 27080 # number of replacements -system.cpu7.l1c.sampled_refs 27420 # Sample count of references to valid blocks. +system.cpu7.l1c.protocol.write_invalid 930930 # write misses to invalid blocks +system.cpu7.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu7.l1c.protocol.write_shared 4465 # write misses to shared blocks +system.cpu7.l1c.replacements 27486 # number of replacements +system.cpu7.l1c.sampled_refs 27827 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 342.061742 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11497 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 344.310963 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11517 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10789 # number of writebacks +system.cpu7.l1c.writebacks 10979 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98350 # number of read accesses completed -system.cpu7.num_writes 53282 # number of write accesses completed -system.l2c.ReadExReq_accesses 75399 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 89.483714 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 6.467886 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits 39632 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 3200564 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 0.474370 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 35767 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 231311 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.474317 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 35763 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 138997 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 89.683271 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 6.196645 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 72568 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 5957570 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.477917 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 66429 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 411544 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.477809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 66414 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable +system.cpu7.num_reads 99734 # number of read accesses completed +system.cpu7.num_writes 53652 # number of write accesses completed +system.l2c.ReadExReq_accesses 75160 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 10115.633652 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 6085.503709 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 39620 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 359509620 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.472858 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 35540 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 220 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 214939991 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.469931 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 35320 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 138762 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 10150.344064 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 6129.500996 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 72597 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 671597515 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.476824 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 66165 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 403069856 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.473898 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 65759 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 78927 # number of ReadReq MSHR uncacheable system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable +system.l2c.ReadResp_mshr_uncacheable_latency 484683934 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 42802 # number of WriteReq MSHR uncacheable system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles -system.l2c.Writeback_accesses 86614 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 18299 # number of Writeback hits -system.l2c.Writeback_miss_rate 0.788729 # miss rate for Writeback accesses -system.l2c.Writeback_misses 68315 # number of Writeback misses -system.l2c.Writeback_mshr_miss_rate 0.788729 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 68315 # number of Writeback MSHR misses -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.WriteResp_mshr_uncacheable_latency 248118294 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 86706 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 18948 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.781468 # miss rate for Writeback accesses +system.l2c.Writeback_misses 67758 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.781468 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 67758 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs 3278 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.277186 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.avg_refs 1.297661 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 3 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 9834 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 138997 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 89.683271 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency -system.l2c.demand_hits 72568 # number of demand (read+write) hits -system.l2c.demand_miss_latency 5957570 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.477917 # miss rate for demand accesses -system.l2c.demand_misses 66429 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 411544 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.477809 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 66414 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 138762 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 10150.344064 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency +system.l2c.demand_hits 72597 # number of demand (read+write) hits +system.l2c.demand_miss_latency 671597515 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.476824 # miss rate for demand accesses +system.l2c.demand_misses 66165 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 406 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 403069856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.473898 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 65759 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 225611 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 44.213991 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency +system.l2c.overall_accesses 225468 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 5014.803394 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.l2c.overall_hits 90867 # number of overall hits -system.l2c.overall_miss_latency 5957570 # number of overall miss cycles -system.l2c.overall_miss_rate 0.597240 # miss rate for overall accesses -system.l2c.overall_misses 134744 # number of overall misses -system.l2c.overall_mshr_hits 15 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 411544 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.294374 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 66414 # number of overall MSHR misses +system.l2c.overall_hits 91545 # number of overall hits +system.l2c.overall_miss_latency 671597515 # number of overall miss cycles +system.l2c.overall_miss_rate 0.593978 # miss rate for overall accesses +system.l2c.overall_misses 133923 # number of overall misses +system.l2c.overall_mshr_hits 406 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 403069856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.291656 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 65759 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 121364 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses 121729 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -941,12 +941,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 101153 # number of replacements -system.l2c.sampled_refs 102177 # Sample count of references to valid blocks. +system.l2c.replacements 100054 # number of replacements +system.l2c.sampled_refs 101078 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1022.647312 # Cycle average of tags in use -system.l2c.total_refs 130499 # Total number of references to valid blocks. -system.l2c.warmup_cycle 31838 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 15786 # number of writebacks +system.l2c.tagsinuse 1023.099242 # Cycle average of tags in use +system.l2c.total_refs 131165 # Total number of references to valid blocks. +system.l2c.warmup_cycle 296156 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 16243 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index 16580296b..d45294bbb 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,74 +1,74 @@ warn: Entering event queue @ 0. Starting simulation... -system.cpu2: completed 10000 read accesses @573559 -system.cpu1: completed 10000 read accesses @574452 -system.cpu4: completed 10000 read accesses @578704 -system.cpu6: completed 10000 read accesses @579414 -system.cpu0: completed 10000 read accesses @588706 -system.cpu5: completed 10000 read accesses @590846 -system.cpu7: completed 10000 read accesses @592958 -system.cpu3: completed 10000 read accesses @604807 -system.cpu2: completed 20000 read accesses @1142209 -system.cpu1: completed 20000 read accesses @1143294 -system.cpu6: completed 20000 read accesses @1150506 -system.cpu4: completed 20000 read accesses @1152288 -system.cpu0: completed 20000 read accesses @1160537 -system.cpu3: completed 20000 read accesses @1175338 -system.cpu5: completed 20000 read accesses @1175648 -system.cpu7: completed 20000 read accesses @1180960 -system.cpu6: completed 30000 read accesses @1716218 -system.cpu3: completed 30000 read accesses @1728281 -system.cpu1: completed 30000 read accesses @1735983 -system.cpu0: completed 30000 read accesses @1736422 -system.cpu2: completed 30000 read accesses @1739692 -system.cpu4: completed 30000 read accesses @1746362 -system.cpu5: completed 30000 read accesses @1766199 -system.cpu7: completed 30000 read accesses @1783424 -system.cpu6: completed 40000 read accesses @2281651 -system.cpu0: completed 40000 read accesses @2300760 -system.cpu3: completed 40000 read accesses @2312993 -system.cpu2: completed 40000 read accesses @2314026 -system.cpu4: completed 40000 read accesses @2332178 -system.cpu1: completed 40000 read accesses @2336380 -system.cpu5: completed 40000 read accesses @2349370 -system.cpu7: completed 40000 read accesses @2365352 -system.cpu6: completed 50000 read accesses @2863317 -system.cpu0: completed 50000 read accesses @2878182 -system.cpu2: completed 50000 read accesses @2884989 -system.cpu3: completed 50000 read accesses @2897940 -system.cpu4: completed 50000 read accesses @2918842 -system.cpu1: completed 50000 read accesses @2929102 -system.cpu5: completed 50000 read accesses @2938269 -system.cpu7: completed 50000 read accesses @2944872 -system.cpu6: completed 60000 read accesses @3435715 -system.cpu2: completed 60000 read accesses @3454809 -system.cpu0: completed 60000 read accesses @3462986 -system.cpu3: completed 60000 read accesses @3485243 -system.cpu4: completed 60000 read accesses @3498361 -system.cpu1: completed 60000 read accesses @3501000 -system.cpu5: completed 60000 read accesses @3516984 -system.cpu7: completed 60000 read accesses @3517323 -system.cpu6: completed 70000 read accesses @4032530 -system.cpu0: completed 70000 read accesses @4041457 -system.cpu2: completed 70000 read accesses @4043695 -system.cpu7: completed 70000 read accesses @4070977 -system.cpu1: completed 70000 read accesses @4075964 -system.cpu4: completed 70000 read accesses @4076518 -system.cpu3: completed 70000 read accesses @4082470 -system.cpu5: completed 70000 read accesses @4104778 -system.cpu0: completed 80000 read accesses @4610101 -system.cpu2: completed 80000 read accesses @4622528 -system.cpu6: completed 80000 read accesses @4627690 -system.cpu1: completed 80000 read accesses @4654033 -system.cpu4: completed 80000 read accesses @4661016 -system.cpu3: completed 80000 read accesses @4662752 -system.cpu7: completed 80000 read accesses @4668924 -system.cpu5: completed 80000 read accesses @4689767 -system.cpu2: completed 90000 read accesses @5186824 -system.cpu0: completed 90000 read accesses @5189006 -system.cpu6: completed 90000 read accesses @5214829 -system.cpu1: completed 90000 read accesses @5229787 -system.cpu3: completed 90000 read accesses @5235400 -system.cpu4: completed 90000 read accesses @5240445 -system.cpu7: completed 90000 read accesses @5254426 -system.cpu5: completed 90000 read accesses @5292462 -system.cpu2: completed 100000 read accesses @5755736 +system.cpu7: completed 10000 read accesses @8253930 +system.cpu1: completed 10000 read accesses @8325085 +system.cpu6: completed 10000 read accesses @8427313 +system.cpu4: completed 10000 read accesses @8438233 +system.cpu2: completed 10000 read accesses @8458126 +system.cpu5: completed 10000 read accesses @8549800 +system.cpu3: completed 10000 read accesses @8559995 +system.cpu0: completed 10000 read accesses @8593654 +system.cpu7: completed 20000 read accesses @16744182 +system.cpu1: completed 20000 read accesses @16774744 +system.cpu4: completed 20000 read accesses @16786220 +system.cpu3: completed 20000 read accesses @16787358 +system.cpu5: completed 20000 read accesses @16795808 +system.cpu6: completed 20000 read accesses @16836913 +system.cpu2: completed 20000 read accesses @17031052 +system.cpu0: completed 20000 read accesses @17126654 +system.cpu5: completed 30000 read accesses @24892576 +system.cpu6: completed 30000 read accesses @24903300 +system.cpu3: completed 30000 read accesses @24935860 +system.cpu4: completed 30000 read accesses @25020642 +system.cpu1: completed 30000 read accesses @25031726 +system.cpu7: completed 30000 read accesses @25112091 +system.cpu2: completed 30000 read accesses @25235960 +system.cpu0: completed 30000 read accesses @25505209 +system.cpu5: completed 40000 read accesses @33191203 +system.cpu6: completed 40000 read accesses @33273684 +system.cpu4: completed 40000 read accesses @33345526 +system.cpu3: completed 40000 read accesses @33406412 +system.cpu7: completed 40000 read accesses @33509130 +system.cpu1: completed 40000 read accesses @33509218 +system.cpu2: completed 40000 read accesses @33664822 +system.cpu0: completed 40000 read accesses @33869626 +system.cpu5: completed 50000 read accesses @41488848 +system.cpu4: completed 50000 read accesses @41582702 +system.cpu7: completed 50000 read accesses @41828988 +system.cpu3: completed 50000 read accesses @41829496 +system.cpu1: completed 50000 read accesses @41849534 +system.cpu6: completed 50000 read accesses @41982608 +system.cpu2: completed 50000 read accesses @42197798 +system.cpu0: completed 50000 read accesses @42443468 +system.cpu5: completed 60000 read accesses @49751344 +system.cpu4: completed 60000 read accesses @49783100 +system.cpu1: completed 60000 read accesses @49918062 +system.cpu7: completed 60000 read accesses @49929008 +system.cpu3: completed 60000 read accesses @50173996 +system.cpu6: completed 60000 read accesses @50351766 +system.cpu2: completed 60000 read accesses @50352657 +system.cpu0: completed 60000 read accesses @50789771 +system.cpu4: completed 70000 read accesses @58352386 +system.cpu5: completed 70000 read accesses @58394758 +system.cpu7: completed 70000 read accesses @58570698 +system.cpu1: completed 70000 read accesses @58764169 +system.cpu3: completed 70000 read accesses @58764648 +system.cpu2: completed 70000 read accesses @58921714 +system.cpu6: completed 70000 read accesses @58929984 +system.cpu0: completed 70000 read accesses @59567320 +system.cpu1: completed 80000 read accesses @67092786 +system.cpu5: completed 80000 read accesses @67153667 +system.cpu4: completed 80000 read accesses @67153760 +system.cpu7: completed 80000 read accesses @67207042 +system.cpu3: completed 80000 read accesses @67238507 +system.cpu2: completed 80000 read accesses @67633112 +system.cpu6: completed 80000 read accesses @67664637 +system.cpu0: completed 80000 read accesses @68437288 +system.cpu1: completed 90000 read accesses @75679048 +system.cpu4: completed 90000 read accesses @75680280 +system.cpu7: completed 90000 read accesses @75751053 +system.cpu5: completed 90000 read accesses @75781514 +system.cpu3: completed 90000 read accesses @75844118 +system.cpu2: completed 90000 read accesses @76346671 +system.cpu6: completed 90000 read accesses @76491728 +system.cpu0: completed 90000 read accesses @77376872 +system.cpu1: completed 100000 read accesses @84350509 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index ea4812a6d..fb8e47d20 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:15 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:46 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional @@ -16,4 +16,4 @@ warning: overwriting port funcmem.functional value cpu4.functional with cpu5.fun warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5755736 because Maximum number of loads reached! +Exiting @ tick 84350509 because Maximum number of loads reached! diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index a14d4767e..57b643510 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,16 +14,21 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/tmp/newmem/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 [drivesys.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=drivesys.iobus.port[0] side_b=drivesys.membus.port[0] @@ -106,6 +111,7 @@ sys=drivesys [drivesys.iobus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=true @@ -116,6 +122,7 @@ port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pi [drivesys.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=1000 responder_set=false @@ -212,6 +219,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 @@ -584,6 +593,8 @@ children=configdata config_latency=20000 configdata=drivesys.tsunami.ide.configdata disks=drivesys.disk0 drivesys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 @@ -693,16 +704,21 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 [testsys.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=testsys.iobus.port[0] side_b=testsys.membus.port[0] @@ -785,6 +801,7 @@ sys=testsys [testsys.iobus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=true @@ -795,6 +812,7 @@ port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio t [testsys.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=1000 responder_set=false @@ -891,6 +909,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:02 intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 @@ -1263,6 +1283,8 @@ children=configdata config_latency=20000 configdata=testsys.tsunami.ide.configdata disks=testsys.disk0 testsys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index f9fd380da..613664aec 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -18,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS symbolfile= init_param=0 system_type=34 @@ -30,6 +30,7 @@ bus_id=1 clock=1000 width=64 responder_set=false +block_size=64 [testsys.intrctrl] type=IntrControl @@ -57,10 +58,15 @@ system=testsys [testsys.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [testsys.disk0.image.child] type=RawDiskImage @@ -479,6 +485,8 @@ BAR5Size=0 type=NSGigE system=testsys platform=testsys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=testsys.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -601,6 +609,8 @@ BAR5Size=0 type=IdeController system=testsys platform=testsys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=testsys.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -615,6 +625,7 @@ bus_id=0 clock=1000 width=64 responder_set=true +block_size=64 [drivesys.physmem] type=PhysicalMemory @@ -632,7 +643,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/tmp/newmem/configs/boot/netperf-server.rcS symbolfile= init_param=0 system_type=34 @@ -686,6 +697,8 @@ BAR5Size=0 type=NSGigE system=drivesys platform=drivesys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=drivesys.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -736,6 +749,7 @@ bus_id=1 clock=1000 width=64 responder_set=false +block_size=64 [drivesys.membus.responder] type=IsaFake @@ -754,10 +768,15 @@ system=drivesys [drivesys.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [drivesys.disk0.image.child] type=RawDiskImage @@ -1229,6 +1248,8 @@ BAR5Size=0 type=IdeController system=drivesys platform=drivesys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=drivesys.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -1243,4 +1264,5 @@ bus_id=0 clock=1000 width=64 responder_set=true +block_size=64 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 8ef183435..1a834ab03 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -39,12 +39,11 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199572064520 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199571744808 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks 199572412849 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199572093137 100.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_used 0.618707 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl @@ -55,13 +54,13 @@ drivesys.cpu.kern.mode_good_idle 3 drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches -drivesys.cpu.kern.mode_switch_good 0.440882 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 106485080 98.57% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.16% 1.40% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 108485080 98.60% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed drivesys.cpu.kern.syscall 22 # number of syscalls executed drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed @@ -101,9 +100,9 @@ drivesys.tsunami.ethernet.coalescedTotal 1 # av drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU @@ -131,7 +130,7 @@ drivesys.tsunami.ethernet.totalRxOk 0 # to drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s) drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted @@ -140,35 +139,35 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 36787265 # Simulator instruction rate (inst/s) -host_mem_usage 407784 # Number of bytes of host memory used -host_seconds 7.46 # Real time elapsed on the host -host_tick_rate 26810828297 # Simulator tick rate (ticks/s) +host_inst_rate 36401739 # Simulator instruction rate (inst/s) +host_mem_usage 388436 # Number of bytes of host memory used +host_seconds 7.51 # Real time elapsed on the host +host_tick_rate 26633033203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 274411697 # Number of instructions simulated +sim_insts 273348482 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163325 # DTB hits +testsys.cpu.dtb.hits 1163322 # DTB hits testsys.cpu.dtb.misses 3815 # DTB misses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658458 # DTB read hits +testsys.cpu.dtb.read_hits 658456 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 504867 # DTB write hits +testsys.cpu.dtb.write_hits 504866 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249840 # ITB accesses +testsys.cpu.itb.accesses 1249851 # ITB accesses testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248343 # ITB hits +testsys.cpu.itb.hits 1248354 # ITB hits testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13124 # number of callpals executed +testsys.cpu.kern.callpal 13125 # number of callpals executed testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11076 84.40% 87.88% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11077 84.40% 87.89% # number of callpals executed testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed @@ -176,41 +175,40 @@ testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # nu testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19055 # number of hwrei instructions executed -testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12506 # number of times we switched to this ipl +testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed +testsys.cpu.kern.ipl_count 12507 # number of times we switched to this ipl testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl testsys.cpu.kern.ipl_count_21 184 1.47% 41.94% # number of times we switched to this ipl testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7056 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7057 56.42% 100.00% # number of times we switched to this ipl testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569922466 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569307215 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199570420798 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569805534 100.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 566595 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used 0.839517 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_ticks_31 566608 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716412 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.mode_good_kernel 654 -testsys.cpu.kern.mode_good_user 649 +testsys.cpu.kern.ipl_used_31 0.716310 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 655 +testsys.cpu.kern.mode_good_user 650 testsys.cpu.kern.mode_good_idle 5 -testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 0.614373 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 650 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 380 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 1.608612 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.595455 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1821131 2.16% 2.16% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 81402279 96.58% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_switch_good_idle 0.013158 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1822940 2.12% 2.12% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065616 1.24% 3.36% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 83000460 96.64% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed @@ -235,9 +233,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 3566068 # number of cpu cycles simulated -testsys.cpu.num_insts 3564502 # Number of instructions executed -testsys.cpu.num_refs 1173608 # Number of memory references +testsys.cpu.numCycles 3566060 # number of cpu cycles simulated +testsys.cpu.num_insts 3564494 # Number of instructions executed +testsys.cpu.num_refs 1173605 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -259,9 +257,9 @@ testsys.tsunami.ethernet.coalescedTotal 1 # av testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU @@ -289,7 +287,7 @@ testsys.tsunami.ethernet.totalRxOk 0 # to testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s) testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted @@ -383,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 80923531996 # Simulator instruction rate (inst/s) -host_mem_usage 407784 # Number of bytes of host memory used +host_inst_rate 79025291125 # Simulator instruction rate (inst/s) +host_mem_usage 388436 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 216582530 # Simulator tick rate (ticks/s) +host_tick_rate 211511841 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 274411697 # Number of instructions simulated +sim_insts 273348482 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index 8fb9590c3..045c1ddf7 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,6 +1,6 @@ Listening for testsys connection on port 3456 -Listening for drivesys connection on port 3457 -0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for drivesys connection on port 3458 +0: testsys.remote_gdb.listener: listening for remote gdb on port 7000 +0: drivesys.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 4fb87de69..4f93fd528 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,11 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 14:01:42 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:12:37 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second - 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 - 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 4300236342388 because checkpoint +Exiting @ tick 4300235844056 because checkpoint |