diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:30:58 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:30:58 -0700 |
| commit | 4fc69db8f89049a881a5f4aa68545840818b124c (patch) | |
| tree | 7388f5b2755f6f4937b7ce9b8ba889f0d48bc403 /tests/quick | |
| parent | dbad391a9b4e861fd3d660069ed448db85144e17 (diff) | |
| download | gem5-4fc69db8f89049a881a5f4aa68545840818b124c.tar.xz | |
stats: update stats for mmap changes
Diffstat (limited to 'tests/quick')
12 files changed, 421 insertions, 413 deletions
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 0946d7533..66af6c729 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -216,7 +216,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false @@ -251,6 +251,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout index 84e37158c..315146752 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:23 -gem5 executing on zizzer, pid 20742 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic +gem5 compiled Mar 14 2016 17:50:51 +gem5 started Mar 14 2016 18:07:36 +gem5 executing on phenom, pid 27152 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 48960011500 because target called exit() +Exiting @ tick 48960022500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index ecfc0b9ca..bcdad61b2 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.048960 # Number of seconds simulated -sim_ticks 48960011500 # Number of ticks simulated -final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 48960022500 # Number of ticks simulated +final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 622932 # Simulator instruction rate (inst/s) -host_op_rate 796644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 430085915 # Simulator tick rate (ticks/s) -host_mem_usage 246536 # Number of bytes of host memory used -host_seconds 113.84 # Real time elapsed on the host -sim_insts 70913182 # Number of instructions simulated -sim_ops 90688137 # Number of ops (including micro ops) simulated +host_inst_rate 991674 # Simulator instruction rate (inst/s) +host_op_rate 1268214 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 684673258 # Simulator tick rate (ticks/s) +host_mem_usage 242788 # Number of bytes of host memory used +host_seconds 71.51 # Real time elapsed on the host +sim_insts 70913204 # Number of instructions simulated +sim_ops 90688159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 312580276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153621 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580276 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory -system.physmem.num_reads::total 101064799 # Number of read requests responded to by this memory +system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6384399562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2176742646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8561142209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6384399562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6384399562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1606621579 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1606621579 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6384399562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3783364226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10167763788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,33 +153,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 97920024 # number of cpu cycles simulated +system.cpu.numCycles 97920046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913182 # Number of instructions committed -system.cpu.committedOps 90688137 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses +system.cpu.committedInsts 70913204 # Number of instructions committed +system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528488 # number of integer instructions +system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528528 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written +system.cpu.num_int_register_reads 141479386 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 266608031 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written system.cpu.num_mem_refs 43422001 # number of memory refs system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 97920023.998000 # Number of busy cycles +system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741486 # Number of branches fetched +system.cpu.Branches 13741468 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction @@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690084 # Class of executed instruction -system.membus.trans_dist::ReadReq 100925136 # Transaction distribution -system.membus.trans_dist::ReadResp 100941055 # Transaction distribution +system.cpu.op_class::total 90690106 # Class of executed instruction +system.membus.trans_dist::ReadReq 100925158 # Transaction distribution +system.membus.trans_dist::ReadResp 100941077 # Transaction distribution system.membus.trans_dist::WriteReq 19849901 # Transaction distribution system.membus.trans_dist::WriteResp 19849901 # Transaction distribution system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution @@ -222,22 +222,22 @@ system.membus.trans_dist::SoftPFResp 123744 # Tr system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861238 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580276 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930619 # Request fanout histogram +system.membus.snoop_fanout::samples 120930641 # Request fanout histogram system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::1 78145069 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 120930619 # Request fanout histogram +system.membus.snoop_fanout::total 120930641 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 5ef054f5d..e8b410808 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -90,7 +90,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -168,7 +167,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -281,7 +279,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -316,6 +313,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -346,7 +344,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false @@ -381,6 +379,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout index de3c6dccc..6b39172d0 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:19 -gem5 executing on zizzer, pid 20723 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing +gem5 compiled Mar 14 2016 17:50:51 +gem5 started Mar 14 2016 18:03:19 +gem5 executing on phenom, pid 27037 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 128076812500 because target called exit() +Exiting @ tick 128076834500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 7f5c6bd39..c10ef56cb 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.128077 # Number of seconds simulated -sim_ticks 128076812500 # Number of ticks simulated -final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 128076834500 # Number of ticks simulated +final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 887065 # Simulator instruction rate (inst/s) -host_op_rate 1132533 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1614418321 # Simulator tick rate (ticks/s) -host_mem_usage 277452 # Number of bytes of host memory used -host_seconds 79.33 # Real time elapsed on the host -sim_insts 70373629 # Number of instructions simulated -sim_ops 89847363 # Number of ops (including micro ops) simulated +host_inst_rate 508798 # Simulator instruction rate (inst/s) +host_op_rate 649592 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 925989388 # Simulator tick rate (ticks/s) +host_mem_usage 253236 # Number of bytes of host memory used +host_seconds 138.31 # Real time elapsed on the host +sim_insts 70373651 # Number of instructions simulated +sim_ops 89847385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123832 # Nu system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61878867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63699274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43049166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43049166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43049166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61878867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106748441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,33 +154,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 256153625 # number of cpu cycles simulated +system.cpu.numCycles 256153669 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373629 # Number of instructions committed -system.cpu.committedOps 89847363 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses +system.cpu.committedInsts 70373651 # Number of instructions committed +system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528488 # number of integer instructions +system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528528 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written +system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802006 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written system.cpu.num_mem_refs 43422001 # number of memory refs system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256153624.998000 # Number of busy cycles +system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741486 # Number of branches fetched +system.cpu.Branches 13741468 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction @@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690084 # Class of executed instruction +system.cpu.op_class::total 90690106 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.927151 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927151 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -352,12 +352,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.356647 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id @@ -366,14 +366,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 22 system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309048 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309048 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78126162 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126162 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126162 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126162 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126162 # number of overall hits -system.cpu.icache.overall_hits::total 78126162 # number of overall hits +system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits +system.cpu.icache.overall_hits::total 78126184 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses @@ -386,12 +386,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 426200500 system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145070 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145070 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145070 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses @@ -440,14 +440,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95333 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30336.891349 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605172 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258764 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027413 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index b68bc2a7d..20fc06e75 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -115,7 +115,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin kvmInSE=false @@ -150,6 +150,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 51bf0b517..98ece2f0d 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:30:54 -gem5 started Jan 21 2016 14:31:25 -gem5 executing on zizzer, pid 8713 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic +gem5 compiled Mar 14 2016 17:46:51 +gem5 started Mar 14 2016 17:54:20 +gem5 executing on phenom, pid 26843 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 68148672000 because target called exit() +Exiting @ tick 68148677000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index ba8d2e144..3ed030f96 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148672000 # Number of ticks simulated -final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 68148677000 # Number of ticks simulated +final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1099944 # Simulator instruction rate (inst/s) -host_op_rate 1114186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 557740246 # Simulator tick rate (ticks/s) -host_mem_usage 228968 # Number of bytes of host memory used -host_seconds 122.19 # Real time elapsed on the host -sim_insts 134398962 # Number of instructions simulated -sim_ops 136139190 # Number of ops (including micro ops) simulated +host_inst_rate 1843276 # Simulator instruction rate (inst/s) +host_op_rate 1867142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 934655607 # Simulator tick rate (ticks/s) +host_mem_usage 225200 # Number of bytes of host memory used +host_seconds 72.91 # Real time elapsed on the host +sim_insts 134398959 # Number of instructions simulated +sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory -system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory +system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory system.physmem.num_other::total 15916 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 136297345 # number of cpu cycles simulated +system.cpu.numCycles 136297355 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398962 # Number of instructions committed -system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.committedInsts 134398959 # Number of instructions committed +system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187746 # number of integer instructions -system.cpu.num_fp_insts 2326977 # number of float instructions -system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187757 # number of integer instructions +system.cpu.num_fp_insts 2326976 # number of float instructions +system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160248 # number of memory refs -system.cpu.num_load_insts 37275867 # Number of load instructions -system.cpu.num_store_insts 20884381 # Number of store instructions +system.cpu.num_mem_refs 58160261 # number of memory refs +system.cpu.num_load_insts 37275864 # Number of load instructions +system.cpu.num_store_insts 20884397 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 136297344.998000 # Number of busy cycles +system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719095 # Number of branches fetched +system.cpu.Branches 12719094 # Number of branches fetched system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction @@ -92,33 +92,33 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293798 # Class of executed instruction -system.membus.trans_dist::ReadReq 171784870 # Transaction distribution -system.membus.trans_dist::ReadResp 171784870 # Transaction distribution +system.cpu.op_class::total 136293808 # Class of executed instruction +system.membus.trans_dist::ReadReq 171784880 # Transaction distribution +system.membus.trans_dist::ReadResp 171784880 # Transaction distribution system.membus.trans_dist::WriteReq 20864304 # Transaction distribution system.membus.trans_dist::WriteResp 20864304 # Transaction distribution system.membus.trans_dist::SwapReq 15916 # Transaction distribution system.membus.trans_dist::SwapResp 15916 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 192665090 # Request fanout histogram +system.membus.snoop_fanout::samples 192665100 # Request fanout histogram system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram -system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 192665090 # Request fanout histogram +system.membus.snoop_fanout::total 192665100 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 4aa8d2f80..9da4061be 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -88,7 +88,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -130,7 +129,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -180,7 +178,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -215,6 +212,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -245,7 +243,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin kvmInSE=false @@ -280,6 +278,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout index a1ad3bacc..d24399f8c 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:30:54 -gem5 started Jan 21 2016 14:31:26 -gem5 executing on zizzer, pid 8734 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing +gem5 compiled Mar 14 2016 17:46:51 +gem5 started Mar 14 2016 17:55:53 +gem5 executing on phenom, pid 26906 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 203115876500 because target called exit() +Exiting @ tick 203115946500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index d6835fc82..75f9fb3c6 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,68 +1,68 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.203116 # Number of seconds simulated -sim_ticks 203115876500 # Number of ticks simulated -final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 203115946500 # Number of ticks simulated +final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130669 # Simulator instruction rate (inst/s) -host_op_rate 1145309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1708768878 # Simulator tick rate (ticks/s) -host_mem_usage 305928 # Number of bytes of host memory used -host_seconds 118.87 # Real time elapsed on the host -sim_insts 134398962 # Number of instructions simulated -sim_ops 136139190 # Number of ops (including micro ops) simulated +host_inst_rate 864116 # Simulator instruction rate (inst/s) +host_op_rate 875304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1305930078 # Simulator tick rate (ticks/s) +host_mem_usage 235576 # Number of bytes of host memory used +host_seconds 155.53 # Real time elapsed on the host +sim_insts 134398959 # Number of instructions simulated +sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7828288 # Number of bytes read from this memory -system.physmem.bytes_read::total 8353344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory +system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122317 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2585007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38540995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41126002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2585007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2585007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26867816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26867816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26867816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2585007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38540995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67993818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 406231753 # number of cpu cycles simulated +system.cpu.numCycles 406231893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398962 # Number of instructions committed -system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.committedInsts 134398959 # Number of instructions committed +system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187746 # number of integer instructions -system.cpu.num_fp_insts 2326977 # number of float instructions -system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187757 # number of integer instructions +system.cpu.num_fp_insts 2326976 # number of float instructions +system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160248 # number of memory refs -system.cpu.num_load_insts 37275867 # Number of load instructions -system.cpu.num_store_insts 20884381 # Number of store instructions +system.cpu.num_mem_refs 58160261 # number of memory refs +system.cpu.num_load_insts 37275864 # Number of load instructions +system.cpu.num_store_insts 20884397 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 406231752.998000 # Number of busy cycles +system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719095 # Number of branches fetched +system.cpu.Branches 12719094 # Number of branches fetched system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction @@ -91,18 +91,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293798 # Class of executed instruction -system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.268920 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.op_class::total 136293808 # Class of executed instruction +system.cpu.dcache.tags.replacements 146583 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -110,38 +110,38 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits -system.cpu.dcache.overall_hits::total 57944941 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits +system.cpu.dcache.overall_hits::total 57944940 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses -system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623254000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1623254000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6329554500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses +system.cpu.dcache.overall_misses::total 150664 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7952808500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7952808500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7952808500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7952808500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35676.696191 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35676.696191 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.464341 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.464341 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52785.411813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52785.411813 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,26 +182,26 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks system.cpu.dcache.writebacks::total 123865 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577755000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577755000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802145500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7802145500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802145500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7802145500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -212,24 +212,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34676.696191 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34676.696191 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.464341 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.464341 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.181257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 144582729500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181257 # Average occupied blocks per requestor +system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id @@ -239,14 +239,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 269294166 # Number of tag accesses -system.cpu.icache.tags.data_accesses 269294166 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits -system.cpu.icache.overall_hits::total 134366547 # number of overall hits +system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses +system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits +system.cpu.icache.overall_hits::total 134366557 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses @@ -259,12 +259,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses @@ -312,19 +312,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 99021 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30843.659201 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 433831 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130064 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.335519 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 99022 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26289.730201 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863843 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.065157 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.802299 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.039797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id @@ -332,8 +332,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5588795 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5588795 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits @@ -354,26 +354,26 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21053 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21053 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122317 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130521 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 122317 # number of overall misses -system.cpu.l2cache.overall_misses::total 130521 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6025890500 # number of ReadExReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses +system.cpu.l2cache.overall_misses::total 130522 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252774500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252774500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7278665000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7767126500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7278665000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7767126500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) @@ -382,38 +382,38 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45499 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 45499 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462713 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462713 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.811777 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.386498 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.811777 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.386498 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.739809 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.739809 # average ReadExReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747399 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747399 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.568997 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59508.634626 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.568997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59508.634626 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -430,115 +430,115 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21053 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21053 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122317 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130521 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122317 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130521 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042244500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042244500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055495000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6461916500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055495000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6461916500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462713 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462713 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811777 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.386498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811777 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.386498 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.739809 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.739809 # average ReadExReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747399 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747399 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36468 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1006962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41378752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 99021 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 436723 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 99022 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 433110 99.17% 99.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 436723 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 643471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 29257 # Transaction distribution +system.membus.trans_dist::ReadResp 29258 # Transaction distribution system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution -system.membus.trans_dist::CleanEvict 10300 # Transaction distribution +system.membus.trans_dist::CleanEvict 10301 # Transaction distribution system.membus.trans_dist::ReadExReq 101264 # Transaction distribution system.membus.trans_dist::ReadExResp 101264 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 29257 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 356612 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13810624 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 226091 # Request fanout histogram +system.membus.snoop_fanout::samples 226093 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 226091 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 226091 # Request fanout histogram -system.membus.reqLayer0.occupancy 568572500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 226093 # Request fanout histogram +system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 652605000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |