diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
| commit | 80cd107e51ceb5aac262ec7dd82870e48d345b43 (patch) | |
| tree | 4bb545ae29522161963a8028f34ca850c98a3403 /tests/quick | |
| parent | 2847d5f5177304236dcdbab112a0369f0bd96aea (diff) | |
| download | gem5-80cd107e51ceb5aac262ec7dd82870e48d345b43.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/quick')
34 files changed, 6978 insertions, 6721 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 01efe7b2f..b3504c645 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1825215 # Simulator instruction rate (inst/s) -host_op_rate 1825215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52491614317 # Simulator tick rate (ticks/s) -host_mem_usage 318168 # Number of bytes of host memory used -host_seconds 35.61 # Real time elapsed on the host +host_inst_rate 2576820 # Simulator instruction rate (inst/s) +host_op_rate 2576818 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74107088123 # Simulator tick rate (ticks/s) +host_mem_usage 319644 # Number of bytes of host memory used +host_seconds 25.23 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -900,17 +900,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5328064 system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1265678 # Request fanout histogram +system.membus.snoop_fanout::samples 1287715 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1265678 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1287715 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1265678 # Request fanout histogram +system.membus.snoop_fanout::total 1287715 # Request fanout histogram system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution @@ -932,19 +932,19 @@ system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 243 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3873082 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.010775 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.103240 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3895119 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.010714 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102951 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3831351 98.92% 98.92% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3853388 98.93% 98.93% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41731 1.07% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3873082 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3895119 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 608395ba3..3fe61f3f7 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1690642 # Simulator instruction rate (inst/s) -host_op_rate 1690641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51512796649 # Simulator tick rate (ticks/s) -host_mem_usage 313048 # Number of bytes of host memory used -host_seconds 35.51 # Real time elapsed on the host +host_inst_rate 2059947 # Simulator instruction rate (inst/s) +host_op_rate 2059945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62765242809 # Simulator tick rate (ticks/s) +host_mem_usage 317596 # Number of bytes of host memory used +host_seconds 29.15 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -441,17 +441,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3838716 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103690 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3855738 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.010822 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103463 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3796990 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3814012 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 1.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3838716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3855738 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -574,17 +574,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232 system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1215692 # Request fanout histogram +system.membus.snoop_fanout::samples 1232714 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1215692 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1232714 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1215692 # Request fanout histogram +system.membus.snoop_fanout::total 1232714 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 18eb6256f..3f2e8762f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.962613 # Nu sim_ticks 1962612686500 # Number of ticks simulated final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1051716 # Simulator instruction rate (inst/s) -host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33894179183 # Simulator tick rate (ticks/s) -host_mem_usage 374244 # Number of bytes of host memory used -host_seconds 57.90 # Real time elapsed on the host +host_inst_rate 1118839 # Simulator instruction rate (inst/s) +host_op_rate 1118839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36057415911 # Simulator tick rate (ticks/s) +host_mem_usage 319640 # Number of bytes of host memory used +host_seconds 54.43 # Real time elapsed on the host sim_insts 60898638 # Number of instructions simulated sim_ops 60898638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -610,6 +610,12 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10834 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17944 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles @@ -652,12 +658,12 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 211730.893483 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210003.817432 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 698758 # number of replacements system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use @@ -1011,6 +1017,12 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3218 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3307 # number of overall MSHR uncacheable misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles @@ -1053,12 +1065,12 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 315648 # number of replacements system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use @@ -1539,6 +1551,15 @@ system.l2c.overall_mshr_misses::cpu0.data 387263 # n system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 14052 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 21251 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles @@ -1620,15 +1641,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193372.151899 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197977.528090 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193429.087373 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 198730.893483 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209613.424487 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201223.064332 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 196607.584708 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 209300.272150 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 198582.772575 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 292759 # Transaction distribution system.membus.trans_dist::ReadResp 292759 # Transaction distribution @@ -1655,17 +1676,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 21558 # Total snoops (count) -system.membus.snoop_fanout::samples 597341 # Request fanout histogram +system.membus.snoop_fanout::samples 618592 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 618592 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 597341 # Request fanout histogram +system.membus.snoop_fanout::total 618592 # Request fanout histogram system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) @@ -1696,19 +1717,19 @@ system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 202 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 98552 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3276706 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012746 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112175 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3234942 98.73% 98.73% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41764 1.27% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3276706 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index d63246d54..8fa2e66de 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.922414 # Nu sim_ticks 1922413663500 # Number of ticks simulated final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1122927 # Simulator instruction rate (inst/s) -host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38428929684 # Simulator tick rate (ticks/s) -host_mem_usage 370248 # Number of bytes of host memory used -host_seconds 50.03 # Real time elapsed on the host +host_inst_rate 912210 # Simulator instruction rate (inst/s) +host_op_rate 912209 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31217732593 # Simulator tick rate (ticks/s) +host_mem_usage 318584 # Number of bytes of host memory used +host_seconds 61.58 # Real time elapsed on the host sim_insts 56174594 # Number of instructions simulated sim_ops 56174594 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -586,6 +586,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles @@ -622,12 +628,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206747.330447 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206747.330447 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209890.673575 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209890.673575 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208576.839566 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 928205 # number of replacements system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use @@ -842,6 +848,12 @@ system.cpu.l2cache.demand_mshr_misses::total 402112 system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles @@ -887,12 +899,12 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192747.330447 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192747.330447 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196890.673575 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196890.673575 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195158.866104 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution @@ -911,17 +923,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41937 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3214755 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012990 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3172994 98.70% 98.70% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41761 1.30% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3214755 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) @@ -1130,17 +1142,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 559589 # Request fanout histogram +system.membus.snoop_fanout::samples 576169 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 576169 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 559589 # Request fanout histogram +system.membus.snoop_fanout::total 576169 # Request fanout histogram system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 52df6c391..a436908c3 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 903946 # Simulator instruction rate (inst/s) -host_op_rate 1100409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17625645989 # Simulator tick rate (ticks/s) -host_mem_usage 615176 # Number of bytes of host memory used -host_seconds 157.94 # Real time elapsed on the host +host_inst_rate 1057273 # Simulator instruction rate (inst/s) +host_op_rate 1287060 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20615299474 # Simulator tick rate (ticks/s) +host_mem_usage 562992 # Number of bytes of host memory used +host_seconds 135.04 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -548,19 +548,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3336291 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.019237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.137356 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3272112 98.08% 98.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 64179 1.92% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3336291 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -694,17 +692,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359045 # Request fanout histogram +system.membus.snoop_fanout::samples 426678 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 426678 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359045 # Request fanout histogram +system.membus.snoop_fanout::total 426678 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index cb5fe02ce..8cc51b925 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,70 +4,70 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1337323 # Simulator instruction rate (inst/s) -host_op_rate 1629508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25528979782 # Simulator tick rate (ticks/s) -host_mem_usage 626168 # Number of bytes of host memory used -host_seconds 109.79 # Real time elapsed on the host +host_inst_rate 935329 # Simulator instruction rate (inst/s) +host_op_rate 1139685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17855077822 # Simulator tick rate (ticks/s) +host_mem_usage 572752 # Number of bytes of host memory used +host_seconds 156.98 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1117604 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9440956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152020 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1081568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1118628 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9439908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 149524 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1084244 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11793812 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1117604 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152020 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1269624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8390656 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_read::total 11793968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1118628 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 149524 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1268152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8394176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8408400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8411740 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25916 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2530 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25932 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16962 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193435 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131104 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193429 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135550 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3368288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 385875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 399097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3367914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386830 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4207726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398732 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452969 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2993568 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4207781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 399097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452444 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2994824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2999899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2993568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3001090 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2994824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3374604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 385890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 399097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3374166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386844 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7207624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7208872 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -291,13 +291,13 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 116882065 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 693477 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853657 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932369 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693989 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.776569 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853657 # Average occupied blocks per requestor +system.cpu0.dcache.tags.replacements 693486 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -305,64 +305,64 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113775 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113775 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108539 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108539 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690376 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690376 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690414 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690414 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363049 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363049 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798915 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798915 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145008 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145008 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373099 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373099 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295764 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295764 # number of WriteReq misses +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363041 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363041 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798955 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798955 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145048 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145048 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295771 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295771 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18436 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18436 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses -system.cpu0.dcache.overall_misses::total 769184 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481638 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481638 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986140 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986140 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668874 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668874 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769195 # number of overall misses +system.cpu0.dcache.overall_misses::total 769195 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467778 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467778 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048327 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048327 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048348 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048348 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,8 +371,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511896 # number of writebacks -system.cpu0.dcache.writebacks::total 511896 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511485 # number of writebacks +system.cpu0.dcache.writebacks::total 511485 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use @@ -429,123 +429,123 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 252330 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16129.294754 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1810154 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268529 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.741000 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8067.926153 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.192846 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.094111 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.670375 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.411269 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.492427 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289836 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201990 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984454 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16192 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 252829 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16127.674334 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1809277 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 269026 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.725287 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 8127.481443 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.302152 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.089300 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4685.625756 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3313.175683 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.496062 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285988 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202220 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984355 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16189 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5555 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7641 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2632 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39452382 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39452382 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7540 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3225 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065497 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 351995 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428257 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511896 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511896 # number of Writeback hits +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5612 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7505 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2706 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988098 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39447877 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39447877 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7572 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3251 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065262 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 351770 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1427855 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511485 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511485 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94089 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94089 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7540 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3225 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065497 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446084 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522346 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7540 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3225 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065497 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446084 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522346 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 210 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44759 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128167 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173260 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26230 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26230 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18436 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18436 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94095 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94095 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7572 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3251 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065262 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 445865 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1521950 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7572 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3251 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065262 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 445865 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1521950 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 137 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44994 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128396 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173743 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 210 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44759 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303595 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348688 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 210 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44759 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303595 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348688 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7750 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3349 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 137 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44994 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303824 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 349171 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 137 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44994 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303824 # number of overall misses +system.cpu0.l2cache.overall_misses::total 349171 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7788 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3388 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480162 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601517 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511896 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511896 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26247 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26247 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18436 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18436 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7750 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3349 # number of demand (read+write) accesses +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480166 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1601598 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511485 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511485 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7788 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3388 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749679 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871034 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7750 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3349 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1871121 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7788 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3388 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749679 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871034 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037026 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040314 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266924 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108185 # miss rate for ReadReq accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1871121 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040437 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040526 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267399 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108481 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650898 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650898 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037026 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040314 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404967 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037026 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040314 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404967 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650883 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650883 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040437 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040526 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.405267 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186611 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040437 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040526 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.405267 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186611 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -554,43 +554,41 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192974 # number of writebacks -system.cpu0.l2cache.writebacks::total 192974 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 193152 # number of writebacks +system.cpu0.l2cache.writebacks::total 193152 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651840 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651840 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28386 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28386 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511896 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26247 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18436 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44683 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1651838 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511485 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44692 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220556 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220081 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4500748 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500273 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80931536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80905668 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152107280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 322019 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2656743 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.082586 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275256 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152081412 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 327909 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2731172 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.090112 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.286342 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 2437332 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 219411 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2485061 90.99% 90.99% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 246111 9.01% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2656743 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2731172 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -806,32 +804,32 @@ system.cpu1.dcache.tags.tag_accesses 39751979 # Nu system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397494 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397494 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397479 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397479 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72460 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72460 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256188 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256188 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306287 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306287 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72442 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72442 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256173 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256173 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306272 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306272 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92468 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92468 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92483 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92483 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22519 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22519 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229098 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229098 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses -system.cpu1.dcache.overall_misses::total 259817 # number of overall misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22537 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22537 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229113 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229113 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259832 # number of overall misses +system.cpu1.dcache.overall_misses::total 259832 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) @@ -848,18 +846,18 @@ system.cpu1.dcache.overall_accesses::cpu1.data 19566104 system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012346 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237095 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237095 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -868,8 +866,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120855 # number of writebacks -system.cpu1.dcache.writebacks::total 120855 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120843 # number of writebacks +system.cpu1.dcache.writebacks::total 120843 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use @@ -925,121 +923,121 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48604 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15305.333897 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716708 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.298662 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48543 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15314.912528 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 717091 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63380 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.314153 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809694 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.091002 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.023143 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.979607 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.430451 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200133 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225368 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934163 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14807 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8302.426392 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.123905 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.034953 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3306.071742 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3701.255535 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.506740 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201787 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225907 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.934748 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14808 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9357 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4911 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903748 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15213345 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15213345 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3151 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1735 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510036 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99375 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614297 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120855 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120855 # number of Writeback hits +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9377 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4900 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15213000 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15213000 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3125 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1708 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510060 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99394 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614287 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120843 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120843 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19784 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19784 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3151 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1735 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510036 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119159 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634081 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3151 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1735 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510036 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119159 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634081 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 261 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13849 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73292 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87740 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28844 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28844 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22519 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22519 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43832 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43832 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 261 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13849 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117124 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131572 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 261 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13849 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117124 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131572 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19811 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19811 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3125 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1708 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510060 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119205 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634098 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3125 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1708 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510060 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119205 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634098 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13825 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73273 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87709 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28859 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28859 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22537 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22537 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43805 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43805 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13825 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117078 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131514 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13825 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117078 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131514 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3469 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1975 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120855 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120855 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28852 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28852 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22519 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22519 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 701996 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120843 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120843 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28867 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28867 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22537 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22537 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3469 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1975 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765653 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3489 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 765612 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3469 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1975 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.130762 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026435 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424470 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.124979 # miss rate for ReadReq accesses +system.cpu1.l2cache.overall_accesses::total 765612 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135190 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026389 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424360 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.124942 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689009 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689009 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.130762 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026435 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495694 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171843 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.130762 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026435 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495694 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171843 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688585 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688585 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135190 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026389 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495499 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171776 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135190 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026389 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495499 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171776 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1048,43 +1046,41 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32977 # number of writebacks -system.cpu1.l2cache.writebacks::total 32977 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks +system.cpu1.l2cache.writebacks::total 32966 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28852 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22519 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51371 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120843 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28867 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22537 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51404 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707623 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707677 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1774441 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774495 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22876014 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22875246 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56442750 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499492 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371571 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.313385 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463870 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56441982 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 568922 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1446930 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.351508 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.477442 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 941741 68.66% 68.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 429830 31.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 938322 64.85% 64.85% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 508608 35.15% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371571 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1446930 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1189,183 +1185,183 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 107683 # number of replacements -system.l2c.tags.tagsinuse 62052.473518 # Cycle average of tags in use -system.l2c.tags.total_refs 207875 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168125 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.236431 # Average number of references to valid blocks. +system.l2c.tags.replacements 107655 # number of replacements +system.l2c.tags.tagsinuse 62149.484460 # Cycle average of tags in use +system.l2c.tags.total_refs 208536 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168097 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.240569 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48595.677496 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972785 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7329.722723 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3756.747244 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1654.505866 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 710.993782 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741511 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 48591.950970 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.942995 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7375.890834 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3824.198641 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1621.181926 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 731.426698 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.741454 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.057323 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.946846 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60435 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1875 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13095 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.922165 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4904261 # Number of tag accesses -system.l2c.tags.data_accesses 4904261 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 71 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 27858 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 76068 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 39 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 20 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11484 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11410 # number of ReadReq hits -system.l2c.ReadReq_hits::total 127013 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 225951 # number of Writeback hits -system.l2c.Writeback_hits::total 225951 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 487 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 552 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 64 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13938 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3112 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17050 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 27858 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90006 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 39 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11484 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14522 # number of demand (read+write) hits -system.l2c.demand_hits::total 144063 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 27858 # number of overall hits -system.l2c.overall_hits::cpu0.data 90006 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 39 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11484 # number of overall hits -system.l2c.overall_hits::cpu1.data 14522 # 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number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 80 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44994 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238378 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13825 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31394 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328837 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.375983 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.168246 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.092811 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199438 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952589 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980821 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.959396 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.922889 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.989899 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.962594 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907022 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.836232 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899131 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.025000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.375983 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621223 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.168246 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.540772 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.560512 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.375983 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621223 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.168246 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.540772 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.560512 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1374,49 +1370,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94914 # number of writebacks -system.l2c.writebacks::total 94914 # number of writebacks +system.l2c.writebacks::writebacks 94969 # number of writebacks +system.l2c.writebacks::total 94969 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 75966 # Transaction distribution -system.membus.trans_dist::ReadResp 75966 # Transaction distribution -system.membus.trans_dist::WriteReq 30891 # Transaction distribution -system.membus.trans_dist::WriteResp 30891 # Transaction distribution -system.membus.trans_dist::Writeback 131104 # Transaction distribution +system.membus.trans_dist::ReadReq 75988 # Transaction distribution +system.membus.trans_dist::ReadResp 75988 # Transaction distribution +system.membus.trans_dist::WriteReq 30846 # Transaction distribution +system.membus.trans_dist::WriteResp 30846 # Transaction distribution +system.membus.trans_dist::Writeback 131159 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60393 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40881 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15635 # Transaction distribution -system.membus.trans_dist::ReadExReq 196339 # Transaction distribution -system.membus.trans_dist::ReadExResp 152220 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15595 # Transaction distribution +system.membus.trans_dist::ReadExReq 196283 # Transaction distribution +system.membus.trans_dist::ReadExResp 152192 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773592 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773470 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 882734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 882612 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17902820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18092602 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17906316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18096098 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22743226 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22746722 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 496901 # Request fanout histogram +system.membus.snoop_fanout::samples 571767 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 496901 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 571767 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 496901 # Request fanout histogram +system.membus.snoop_fanout::total 571767 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1448,33 +1444,33 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 305006 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305006 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30891 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30891 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225951 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40955 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101503 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 305452 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305452 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 226118 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60537 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40981 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101518 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117662 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528323 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664008 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10429874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45093882 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1118722 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410600 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1529322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34707388 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425906 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45133294 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838716 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043490 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203958 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 914196 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039900 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195723 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802240 95.65% 95.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 877720 96.01% 96.01% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36476 3.99% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838716 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 914196 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 20c993e31..383222d5f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1378466 # Simulator instruction rate (inst/s) -host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26878113924 # Simulator tick rate (ticks/s) -host_mem_usage 614624 # Number of bytes of host memory used -host_seconds 103.57 # Real time elapsed on the host +host_inst_rate 1032026 # Simulator instruction rate (inst/s) +host_op_rate 1256326 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20123025378 # Simulator tick rate (ticks/s) +host_mem_usage 560940 # Number of bytes of host memory used +host_seconds 138.34 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -548,19 +548,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3336291 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.019237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.137356 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3272112 98.08% 98.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 64179 1.92% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3336291 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -694,17 +692,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359045 # Request fanout histogram +system.membus.snoop_fanout::samples 426678 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 426678 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359045 # Request fanout histogram +system.membus.snoop_fanout::total 426678 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 64a01b6e7..81dc58761 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,157 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868581 # Number of seconds simulated -sim_ticks 2868581440500 # Number of ticks simulated -final_tick 2868581440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868578 # Number of seconds simulated +sim_ticks 2868577613500 # Number of ticks simulated +final_tick 2868577613500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 717360 # Simulator instruction rate (inst/s) -host_op_rate 867708 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15647358559 # Simulator tick rate (ticks/s) -host_mem_usage 639748 # Number of bytes of host memory used -host_seconds 183.33 # Real time elapsed on the host -sim_insts 131511324 # Number of instructions simulated -sim_ops 159074269 # Number of ops (including micro ops) simulated +host_inst_rate 558438 # Simulator instruction rate (inst/s) +host_op_rate 675477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12195118142 # Simulator tick rate (ticks/s) +host_mem_usage 590596 # Number of bytes of host memory used +host_seconds 235.22 # Real time elapsed on the host +sim_insts 131357672 # Number of instructions simulated +sim_ops 158887964 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1161572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1227520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8321088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 141140 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 467936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 345792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1167908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1250980 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8365696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 137236 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 508432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 356544 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11666584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1161572 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 141140 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1302712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8208384 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_read::total 11788332 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1167908 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 137236 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1305144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8293056 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8226128 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8310620 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26603 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 130017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7964 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5571 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 191448 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 128256 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193340 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129579 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 132692 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 133970 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 404929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 427919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2900768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 163125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 120545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 407138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 436098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2916322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 177242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 124293 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4067022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 404929 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49202 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2861478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4109469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 407138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47841 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2890999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2867664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2861478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2897122 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2890999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 404929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 434091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2900768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 163138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 120545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 407138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 442207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2916322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 177256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 124293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6934686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 191448 # Number of read requests accepted -system.physmem.writeReqs 168916 # Number of write requests accepted -system.physmem.readBursts 191448 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 168916 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12244160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue -system.physmem.bytesWritten 9286016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11666584 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10544464 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23799 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13043 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11402 # Per bank write bursts -system.physmem.perBankRdBursts::1 11523 # Per bank write bursts -system.physmem.perBankRdBursts::2 11617 # Per bank write bursts -system.physmem.perBankRdBursts::3 11771 # Per bank write bursts -system.physmem.perBankRdBursts::4 20348 # Per bank write bursts -system.physmem.perBankRdBursts::5 12097 # Per bank write bursts -system.physmem.perBankRdBursts::6 11123 # Per bank write bursts -system.physmem.perBankRdBursts::7 11241 # Per bank write bursts -system.physmem.perBankRdBursts::8 11419 # Per bank write bursts -system.physmem.perBankRdBursts::9 11532 # Per bank write bursts -system.physmem.perBankRdBursts::10 11480 # Per bank write bursts -system.physmem.perBankRdBursts::11 10715 # Per bank write bursts -system.physmem.perBankRdBursts::12 11252 # Per bank write bursts -system.physmem.perBankRdBursts::13 11225 # Per bank write bursts -system.physmem.perBankRdBursts::14 11052 # Per bank write bursts -system.physmem.perBankRdBursts::15 11518 # Per bank write bursts -system.physmem.perBankWrBursts::0 9249 # Per bank write bursts -system.physmem.perBankWrBursts::1 9496 # Per bank write bursts -system.physmem.perBankWrBursts::2 9535 # Per bank write bursts -system.physmem.perBankWrBursts::3 9435 # Per bank write bursts -system.physmem.perBankWrBursts::4 8870 # Per bank write bursts -system.physmem.perBankWrBursts::5 9467 # Per bank write bursts -system.physmem.perBankWrBursts::6 9116 # Per bank write bursts -system.physmem.perBankWrBursts::7 8737 # Per bank write bursts -system.physmem.perBankWrBursts::8 8796 # Per bank write bursts -system.physmem.perBankWrBursts::9 9230 # Per bank write bursts -system.physmem.perBankWrBursts::10 9164 # Per bank write bursts -system.physmem.perBankWrBursts::11 8822 # Per bank write bursts -system.physmem.perBankWrBursts::12 9029 # Per bank write bursts -system.physmem.perBankWrBursts::13 8642 # Per bank write bursts -system.physmem.perBankWrBursts::14 8756 # Per bank write bursts -system.physmem.perBankWrBursts::15 8750 # Per bank write bursts +system.physmem.bw_total::total 7006592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 193340 # Number of read requests accepted +system.physmem.writeReqs 170194 # Number of write requests accepted +system.physmem.readBursts 193340 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 170194 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12365312 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue +system.physmem.bytesWritten 9398080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11788332 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10628956 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23320 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12970 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11741 # Per bank write bursts +system.physmem.perBankRdBursts::1 11572 # Per bank write bursts +system.physmem.perBankRdBursts::2 11914 # Per bank write bursts +system.physmem.perBankRdBursts::3 12194 # Per bank write bursts +system.physmem.perBankRdBursts::4 20279 # Per bank write bursts +system.physmem.perBankRdBursts::5 11715 # Per bank write bursts +system.physmem.perBankRdBursts::6 11292 # Per bank write bursts +system.physmem.perBankRdBursts::7 11716 # Per bank write bursts +system.physmem.perBankRdBursts::8 11966 # Per bank write bursts +system.physmem.perBankRdBursts::9 12328 # Per bank write bursts +system.physmem.perBankRdBursts::10 11336 # Per bank write bursts +system.physmem.perBankRdBursts::11 10554 # Per bank write bursts +system.physmem.perBankRdBursts::12 10992 # Per bank write bursts +system.physmem.perBankRdBursts::13 11462 # Per bank write bursts +system.physmem.perBankRdBursts::14 10907 # Per bank write bursts +system.physmem.perBankRdBursts::15 11240 # Per bank write bursts +system.physmem.perBankWrBursts::0 9545 # Per bank write bursts +system.physmem.perBankWrBursts::1 9662 # Per bank write bursts +system.physmem.perBankWrBursts::2 9792 # Per bank write bursts +system.physmem.perBankWrBursts::3 9578 # Per bank write bursts +system.physmem.perBankWrBursts::4 8974 # Per bank write bursts +system.physmem.perBankWrBursts::5 9217 # Per bank write bursts +system.physmem.perBankWrBursts::6 9112 # Per bank write bursts +system.physmem.perBankWrBursts::7 9138 # Per bank write bursts +system.physmem.perBankWrBursts::8 9280 # Per bank write bursts +system.physmem.perBankWrBursts::9 9864 # Per bank write bursts +system.physmem.perBankWrBursts::10 9143 # Per bank write bursts +system.physmem.perBankWrBursts::11 8671 # Per bank write bursts +system.physmem.perBankWrBursts::12 8940 # Per bank write bursts +system.physmem.perBankWrBursts::13 8704 # Per bank write bursts +system.physmem.perBankWrBursts::14 8686 # Per bank write bursts +system.physmem.perBankWrBursts::15 8539 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 83 # Number of times write queue was full causing retry -system.physmem.totGap 2868581033500 # Total gap between requests +system.physmem.numWrRetry 53 # Number of times write queue was full causing retry +system.physmem.totGap 2868577154000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 9742 # Read request sizes (log2) +system.physmem.readPktSize::2 9731 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 181678 # Read request sizes (log2) +system.physmem.readPktSize::6 183581 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4436 # Write request sizes (log2) +system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 164480 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 134188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 74 # What read queue length does an incoming req see +system.physmem.writePktSize::6 165803 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 135144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 9961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 82 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -180,162 +184,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 81717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 263.471640 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.531290 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.110863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41089 50.28% 50.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16342 20.00% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5746 7.03% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3516 4.30% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2447 2.99% 84.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1416 1.73% 86.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 997 1.22% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 891 1.09% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9273 11.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 81717 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5972 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.034494 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 599.214233 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5970 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5972 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5972 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.295713 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.853114 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 39.858214 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5595 93.69% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 97 1.62% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 24 0.40% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 14 0.23% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 35 0.59% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 43 0.72% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 25 0.42% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 12 0.20% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 18 0.30% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 5 0.08% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 30 0.50% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 15 0.25% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.12% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.07% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.05% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 7 0.12% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.10% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 7 0.12% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5972 # Writes before turning the bus around for reads -system.physmem.totQLat 4538980935 # Total ticks spent queuing -system.physmem.totMemAccLat 8126137185 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 956575000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23725.17 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 83936 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 259.284788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.169379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.901486 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42814 51.01% 51.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16839 20.06% 71.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5671 6.76% 77.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3554 4.23% 82.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2350 2.80% 84.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1452 1.73% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1048 1.25% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 956 1.14% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9252 11.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 83936 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.152937 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.980980 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6006 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6009 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.437510 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.815074 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 42.361816 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5653 94.08% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 88 1.46% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 21 0.35% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 11 0.18% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 30 0.50% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 35 0.58% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 32 0.53% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 15 0.25% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.18% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 9 0.15% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 22 0.37% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 19 0.32% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 8 0.13% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.03% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 4 0.07% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.05% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.08% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.08% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.10% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 6 0.10% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6009 # Writes before turning the bus around for reads +system.physmem.totQLat 4585121898 # Total ticks spent queuing +system.physmem.totMemAccLat 8207771898 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 966040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23731.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42475.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42481.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.28 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing -system.physmem.readRowHits 160412 # Number of row buffer hits during reads -system.physmem.writeRowHits 94279 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.97 # Row buffer hit rate for writes -system.physmem.avgGap 7960231.97 # Average gap between requests -system.physmem.pageHitRate 75.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 319183200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 174157500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 788743800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 478904400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83526196590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647879002250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920527828700 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.504870 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2741264066617 # Time in different power states -system.physmem_0.memoryStateTime::REF 95788160000 # Time in different power states +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing +system.physmem.readRowHits 161661 # Number of row buffer hits during reads +system.physmem.writeRowHits 94455 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.31 # Row buffer hit rate for writes +system.physmem.avgGap 7890808.44 # Average gap between requests +system.physmem.pageHitRate 75.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 329026320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 179528250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 798891600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486116640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187361132400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84057386715 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647408374250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920620456175 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.538978 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740481725360 # Time in different power states +system.physmem_0.memoryStateTime::REF 95787900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31529102383 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32307893640 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 298597320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 162925125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 703505400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 461304720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82377359595 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648886754000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920252087120 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.408745 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742945725805 # Time in different power states -system.physmem_1.memoryStateTime::REF 95788160000 # Time in different power states +system.physmem_1.actEnergy 305529840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 166707750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 708123000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 465438960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187361132400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82818901260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648494765000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920320598210 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.434445 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742293590423 # Time in different power states +system.physmem_1.memoryStateTime::REF 95787900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29845454195 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30490063327 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -391,58 +396,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7634 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7634 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1372 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7634 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7634 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7634 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6240 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9567.588141 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8440.173252 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5686.595019 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6084 97.50% 97.50% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 143 2.29% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 8 0.13% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 7618 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7618 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1341 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6277 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7618 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7618 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7618 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6224 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9157.575514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8041.236075 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5531.388532 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6077 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 137 2.20% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6224 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4907 78.64% 78.64% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1333 21.36% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6240 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7634 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 4922 79.08% 79.08% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1302 20.92% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6224 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7618 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7634 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6240 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7618 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6224 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6240 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 13874 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6224 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 13842 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25111402 # DTB read hits -system.cpu0.dtb.read_misses 6533 # DTB read misses -system.cpu0.dtb.write_hits 18719047 # DTB write hits -system.cpu0.dtb.write_misses 1101 # DTB write misses +system.cpu0.dtb.read_hits 25125547 # DTB read hits +system.cpu0.dtb.read_misses 6527 # DTB read misses +system.cpu0.dtb.write_hits 18731781 # DTB write hits +system.cpu0.dtb.write_misses 1091 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1785 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1741 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25117935 # DTB read accesses -system.cpu0.dtb.write_accesses 18720148 # DTB write accesses +system.cpu0.dtb.read_accesses 25132074 # DTB read accesses +system.cpu0.dtb.write_accesses 18732872 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43830449 # DTB hits -system.cpu0.dtb.misses 7634 # DTB misses -system.cpu0.dtb.accesses 43838083 # DTB accesses +system.cpu0.dtb.hits 43857328 # DTB hits +system.cpu0.dtb.misses 7618 # DTB misses +system.cpu0.dtb.accesses 43864946 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -480,14 +485,14 @@ system.cpu0.itb.walker.walkWaitTime::samples 3348 system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9914.451115 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8640.132285 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5844.480359 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 848 36.36% 36.36% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1427 61.19% 97.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.68% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 51 2.19% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9422.169811 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8126.335555 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5925.919906 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 980 42.02% 42.02% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1299 55.70% 97.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.93% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.13% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency @@ -504,7 +509,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 118783416 # ITB inst hits +system.cpu0.itb.inst_hits 118901491 # ITB inst hits system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -521,172 +526,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 118786764 # ITB inst accesses -system.cpu0.itb.hits 118783416 # DTB hits +system.cpu0.itb.inst_accesses 118904839 # ITB inst accesses +system.cpu0.itb.hits 118901491 # DTB hits system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 118786764 # DTB accesses -system.cpu0.numCycles 5737162881 # number of cpu cycles simulated +system.cpu0.itb.accesses 118904839 # DTB accesses +system.cpu0.numCycles 5737155227 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 115118664 # Number of instructions committed -system.cpu0.committedOps 139117689 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123147620 # Number of integer alu accesses +system.cpu0.committedInsts 115236645 # Number of instructions committed +system.cpu0.committedOps 139243080 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123236123 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 12673072 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15652345 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123147620 # number of integer instructions +system.cpu0.num_func_calls 12671679 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15683932 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123236123 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 226729132 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85574900 # number of times the integer registers were written +system.cpu0.num_int_register_reads 226877119 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85629478 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 504016583 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52146919 # number of times the CC registers were written -system.cpu0.num_mem_refs 44965604 # number of memory refs -system.cpu0.num_load_insts 25362826 # Number of load instructions -system.cpu0.num_store_insts 19602778 # Number of store instructions -system.cpu0.num_idle_cycles 5466015382.984095 # Number of idle cycles -system.cpu0.num_busy_cycles 271147498.015905 # Number of busy cycles -system.cpu0.not_idle_fraction 0.047262 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.952738 # Percentage of idle cycles -system.cpu0.Branches 29061799 # Number of branches fetched +system.cpu0.num_cc_register_reads 504430555 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52228186 # number of times the CC registers were written +system.cpu0.num_mem_refs 44991026 # number of memory refs +system.cpu0.num_load_insts 25375377 # Number of load instructions +system.cpu0.num_store_insts 19615649 # Number of store instructions +system.cpu0.num_idle_cycles 5465784255.910094 # Number of idle cycles +system.cpu0.num_busy_cycles 271370971.089905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047301 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952699 # Percentage of idle cycles +system.cpu0.Branches 29094451 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 97796607 68.45% 68.45% # Class of executed instruction -system.cpu0.op_class::IntMult 109233 0.08% 68.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8187 0.01% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::MemRead 25362826 17.75% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19602778 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 97895605 68.46% 68.46% # Class of executed instruction +system.cpu0.op_class::IntMult 108367 0.08% 68.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8067 0.01% 68.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction +system.cpu0.op_class::MemRead 25375377 17.74% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19615649 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 142881904 # Class of executed instruction +system.cpu0.op_class::total 143005338 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 688886 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.817079 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42962889 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 689398 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.319428 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1149671500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.817079 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966440 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966440 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 691902 # number of replacements +system.cpu0.dcache.tags.tagsinuse 493.788529 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42987184 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 692414 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.083066 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1147014500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.788529 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964431 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.964431 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88293922 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88293922 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23854264 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23854264 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17989541 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17989541 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318725 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318725 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364533 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 364533 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361797 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361797 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41843805 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41843805 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42162530 # number of overall hits -system.cpu0.dcache.overall_hits::total 42162530 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 393288 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 393288 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 323540 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 323540 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127427 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127427 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21927 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21927 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19722 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19722 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 716828 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 716828 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 844255 # number of overall misses -system.cpu0.dcache.overall_misses::total 844255 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5012719236 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5012719236 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5098069375 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5098069375 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332035250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 332035250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435652050 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 435652050 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1835500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1835500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10110788611 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10110788611 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10110788611 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10110788611 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24247552 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24247552 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18313081 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18313081 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446152 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446152 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386460 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386460 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42560633 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42560633 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43006785 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43006785 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016220 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016220 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017667 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017667 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285613 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285613 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056738 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056738 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051693 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051693 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016843 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016843 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019631 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019631 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12745.670440 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12745.670440 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15757.153289 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15757.153289 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15142.757787 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15142.757787 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22089.648616 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22089.648616 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88350780 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88350780 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23864345 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23864345 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18002045 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18002045 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319294 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319294 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365178 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365178 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362317 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362317 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41866390 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41866390 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42185684 # number of overall hits +system.cpu0.dcache.overall_hits::total 42185684 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 396651 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396651 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 323350 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 323350 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127092 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127092 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21763 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21763 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19681 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19681 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 720001 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 720001 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 847093 # number of overall misses +system.cpu0.dcache.overall_misses::total 847093 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5048891005 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5048891005 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5105410053 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5105410053 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330377500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 330377500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 436252524 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 436252524 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1279500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1279500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10154301058 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10154301058 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10154301058 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10154301058 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24260996 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24260996 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18325395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18325395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446386 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446386 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386941 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386941 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381998 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381998 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42586391 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42586391 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43032777 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43032777 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016349 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016349 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017645 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017645 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284713 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284713 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056244 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056244 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051521 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051521 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016907 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016907 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019685 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019685 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12728.799385 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12728.799385 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15789.114127 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15789.114127 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15180.696595 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15180.696595 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22166.176719 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22166.176719 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14104.901889 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14104.901889 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11975.989021 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11975.989021 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14103.176326 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14103.176326 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11987.232875 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11987.232875 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -695,141 +700,147 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 504121 # number of writebacks -system.cpu0.dcache.writebacks::total 504121 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25265 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25265 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15169 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15169 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25265 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25265 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25265 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25265 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368023 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 368023 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323540 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 323540 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100320 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100320 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6758 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6758 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19722 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19722 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 691563 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 691563 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 791883 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 791883 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4066612315 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4066612315 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4601719625 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4601719625 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1548565203 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1548565203 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97840500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97840500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 405700950 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 405700950 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1754500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1754500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8668331940 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8668331940 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10216897143 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10216897143 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6181726750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6181726750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4820424000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4820424000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11002150750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11002150750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015178 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015178 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017667 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017667 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224856 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224856 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051693 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051693 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016249 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018413 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018413 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11049.886325 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11049.886325 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14223.031542 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14223.031542 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15436.256011 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15436.256011 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14477.730098 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14477.730098 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20570.984180 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20570.984180 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 505765 # number of writebacks +system.cpu0.dcache.writebacks::total 505765 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25164 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25164 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15036 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15036 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25164 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25164 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25164 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25164 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371487 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 371487 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323350 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323350 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100065 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100065 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6727 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6727 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19681 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19681 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 694837 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 694837 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 794902 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 794902 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31775 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31775 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28452 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28452 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60227 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60227 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4098614569 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4098614569 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4609386947 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4609386947 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1545410442 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1545410442 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97646500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97646500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 406311476 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 406311476 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1224000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1224000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8708001516 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8708001516 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10253411958 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10253411958 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6180823750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6180823750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4817819000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4817819000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10998642750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10998642750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017645 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017645 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224167 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224167 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017385 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017385 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051521 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051521 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016316 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016316 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018472 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018472 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11032.995957 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11032.995957 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14255.101120 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14255.101120 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15444.065777 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15444.065777 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14515.608741 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14515.608741 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20644.859306 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20644.859306 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12534.406757 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12534.406757 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12902.028637 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12902.028637 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12532.437847 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12532.437847 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12898.963593 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12898.963593 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194518.450039 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194518.450039 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169331.470547 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169331.470547 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182619.800920 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182619.800920 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1101309 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.453846 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 117681586 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1101821 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.806447 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13496302250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.453846 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998933 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998933 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1099684 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.454126 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117801286 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1100196 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 107.073000 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13491746250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454126 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998934 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998934 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 238668662 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 238668662 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 117681586 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 117681586 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 117681586 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 117681586 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 117681586 # number of overall hits -system.cpu0.icache.overall_hits::total 117681586 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1101830 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1101830 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1101830 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1101830 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1101830 # number of overall misses -system.cpu0.icache.overall_misses::total 1101830 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10869872254 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10869872254 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10869872254 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10869872254 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10869872254 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10869872254 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 118783416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 118783416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 118783416 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 118783416 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 118783416 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 118783416 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9865.289794 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9865.289794 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9865.289794 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9865.289794 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 238903187 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 238903187 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 117801286 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117801286 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117801286 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117801286 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117801286 # number of overall hits +system.cpu0.icache.overall_hits::total 117801286 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1100205 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1100205 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1100205 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1100205 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1100205 # number of overall misses +system.cpu0.icache.overall_misses::total 1100205 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10864366523 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10864366523 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10864366523 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10864366523 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10864366523 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10864366523 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 118901491 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 118901491 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 118901491 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 118901491 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 118901491 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 118901491 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009253 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009253 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009253 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009253 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009253 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009253 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9874.856525 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9874.856525 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9874.856525 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9874.856525 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9874.856525 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9874.856525 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,224 +849,228 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101830 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1101830 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101830 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1101830 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101830 # 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number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100205 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1100205 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9757723477 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9757723477 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9757723477 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9757723477 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9757723477 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9757723477 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 802157500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # 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Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 284001 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.937349 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 235795 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 266928 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16114.496747 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1972101 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 283159 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.964642 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7915.761025 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.539297 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.155291 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4574.741605 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1897.934094 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1714.806946 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.483140 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000033 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.279220 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.115841 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104664 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982906 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1117 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 7721.313532 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.317590 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.113534 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4537.329831 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1964.577716 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1889.844545 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.471272 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000080 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3213 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8038 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3680 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068176 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15100 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 368 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 474 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3254 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7638 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4052 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068542 # 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number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28198 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1754 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1754 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 225223 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 225223 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 8046 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3668 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1054676 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 606101 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1672491 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 8046 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3668 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1054676 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 606101 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1672491 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 223 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 133 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47154 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 94223 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 141733 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26109 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26109 # number of UpgradeReq misses +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921631 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39669375 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39669375 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7528 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3363 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053127 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 384165 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1448183 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 505760 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 505760 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28149 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28149 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1715 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1715 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 225012 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 225012 # 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mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027013 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035284 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042790 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.183184 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230592 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22742.345957 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29542.690680 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55320.103445 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19621.173082 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19621.173082 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14375.037581 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14375.037581 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 192571 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192571 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36152.288892 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36152.288892 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31075.910829 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44881.149122 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231234 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22821.854560 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29670.583433 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55085.343530 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19528.282560 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19528.282560 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14419.048160 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14419.048160 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 189099.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 189099.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36473.710048 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36473.710048 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27091.512404 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31250.956420 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27091.512404 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44864.886478 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186511.959087 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163165.698458 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161831.470547 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161831.470547 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 174852.582729 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 162617.510722 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1733379 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1686259 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28500 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28500 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 504119 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 307885 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42217 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111625 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 297195 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284749 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2221704 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2362865 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10199 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22165 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4616933 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70553208 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84179104 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 15204 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 33076 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 154780592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 633519 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2968459 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.176473 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.381222 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1738254 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1687491 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28452 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 505760 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 309559 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88185 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42256 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111549 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297072 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284592 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218454 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2369943 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9884 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21632 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4619913 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70449208 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84455860 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13944 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 30948 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154949960 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 641653 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3048291 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.181009 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.385025 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 2444606 82.35% 82.35% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 523853 17.65% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2496524 81.90% 81.90% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 551767 18.10% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2968459 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1775328997 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3048291 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1778395498 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114507000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114075998 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1667097754 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1664668023 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1206509407 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1210905566 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13896250 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13895250 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1274,62 +1295,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3283 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3283 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 611 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2672 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3283 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3283 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3283 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2513 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9027.258257 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8086.769918 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4736.776885 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 485 19.30% 19.30% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 533 21.21% 40.51% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1045 41.58% 82.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 324 12.89% 94.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 44 1.75% 96.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 19 0.76% 97.49% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 51 2.03% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 8 0.32% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2513 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1651557968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1651557968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1651557968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1910 76.00% 76.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 603 24.00% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2513 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3283 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3295 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3295 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 601 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3295 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3295 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3295 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2525 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9355.742574 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8433.023249 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5123.717679 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 905 35.84% 35.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1497 59.29% 95.13% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.46% 97.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 54 2.14% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.08% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.16% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2525 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1642630968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1642630968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1642630968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1932 76.51% 76.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 593 23.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2525 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3295 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3283 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2513 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3295 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2525 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2513 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5796 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2525 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5820 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3974119 # DTB read hits -system.cpu1.dtb.read_misses 2776 # DTB read misses -system.cpu1.dtb.write_hits 3444686 # DTB write hits -system.cpu1.dtb.write_misses 507 # DTB write misses +system.cpu1.dtb.read_hits 3921520 # DTB read hits +system.cpu1.dtb.read_misses 2787 # DTB read misses +system.cpu1.dtb.write_hits 3403460 # DTB write hits +system.cpu1.dtb.write_misses 508 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2006 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 362 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 344 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3976895 # DTB read accesses -system.cpu1.dtb.write_accesses 3445193 # DTB write accesses +system.cpu1.dtb.read_accesses 3924307 # DTB read accesses +system.cpu1.dtb.write_accesses 3403968 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7418805 # DTB hits -system.cpu1.dtb.misses 3283 # DTB misses -system.cpu1.dtb.accesses 7422088 # DTB accesses +system.cpu1.dtb.hits 7324980 # DTB hits +system.cpu1.dtb.misses 3295 # DTB misses +system.cpu1.dtb.accesses 7328275 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1367,23 +1385,23 @@ system.cpu1.itb.walker.walkWaitTime::samples 1740 system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9655.767484 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8490.755174 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5670.300287 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 219 19.89% 19.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 163 14.80% 34.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 463 42.05% 76.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 25 2.27% 97.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.91% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9831.970936 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8728.225186 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5541.612386 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.71% 16.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 162 14.71% 31.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 45.14% 76.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.54% 97.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.73% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1651010968 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1651010968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples 1642083968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1642083968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1642083968 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated @@ -1394,7 +1412,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16749094 # ITB inst hits +system.cpu1.itb.inst_hits 16475856 # ITB inst hits system.cpu1.itb.inst_misses 1740 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1411,171 +1429,171 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16750834 # ITB inst accesses -system.cpu1.itb.hits 16749094 # DTB hits +system.cpu1.itb.inst_accesses 16477596 # ITB inst accesses +system.cpu1.itb.hits 16475856 # DTB hits system.cpu1.itb.misses 1740 # DTB misses -system.cpu1.itb.accesses 16750834 # DTB accesses -system.cpu1.numCycles 5736248293 # number of cpu cycles simulated +system.cpu1.itb.accesses 16477596 # DTB accesses +system.cpu1.numCycles 5736236800 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 16392660 # Number of instructions committed -system.cpu1.committedOps 19956580 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17976734 # Number of integer alu accesses +system.cpu1.committedInsts 16121027 # Number of instructions committed +system.cpu1.committedOps 19644884 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17715670 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 1033061 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1853914 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17976734 # number of integer instructions +system.cpu1.num_func_calls 1024357 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1805296 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17715670 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 32611379 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12600410 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32157611 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12423544 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 72918750 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6543930 # number of times the CC registers were written -system.cpu1.num_mem_refs 7653523 # number of memory refs -system.cpu1.num_load_insts 4085696 # Number of load instructions -system.cpu1.num_store_insts 3567827 # Number of store instructions -system.cpu1.num_idle_cycles 5685220667.433728 # Number of idle cycles -system.cpu1.num_busy_cycles 51027625.566272 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008896 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991104 # Percentage of idle cycles -system.cpu1.Branches 2968133 # Number of branches fetched +system.cpu1.num_cc_register_reads 71811842 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6390929 # number of times the CC registers were written +system.cpu1.num_mem_refs 7557236 # number of memory refs +system.cpu1.num_load_insts 4032278 # Number of load instructions +system.cpu1.num_store_insts 3524958 # Number of store instructions +system.cpu1.num_idle_cycles 5685648636.968273 # Number of idle cycles +system.cpu1.num_busy_cycles 50588163.031727 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008819 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991181 # Percentage of idle cycles +system.cpu1.Branches 2908306 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12626391 62.17% 62.17% # Class of executed instruction -system.cpu1.op_class::IntMult 25909 0.13% 62.30% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3321 0.02% 62.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction -system.cpu1.op_class::MemRead 4085696 20.12% 82.43% # Class of executed instruction -system.cpu1.op_class::MemWrite 3567827 17.57% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12407832 62.06% 62.06% # Class of executed instruction +system.cpu1.op_class::IntMult 25890 0.13% 62.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3309 0.02% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::MemRead 4032278 20.17% 82.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 3524958 17.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 20309210 # Class of executed instruction +system.cpu1.op_class::total 19994333 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2726 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 187627 # number of replacements -system.cpu1.dcache.tags.tagsinuse 465.215072 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7146939 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187994 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.016846 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104853894000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.215072 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.908623 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.908623 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 52 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15057330 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15057330 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3659340 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3659340 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3255921 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3255921 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49714 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49714 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79782 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79782 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71812 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71812 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6915261 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6915261 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6964975 # number of overall hits -system.cpu1.dcache.overall_hits::total 6964975 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 134401 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 134401 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 90853 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 90853 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30496 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30496 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17326 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23466 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23466 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 225254 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 225254 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255750 # number of overall misses -system.cpu1.dcache.overall_misses::total 255750 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1931922000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1931922000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2253615359 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2253615359 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317972750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 317972750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 552026738 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 552026738 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2980000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2980000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4185537359 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4185537359 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4185537359 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4185537359 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3793741 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3793741 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3346774 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3346774 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80210 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80210 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97108 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97108 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95278 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95278 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7140515 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7140515 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7220725 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7220725 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035427 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035427 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027146 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027146 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380202 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380202 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178420 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178420 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246290 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246290 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031546 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031546 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035419 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035419 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14374.312691 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14374.312691 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24805.073679 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24805.073679 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18352.346185 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18352.346185 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23524.534987 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23524.534987 # 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Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 84 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14867676 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14867676 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3611065 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3611065 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3216741 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3216741 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48524 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48524 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78212 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78212 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70143 # 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average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23544.623771 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23544.623771 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18581.411913 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18581.411913 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16365.737474 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16365.737474 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18893.348708 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18893.348708 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16639.735666 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16639.735666 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1584,141 +1602,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 117066 # number of writebacks -system.cpu1.dcache.writebacks::total 117066 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12071 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12071 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 249 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 249 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 249 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134152 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 134152 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90853 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 90853 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29793 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29793 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5255 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5255 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23466 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23466 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 225005 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 225005 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254798 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254798 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724213250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724213250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2112235141 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2112235141 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 459472252 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 459472252 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82571000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82571000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 515647762 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 515647762 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2900500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2900500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3836448391 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3836448391 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4295920643 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4295920643 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406973750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406973750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 280407500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 280407500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 687381250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 687381250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035361 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035361 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027146 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027146 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.371437 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.371437 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054115 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054115 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246290 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246290 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031511 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031511 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035287 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035287 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12852.683896 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12852.683896 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23248.931142 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23248.931142 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.154600 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15422.154600 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15712.844910 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15712.844910 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21974.250490 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21974.250490 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 114520 # number of writebacks +system.cpu1.dcache.writebacks::total 114520 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 275 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12066 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12066 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 275 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 275 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132866 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 132866 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90456 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90456 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29572 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29572 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5172 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5172 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23491 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23491 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 223322 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 223322 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 252894 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 252894 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3084 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3084 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2437 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2437 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5521 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5521 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1717533750 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1717533750 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2155103647 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2155103647 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 472304765 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 472304765 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84734500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84734500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 516677243 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 516677243 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2366000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2366000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3872637397 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3872637397 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344942162 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4344942162 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406850750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406850750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 279944500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279944500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 686795250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 686795250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035486 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035486 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027351 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027351 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.375246 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.375246 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054185 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054185 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250881 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250881 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031671 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031671 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035468 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035468 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12926.811600 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12926.811600 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23824.883336 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23824.883336 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15971.350095 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15971.350095 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.313998 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.313998 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.689158 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.689158 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17050.502838 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17050.502838 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16860.103466 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16860.103466 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17341.047443 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17341.047443 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17180.882749 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17180.882749 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131923.070687 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131923.070687 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114872.589249 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114872.589249 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124396.893679 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124396.893679 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 506368 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.574535 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16242209 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 506880 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 32.043499 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84702777500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.574535 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973778 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973778 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 502966 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.575795 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15972373 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 503478 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.724073 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84694032500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.575795 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973781 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973781 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 34005058 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 34005058 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 16242209 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16242209 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16242209 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16242209 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16242209 # number of overall hits -system.cpu1.icache.overall_hits::total 16242209 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 506880 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 506880 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 506880 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 506880 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 506880 # number of overall misses -system.cpu1.icache.overall_misses::total 506880 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4441098014 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4441098014 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4441098014 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4441098014 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4441098014 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4441098014 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16749089 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16749089 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16749089 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16749089 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16749089 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16749089 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030263 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030263 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030263 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030263 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030263 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030263 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8761.635918 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8761.635918 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8761.635918 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8761.635918 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33455180 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33455180 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15972373 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15972373 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15972373 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15972373 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15972373 # number of overall hits +system.cpu1.icache.overall_hits::total 15972373 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 503478 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 503478 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 503478 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 503478 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 503478 # number of overall misses +system.cpu1.icache.overall_misses::total 503478 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4406075262 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4406075262 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4406075262 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4406075262 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4406075262 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4406075262 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16475851 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16475851 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16475851 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16475851 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16475851 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16475851 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030559 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030559 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030559 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030559 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030559 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030559 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8751.276644 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8751.276644 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8751.276644 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8751.276644 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8751.276644 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8751.276644 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1727,220 +1751,224 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3933409986 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933409986 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3933409986 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15446750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15446750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15446750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15446750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030263 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030263 # 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average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 503478 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 503478 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 503478 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 503478 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 503478 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 503478 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # 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Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.068283 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3300.044649 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1917.167815 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 684.742061 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.546005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000246 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201419 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.117015 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041793 # 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number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1668 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 493694 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 130314 # number of overall hits -system.cpu1.l2cache.overall_hits::total 628625 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 319 # number of ReadReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 8839.546228 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.119643 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.076473 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.274029 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1936.419828 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 726.511560 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.539523 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000129 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.194841 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.118190 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.044343 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.897153 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1124 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13429 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1096 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1612 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11521 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068604 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.819641 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 14679345 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 14679345 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3122 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1719 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 490518 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 100742 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 596101 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 114520 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 114520 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1111 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1111 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 866 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 866 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27369 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27369 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3122 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1719 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 490518 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 128111 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 623470 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3122 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1719 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 490518 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 128111 # number of overall hits +system.cpu1.l2cache.overall_hits::total 623470 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13186 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 66797 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 80569 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27938 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 27938 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22546 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22546 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33942 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33942 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 319 # number of demand (read+write) misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 12960 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 66868 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 80413 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27915 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 27915 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22615 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22615 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 10 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34061 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34061 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13186 # 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average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 278111.111111 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 278111.111111 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 28967.204738 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 28967.204738 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20694.834000 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22439.264722 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185238 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15203.520159 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17407.869349 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33326.302109 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15746.097009 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15746.097009 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15070.959850 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15070.959850 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 202850 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 202850 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30229.576224 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30229.576224 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20267.625828 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21217.453372 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20267.625828 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23191.967716 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 123920.719844 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 121441.045692 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107372.589249 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107372.589249 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116616.283282 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 115424.052299 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1026038 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 726618 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2443 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2443 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 117066 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 27637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75553 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41371 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 84221 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66421 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1014114 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 770781 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5251 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9223 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1799369 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32441028 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25029390 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7740 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 57491230 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 567913 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1404964 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.347502 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.476177 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1060646 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 722071 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2437 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 114520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 27384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75380 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41410 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85537 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 84086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66129 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1007310 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 764894 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5302 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9429 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1786935 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32223300 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24770860 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7944 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 57015864 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 636167 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1470628 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.384445 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.486464 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 916736 65.25% 65.25% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 488228 34.75% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 905253 61.56% 61.56% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 565375 38.44% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1404964 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 579509000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1470628 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 573017999 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80431999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81259000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 760939764 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 755831512 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 380431845 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 377529095 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5955000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5989250 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59423 # Transaction distribution -system.iobus.trans_dist::WriteResp 23199 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2154,11 +2188,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2179,11 +2213,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2223,23 +2257,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198981721 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 199086925 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36787516 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36785519 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.385318 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.391068 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 288337625000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.385318 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899082 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899082 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 288263513000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.391068 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899442 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899442 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2253,14 +2287,14 @@ system.iocache.demand_misses::realview.ide 255 # system.iocache.demand_misses::total 255 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 255 # number of overall misses system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32669377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32669377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649988828 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6649988828 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32669377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32669377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32669377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32669377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32671377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32671377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6655899029 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6655899029 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32671377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32671377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32671377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32671377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2277,19 +2311,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128115.203922 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128115.203922 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183579.638582 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183579.638582 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128115.203922 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128115.203922 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22637 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128123.047059 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128123.047059 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183742.795633 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183742.795633 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128123.047059 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128123.047059 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128123.047059 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128123.047059 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23173 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3456 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3543 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.550058 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.540502 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2303,14 +2337,14 @@ system.iocache.demand_mshr_misses::realview.ide 255 system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19398377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19398377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766308860 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766308860 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19398377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19398377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19398377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19398377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19404377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19404377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772213067 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772213067 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19404377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19404377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19404377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19404377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2319,290 +2353,303 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76072.066667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76072.066667 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131578.756073 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131578.756073 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76095.596078 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76095.596078 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131741.747653 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131741.747653 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76095.596078 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76095.596078 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76095.596078 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76095.596078 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 120296 # number of replacements -system.l2c.tags.tagsinuse 63905.436039 # Cycle average of tags in use -system.l2c.tags.total_refs 339434 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 184689 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.837868 # Average number of references to valid blocks. +system.l2c.tags.replacements 122211 # number of replacements +system.l2c.tags.tagsinuse 63914.238063 # Cycle average of tags in use +system.l2c.tags.total_refs 336222 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 186592 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.801910 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11082.113172 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.011404 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.058569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7219.690376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2883.100910 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39595.862719 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1402.790170 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 257.162663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1460.646056 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.169100 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 11496.547602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049900 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.062133 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7182.549375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2988.985612 # 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Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.003924 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022288 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975120 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33682 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 30706 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 154 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4910 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 28614 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1859 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 28608 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.513947 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.468536 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4789457 # Number of tag accesses -system.l2c.tags.data_accesses 4789457 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 70 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 29564 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 45272 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045608 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.592512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021045 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.005224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025783 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.975254 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32922 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31453 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 129 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4653 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 28140 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 241 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1916 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29284 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.502350 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.479935 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4784413 # Number of tag accesses +system.l2c.tags.data_accesses 4784413 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 62 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 29385 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 44972 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45934 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 27 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 29 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 10817 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 7566 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4637 # number of ReadReq hits +system.l2c.ReadReq_hits::total 143498 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 220641 # number of Writeback hits +system.l2c.Writeback_hits::total 220641 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2604 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 702 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3306 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 145 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 242 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 387 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4135 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1764 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5899 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 62 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 29385 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49107 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45934 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 27 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 10817 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164660 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.460351 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545748 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.551906 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74043.338888 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77776.541096 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 83286.026000 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.231729 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17823.284639 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17843.097730 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17983.333333 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.297940 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17850.852478 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76674.395959 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67752.447505 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73210.363422 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74381.215379 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 93514.850941 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83357.845597 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17858.360080 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17816.522710 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17848.279781 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17981.121339 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.105052 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17847.373333 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75573.120646 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68714.125894 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72839.152572 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75041.905525 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70867.323659 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82315.618920 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75041.905525 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70867.323659 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82315.618920 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166987.993706 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104443.668831 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 140460.599492 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143321.488823 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88788.879770 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 139019.116838 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155807.636110 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97528.548124 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 139866.468516 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 209058 # Transaction distribution -system.membus.trans_dist::ReadResp 209058 # Transaction distribution -system.membus.trans_dist::WriteReq 30943 # Transaction distribution -system.membus.trans_dist::WriteResp 30943 # Transaction distribution -system.membus.trans_dist::Writeback 128256 # Transaction distribution +system.membus.trans_dist::ReadReq 210102 # Transaction distribution +system.membus.trans_dist::ReadResp 210102 # Transaction distribution +system.membus.trans_dist::WriteReq 30889 # Transaction distribution +system.membus.trans_dist::WriteResp 30889 # Transaction distribution +system.membus.trans_dist::Writeback 129579 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40095 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13060 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.membus.trans_dist::ReadExReq 37613 # Transaction distribution -system.membus.trans_dist::ReadExResp 17283 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77022 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40122 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12986 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution +system.membus.trans_dist::ReadExReq 38648 # Transaction distribution +system.membus.trans_dist::ReadExResp 18121 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 634735 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 756359 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13636 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 639843 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 761429 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 865267 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 870337 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17575592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17765802 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17781832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17971968 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22401258 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125085 # Total snoops (count) -system.membus.snoop_fanout::samples 484369 # Request fanout histogram +system.membus.pkt_size::total 22607424 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125322 # Total snoops (count) +system.membus.snoop_fanout::samples 562672 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 484369 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 562672 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 484369 # Request fanout histogram -system.membus.reqLayer0.occupancy 88115000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 562672 # Request fanout histogram +system.membus.reqLayer0.occupancy 88118500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11425000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1105573957 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1114763998 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1100453088 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1110191376 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37520484 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37521481 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2877,44 +2949,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 476594 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 476579 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30943 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30943 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 220623 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 80382 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40416 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 120798 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 107 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50330 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50330 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1064234 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 261111 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1325345 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31566808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4207570 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 35774378 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 289326 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 860656 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.042449 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.201611 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 475433 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 475418 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 220641 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80215 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40509 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 120724 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50702 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50702 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1061225 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 262179 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1323404 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31467168 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4256160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 35723328 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 289388 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 934737 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039071 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.193764 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 824122 95.76% 95.76% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36534 4.24% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 898216 96.09% 96.09% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36521 3.91% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 860656 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 750507689 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 934737 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 749457686 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 653714719 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 652203239 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 219646363 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 220037759 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 08c475a80..c544f96e6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.903548 # Nu sim_ticks 2903547931500 # Number of ticks simulated final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 732027 # Simulator instruction rate (inst/s) -host_op_rate 882601 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18897780106 # Simulator tick rate (ticks/s) -host_mem_usage 614620 # Number of bytes of host memory used -host_seconds 153.65 # Real time elapsed on the host +host_inst_rate 571103 # Simulator instruction rate (inst/s) +host_op_rate 688575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14743405801 # Simulator tick rate (ticks/s) +host_mem_usage 560940 # Number of bytes of host memory used +host_seconds 196.94 # Real time elapsed on the host sim_insts 112472279 # Number of instructions simulated sim_ops 135607130 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -687,6 +687,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 698894 system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles @@ -735,12 +741,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187331.540240 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187331.540240 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163580.847439 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163580.847439 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176173.846783 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176173.846783 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1698619 # number of replacements system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use @@ -809,6 +815,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles @@ -831,10 +841,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 89783 # number of replacements system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use @@ -1024,6 +1034,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles @@ -1095,14 +1113,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173318.092042 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147983.478586 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150576.987205 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150576.987205 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162634.686771 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149039.616821 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution @@ -1126,19 +1144,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 53413 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3338113 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.019032 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.136637 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3274582 98.10% 98.10% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 63531 1.90% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3338113 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) @@ -1380,17 +1396,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 319985 # Request fanout histogram +system.membus.snoop_fanout::samples 387734 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 387734 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 319985 # Request fanout histogram +system.membus.snoop_fanout::total 387734 # Request fanout histogram system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 33aa26eaf..2cf9c3fee 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1291395 # Simulator instruction rate (inst/s) -host_op_rate 1572066 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25180347721 # Simulator tick rate (ticks/s) -host_mem_usage 616688 # Number of bytes of host memory used -host_seconds 110.56 # Real time elapsed on the host +host_inst_rate 898221 # Simulator instruction rate (inst/s) +host_op_rate 1093441 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17514028577 # Simulator tick rate (ticks/s) +host_mem_usage 560944 # Number of bytes of host memory used +host_seconds 158.95 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -973,17 +973,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359033 # Request fanout histogram +system.membus.snoop_fanout::samples 426666 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359033 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 426666 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359033 # Request fanout histogram +system.membus.snoop_fanout::total 426666 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1036,18 +1036,16 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36631 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272324 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011143 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104971 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3339957 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.020246 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.140841 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3235860 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 36464 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3272336 97.98% 97.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 67621 2.02% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272324 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3339957 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 7478799f2..5b65637a2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.903641 # Nu sim_ticks 2903640922500 # Number of ticks simulated final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 705602 # Simulator instruction rate (inst/s) -host_op_rate 850741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18218787173 # Simulator tick rate (ticks/s) -host_mem_usage 616688 # Number of bytes of host memory used -host_seconds 159.38 # Real time elapsed on the host +host_inst_rate 541770 # Simulator instruction rate (inst/s) +host_op_rate 653210 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13988619879 # Simulator tick rate (ticks/s) +host_mem_usage 561968 # Number of bytes of host memory used +host_seconds 207.57 # Real time elapsed on the host sim_insts 112456119 # Number of instructions simulated sim_ops 135587804 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -755,6 +755,15 @@ system.cpu0.dcache.demand_mshr_misses::total 699973 system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31142 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58736 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles @@ -824,15 +833,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181268.674931 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193354.234894 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187312.231071 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143051.398911 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191019.922007 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163557.186345 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 162020.531131 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192348.149366 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176152.180945 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1701384 # number of replacements system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use @@ -924,6 +933,10 @@ system.cpu0.icache.demand_mshr_misses::total 1701902 system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles @@ -955,10 +968,10 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1662,6 +1675,17 @@ system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 system.l2c.overall_mshr_misses::cpu1.inst 9421 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 79599 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 40164 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 67758 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 223750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 141000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574142498 # number of ReadReq MSHR miss cycles @@ -1769,17 +1793,17 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167244.026591 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179351.891094 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147970.993925 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 130046.334979 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178017.166836 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150553.109372 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148509.396818 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 178776.626841 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 149022.543464 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 70492 # Transaction distribution system.membus.trans_dist::ReadResp 70492 # Transaction distribution @@ -1810,17 +1834,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 313389 # Request fanout histogram +system.membus.snoop_fanout::samples 381147 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 313389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 381147 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 313389 # Request fanout histogram +system.membus.snoop_fanout::total 381147 # Request fanout histogram system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) @@ -1886,19 +1910,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 52269 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3285526 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011103 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104785 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3353284 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.021354 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144561 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3249046 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 36480 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3281678 97.86% 97.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 71606 2.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3285526 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3353284 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks) diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index e85225b4f..131e14cd8 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1049184 # Simulator instruction rate (inst/s) -host_op_rate 2147909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26808985343 # Simulator tick rate (ticks/s) -host_mem_usage 640900 # Number of bytes of host memory used -host_seconds 190.69 # Real time elapsed on the host +host_inst_rate 1219492 # Simulator instruction rate (inst/s) +host_op_rate 2496566 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31160731508 # Simulator tick rate (ticks/s) +host_mem_usage 598628 # Number of bytes of host memory used +host_seconds 164.06 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -368,8 +368,8 @@ system.cpu.l2cache.ReadReq_hits::cpu.data 1275199 # n system.cpu.l2cache.ReadReq_hits::total 2064118 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 179771 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 179771 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits @@ -387,8 +387,8 @@ system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 32163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 45524 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1807 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1807 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 134650 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 134650 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses @@ -427,8 +427,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001724 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987972 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987972 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428247 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.428247 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses @@ -471,20 +471,20 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 279335801 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 48002 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4017264 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011855 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108231 # Request fanout histogram +system.cpu.toL2Bus.snoops 49698 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 17890240 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002757 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.052432 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3969641 98.81% 98.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47623 1.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 17840921 99.72% 99.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 49319 0.28% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4017264 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 17890240 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -596,8 +596,8 @@ system.membus.trans_dist::WriteResp 13943 # Tr system.membus.trans_dist::Writeback 144777 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2545 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2093 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution system.membus.trans_dist::ReadExReq 134369 # Transaction distribution system.membus.trans_dist::ReadExResp 134364 # Transaction distribution system.membus.trans_dist::MessageReq 1696 # Transaction distribution @@ -606,11 +606,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462529 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205089 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462531 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205091 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141913 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 141913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28350394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28350396 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) @@ -621,17 +621,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034560 system.membus.pkt_size_system.iocache.mem_side::total 6034560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 49257977 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 374838 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 14247815 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.010910 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 374838 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 14246119 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 374838 # Request fanout histogram +system.membus.snoop_fanout::max_value 2 # Request fanout histogram +system.membus.snoop_fanout::total 14247815 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 3b1b184c8..999af0daa 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.184750 # Nu sim_ticks 5184749789500 # Number of ticks simulated final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 858252 # Simulator instruction rate (inst/s) -host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34581252938 # Simulator tick rate (ticks/s) -host_mem_usage 653812 # Number of bytes of host memory used -host_seconds 149.93 # Real time elapsed on the host +host_inst_rate 812427 # Simulator instruction rate (inst/s) +host_op_rate 1566083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32734861616 # Simulator tick rate (ticks/s) +host_mem_usage 599680 # Number of bytes of host memory used +host_seconds 158.39 # Real time elapsed on the host sim_insts 128677191 # Number of instructions simulated sim_ops 248045844 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -55,7 +55,7 @@ system.physmem.bytesReadSys 9871616 # To system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 1619 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9927 # Per bank write bursts system.physmem.perBankRdBursts::1 9220 # Per bank write bursts system.physmem.perBankRdBursts::2 9906 # Per bank write bursts @@ -259,12 +259,12 @@ system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Wr system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads -system.physmem.totQLat 1425327951 # Total ticks spent queuing -system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1425306951 # Total ticks spent queuing +system.physmem.totMemAccLat 4315600701 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9246.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27996.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s @@ -286,14 +286,14 @@ system.physmem_0.preEnergy 115846500 # En system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ) +system.physmem_0.actBackEnergy 133930593495 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2993365419750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3467346235185 # Total energy per rank (pJ) system.physmem_0.averagePower 668.758961 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 4979642480610 # Time in different power states system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31977087390 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) @@ -411,12 +411,12 @@ system.cpu.dcache.overall_misses::cpu.data 1634737 # system.cpu.dcache.overall_misses::total 1634737 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149973597 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12149973597 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24985949815 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24985949815 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24985949815 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24985949815 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) @@ -439,12 +439,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.737593 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.737593 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.785581 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20287.785581 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.385082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15284.385082 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked @@ -473,16 +473,22 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117329359 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117329359 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586088141 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22586088141 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213385641 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28213385641 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles @@ -501,20 +507,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.793240 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.793240 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18481.011862 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18481.011862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.423474 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.423474 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 164165.785509 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164165.785509 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186353.370221 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186353.370221 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 164690.242353 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 164690.242353 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use @@ -632,12 +638,12 @@ system.cpu.icache.demand_misses::cpu.inst 794984 # n system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses system.cpu.icache.overall_misses::total 794984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253068237 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11253068237 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11253068237 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11253068237 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11253068237 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11253068237 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses @@ -650,12 +656,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.087696 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14155.087696 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14155.087696 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14155.087696 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,24 +676,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 794984 system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055806763 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10055806763 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055806763 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10055806763 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055806763 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10055806763 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.068111 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.068111 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use @@ -812,8 +818,8 @@ system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # n system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits @@ -830,8 +836,8 @@ system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1358 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1358 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses @@ -843,21 +849,21 @@ system.cpu.l2cache.overall_misses::cpu.inst 12937 # system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses system.cpu.l2cache.overall_misses::total 154732 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049428751 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3391229783 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21365858 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 21365858 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1049428751 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12043716754 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1049428751 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12043716754 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses) @@ -883,8 +889,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.811231 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.811231 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses @@ -896,21 +902,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274 system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81118.400788 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.219079 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15733.326951 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15733.326951 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77835.979332 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77835.979332 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -925,8 +931,8 @@ system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1358 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1358 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses @@ -937,22 +943,28 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887274749 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10108385746 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887274749 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10108385746 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles @@ -963,8 +975,8 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811231 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811231 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses @@ -976,27 +988,27 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68584.273711 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.463507 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18192.812960 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18192.812960 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149863.747625 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149863.747625 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173260.311871 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173260.311871 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150416.781604 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150416.781604 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution @@ -1008,6 +1020,7 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) @@ -1018,27 +1031,27 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 54167 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram +system.cpu.toL2Bus.snoops 55819 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4616997 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.102742 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4567735 98.93% 98.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 49262 1.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4616997 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047835587 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1249,8 +1262,8 @@ system.membus.trans_dist::WriteResp 13916 # Tr system.membus.trans_dist::Writeback 126970 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1637 # Transaction distribution system.membus.trans_dist::ReadExReq 112993 # Transaction distribution system.membus.trans_dist::ReadExResp 112993 # Transaction distribution system.membus.trans_dist::MessageReq 1652 # Transaction distribution @@ -1259,11 +1272,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392332 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569788 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1714479 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) @@ -1274,28 +1287,28 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 1583 # Total snoops (count) -system.membus.snoop_fanout::samples 331203 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 921584 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001793 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.042301 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 919932 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331203 # Request fanout histogram +system.membus.snoop_fanout::max_value 2 # Request fanout histogram +system.membus.snoop_fanout::total 921584 # Request fanout histogram system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1034075968 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2159262414 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 456f8f93d..7d0bc2ece 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu sim_ticks 200409271000 # Number of ticks simulated final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10268281 # Simulator instruction rate (inst/s) -host_op_rate 10268278 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3928851236 # Simulator tick rate (ticks/s) -host_mem_usage 533084 # Number of bytes of host memory used -host_seconds 51.01 # Real time elapsed on the host +host_inst_rate 20752053 # Simulator instruction rate (inst/s) +host_op_rate 20752044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7940152278 # Simulator tick rate (ticks/s) +host_mem_usage 485568 # Number of bytes of host memory used +host_seconds 25.24 # Real time elapsed on the host sim_insts 523780905 # Number of instructions simulated sim_ops 523780905 # Number of ops (including micro ops) simulated drivesys.voltage_domain.voltage 1 # Voltage in Volts @@ -244,16 +244,16 @@ drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 572 drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes) drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes) drivesys.membus.snoops 0 # Total snoops (count) -drivesys.membus.snoop_fanout::samples 27109094 # Request fanout histogram -drivesys.membus.snoop_fanout::mean 0.790778 # Request fanout histogram -drivesys.membus.snoop_fanout::stdev 0.406753 # Request fanout histogram +drivesys.membus.snoop_fanout::samples 27247410 # Request fanout histogram +drivesys.membus.snoop_fanout::mean 0.786764 # Request fanout histogram +drivesys.membus.snoop_fanout::stdev 0.409593 # Request fanout histogram drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -drivesys.membus.snoop_fanout::0 5671825 20.92% 20.92% # Request fanout histogram -drivesys.membus.snoop_fanout::1 21437269 79.08% 100.00% # Request fanout histogram +drivesys.membus.snoop_fanout::0 5810141 21.32% 21.32% # Request fanout histogram +drivesys.membus.snoop_fanout::1 21437269 78.68% 100.00% # Request fanout histogram drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram -drivesys.membus.snoop_fanout::total 27109094 # Request fanout histogram +drivesys.membus.snoop_fanout::total 27247410 # Request fanout histogram drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received @@ -551,16 +551,16 @@ testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 572613 testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes) testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes) testsys.membus.snoops 0 # Total snoops (count) -testsys.membus.snoop_fanout::samples 28747524 # Request fanout histogram -testsys.membus.snoop_fanout::mean 0.787786 # Request fanout histogram -testsys.membus.snoop_fanout::stdev 0.408876 # Request fanout histogram +testsys.membus.snoop_fanout::samples 28885173 # Request fanout histogram +testsys.membus.snoop_fanout::mean 0.784032 # Request fanout histogram +testsys.membus.snoop_fanout::stdev 0.411493 # Request fanout histogram testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -testsys.membus.snoop_fanout::0 6100637 21.22% 21.22% # Request fanout histogram -testsys.membus.snoop_fanout::1 22646887 78.78% 100.00% # Request fanout histogram +testsys.membus.snoop_fanout::0 6238286 21.60% 21.60% # Request fanout histogram +testsys.membus.snoop_fanout::1 22646887 78.40% 100.00% # Request fanout histogram testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram -testsys.membus.snoop_fanout::total 28747524 # Request fanout histogram +testsys.membus.snoop_fanout::total 28885173 # Request fanout histogram testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.rxBytes 798 # Bytes Received @@ -619,11 +619,11 @@ sim_seconds 0.000407 # Nu sim_ticks 407341500 # Number of ticks simulated final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 5226750004 # Simulator instruction rate (inst/s) -host_op_rate 5225740576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4062718512 # Simulator tick rate (ticks/s) -host_mem_usage 533084 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 10415397218 # Simulator instruction rate (inst/s) +host_op_rate 10413013630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8095289719 # Simulator tick rate (ticks/s) +host_mem_usage 485568 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 523853183 # Number of instructions simulated sim_ops 523853183 # Number of ops (including micro ops) simulated drivesys.voltage_domain.voltage 1 # Voltage in Volts @@ -838,16 +838,16 @@ drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 1 drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes) drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes) drivesys.membus.snoops 0 # Total snoops (count) -drivesys.membus.snoop_fanout::samples 51723 # Request fanout histogram -drivesys.membus.snoop_fanout::mean 0.792723 # Request fanout histogram -drivesys.membus.snoop_fanout::stdev 0.405360 # Request fanout histogram +drivesys.membus.snoop_fanout::samples 52004 # Request fanout histogram +drivesys.membus.snoop_fanout::mean 0.788439 # Request fanout histogram +drivesys.membus.snoop_fanout::stdev 0.408419 # Request fanout histogram drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -drivesys.membus.snoop_fanout::0 10721 20.73% 20.73% # Request fanout histogram -drivesys.membus.snoop_fanout::1 41002 79.27% 100.00% # Request fanout histogram +drivesys.membus.snoop_fanout::0 11002 21.16% 21.16% # Request fanout histogram +drivesys.membus.snoop_fanout::1 41002 78.84% 100.00% # Request fanout histogram drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram -drivesys.membus.snoop_fanout::total 51723 # Request fanout histogram +drivesys.membus.snoop_fanout::total 52004 # Request fanout histogram drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1092,16 +1092,16 @@ testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 1163 testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes) testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes) testsys.membus.snoops 0 # Total snoops (count) -testsys.membus.snoop_fanout::samples 51694 # Request fanout histogram -testsys.membus.snoop_fanout::mean 0.792645 # Request fanout histogram -testsys.membus.snoop_fanout::stdev 0.405416 # Request fanout histogram +testsys.membus.snoop_fanout::samples 51975 # Request fanout histogram +testsys.membus.snoop_fanout::mean 0.788360 # Request fanout histogram +testsys.membus.snoop_fanout::stdev 0.408475 # Request fanout histogram testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -testsys.membus.snoop_fanout::0 10719 20.74% 20.74% # Request fanout histogram -testsys.membus.snoop_fanout::1 40975 79.26% 100.00% # Request fanout histogram +testsys.membus.snoop_fanout::0 11000 21.16% 21.16% # Request fanout histogram +testsys.membus.snoop_fanout::1 40975 78.84% 100.00% # Request fanout histogram testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram -testsys.membus.snoop_fanout::total 51694 # Request fanout histogram +testsys.membus.snoop_fanout::total 51975 # Request fanout histogram testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 0b52af291..6403398b5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -744,17 +744,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 94ce3d081..725976bdf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17398000 # Number of ticks simulated final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32773 # Simulator instruction rate (inst/s) -host_op_rate 38377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 124135140 # Simulator tick rate (ticks/s) -host_mem_usage 303432 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 57922 # Simulator instruction rate (inst/s) +host_op_rate 67825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219380871 # Simulator tick rate (ticks/s) +host_mem_usage 310080 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1162,19 +1162,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index a58641eea..835d1798d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1074,17 +1074,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 64 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.127237 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 439 87.28% 87.28% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 64 12.72% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 5334b6829..e88fbd103 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88081 # Simulator instruction rate (inst/s) -host_op_rate 103121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51657705 # Simulator tick rate (ticks/s) -host_mem_usage 292672 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 803078 # Simulator instruction rate (inst/s) +host_op_rate 938405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 469266934 # Simulator tick rate (ticks/s) +host_mem_usage 299548 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -347,16 +347,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram +system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram +system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index cc40f6f8e..d7a1f965a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99386 # Simulator instruction rate (inst/s) -host_op_rate 116351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58281162 # Simulator tick rate (ticks/s) -host_mem_usage 291652 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 829930 # Simulator instruction rate (inst/s) +host_op_rate 969708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 484799424 # Simulator tick rate (ticks/s) +host_mem_usage 298800 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -228,16 +228,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram +system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram +system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 578791a49..eccfa92c7 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -549,17 +549,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index ab4491575..66fb99cb1 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -896,17 +896,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 3bcc97a18..decb816ca 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 365210 # Simulator instruction rate (inst/s) -host_op_rate 661016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 380445830 # Simulator tick rate (ticks/s) -host_mem_usage 292780 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 96804 # Simulator instruction rate (inst/s) +host_op_rate 175298 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 100934348 # Simulator tick rate (ticks/s) +host_mem_usage 242164 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 1266607302 # Wr system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 7917 # Transaction distribution -system.membus.trans_dist::ReadResp 7917 # Transaction distribution -system.membus.trans_dist::WriteReq 935 # Transaction distribution -system.membus.trans_dist::WriteResp 935 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 8852 # Request fanout histogram -system.membus.snoop_fanout::mean 2.775418 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1988 22.46% 22.46% # Request fanout histogram -system.membus.snoop_fanout::3 6864 77.54% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 8852 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.membus.trans_dist::ReadReq 7917 # Transaction distribution +system.membus.trans_dist::ReadResp 7917 # Transaction distribution +system.membus.trans_dist::WriteReq 935 # Transaction distribution +system.membus.trans_dist::WriteResp 935 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 8852 # Request fanout histogram +system.membus.snoop_fanout::mean 0.775418 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1988 22.46% 22.46% # Request fanout histogram +system.membus.snoop_fanout::1 6864 77.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 8852 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 2ef89d07d..5185b356a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358500 # Number of ticks simulated final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 312703 # Simulator instruction rate (inst/s) -host_op_rate 566020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1645401799 # Simulator tick rate (ticks/s) -host_mem_usage 307640 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 97635 # Simulator instruction rate (inst/s) +host_op_rate 176805 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 514168344 # Simulator tick rate (ticks/s) +host_mem_usage 251928 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -423,17 +423,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index cffe156e4..5787f53df 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000500 # Number of ticks simulated final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1362402 # Simulator instruction rate (inst/s) -host_op_rate 1369187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 814125846 # Simulator tick rate (ticks/s) -host_mem_usage 428768 # Number of bytes of host memory used -host_seconds 66.50 # Real time elapsed on the host +host_inst_rate 1892320 # Simulator instruction rate (inst/s) +host_op_rate 1901744 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1130787212 # Simulator tick rate (ticks/s) +host_mem_usage 435148 # Number of bytes of host memory used +host_seconds 47.88 # Real time elapsed on the host sim_insts 90602408 # Number of instructions simulated sim_ops 91053639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 135031171 # Request fanout histogram -system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram +system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::3 107830771 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 135031171 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index c88ed3ac4..fd1fa8729 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -589,17 +589,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 844bb352a..c6a32009b 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1180838 # Simulator instruction rate (inst/s) -host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1262766288 # Simulator tick rate (ticks/s) -host_mem_usage 436624 # Number of bytes of host memory used -host_seconds 133.79 # Real time elapsed on the host +host_inst_rate 1204419 # Simulator instruction rate (inst/s) +host_op_rate 2120788 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1287982979 # Simulator tick rate (ticks/s) +host_mem_usage 383444 # Number of bytes of host memory used +host_seconds 131.17 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 1439319677 # Wr system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 308475611 # Transaction distribution -system.membus.trans_dist::ReadResp 308475611 # Transaction distribution -system.membus.trans_dist::WriteReq 31439752 # Transaction distribution -system.membus.trans_dist::WriteResp 31439752 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 339915363 # Request fanout histogram -system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram -system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 339915363 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.membus.trans_dist::ReadReq 308475611 # Transaction distribution +system.membus.trans_dist::ReadResp 308475611 # Transaction distribution +system.membus.trans_dist::WriteReq 31439752 # Transaction distribution +system.membus.trans_dist::WriteResp 31439752 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 339915363 # Request fanout histogram +system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram +system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 339915363 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 1b6566181..c01cc2902 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1735 +1,1809 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000730 # Number of seconds simulated -sim_ticks 729906500 # Number of ticks simulated -final_tick 729906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000790 # Number of seconds simulated +sim_ticks 789792500 # Number of ticks simulated +final_tick 789792500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 158517498 # Simulator tick rate (ticks/s) -host_mem_usage 277860 # Number of bytes of host memory used -host_seconds 4.60 # Real time elapsed on the host +host_tick_rate 129975147 # Simulator tick rate (ticks/s) +host_mem_usage 221936 # Number of bytes of host memory used +host_seconds 6.08 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 76606 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 79713 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 76745 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 78087 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 75189 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77277 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 77630 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 79795 # Number of bytes read from this memory -system.physmem.bytes_read::total 621042 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 386688 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5335 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5543 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5476 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5451 # Number of bytes written to this memory -system.physmem.bytes_written::total 430089 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10810 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6042 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5335 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5543 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5476 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49443 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 104953169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 109209878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 105143604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 106982196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 103011824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 105872464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 106356088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 109322221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 850851445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 529777444 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7329706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 7309155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7313265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7594123 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 7485890 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7502331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7458490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7468080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 589238485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 529777444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 112282875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 116519034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 112456869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 114576319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 110497714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 113374795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 113814578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 116790301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1440089929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 78179 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78681 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79146 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 76465 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 76157 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 75918 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79229 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 81414 # Number of bytes read from this memory +system.physmem.bytes_read::total 625189 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 393152 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5414 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5436 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5494 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5519 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5358 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5447 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5462 # Number of bytes written to this memory +system.physmem.bytes_written::total 436740 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10874 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87862 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6143 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5414 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5436 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5494 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5519 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5358 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5447 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5462 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49731 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 98986759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 99622369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 100211131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 96816569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 96426593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 96123982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 100316222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 103082772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 791586398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 497791509 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 6854965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6882820 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 6956257 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6987911 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6784060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 6910676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 6896748 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 6915741 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 552980688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 497791509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 105841724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 106505190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 107167389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 103804480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 103210653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 103034658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 107212970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 109998512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1344567086 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99153 # number of read accesses completed -system.cpu0.num_writes 54942 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22508 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.884164 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13343 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22908 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.582460 # Average number of references to valid blocks. +system.cpu0.num_reads 99211 # number of read accesses completed +system.cpu0.num_writes 54990 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22470 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.865816 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13332 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22858 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.583253 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.884164 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.769305 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.769305 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337372 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337372 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8651 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8651 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1083 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9734 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9734 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9734 # number of overall hits -system.cpu0.l1c.overall_hits::total 9734 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36335 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36335 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24086 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24086 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60421 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60421 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60421 # number of overall misses -system.cpu0.l1c.overall_misses::total 60421 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1008804376 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1008804376 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 935467464 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 935467464 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1944271840 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1944271840 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1944271840 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1944271840 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44986 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44986 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25169 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70155 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70155 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807696 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807696 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956971 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956971 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861250 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861250 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861250 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861250 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27763.984478 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 27763.984478 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38838.639209 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 38838.639209 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 32178.743152 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 32178.743152 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 32178.743152 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 32178.743152 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1068204 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 393.865816 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.769269 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.769269 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337265 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337265 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8594 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8594 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9737 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9737 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9737 # number of overall hits +system.cpu0.l1c.overall_hits::total 9737 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36367 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36367 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 24030 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 24030 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60397 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60397 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60397 # number of overall misses +system.cpu0.l1c.overall_misses::total 60397 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1097985534 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1097985534 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1003527320 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1003527320 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2101512854 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2101512854 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2101512854 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2101512854 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44961 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44961 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25173 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25173 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70134 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70134 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70134 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70134 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808857 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808857 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954594 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954594 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861166 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861166 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861166 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861166 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 30191.809443 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 30191.809443 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 41761.436538 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 41761.436538 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 34794.987400 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 34794.987400 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 34794.987400 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 34794.987400 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1144726 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61717 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61078 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.308100 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 18.742035 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9915 # number of writebacks -system.cpu0.l1c.writebacks::total 9915 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36335 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36335 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24086 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24086 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60421 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60421 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60421 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60421 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 953224016 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 953224016 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 898871386 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 898871386 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1852095402 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1852095402 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1852095402 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1852095402 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 743740324 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 743740324 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1921383275 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1921383275 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2665123599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2665123599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807696 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807696 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956971 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956971 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861250 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861250 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26234.319967 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26234.319967 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37319.247115 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37319.247115 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9946 # number of writebacks +system.cpu0.l1c.writebacks::total 9946 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36367 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36367 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24030 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 24030 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60397 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60397 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60397 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60397 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9956 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5416 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5416 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15372 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15372 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1042449014 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1042449014 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 966947420 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 966947420 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2009396434 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2009396434 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2009396434 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2009396434 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 778948863 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 778948863 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 2127994240 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 2127994240 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2906943103 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2906943103 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808857 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808857 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954594 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954594 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861166 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861166 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 28664.696401 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 28664.696401 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 40239.176862 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 40239.176862 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78239.138509 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78239.138509 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 392908.833087 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392908.833087 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 189106.368918 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 189106.368918 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 54938 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22377 # number of replacements -system.cpu1.l1c.tags.tagsinuse 394.468790 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13456 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.590564 # Average number of references to valid blocks. +system.cpu1.num_writes 55318 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22177 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.980771 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13598 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22566 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.602588 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 394.468790 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.770447 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.770447 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338150 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338150 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8709 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8709 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1179 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1179 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9888 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9888 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9888 # number of overall hits -system.cpu1.l1c.overall_hits::total 9888 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36587 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36587 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23856 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23856 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60443 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60443 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60443 # number of overall misses -system.cpu1.l1c.overall_misses::total 60443 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1017715976 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1017715976 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 924313604 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 924313604 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1942029580 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1942029580 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1942029580 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1942029580 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45296 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45296 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25035 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70331 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70331 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70331 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70331 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807731 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807731 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.952906 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.952906 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859408 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859408 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859408 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859408 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27816.327548 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 27816.327548 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38745.540074 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 38745.540074 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 32129.933657 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 32129.933657 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 32129.933657 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 32129.933657 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1075887 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.980771 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.769494 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.769494 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338430 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338430 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8884 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8884 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1068 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1068 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9952 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9952 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9952 # number of overall hits +system.cpu1.l1c.overall_hits::total 9952 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36538 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36538 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23930 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23930 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60468 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60468 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60468 # number of overall misses +system.cpu1.l1c.overall_misses::total 60468 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1108002821 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1108002821 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 993849096 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 993849096 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2101851917 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2101851917 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2101851917 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2101851917 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45422 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45422 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24998 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24998 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70420 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70420 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70420 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70420 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804412 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.804412 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.957277 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.957277 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858677 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858677 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858677 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858677 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 30324.670781 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 30324.670781 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 41531.512578 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 41531.512578 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 34759.739317 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 34759.739317 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 34759.739317 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 34759.739317 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1147241 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62059 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61428 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.336518 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 18.676190 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9753 # number of writebacks -system.cpu1.l1c.writebacks::total 9753 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36587 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36587 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23856 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23856 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60443 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60443 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 961736168 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 961736168 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 888050076 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 888050076 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1849786244 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1849786244 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1849786244 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1849786244 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 753708733 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 753708733 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1923800282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1923800282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2677509015 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2677509015 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807731 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807731 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952906 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952906 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859408 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859408 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26286.281138 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26286.281138 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37225.439135 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37225.439135 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9780 # number of writebacks +system.cpu1.l1c.writebacks::total 9780 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36538 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36538 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23930 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23930 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60468 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60468 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60468 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 10010 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 10010 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5438 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15448 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15448 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1052180887 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1052180887 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 957433148 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 957433148 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2009614035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2009614035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2009614035 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2009614035 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 780874824 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 780874824 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 2141613646 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 2141613646 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2922488470 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2922488470 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804412 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804412 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.957277 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.957277 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858677 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858677 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 28796.893289 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 28796.893289 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 40009.742917 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 40009.742917 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78009.472927 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78009.472927 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 393823.767194 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 393823.767194 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 189182.319394 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 189182.319394 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99515 # number of read accesses completed -system.cpu2.num_writes 55356 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22413 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.491739 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22815 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.589437 # Average number of references to valid blocks. +system.cpu2.num_reads 99906 # number of read accesses completed +system.cpu2.num_writes 55186 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22429 # number of replacements +system.cpu2.l1c.tags.tagsinuse 394.168243 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13360 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.585605 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.491739 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.770492 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.770492 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338294 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338294 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8726 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8726 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1175 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1175 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9901 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9901 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9901 # number of overall hits -system.cpu2.l1c.overall_hits::total 9901 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36442 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36442 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24017 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24017 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses -system.cpu2.l1c.overall_misses::total 60459 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1013968188 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1013968188 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 926155084 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 926155084 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1940123272 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1940123272 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1940123272 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1940123272 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45168 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25192 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25192 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70360 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70360 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806810 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806810 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953358 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953358 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859281 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859281 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859281 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859281 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27824.164096 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 27824.164096 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38562.480077 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 38562.480077 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 32089.900131 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 32089.900131 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 32089.900131 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 32089.900131 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1067763 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 394.168243 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.769860 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.769860 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338029 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338029 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8660 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8660 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1124 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1124 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9784 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9784 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9784 # number of overall hits +system.cpu2.l1c.overall_hits::total 9784 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36507 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36507 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24000 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24000 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60507 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60507 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60507 # number of overall misses +system.cpu2.l1c.overall_misses::total 60507 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1106428919 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1106428919 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1000960978 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1000960978 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2107389897 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2107389897 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2107389897 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2107389897 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45167 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45167 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70291 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70291 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70291 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70291 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808267 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.808267 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955262 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955262 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860807 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860807 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860807 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860807 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 30307.308708 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 30307.308708 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 41706.707417 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 41706.707417 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 34828.861074 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 34828.861074 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 34828.861074 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 34828.861074 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1143492 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 61601 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.333534 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 18.666514 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9861 # number of writebacks -system.cpu2.l1c.writebacks::total 9861 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36442 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36442 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24017 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24017 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958233322 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958233322 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 889641050 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 889641050 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847874372 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1847874372 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847874372 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1847874372 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 744958366 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 744958366 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1919549279 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1919549279 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2664507645 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2664507645 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806810 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806810 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953358 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953358 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859281 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859281 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26294.751166 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26294.751166 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37042.138902 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37042.138902 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9834 # number of writebacks +system.cpu2.l1c.writebacks::total 9834 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36507 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36507 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24000 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60507 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60507 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60507 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60507 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9899 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9899 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5496 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5496 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15395 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1050702877 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1050702877 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 964435030 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 964435030 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2015137907 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2015137907 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2015137907 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2015137907 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 774345338 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 774345338 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 2129438676 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 2129438676 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2903784014 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2903784014 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808267 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808267 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955262 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955262 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860807 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860807 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 28780.860575 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 28780.860575 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 40184.792917 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 40184.792917 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78224.602283 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78224.602283 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 387452.451965 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 387452.451965 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 188618.643326 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 188618.643326 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99509 # number of read accesses completed -system.cpu3.num_writes 55322 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22357 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.352238 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13564 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22743 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.596403 # Average number of references to valid blocks. +system.cpu3.num_reads 99687 # number of read accesses completed +system.cpu3.num_writes 54914 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22514 # number of replacements +system.cpu3.l1c.tags.tagsinuse 394.486423 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13398 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22905 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.584938 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.352238 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770219 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770219 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338647 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338647 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8763 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8763 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1221 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1221 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9984 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9984 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9984 # number of overall hits -system.cpu3.l1c.overall_hits::total 9984 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36641 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36641 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23832 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23832 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60473 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60473 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60473 # number of overall misses -system.cpu3.l1c.overall_misses::total 60473 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1024295614 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1024295614 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 922064777 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 922064777 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1946360391 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1946360391 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1946360391 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1946360391 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45404 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45404 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25053 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25053 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70457 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70457 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70457 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70457 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806999 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806999 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.951263 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.951263 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858297 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858297 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858297 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858297 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27954.903360 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 27954.903360 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38690.197088 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 38690.197088 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 32185.609958 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 32185.609958 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 32185.609958 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 32185.609958 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1061792 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 394.486423 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.770481 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.770481 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 351 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337490 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337490 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8775 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8775 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1091 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1091 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9866 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9866 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9866 # number of overall hits +system.cpu3.l1c.overall_hits::total 9866 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36393 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36393 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23929 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23929 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60322 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60322 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60322 # number of overall misses +system.cpu3.l1c.overall_misses::total 60322 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1101223942 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1101223942 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 999641040 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 999641040 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2100864982 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2100864982 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2100864982 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2100864982 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45168 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25020 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25020 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70188 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70188 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70188 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70188 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805725 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805725 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956395 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956395 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859435 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859435 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859435 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859435 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 30259.224082 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 30259.224082 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 41775.295248 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 41775.295248 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 34827.508736 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 34827.508736 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 34827.508736 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 34827.508736 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1140042 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61430 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 60968 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.284584 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 18.699022 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9814 # number of writebacks -system.cpu3.l1c.writebacks::total 9814 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36641 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23832 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60473 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60473 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 968238306 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 968238306 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 885855695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 885855695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1854094001 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1854094001 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1854094001 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1854094001 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 733819505 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 733819505 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1976786114 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1976786114 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2710605619 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2710605619 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806999 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.951263 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.951263 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858297 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858297 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26424.996752 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26424.996752 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37170.849908 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37170.849908 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9981 # number of writebacks +system.cpu3.l1c.writebacks::total 9981 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36393 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36393 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23929 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60322 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60322 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60322 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60322 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9906 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5522 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15428 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1045674368 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1045674368 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 963227618 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 963227618 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2008901986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2008901986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2008901986 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2008901986 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 776644993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 776644993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 2134037166 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 2134037166 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2910682159 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2910682159 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805725 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805725 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956395 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956395 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859435 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859435 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 28732.843349 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 28732.843349 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 40253.567554 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 40253.567554 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78401.473148 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78401.473148 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 386460.913799 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 386460.913799 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 188662.312613 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 188662.312613 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99688 # number of read accesses completed -system.cpu4.num_writes 55538 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22215 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.788113 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13621 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22618 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.602219 # Average number of references to valid blocks. +system.cpu4.num_reads 99646 # number of read accesses completed +system.cpu4.num_writes 55076 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22475 # number of replacements +system.cpu4.l1c.tags.tagsinuse 394.666578 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13432 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587243 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.788113 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.765211 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.765211 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 365 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338206 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338206 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8861 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8861 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1198 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1198 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits -system.cpu4.l1c.overall_hits::total 10059 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36318 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36318 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24000 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24000 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60318 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60318 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60318 # number of overall misses -system.cpu4.l1c.overall_misses::total 60318 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1007698293 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1007698293 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 930213172 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 930213172 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1937911465 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1937911465 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1937911465 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1937911465 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45179 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45179 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25198 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25198 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70377 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70377 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70377 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70377 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803869 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.803869 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952457 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952457 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857070 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857070 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857070 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857070 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27746.524946 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 27746.524946 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38758.882167 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 38758.882167 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 32128.244720 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 32128.244720 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 32128.244720 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 32128.244720 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1066740 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 394.666578 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.770833 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.770833 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338590 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338590 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8683 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8683 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1163 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1163 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9846 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9846 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9846 # number of overall hits +system.cpu4.l1c.overall_hits::total 9846 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36657 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36657 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23918 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23918 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60575 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60575 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60575 # number of overall misses +system.cpu4.l1c.overall_misses::total 60575 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1108449638 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1108449638 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 999797609 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 999797609 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2108247247 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2108247247 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2108247247 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2108247247 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45340 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45340 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25081 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25081 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70421 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70421 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70421 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70421 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808491 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.808491 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953630 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953630 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.860184 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.860184 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.860184 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.860184 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 30238.416619 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 30238.416619 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 41801.053976 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 41801.053976 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 34803.916583 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 34803.916583 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 34803.916583 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 34803.916583 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1151337 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61639 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61602 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.306251 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 18.689929 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9826 # number of writebacks -system.cpu4.l1c.writebacks::total 9826 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36318 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36318 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24000 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60318 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60318 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60318 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60318 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 952156937 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 952156937 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 893690718 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 893690718 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1845847655 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1845847655 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1845847655 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1845847655 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748268844 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748268844 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1945456088 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1945456088 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2693724932 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2693724932 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803869 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803869 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952457 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952457 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857070 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857070 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26217.218377 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26217.218377 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37237.113250 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37237.113250 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9802 # number of writebacks +system.cpu4.l1c.writebacks::total 9802 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36657 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36657 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23918 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60575 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60575 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60575 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60575 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9982 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5360 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5360 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15342 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15342 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1052462662 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1052462662 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 963409159 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 963409159 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2015871821 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2015871821 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2015871821 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2015871821 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 780487806 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 780487806 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 2113182760 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 2113182760 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2893670566 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2893670566 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808491 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808491 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953630 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953630 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.860184 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.860184 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 28711.096435 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 28711.096435 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 40279.670499 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 40279.670499 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78189.521739 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78189.521739 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 394250.514925 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 394250.514925 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 188611.039369 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 188611.039369 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98777 # number of read accesses completed -system.cpu5.num_writes 55102 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22389 # number of replacements -system.cpu5.l1c.tags.tagsinuse 394.368473 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13612 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.597411 # Average number of references to valid blocks. +system.cpu5.num_reads 99659 # number of read accesses completed +system.cpu5.num_writes 54989 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22353 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.762821 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13360 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22726 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.587873 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 394.368473 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.770251 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.770251 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338353 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338353 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8788 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8788 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1200 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1200 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9988 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9988 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9988 # number of overall hits -system.cpu5.l1c.overall_hits::total 9988 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36608 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36608 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23815 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23815 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60423 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60423 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60423 # number of overall misses -system.cpu5.l1c.overall_misses::total 60423 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1017800983 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1017800983 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 926597102 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 926597102 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1944398085 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1944398085 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1944398085 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1944398085 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45396 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45396 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25015 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25015 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70411 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70411 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70411 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70411 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806415 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806415 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952029 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952029 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858147 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858147 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858147 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858147 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27802.692936 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 27802.692936 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38908.129414 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 38908.129414 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 32179.767390 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 32179.767390 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 32179.767390 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 32179.767390 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1064852 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.762821 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.767115 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.767115 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 325 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.728516 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337942 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337942 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8666 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8666 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1136 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1136 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9802 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9802 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9802 # number of overall hits +system.cpu5.l1c.overall_hits::total 9802 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36641 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36641 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23834 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23834 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60475 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60475 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60475 # number of overall misses +system.cpu5.l1c.overall_misses::total 60475 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1106472248 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1106472248 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 994607245 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 994607245 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2101079493 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2101079493 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2101079493 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2101079493 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45307 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45307 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24970 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24970 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70277 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70277 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70277 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70277 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808727 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808727 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954505 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954505 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860523 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860523 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860523 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860523 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 30197.654212 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 30197.654212 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 41730.605228 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 41730.605228 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 34742.943249 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 34742.943249 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 34742.943249 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 34742.943249 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1144155 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61539 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61191 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.303694 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 18.698093 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9851 # number of writebacks -system.cpu5.l1c.writebacks::total 9851 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36608 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23815 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60423 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60423 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 961777191 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 961777191 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890427492 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890427492 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1852204683 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1852204683 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1852204683 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1852204683 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 736504009 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 736504009 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1948720715 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1948720715 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2685224724 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2685224724 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806415 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806415 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952029 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952029 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858147 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858147 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26272.322744 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26272.322744 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37389.355112 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37389.355112 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9829 # number of writebacks +system.cpu5.l1c.writebacks::total 9829 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36641 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23834 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23834 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60475 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60475 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5460 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5460 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15394 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15394 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1050521774 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1050521774 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 958365245 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 958365245 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2008887019 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2008887019 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2008887019 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2008887019 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 778256892 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 778256892 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 2141596587 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 2141596587 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2919853479 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2919853479 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808727 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808727 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954505 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954505 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860523 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860523 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 28670.663301 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 28670.663301 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 40210.004405 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 40210.004405 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78342.751359 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78342.751359 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 392233.807143 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392233.807143 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 189674.774523 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 189674.774523 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99339 # number of read accesses completed -system.cpu6.num_writes 55520 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22403 # number of replacements -system.cpu6.l1c.tags.tagsinuse 393.263413 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13582 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22789 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.595989 # Average number of references to valid blocks. +system.cpu6.num_reads 99691 # number of read accesses completed +system.cpu6.num_writes 55108 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22433 # number of replacements +system.cpu6.l1c.tags.tagsinuse 394.732703 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13465 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.590234 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 393.263413 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.768093 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.768093 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338803 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338803 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8815 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8815 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1164 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1164 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9979 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9979 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9979 # number of overall hits -system.cpu6.l1c.overall_hits::total 9979 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36385 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36385 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24126 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24126 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60511 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60511 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60511 # number of overall misses -system.cpu6.l1c.overall_misses::total 60511 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1008730718 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1008730718 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 936995994 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 936995994 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1945726712 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1945726712 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1945726712 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1945726712 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45200 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45200 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25290 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25290 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70490 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70490 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70490 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70490 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804978 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.804978 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953974 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858434 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858434 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858434 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858434 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27723.807008 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 27723.807008 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38837.602338 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 38837.602338 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 32154.925749 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 32154.925749 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 32154.925749 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 32154.925749 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1063684 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 394.732703 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.770962 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.770962 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 339043 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 339043 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8806 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8806 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9950 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9950 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9950 # number of overall hits +system.cpu6.l1c.overall_hits::total 9950 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36628 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36628 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23944 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23944 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60572 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60572 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60572 # number of overall misses +system.cpu6.l1c.overall_misses::total 60572 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1115774950 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1115774950 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 994580574 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 994580574 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2110355524 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2110355524 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2110355524 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2110355524 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45434 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45434 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25088 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25088 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70522 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70522 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70522 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70522 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806180 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806180 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954401 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954401 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858909 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858909 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858909 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858909 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 30462.349842 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 30462.349842 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 41537.778734 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 41537.778734 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 34840.446477 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 34840.446477 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 34840.446477 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 34840.446477 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1141787 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61545 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61213 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.283029 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 18.652688 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9842 # number of writebacks -system.cpu6.l1c.writebacks::total 9842 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36385 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36385 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24126 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24126 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60511 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60511 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60511 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60511 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 953086366 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 953086366 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 900293024 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 900293024 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1853379390 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1853379390 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1853379390 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1853379390 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 738599910 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 738599910 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1965255677 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1965255677 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2703855587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2703855587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804978 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804978 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953974 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858434 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858434 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26194.485805 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26194.485805 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37316.298765 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37316.298765 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9839 # number of writebacks +system.cpu6.l1c.writebacks::total 9839 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36628 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36628 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23944 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60572 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60572 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60572 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60572 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5449 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1059827480 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1059827480 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 958175570 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 958175570 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2018003050 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2018003050 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2018003050 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2018003050 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767222409 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767222409 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 2138123651 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 2138123651 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2905346060 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2905346060 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806180 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806180 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954401 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954401 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858909 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858909 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 28934.898984 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 28934.898984 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 40017.355914 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 40017.355914 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78367.968233 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78367.968233 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 392388.264085 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392388.264085 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 190652.015224 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 190652.015224 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99565 # number of read accesses completed -system.cpu7.num_writes 55051 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22600 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.642544 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13380 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22986 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.582093 # Average number of references to valid blocks. +system.cpu7.num_reads 99881 # number of read accesses completed +system.cpu7.num_writes 55258 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22490 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.773487 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13394 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22887 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.585223 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.642544 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.770786 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.770786 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338392 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338392 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8664 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8664 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1142 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1142 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9806 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9806 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9806 # number of overall hits -system.cpu7.l1c.overall_hits::total 9806 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36635 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36635 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23923 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23923 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60558 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60558 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60558 # number of overall misses -system.cpu7.l1c.overall_misses::total 60558 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1023029462 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1023029462 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 929610099 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 929610099 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1952639561 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1952639561 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1952639561 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1952639561 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25065 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70364 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70364 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70364 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70364 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808737 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.808737 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954438 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954438 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860639 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860639 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860639 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860639 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27924.920486 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 27924.920486 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38858.424905 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 38858.424905 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 32244.122346 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 32244.122346 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 32244.122346 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 32244.122346 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1066072 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 394.773487 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.771042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.771042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 361 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338728 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338728 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8705 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8705 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1114 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1114 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9819 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9819 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9819 # number of overall hits +system.cpu7.l1c.overall_hits::total 9819 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36637 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36637 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23983 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23983 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60620 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60620 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60620 # number of overall misses +system.cpu7.l1c.overall_misses::total 60620 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1106293724 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1106293724 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1002572296 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1002572296 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2108866020 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2108866020 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2108866020 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2108866020 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45342 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45342 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25097 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25097 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70439 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70439 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70439 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70439 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808015 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.808015 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955612 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955612 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860603 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860603 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860603 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860603 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 30196.078391 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 30196.078391 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 41803.456448 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 41803.456448 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 34788.288024 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 34788.288024 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 34788.288024 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 34788.288024 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1141532 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61535 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61288 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.324645 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 18.625702 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9831 # number of writebacks -system.cpu7.l1c.writebacks::total 9831 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36635 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36635 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23923 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23923 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60558 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60558 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60558 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60558 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 966974672 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 966974672 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 893289987 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 893289987 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1860264659 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1860264659 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1860264659 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1860264659 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 731988929 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 731988929 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1960595657 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1960595657 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2692584586 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2692584586 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808737 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808737 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954438 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954438 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860639 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860639 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26394.832046 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26394.832046 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37340.215985 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37340.215985 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9784 # number of writebacks +system.cpu7.l1c.writebacks::total 9784 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36637 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23983 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60620 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60620 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60620 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60620 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9862 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5465 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5465 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15327 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15327 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1050368666 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1050368666 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 966121280 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 966121280 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2016489946 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2016489946 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2016489946 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2016489946 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 770060879 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 770060879 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 2135523645 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 2135523645 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2905584524 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2905584524 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808015 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808015 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955612 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955612 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860603 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860603 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 28669.614488 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 28669.614488 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 40283.587541 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 40283.587541 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78083.642162 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78083.642162 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 390763.704483 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 390763.704483 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 189572.944738 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 189572.944738 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12974 # number of replacements -system.l2c.tags.tagsinuse 782.339791 # Cycle average of tags in use -system.l2c.tags.total_refs 149980 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13746 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.910810 # Average number of references to valid blocks. +system.l2c.tags.replacements 12865 # number of replacements +system.l2c.tags.tagsinuse 778.482244 # Cycle average of tags in use +system.l2c.tags.total_refs 150454 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13664 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.010978 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 728.962494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.892190 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.186949 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.375204 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.806314 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.399875 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.389081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.432209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.895475 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.711877 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007019 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006226 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006647 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006250 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006281 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764004 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 772 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 551 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1963370 # Number of tag accesses -system.l2c.tags.data_accesses 1963370 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10704 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10790 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10626 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10750 # 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number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5113 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5101 # number of demand (read+write) misses -system.l2c.demand_misses::total 40754 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5121 # number of overall misses -system.l2c.overall_misses::cpu1 5114 # number of overall misses -system.l2c.overall_misses::cpu2 5067 # number of overall misses -system.l2c.overall_misses::cpu3 5063 # number of overall misses -system.l2c.overall_misses::cpu4 5102 # number of overall misses -system.l2c.overall_misses::cpu5 5073 # number of overall misses -system.l2c.overall_misses::cpu6 5113 # number of overall misses -system.l2c.overall_misses::cpu7 5101 # number of overall misses -system.l2c.overall_misses::total 40754 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 40741945 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 44011935 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 41982431 # 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number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 56606999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 452649995 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 243244959 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 240870461 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 239571460 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 239260458 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 242194954 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 240150463 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 242838464 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 239503467 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1927634686 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 283986904 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 91101 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 75955 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 75955 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2280 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2211 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2259 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2295 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2293 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18292 # 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miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.848485 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851262 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.851852 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.845855 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.859732 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.858264 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.852832 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.695034 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.693701 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.695066 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.691139 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.702155 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.065793 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.555833 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.650782 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.161030 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.709195 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.005802 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006453 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006609 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.005924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006402 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006495 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.760237 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 799 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 529 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.780273 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1961721 # Number of tag accesses +system.l2c.tags.data_accesses 1961721 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10688 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10718 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10681 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10576 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10796 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10643 # 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number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 680 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 698 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5369 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 2017 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2027 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2036 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2040 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2009 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1982 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1969 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2002 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16082 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4591 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4534 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4582 # 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number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 75954 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 75954 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2310 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2295 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2298 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2265 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2248 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2278 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18274 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6311 # 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miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.885033 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.874238 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.875055 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.875890 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.878841 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880048 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.727460 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.722090 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.730548 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.724988 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717829 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.726705 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.715905 # 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miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.298855 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.298473 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.294470 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.300525 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.291909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.303873 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.297448 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60390.740506 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61394.381368 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61453.606368 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61192.859112 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 60431.632777 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61890.053812 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61174.914706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 60878.852436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61108.128143 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30275.160635 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 30610.754810 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 30825.884086 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30288.479902 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28343.454455 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 30092.078708 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29379.632301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29716.782717 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29945.839634 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54781.955130 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54618.652404 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54659.601702 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54677.013734 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54851.685137 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54590.629296 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54679.671648 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54794.138511 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54706.996788 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55460.636416 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55510.229841 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55549.921676 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55489.007443 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55550.636951 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55507.683756 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55535.136549 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55580.935532 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55523.253539 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55460.636416 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55510.229841 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55549.921676 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55489.007443 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55550.636951 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55507.683756 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55535.136549 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55580.935532 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55523.253539 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 8422 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1439 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1138 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.295344 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.400703 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6042 # number of writebacks -system.l2c.writebacks::total 6042 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6144 # number of writebacks +system.l2c.writebacks::total 6144 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::total 23 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 662 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 705 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 678 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 691 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 663 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 677 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 662 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 707 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5445 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1985 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1941 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1876 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1922 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1955 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1959 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1992 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1967 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15597 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4445 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4400 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4378 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4367 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4441 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35235 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5107 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5105 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5058 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5093 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5064 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5103 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5094 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40680 # 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number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 32539439 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 33571932 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 33370421 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 35357421 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 270275455 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 83067491 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81344988 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78653997 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 80593493 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81980984 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 82268488 # 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number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1499819054 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 221587387 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 222698881 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 219929872 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 220451383 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 220969379 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 220483880 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 222363367 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 221610360 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1770094509 # 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number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 413234441 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 407408946 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 415648431 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 408376439 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 410035928 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406831940 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3293198967 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 229215970 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 228786954 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 227259971 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 236423452 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 233573451 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 234334469 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233635458 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 232899980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1856129705 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 641862881 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 647802885 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 640494412 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 643832398 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 649221882 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 642710908 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 643671386 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 639731920 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5149328672 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.058203 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.061310 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.059936 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060376 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.058163 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.059553 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.058465 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062121 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.059769 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.855235 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851316 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.848485 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850819 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851852 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845855 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.859732 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.857828 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.852668 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.694097 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.692913 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.694590 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.690981 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.701838 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698122 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.698161 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.695576 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.695780 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.287000 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.287000 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49027.101208 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50060.902128 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49440.893805 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49444.918958 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49079.093514 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49589.264402 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50408.490937 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50010.496464 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49637.365473 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41847.602519 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41908.803709 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41926.437633 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41932.098335 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41934.007161 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41995.144461 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41868.713855 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41893.742755 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41912.990383 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42549.256693 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42592.260227 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42578.562357 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42657.417907 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42534.975169 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42605.869159 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42556.394055 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42455.650558 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42566.171534 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.demand_mshr_hits::cpu0 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 63 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 628 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 680 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 688 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 646 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 652 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 666 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 693 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5329 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2017 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2027 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2034 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2040 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2008 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1968 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2002 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16078 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4588 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4530 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4579 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4586 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4599 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4651 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4482 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4697 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 36712 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5216 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5210 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5267 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5232 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5251 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5317 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5390 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42041 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5216 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5210 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5267 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5232 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5251 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5317 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5390 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42041 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 10009 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9898 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 79337 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5436 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5494 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5519 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5358 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5458 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5448 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5462 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43589 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15370 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15445 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15392 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15425 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15340 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15392 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15238 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15324 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122926 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 30458949 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 33700940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 34051940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 31884439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 31746444 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 33289946 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 33296940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 33931439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 262361037 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 84760496 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 85183996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 85374489 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85565499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 84458998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83295996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82516991 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 84106992 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 675263457 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 195759954 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192669961 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 194828295 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 195239452 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 196619949 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 197755466 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 190831957 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 200614450 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1564319484 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 226218903 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 226370901 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 228880235 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 227123891 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 228366393 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 231045412 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 224128897 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 234545889 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1826680521 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 226218903 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 226370901 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 228880235 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 227123891 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 228366393 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 231045412 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 224128897 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 234545889 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1826680521 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420391962 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 422439462 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417792957 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 418505281 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 421118468 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 419294453 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413123964 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416090788 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3348757335 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 237106474 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237782975 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 241705476 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 241076980 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 235943478 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 241042480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 238750464 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 240064477 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1913472804 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 657498436 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 660222437 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 659498433 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 659582261 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 657061946 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 660336933 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 651874428 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 656155265 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5262230139 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055477 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.059623 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.060499 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.057530 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.056918 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058876 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061338 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.058679 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877489 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.886275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885033 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.873803 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875055 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.875445 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878841 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.879829 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726985 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.721452 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730070 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.724830 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717361 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.725925 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.715746 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.726415 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.723603 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297002 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297002 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48501.511146 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49560.205882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49494.098837 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49356.716718 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48690.865031 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49984.903904 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49255.828402 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 48963.115440 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49232.696003 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42023.052058 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42024.665022 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41973.691740 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.872059 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42061.253984 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42026.234107 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41929.365346 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42011.484515 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41999.219866 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42667.819093 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42532.000221 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42548.219043 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42572.928914 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42752.761252 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42518.913352 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42577.411200 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42711.187992 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42610.576487 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42224.986139 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42205.960835 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42209.836027 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42247.656067 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42187.784813 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42208.018220 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42198.566292 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42191.319002 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42209.276063 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 43795.063539 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 43742.269132 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 43994.444121 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 43681.279217 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44035.736842 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44163.151337 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 43823.506608 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 43951.753387 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 43898.066118 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 42778.037476 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 42746.677695 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 42846.831666 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 42760.600389 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 42833.242894 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 42901.308017 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 42779.526710 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 42818.798290 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 42808.113328 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 123330 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 121282 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 252480 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 249408 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 84079 # Transaction distribution -system.membus.trans_dist::ReadResp 84076 # Transaction distribution -system.membus.trans_dist::WriteReq 43401 # Transaction distribution -system.membus.trans_dist::WriteResp 43399 # Transaction distribution -system.membus.trans_dist::Writeback 6042 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58662 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47800 # Transaction distribution -system.membus.trans_dist::ReadExReq 50251 # Transaction distribution -system.membus.trans_dist::ReadExResp 3038 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 420748 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1051128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1051128 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58073 # Total snoops (count) -system.membus.snoop_fanout::samples 123330 # Request fanout histogram +system.membus.trans_dist::ReadReq 84654 # Transaction distribution +system.membus.trans_dist::ReadResp 84652 # Transaction distribution +system.membus.trans_dist::WriteReq 43588 # Transaction distribution +system.membus.trans_dist::WriteResp 43585 # Transaction distribution +system.membus.trans_dist::Writeback 6143 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60492 # Transaction distribution +system.membus.trans_dist::UpgradeResp 49595 # Transaction distribution +system.membus.trans_dist::ReadExReq 50638 # Transaction distribution +system.membus.trans_dist::ReadExResp 3207 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 426554 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1061863 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1061863 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 58325 # Total snoops (count) +system.membus.snoop_fanout::samples 252480 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 252480 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123330 # Request fanout histogram -system.membus.reqLayer0.occupancy 349185814 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 47.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 311191349 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 42.6 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 561297 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 261699 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 297550 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 252480 # Request fanout histogram +system.membus.reqLayer0.occupancy 472884580 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 59.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 313892142 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 39.7 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 684630 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 383351 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 298207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 370588 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370576 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43402 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43399 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75955 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29152 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29150 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162499 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162497 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120652 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120226 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120519 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120569 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120393 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120447 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120346 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 963662 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766434 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1752931 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1758190 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1756878 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1755329 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1752897 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1753790 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14054393 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 323559 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 561297 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.683086 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.176196 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 371695 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371689 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43589 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43585 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 75954 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29169 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29167 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162397 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162391 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120614 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120783 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120664 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120646 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120853 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120726 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120516 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120736 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 965538 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1750933 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1748576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754368 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1762730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757509 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1755676 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14042920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 324098 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 684630 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.384232 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.250303 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 53942 9.61% 9.61% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 251180 44.75% 54.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141382 25.19% 79.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 68926 12.28% 91.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 30158 5.37% 97.20% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11557 2.06% 99.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3492 0.62% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 660 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 176832 25.83% 25.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 250927 36.65% 62.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141295 20.64% 83.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 69195 10.11% 93.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 30377 4.44% 97.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11672 1.70% 99.37% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3607 0.53% 99.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 725 0.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 561297 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 720580520 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100512947 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100775889 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 100644932 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100575951 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100528413 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100450921 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 100623449 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100655480 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 684630 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 782327755 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 99.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100591456 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 12.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100721944 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100768962 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100555978 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 12.7 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100847968 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100723976 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100740497 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100846524 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 12.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index e072d02ad..ff9b64e46 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1689 +1,1764 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000473 # Number of seconds simulated -sim_ticks 473250000 # Number of ticks simulated -final_tick 473250000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 473398500 # Number of ticks simulated +final_tick 473398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 101630905 # Simulator tick rate (ticks/s) -host_mem_usage 277340 # Number of bytes of host memory used -host_seconds 4.66 # Real time elapsed on the host +host_tick_rate 74773462 # Simulator tick rate (ticks/s) +host_mem_usage 221944 # Number of bytes of host memory used +host_seconds 6.33 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 80424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 83171 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 80813 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 86214 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 79490 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 82665 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 85333 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 80902 # Number of bytes read from this memory -system.physmem.bytes_read::total 659012 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 419392 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5448 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5355 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5405 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5451 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5481 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5462 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5450 # Number of bytes written to this memory -system.physmem.bytes_written::total 462904 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10946 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11055 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11056 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10909 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6553 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5448 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5355 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5405 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5481 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5462 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5450 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50065 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 169939778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 175744321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 170761754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 182174326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 167966191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 174675119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 180312731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 170949815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1392524036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 886195457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 11537242 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 11511886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 11315372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 11421025 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 11518225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 11581616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 11541469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 11516112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 978138405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 886195457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 181477021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 187256207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 182077126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 193595351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 179484416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 186256735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 191854200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 182465927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2370662441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 85610 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 86349 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 81279 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 82686 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 83314 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 81031 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 83113 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 86498 # Number of bytes read from this memory +system.physmem.bytes_read::total 669880 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 430080 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5517 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5460 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5549 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5366 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5497 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5427 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5336 # Number of bytes written to this memory +system.physmem.bytes_written::total 473601 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10845 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10927 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10898 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87697 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6720 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5517 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5460 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5549 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5366 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5497 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5427 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5336 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50241 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 180841300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 182402352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 171692559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 174664685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 175991263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 171168688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 175566674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 182717098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1415044619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 908494640 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 11654029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 11533623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 11721626 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11335059 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 11341396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 11611782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 11463915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 11271688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1000427758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 908494640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 192495329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 193935976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 183414185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 185999744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 187332659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 182780469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 187030588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 193988785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2415472377 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 98988 # number of read accesses completed -system.cpu0.num_writes 54550 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22171 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.248330 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13318 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22569 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.590101 # Average number of references to valid blocks. +system.cpu0.num_reads 99308 # number of read accesses completed +system.cpu0.num_writes 55247 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22271 # number of replacements +system.cpu0.l1c.tags.tagsinuse 390.476059 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13537 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22673 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.597054 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.248330 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.764157 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.764157 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 335805 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 335805 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8501 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8501 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9644 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9644 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9644 # number of overall hits -system.cpu0.l1c.overall_hits::total 9644 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36474 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36474 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23719 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23719 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60193 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60193 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60193 # number of overall misses -system.cpu0.l1c.overall_misses::total 60193 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 587864141 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 587864141 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 652231215 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 652231215 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1240095356 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1240095356 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1240095356 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1240095356 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44975 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44975 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24862 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24862 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 69837 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 69837 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 69837 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 69837 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810984 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.810984 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954026 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954026 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861907 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861907 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861907 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861907 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16117.347727 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16117.347727 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27498.259412 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 27498.259412 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20601.986211 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20601.986211 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20601.986211 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20601.986211 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 773904 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 390.476059 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.762649 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.762649 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337706 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337706 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8778 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8778 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1202 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1202 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9980 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9980 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9980 # number of overall hits +system.cpu0.l1c.overall_hits::total 9980 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36312 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36312 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23969 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23969 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60281 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60281 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60281 # number of overall misses +system.cpu0.l1c.overall_misses::total 60281 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 585914746 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 585914746 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 661973304 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 661973304 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1247888050 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1247888050 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1247888050 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1247888050 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45090 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45090 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25171 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25171 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70261 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70261 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70261 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70261 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805323 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805323 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952247 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952247 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.857958 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.857958 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.857958 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.857958 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16135.568022 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16135.568022 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27617.894113 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 27617.894113 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20701.183623 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20701.183623 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20701.183623 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20701.183623 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 772989 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66096 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66053 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.708787 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.702557 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9687 # number of writebacks -system.cpu0.l1c.writebacks::total 9687 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36474 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36474 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23719 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23719 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60193 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60193 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60193 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60193 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 531003039 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 531003039 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 615653301 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 615653301 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1146656340 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1146656340 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1146656340 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1146656340 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 646054384 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 646054384 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 971060215 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 971060215 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1617114599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1617114599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810984 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810984 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954026 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954026 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861907 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861907 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14558.398832 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14558.398832 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25956.123825 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25956.123825 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9819 # number of writebacks +system.cpu0.l1c.writebacks::total 9819 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36312 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36312 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23969 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60281 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60281 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60281 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60281 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9835 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9835 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5519 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15354 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15354 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 529167946 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 529167946 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 625061532 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 625061532 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1154229478 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1154229478 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1154229478 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1154229478 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 639072193 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 639072193 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 970312557 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 970312557 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1609384750 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1609384750 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805323 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805323 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952247 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952247 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857958 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.857958 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857958 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.857958 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14572.811908 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14572.811908 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 26077.914473 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 26077.914473 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19147.483917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19147.483917 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 64979.379054 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64979.379054 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 175813.110527 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175813.110527 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 104818.597760 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 104818.597760 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99262 # number of read accesses completed -system.cpu1.num_writes 54743 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22415 # number of replacements -system.cpu1.l1c.tags.tagsinuse 391.761420 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13414 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.587972 # Average number of references to valid blocks. +system.cpu1.num_reads 98972 # number of read accesses completed +system.cpu1.num_writes 54740 # number of write accesses completed +system.cpu1.l1c.tags.replacements 21894 # number of replacements +system.cpu1.l1c.tags.tagsinuse 389.013692 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13227 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22299 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.593166 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 391.761420 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.765159 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.765159 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 336589 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 336589 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8598 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8598 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1162 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1162 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9760 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9760 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9760 # number of overall hits -system.cpu1.l1c.overall_hits::total 9760 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36477 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36477 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23776 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23776 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses -system.cpu1.l1c.overall_misses::total 60253 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 595460828 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 595460828 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 649149772 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 649149772 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1244610600 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1244610600 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1244610600 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1244610600 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45075 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45075 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24938 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24938 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70013 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70013 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70013 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70013 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809251 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.809251 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953404 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953404 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860597 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860597 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860597 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860597 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16324.281821 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16324.281821 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27302.732672 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 27302.732672 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20656.408810 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20656.408810 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20656.408810 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20656.408810 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 769857 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 389.013692 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.759792 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.759792 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 335323 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 335323 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8521 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8521 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9673 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9673 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9673 # number of overall hits +system.cpu1.l1c.overall_hits::total 9673 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36191 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36191 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23860 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23860 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60051 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60051 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60051 # number of overall misses +system.cpu1.l1c.overall_misses::total 60051 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 587357926 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 587357926 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 665550173 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 665550173 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1252908099 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1252908099 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1252908099 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1252908099 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44712 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44712 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25012 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69724 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69724 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69724 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69724 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809425 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.809425 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953942 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.861267 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.861267 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.861267 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.861267 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16229.392004 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16229.392004 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27893.972045 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 27893.972045 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20864.067193 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20864.067193 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20864.067193 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20864.067193 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 781068 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 65915 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.679542 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.805922 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9826 # number of writebacks -system.cpu1.l1c.writebacks::total 9826 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36477 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23776 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23776 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 538442174 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 538442174 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 612498892 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 612498892 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1150941066 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1150941066 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1150941066 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1150941066 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 637533564 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 637533564 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 980538192 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 980538192 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1618071756 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1618071756 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809251 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809251 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953404 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953404 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860597 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860597 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14761.141925 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14761.141925 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25761.225269 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25761.225269 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9676 # number of writebacks +system.cpu1.l1c.writebacks::total 9676 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36191 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36191 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23860 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60051 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60051 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60051 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60051 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9870 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9870 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5462 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5462 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15332 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15332 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 530766130 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 530766130 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 628779775 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 628779775 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1159545905 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1159545905 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1159545905 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1159545905 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 639204350 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 639204350 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 954877634 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 954877634 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1594081984 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1594081984 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809425 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809425 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953942 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861267 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.861267 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861267 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.861267 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14665.693957 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14665.693957 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 26352.882439 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 26352.882439 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19309.352134 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19309.352134 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19309.352134 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19309.352134 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 64762.345491 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64762.345491 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 174821.976199 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174821.976199 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103970.909470 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103970.909470 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99661 # number of read accesses completed -system.cpu2.num_writes 54617 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22463 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.489979 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13594 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22875 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.594273 # Average number of references to valid blocks. +system.cpu2.num_reads 99459 # number of read accesses completed +system.cpu2.num_writes 55455 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22538 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.681778 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22938 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.590810 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.489979 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.766582 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.766582 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 412 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.804688 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338191 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338191 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8852 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8852 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1132 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1132 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9984 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9984 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9984 # number of overall hits -system.cpu2.l1c.overall_hits::total 9984 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36597 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36597 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23791 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23791 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60388 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60388 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60388 # number of overall misses -system.cpu2.l1c.overall_misses::total 60388 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 596108462 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 596108462 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 646461820 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 646461820 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1242570282 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1242570282 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1242570282 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1242570282 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24923 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24923 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70372 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70372 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805232 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805232 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954580 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954580 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858125 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858125 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858125 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858125 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16288.451567 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16288.451567 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27172.536674 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 27172.536674 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 20576.443697 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 20576.443697 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 20576.443697 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 20576.443697 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 768951 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.681778 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766957 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337495 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337495 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8694 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8694 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1182 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9876 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9876 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9876 # number of overall hits +system.cpu2.l1c.overall_hits::total 9876 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36455 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36455 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23891 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23891 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60346 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60346 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60346 # number of overall misses +system.cpu2.l1c.overall_misses::total 60346 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 592802045 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 592802045 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 663383699 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 663383699 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1256185744 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1256185744 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1256185744 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1256185744 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45149 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45149 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25073 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70222 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70222 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70222 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70222 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807438 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.807438 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952858 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.952858 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859360 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859360 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859360 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859360 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16261.199973 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16261.199973 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27767.096354 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 27767.096354 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20816.387896 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20816.387896 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20816.387896 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20816.387896 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 773062 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 65985 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66064 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.653421 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.701713 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9852 # number of writebacks -system.cpu2.l1c.writebacks::total 9852 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36597 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36597 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23791 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23791 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60388 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60388 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60388 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60388 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 538960044 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 538960044 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 609774472 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 609774472 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1148734516 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1148734516 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1148734516 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1148734516 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638400628 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638400628 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 959722740 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 959722740 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1598123368 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1598123368 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805232 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805232 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954580 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954580 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858125 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858125 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14726.891385 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14726.891385 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 25630.468328 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 25630.468328 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9793 # number of writebacks +system.cpu2.l1c.writebacks::total 9793 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36455 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36455 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23891 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23891 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60346 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60346 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60346 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60346 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9727 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9727 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5550 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5550 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15277 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535820289 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535820289 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 626605165 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 626605165 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162425454 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1162425454 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162425454 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1162425454 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 629981617 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 629981617 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 971621622 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 971621622 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1601603239 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1601603239 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807438 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807438 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952858 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952858 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859360 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859360 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859360 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859360 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14698.128899 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14698.128899 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26227.665857 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26227.665857 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19262.676134 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19262.676134 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19262.676134 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19262.676134 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 64766.281176 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64766.281176 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 175066.958919 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175066.958919 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 104837.549192 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 104837.549192 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 55095 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22209 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.627346 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13529 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22601 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.598602 # Average number of references to valid blocks. +system.cpu3.num_reads 99575 # number of read accesses completed +system.cpu3.num_writes 55091 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22304 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.069306 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13533 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22710 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.595905 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.627346 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.764897 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.764897 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338542 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338542 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8783 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8783 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1149 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1149 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9932 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9932 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9932 # number of overall hits -system.cpu3.l1c.overall_hits::total 9932 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36678 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36678 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23815 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23815 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60493 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60493 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60493 # number of overall misses -system.cpu3.l1c.overall_misses::total 60493 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 595385248 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 595385248 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 651992109 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 651992109 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1247377357 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1247377357 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1247377357 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1247377357 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45461 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45461 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24964 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70425 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70425 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70425 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70425 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806801 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806801 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953974 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858971 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858971 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858971 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858971 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16232.762092 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16232.762092 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27377.371782 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 27377.371782 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20620.193361 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20620.193361 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20620.193361 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20620.193361 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 774947 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.069306 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.765760 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.765760 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336765 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336765 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8633 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8633 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1152 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1152 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9785 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9785 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9785 # number of overall hits +system.cpu3.l1c.overall_hits::total 9785 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36428 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36428 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23860 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23860 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60288 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60288 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60288 # number of overall misses +system.cpu3.l1c.overall_misses::total 60288 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 584499068 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 584499068 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 664565432 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 664565432 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1249064500 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1249064500 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1249064500 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1249064500 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45061 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45061 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25012 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70073 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70073 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70073 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70073 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808415 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808415 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953942 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860360 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860360 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860360 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860360 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16045.324146 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16045.324146 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27852.700419 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 27852.700419 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20718.293856 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20718.293856 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20718.293856 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20718.293856 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 775679 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66468 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66211 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.658949 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.715259 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9869 # number of writebacks -system.cpu3.l1c.writebacks::total 9869 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36678 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36678 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23815 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60493 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60493 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60493 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60493 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 538014612 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 538014612 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 615289695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 615289695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1153304307 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1153304307 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1153304307 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1153304307 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 640462998 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 640462998 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962755753 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962755753 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1603218751 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1603218751 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806801 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806801 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953974 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858971 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858971 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14668.591853 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14668.591853 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25836.224858 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25836.224858 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9857 # number of writebacks +system.cpu3.l1c.writebacks::total 9857 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36428 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36428 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23860 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60288 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60288 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60288 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60288 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9854 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9854 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5367 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5367 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15221 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 527611348 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 527611348 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 627817964 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 627817964 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155429312 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1155429312 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155429312 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1155429312 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639378023 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639378023 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962583192 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962583192 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1601961215 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1601961215 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808415 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808415 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953942 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860360 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860360 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860360 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860360 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14483.675964 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14483.675964 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 26312.571836 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 26312.571836 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19165.162420 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19165.162420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19165.162420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19165.162420 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 64885.125127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64885.125127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 179352.187814 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179352.187814 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 105246.778464 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 105246.778464 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99958 # number of read accesses completed -system.cpu4.num_writes 55186 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22162 # number of replacements -system.cpu4.l1c.tags.tagsinuse 390.917230 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13739 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22564 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.608890 # Average number of references to valid blocks. +system.cpu4.num_reads 99348 # number of read accesses completed +system.cpu4.num_writes 54723 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22403 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.522543 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13385 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587448 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 390.917230 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.763510 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.763510 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338274 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338274 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8951 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8951 # number of ReadReq hits +system.cpu4.l1c.tags.occ_blocks::cpu4 391.522543 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.764692 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.764692 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 382 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.746094 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337332 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337332 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8635 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8635 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1108 # number of WriteReq hits system.cpu4.l1c.WriteReq_hits::total 1108 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits -system.cpu4.l1c.overall_hits::total 10059 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36463 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36463 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23892 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23892 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60355 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60355 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60355 # number of overall misses -system.cpu4.l1c.overall_misses::total 60355 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 590532010 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 590532010 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 657391664 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 657391664 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1247923674 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1247923674 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1247923674 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1247923674 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45414 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45414 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25000 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25000 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70414 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70414 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70414 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70414 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.802902 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.802902 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955680 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.955680 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857145 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857145 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857145 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857145 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16195.376409 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16195.376409 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27515.137452 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 27515.137452 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20676.392577 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20676.392577 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20676.392577 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20676.392577 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 772044 # number of cycles access was blocked +system.cpu4.l1c.demand_hits::cpu4 9743 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9743 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9743 # number of overall hits +system.cpu4.l1c.overall_hits::total 9743 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36706 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36706 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23706 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23706 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60412 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60412 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60412 # number of overall misses +system.cpu4.l1c.overall_misses::total 60412 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 597809741 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 597809741 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 658168265 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 658168265 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1255978006 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1255978006 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1255978006 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1255978006 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45341 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45341 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24814 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24814 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70155 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70155 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809554 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.809554 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955348 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955348 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.861122 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.861122 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.861122 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.861122 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16286.431128 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16286.431128 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27763.784063 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 27763.784063 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20790.207343 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20790.207343 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20790.207343 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20790.207343 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 777995 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66046 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66371 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.689489 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.721912 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks -system.cpu4.l1c.writebacks::total 9680 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36463 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36463 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23892 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23892 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60355 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60355 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60355 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60355 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533535272 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533535272 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 620520370 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 620520370 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1154055642 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1154055642 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1154055642 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1154055642 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 636776082 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636776082 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 976656146 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 976656146 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1613432228 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1613432228 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.802902 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802902 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955680 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955680 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857145 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857145 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14632.237391 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14632.237391 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25971.888917 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25971.888917 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9776 # number of writebacks +system.cpu4.l1c.writebacks::total 9776 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36706 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36706 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23706 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23706 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60412 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60412 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60412 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60412 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9778 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5370 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5370 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15148 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15148 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 540346315 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 540346315 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 621672271 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 621672271 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1162018586 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1162018586 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1162018586 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1162018586 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 636494546 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636494546 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 958781259 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 958781259 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1595275805 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1595275805 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809554 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809554 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955348 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955348 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861122 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.861122 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861122 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.861122 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14720.926143 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14720.926143 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 26224.258458 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 26224.258458 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65094.553692 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65094.553692 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 178543.996089 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 178543.996089 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 105312.635661 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 105312.635661 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98793 # number of read accesses completed -system.cpu5.num_writes 54966 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22337 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.447401 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13310 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22755 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.584926 # Average number of references to valid blocks. +system.cpu5.num_reads 99076 # number of read accesses completed +system.cpu5.num_writes 54802 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22210 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.101349 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13412 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22600 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.593451 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.447401 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.766499 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 335862 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 335862 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8554 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8554 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1127 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1127 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9681 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9681 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9681 # number of overall hits -system.cpu5.l1c.overall_hits::total 9681 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36144 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36144 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24019 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24019 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60163 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60163 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60163 # number of overall misses -system.cpu5.l1c.overall_misses::total 60163 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 586243376 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 586243376 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 664085386 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 664085386 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1250328762 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1250328762 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1250328762 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1250328762 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44698 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44698 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25146 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25146 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69844 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69844 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69844 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69844 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808627 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808627 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955182 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.955182 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.861391 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.861391 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.861391 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.861391 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16219.659584 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16219.659584 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27648.336151 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 27648.336151 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20782.353972 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20782.353972 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20782.353972 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20782.353972 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 771700 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.101349 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765823 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765823 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 335763 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 335763 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8687 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8687 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1188 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9875 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9875 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9875 # number of overall hits +system.cpu5.l1c.overall_hits::total 9875 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36386 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36386 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23589 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23589 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59975 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59975 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59975 # number of overall misses +system.cpu5.l1c.overall_misses::total 59975 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 587220514 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 587220514 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 653847941 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 653847941 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1241068455 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1241068455 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1241068455 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1241068455 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45073 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45073 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24777 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24777 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69850 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69850 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69850 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69850 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807268 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952052 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952052 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858626 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858626 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858626 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858626 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16138.638872 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16138.638872 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27718.340794 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 27718.340794 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20693.096373 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20693.096373 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20693.096373 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20693.096373 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 773798 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 65809 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 65921 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.726360 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.738262 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9916 # number of writebacks -system.cpu5.l1c.writebacks::total 9916 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36144 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24019 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24019 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60163 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60163 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60163 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60163 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 529678552 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 529678552 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 626959212 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 626959212 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156637764 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1156637764 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156637764 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1156637764 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632837521 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632837521 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 970316626 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 970316626 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1603154147 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1603154147 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808627 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808627 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955182 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955182 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.861391 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.861391 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14654.674413 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14654.674413 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26102.635913 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26102.635913 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9805 # number of writebacks +system.cpu5.l1c.writebacks::total 9805 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36386 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36386 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23589 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23589 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59975 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59975 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59975 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59975 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9927 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9927 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5497 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5497 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15424 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15424 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 530387712 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 530387712 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 617501507 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 617501507 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1147889219 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1147889219 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1147889219 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1147889219 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 644126924 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 644126924 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 971277615 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 971277615 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1615404539 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1615404539 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807268 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952052 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952052 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858626 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858626 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858626 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858626 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14576.697411 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14576.697411 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26177.519479 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26177.519479 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19139.461759 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19139.461759 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 64886.362849 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64886.362849 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 176692.307622 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176692.307622 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 104733.178099 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 104733.178099 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99383 # number of read accesses completed -system.cpu6.num_writes 54752 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22371 # number of replacements -system.cpu6.l1c.tags.tagsinuse 391.299314 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13429 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.589975 # Average number of references to valid blocks. +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 55196 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22166 # number of replacements +system.cpu6.l1c.tags.tagsinuse 390.500017 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13797 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22571 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.611271 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 391.299314 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.764256 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.764256 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 336995 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 336995 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1088 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1088 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9819 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9819 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9819 # number of overall hits -system.cpu6.l1c.overall_hits::total 9819 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36545 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36545 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23737 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23737 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60282 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60282 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60282 # number of overall misses -system.cpu6.l1c.overall_misses::total 60282 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 590611551 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 590611551 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 651380889 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 651380889 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1241992440 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1241992440 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1241992440 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1241992440 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45276 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45276 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24825 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24825 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70101 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70101 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70101 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70101 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807161 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807161 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956173 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956173 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859931 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859931 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859931 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859931 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16161.213600 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16161.213600 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27441.584404 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 27441.584404 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 20603.039713 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 20603.039713 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 20603.039713 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 20603.039713 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 771561 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 390.500017 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.762695 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.762695 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338189 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338189 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8999 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8999 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1089 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1089 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 10088 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 10088 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 10088 # number of overall hits +system.cpu6.l1c.overall_hits::total 10088 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36489 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36489 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23831 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23831 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60320 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60320 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60320 # number of overall misses +system.cpu6.l1c.overall_misses::total 60320 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 591265797 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 591265797 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 669884291 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 669884291 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1261150088 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1261150088 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1261150088 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1261150088 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45488 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45488 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24920 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24920 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70408 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70408 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70408 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70408 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.802168 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.802168 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956300 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.956300 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.856721 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.856721 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.856721 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.856721 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16203.946313 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16203.946313 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28109.785196 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28109.785196 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20907.660610 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20907.660610 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20907.660610 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20907.660610 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 779089 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66088 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66360 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.674752 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.740341 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9782 # number of writebacks -system.cpu6.l1c.writebacks::total 9782 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36545 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36545 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23737 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23737 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60282 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60282 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60282 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60282 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 533644023 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 533644023 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 614831387 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 614831387 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148475410 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1148475410 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148475410 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1148475410 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 641180935 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 641180935 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 971245186 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 971245186 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1612426121 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1612426121 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807161 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807161 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956173 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956173 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859931 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859931 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14602.381256 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14602.381256 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25901.815183 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25901.815183 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9642 # number of writebacks +system.cpu6.l1c.writebacks::total 9642 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36489 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36489 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23831 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60320 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60320 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60320 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60320 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9769 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9769 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5428 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15197 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15197 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 534211155 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 534211155 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 633170857 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 633170857 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1167382012 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1167382012 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1167382012 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1167382012 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 633249047 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 633249047 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 972097686 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 972097686 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1605346733 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1605346733 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.802168 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.802168 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956300 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956300 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.856721 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.856721 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.856721 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.856721 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14640.334210 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14640.334210 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 26569.210566 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 26569.210566 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19353.150066 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19353.150066 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 64822.299826 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64822.299826 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 179089.477892 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179089.477892 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 105635.765809 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 105635.765809 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99477 # number of read accesses completed -system.cpu7.num_writes 54915 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22352 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.525005 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13561 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22758 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.595878 # Average number of references to valid blocks. +system.cpu7.num_reads 99558 # number of read accesses completed +system.cpu7.num_writes 55171 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22301 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.314330 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13511 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22696 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.595303 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.525005 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.764697 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.764697 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337629 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337629 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8790 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8790 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1137 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1137 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9927 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9927 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9927 # number of overall hits -system.cpu7.l1c.overall_hits::total 9927 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36477 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36477 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23844 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23844 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60321 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60321 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60321 # number of overall misses -system.cpu7.l1c.overall_misses::total 60321 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 593716610 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 593716610 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 651325348 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 651325348 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1245041958 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1245041958 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1245041958 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1245041958 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45267 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45267 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24981 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24981 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70248 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70248 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70248 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70248 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805819 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805819 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954485 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954485 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858686 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858686 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858686 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858686 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16276.464896 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16276.464896 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27316.110887 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 27316.110887 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 20640.273835 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 20640.273835 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 20640.273835 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 20640.273835 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 768557 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 392.314330 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766239 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766239 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337937 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337937 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8724 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8724 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1105 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1105 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9829 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9829 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9829 # number of overall hits +system.cpu7.l1c.overall_hits::total 9829 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36568 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36568 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23906 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23906 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses +system.cpu7.l1c.overall_misses::total 60474 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 596090233 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 596090233 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 664580608 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 664580608 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1260670841 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1260670841 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1260670841 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1260670841 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45292 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45292 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25011 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25011 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70303 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70303 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70303 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70303 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807383 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807383 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955819 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955819 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860191 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860191 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860191 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860191 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16300.870515 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16300.870515 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27799.740986 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 27799.740986 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20846.493386 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20846.493386 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20846.493386 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20846.493386 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 776345 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 65923 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66228 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.658405 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.722308 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9939 # number of writebacks -system.cpu7.l1c.writebacks::total 9939 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36477 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23844 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23844 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60321 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60321 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 536729312 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 536729312 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 614614324 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 614614324 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1151343636 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1151343636 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1151343636 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1151343636 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 635643033 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 635643033 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 965131654 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 965131654 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1600774687 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1600774687 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805819 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805819 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954485 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954485 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858686 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858686 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14714.184609 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14714.184609 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25776.477269 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25776.477269 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9814 # number of writebacks +system.cpu7.l1c.writebacks::total 9814 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36568 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36568 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23906 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23906 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9700 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9700 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5336 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5336 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15036 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15036 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538984883 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538984883 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 627714786 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 627714786 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1166699669 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1166699669 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1166699669 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1166699669 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 629180127 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 629180127 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 945700289 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 945700289 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574880416 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574880416 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807383 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807383 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955819 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955819 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860191 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860191 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860191 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860191 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14739.249699 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14739.249699 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 26257.625115 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 26257.625115 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19292.583077 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19292.583077 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19292.583077 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19292.583077 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 64863.930619 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64863.930619 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 177230.189093 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 177230.189093 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 104740.650173 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 104740.650173 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13851 # number of replacements -system.l2c.tags.tagsinuse 783.697862 # Cycle average of tags in use -system.l2c.tags.total_refs 151322 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14625 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.346803 # Average number of references to valid blocks. +system.l2c.tags.replacements 14031 # number of replacements +system.l2c.tags.tagsinuse 784.967814 # Cycle average of tags in use +system.l2c.tags.total_refs 150152 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14812 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.137186 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 724.401984 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.094586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.546674 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.606935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.397120 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.288170 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.917650 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.470007 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.974735 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.707424 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006928 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007370 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007429 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007224 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007117 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007732 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007295 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006811 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765330 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 774 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 649 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1983958 # Number of tag accesses -system.l2c.tags.data_accesses 1983958 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10778 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10851 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10733 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10660 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10974 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86237 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76857 # number of Writeback hits -system.l2c.Writeback_hits::total 76857 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 346 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 384 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 373 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 367 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 376 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2885 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1990 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1993 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1893 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2001 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2049 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1965 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1890 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15680 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12610 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12768 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12844 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12641 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12783 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12864 # number of demand (read+write) hits -system.l2c.demand_hits::total 101917 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12610 # number of overall hits -system.l2c.overall_hits::cpu1 12768 # number of overall hits -system.l2c.overall_hits::cpu2 12844 # number of overall hits -system.l2c.overall_hits::cpu3 12641 # number of overall hits -system.l2c.overall_hits::cpu4 12783 # number of overall hits -system.l2c.overall_hits::cpu5 12782 # number of overall hits -system.l2c.overall_hits::cpu6 12625 # number of overall hits -system.l2c.overall_hits::cpu7 12864 # number of overall hits -system.l2c.overall_hits::total 101917 # number of overall hits -system.l2c.ReadReq_misses::cpu0 698 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 756 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 731 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 765 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 706 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 759 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 730 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 718 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5863 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1969 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1976 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1906 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1935 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2000 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15706 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4442 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4288 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4325 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4406 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4415 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4506 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4417 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4371 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35170 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5140 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5056 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5171 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5121 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5265 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5147 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5089 # number of demand (read+write) misses -system.l2c.demand_misses::total 41033 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5140 # number of overall misses -system.l2c.overall_misses::cpu1 5044 # number of overall misses -system.l2c.overall_misses::cpu2 5056 # number of overall misses -system.l2c.overall_misses::cpu3 5171 # number of overall misses -system.l2c.overall_misses::cpu4 5121 # number of overall misses -system.l2c.overall_misses::cpu5 5265 # number of overall misses -system.l2c.overall_misses::cpu6 5147 # number of overall misses -system.l2c.overall_misses::cpu7 5089 # number of overall misses -system.l2c.overall_misses::total 41033 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 43733919 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 46361427 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 45254929 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 46924929 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 44013419 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 46972420 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 45169428 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 45070420 # 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number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2315 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2360 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2279 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2302 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2376 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2355 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2322 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18591 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6341 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6278 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6318 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6299 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6416 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6555 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6382 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6261 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50850 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17812 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17900 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17812 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17904 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18047 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17772 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17953 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142950 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17812 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17900 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17812 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17904 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18047 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17772 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17953 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142950 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.061180 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.065545 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.063115 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.066447 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.061455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.066046 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.064091 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.061410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.063659 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.850540 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.837288 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.836332 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.840573 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.841751 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.854352 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.841805 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.855728 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.844817 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.700520 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.683020 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.684552 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.699476 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.688123 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.687414 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692103 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.698131 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.691642 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.289577 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.283180 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.282458 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.290310 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.286025 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291738 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.289613 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.283462 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.287044 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.289577 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.283180 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.282458 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.290310 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.286025 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291738 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.289613 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.283462 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.287044 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 62656.044413 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61324.638889 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 61908.247606 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61339.776471 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 62341.953258 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 61887.246377 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61875.928767 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 62772.172702 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61999.128603 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 30420.009142 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28822.618927 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28386.671563 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29329.455297 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29187.497000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28914.759443 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28532.013535 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29326.620030 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29118.901503 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 55094.540072 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 55113.909515 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 55006.230520 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 55044.244666 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 55035.773952 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 55082.876387 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 55162.311976 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54882.624800 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55053.043730 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 56121.374708 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 56044.780135 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 56004.128956 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55975.608393 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 56043.030853 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 56063.791263 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 56114.505537 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55995.750246 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 56045.535033 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 56121.374708 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 56044.780135 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 56004.128956 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55975.608393 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 56043.030853 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 56063.791263 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 56114.505537 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55995.750246 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 56045.535033 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 17878 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 723.923615 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.649200 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 8.016952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.636701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.493514 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.626072 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.131481 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.354188 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 8.136089 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.706957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007470 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007829 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007458 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007318 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007447 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006964 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007945 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.766570 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 781 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 686 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.762695 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1978435 # Number of tag accesses +system.l2c.tags.data_accesses 1978435 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10607 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10697 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10702 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 11123 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10597 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10776 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10709 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85924 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 76544 # number of Writeback hits +system.l2c.Writeback_hits::total 76544 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 268 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 299 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 302 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 259 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 274 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 287 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 307 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2268 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1803 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1734 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1772 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1671 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1762 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1808 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1767 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1864 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14181 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12516 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12341 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12469 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12373 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12885 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12405 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12543 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12573 # number of demand (read+write) hits +system.l2c.demand_hits::total 100105 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12516 # number of overall hits +system.l2c.overall_hits::cpu1 12341 # number of overall hits +system.l2c.overall_hits::cpu2 12469 # number of overall hits +system.l2c.overall_hits::cpu3 12373 # number of overall hits +system.l2c.overall_hits::cpu4 12885 # number of overall hits +system.l2c.overall_hits::cpu5 12405 # number of overall hits +system.l2c.overall_hits::cpu6 12543 # number of overall hits +system.l2c.overall_hits::cpu7 12573 # number of overall hits +system.l2c.overall_hits::total 100105 # number of overall hits +system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 785 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 742 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 727 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 760 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 712 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 735 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 780 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5986 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1959 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2034 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2073 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2095 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2075 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1984 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2104 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2050 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16374 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4569 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4626 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4511 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4582 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4471 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4493 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4628 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4552 # 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number of overall misses +system.l2c.overall_misses::cpu4 5231 # number of overall misses +system.l2c.overall_misses::cpu5 5205 # number of overall misses +system.l2c.overall_misses::cpu6 5363 # number of overall misses +system.l2c.overall_misses::cpu7 5332 # number of overall misses +system.l2c.overall_misses::total 42418 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 46187916 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 48036419 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 45900428 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 44726930 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 46758924 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 44218925 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 45379928 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 48529420 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 369738890 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 57866497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 60355991 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 61207994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 63805822 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 62183492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 61767496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 63498496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 63160496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 493846284 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 251689442 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 254959951 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 248273936 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 252714443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 246321934 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 247674443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 255400930 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 250363448 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2007398527 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 297877358 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 302996370 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 294174364 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 297441373 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 293080858 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 291893368 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 300780858 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 298892868 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2377137417 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 297877358 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 302996370 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 294174364 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 297441373 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 293080858 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 291893368 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 300780858 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 298892868 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2377137417 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11458 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11392 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11439 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11883 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11309 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11511 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91910 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 76544 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 76544 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2231 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2302 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2372 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2397 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2334 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2258 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2391 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2357 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18642 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6372 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6360 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6283 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6253 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6233 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6301 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6395 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6416 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50613 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17830 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17752 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17722 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17682 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18116 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17610 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17906 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17905 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 142523 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17830 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17752 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17722 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17682 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18116 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17610 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17906 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17905 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 142523 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.065020 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.068908 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064866 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.063610 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.063957 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.062959 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.063852 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.067891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.065129 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.878082 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.883579 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.873946 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.874009 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.889032 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.878654 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.879967 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.869750 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.878339 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.717043 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.727358 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.717969 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.732768 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717311 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.713061 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.723690 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.709476 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.719815 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.298037 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.304811 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.296411 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.300249 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.288750 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.295571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.299509 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.297794 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.297622 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.298037 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.304811 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.296411 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.300249 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.288750 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.295571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.299509 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.297794 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.297622 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 61997.202685 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61192.890446 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61860.415094 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61522.599725 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61524.900000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 62105.231742 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61741.398639 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 62217.205128 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61767.271968 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29538.793772 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29673.545231 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29526.287506 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30456.239618 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 29967.947952 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 31132.810484 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30179.893536 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 30809.998049 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 30160.393551 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55086.330050 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55114.559230 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55037.449789 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55153.741379 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55093.252964 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55124.514356 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55186.026361 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55000.757469 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55099.871734 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56055.204742 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55996.372205 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56001.211498 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 56025.875494 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56027.692219 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56079.417483 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56084.441171 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 56056.426857 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56040.770828 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56055.204742 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55996.372205 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56001.211498 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 56025.875494 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56027.692219 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56079.417483 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56084.441171 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 56056.426857 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56040.770828 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 18299 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3319 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3476 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.386562 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.264384 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6553 # number of writebacks -system.l2c.writebacks::total 6553 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 8 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6720 # number of writebacks +system.l2c.writebacks::total 6720 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 3 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 48 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 108 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 690 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 748 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 723 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 759 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 699 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 748 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 725 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 711 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5803 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1969 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1976 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1906 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1935 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1999 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2012 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1921 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1986 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15704 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4438 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4282 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4318 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4399 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4410 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4497 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4413 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4365 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35122 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5128 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5030 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5041 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5158 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5109 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5245 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5138 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5076 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40925 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5128 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5030 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5041 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5158 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5109 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5245 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5138 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5076 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40925 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 35173417 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 37031918 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 36254417 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 37641417 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 35371412 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 37570056 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 36289420 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 36247403 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 291579460 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 83090959 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 83391451 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80567464 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 81939961 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 84801962 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 85113946 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 81126982 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 83903452 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 663936177 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 190977391 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 184459864 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 185520379 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 189280870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 189565364 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 193586876 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 190188358 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 187005383 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1510584485 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 226150808 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 221491782 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 221774796 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 226922287 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 224936776 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 231156932 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 226477778 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 223252786 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1802163945 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 226150808 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 221491782 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 221774796 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 226922287 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 224936776 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 231156932 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 226477778 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 223252786 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1802163945 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 423951568 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 418494765 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 418742272 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 420173606 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 417698791 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 416045242 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 420505761 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416931790 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3352543795 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 241936896 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 242321875 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237941390 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 239219888 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241365909 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 242888399 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 243671384 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 242767880 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1932113621 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 665888464 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 660816640 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 656683662 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 659393494 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 659064700 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 658933641 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 664177145 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 659699670 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5284657416 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060479 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064852 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062424 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.065925 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060846 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.065089 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063652 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060811 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.063008 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.850540 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.837288 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.836332 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.840573 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.841330 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.854352 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841805 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.855297 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.844710 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.699890 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682064 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.683444 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.698365 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687344 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.686041 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691476 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.697173 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.690698 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.286289 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.286289 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50975.966667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49507.911765 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50144.421853 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49593.434783 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50602.878398 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.347594 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50054.372414 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50980.876231 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 50246.331208 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42199.572880 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42202.151316 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42270.442812 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42346.233075 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42422.192096 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42303.154076 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42231.640812 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42247.458207 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42278.156966 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43032.309824 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43077.969173 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42964.423113 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43028.158672 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42985.343311 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43048.004447 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43097.293904 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42842.012142 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 43009.637407 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 35 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 738 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 776 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 734 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 724 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 745 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 706 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 731 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 774 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5928 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1959 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2034 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2073 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2095 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1984 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2101 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2050 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16370 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4565 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4622 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4503 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4580 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4467 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4488 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4624 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4548 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 36397 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5303 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5398 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5237 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5304 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5212 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5194 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5355 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5322 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42325 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5303 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5398 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5237 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5304 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5212 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5194 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5355 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5322 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42325 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9834 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 9869 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9727 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9854 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9778 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9927 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9769 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9700 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 78458 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5517 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5460 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5550 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5367 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5370 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5497 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5427 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5336 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43524 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15351 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15329 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15277 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15221 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15148 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15424 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15196 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15036 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 121982 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 37081908 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 38421892 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 36752422 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 35943926 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 37213921 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 35460411 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 36445418 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 38946899 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 296266797 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 82978964 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 86239947 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 87750966 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 88854787 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 87819107 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83999460 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 88854959 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 87064968 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 693563158 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 196462368 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 199050885 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193595340 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 197409379 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 192312836 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 193341369 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 199367330 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 195358866 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1566898373 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 233544276 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 237472777 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 230347762 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 233353305 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 229526757 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 228801780 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 235812748 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 234305765 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1863165170 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 233544276 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 237472777 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 230347762 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 233353305 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 229526757 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 228801780 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 412865244 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3344214073 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 244799897 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 243732417 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 247505386 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 237594430 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 238425396 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 244815873 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 242422406 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 237975886 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1937271691 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 664390319 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 664144216 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 662031124 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 657709027 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 655784643 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 667858655 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 658726650 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 650841130 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5281485764 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064409 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068118 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064166 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.063348 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.062695 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.062428 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063504 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067369 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.064498 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.878082 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883579 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.873946 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.874009 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.888603 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878654 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.878712 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.869750 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.878125 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.716416 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726730 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.716696 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.732448 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716669 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.712268 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723065 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.708853 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.719124 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.297420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.304078 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.295508 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.299966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.287701 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.294946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.299062 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.297235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.296970 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.297420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.304078 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.295508 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.299966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.287701 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.294946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.299062 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.297235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.296970 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50246.487805 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49512.747423 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50071.419619 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49646.306630 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49951.571812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.211048 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49856.932969 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50318.990956 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49977.529858 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42357.817254 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42399.187316 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42330.422576 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42412.786158 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42342.867406 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42338.437500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42291.746311 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42470.716098 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42367.938790 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43036.663308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43065.963868 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42992.524983 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43102.484498 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43051.899709 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43079.627674 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43115.772059 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42954.895778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43050.206693 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 44040.029417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43992.733790 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43984.678633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43995.721154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 44038.134497 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 44051.170581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 44035.994024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 44025.885945 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 44020.441110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 44040.029417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43992.733790 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43984.678633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43995.721154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 44038.134497 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 44051.170581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 44035.994024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 44025.885945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 44020.441110 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42667.319707 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42599.229811 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42615.990336 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42633.914857 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42683.498364 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42615.370404 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42614.826901 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42563.427216 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42624.258495 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 44371.922603 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 44639.636813 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 44595.565045 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 44269.504379 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44399.515084 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44536.269420 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 44669.689700 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 44598.179535 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 44510.423927 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 43279.937398 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 43325.997521 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 43335.152451 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 43210.631824 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 43291.830143 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 43299.964665 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 43348.687155 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 43285.523410 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 43297.255038 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 84510 # Transaction distribution -system.membus.trans_dist::ReadResp 84504 # Transaction distribution -system.membus.trans_dist::WriteReq 43512 # Transaction distribution -system.membus.trans_dist::WriteResp 43509 # Transaction distribution -system.membus.trans_dist::Writeback 6553 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58529 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47554 # Transaction distribution -system.membus.trans_dist::ReadExReq 49190 # Transaction distribution -system.membus.trans_dist::ReadExResp 3281 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 421142 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1121847 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1121847 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56880 # Total snoops (count) -system.membus.snoop_fanout::samples 123632 # Request fanout histogram +system.membus.trans_dist::ReadReq 84372 # Transaction distribution +system.membus.trans_dist::ReadResp 84365 # Transaction distribution +system.membus.trans_dist::WriteReq 43521 # Transaction distribution +system.membus.trans_dist::WriteResp 43519 # Transaction distribution +system.membus.trans_dist::Writeback 6720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60428 # Transaction distribution +system.membus.trans_dist::UpgradeResp 49463 # Transaction distribution +system.membus.trans_dist::ReadExReq 49409 # Transaction distribution +system.membus.trans_dist::ReadExResp 3325 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 425122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 425122 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1143411 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1143411 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57048 # Total snoops (count) +system.membus.snoop_fanout::samples 253034 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123632 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253034 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123632 # Request fanout histogram -system.membus.reqLayer0.occupancy 285799779 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 60.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 306149550 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 64.7 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 370575 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370557 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 7 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43514 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43509 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 76857 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29562 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29559 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161030 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161024 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120575 # Packet count per connected master and slave (bytes) +system.membus.snoop_fanout::total 253034 # Request fanout histogram +system.membus.reqLayer0.occupancy 288296633 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 60.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 308136269 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 65.1 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 369990 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 369967 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43524 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43518 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 76544 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29606 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29605 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161002 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 160999 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120638 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120231 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120586 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120766 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120839 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 965293 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1758906 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1769834 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1777815 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1771618 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1766732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1765164 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14189303 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 320901 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 563826 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120464 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120699 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120288 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120457 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120419 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 963786 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1770551 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1763883 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1765044 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785450 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756799 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1766043 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1776312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14141746 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 320975 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 687560 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1694,29 +1769,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 563826 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 687560 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 563826 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 445759226 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 94.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101149991 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 687560 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 445191055 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 94.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101323906 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101191512 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101359906 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 101013875 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101243878 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101648274 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 21.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101307289 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 101066643 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101367492 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101134998 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101213033 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 100955896 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101182766 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101242964 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 101290842 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 313b6d716..d571b5762 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011500 # Number of ticks simulated final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1111911 # Simulator instruction rate (inst/s) -host_op_rate 1421979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 767686935 # Simulator tick rate (ticks/s) -host_mem_usage 303468 # Number of bytes of host memory used -host_seconds 63.78 # Real time elapsed on the host +host_inst_rate 1547474 # Simulator instruction rate (inst/s) +host_op_rate 1979004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1068409192 # Simulator tick rate (ticks/s) +host_mem_usage 311136 # Number of bytes of host memory used +host_seconds 45.83 # Real time elapsed on the host sim_insts 70913182 # Number of instructions simulated sim_ops 90688137 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 120930619 # Request fanout histogram -system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram +system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::3 78145069 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::1 78145069 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 120930619 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 91d42cd77..90d753109 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -597,17 +597,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 307145 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 772df96ed..37a976075 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491500 # Number of ticks simulated final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1304038 # Simulator instruction rate (inst/s) -host_op_rate 1374666 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 753711187 # Simulator tick rate (ticks/s) -host_mem_usage 298984 # Number of bytes of host memory used -host_seconds 132.14 # Real time elapsed on the host +host_inst_rate 1968226 # Simulator instruction rate (inst/s) +host_op_rate 2074827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1137600357 # Simulator tick rate (ticks/s) +host_mem_usage 306644 # Number of bytes of host memory used +host_seconds 87.55 # Real time elapsed on the host sim_insts 172317410 # Number of instructions simulated sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 230024467 # Request fanout histogram -system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram +system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::3 189860052 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 230024467 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index e97c269ba..c495da061 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -585,17 +585,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 7b91ddd8b..b19da3109 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1264426 # Simulator instruction rate (inst/s) -host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1257935779 # Simulator tick rate (ticks/s) -host_mem_usage 324376 # Number of bytes of host memory used -host_seconds 104.45 # Real time elapsed on the host +host_inst_rate 851639 # Simulator instruction rate (inst/s) +host_op_rate 1427424 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 847267215 # Simulator tick rate (ticks/s) +host_mem_usage 272248 # Number of bytes of host memory used +host_seconds 155.08 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 759720678 # Wr system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 230176372 # Transaction distribution -system.membus.trans_dist::ReadResp 230176372 # Transaction distribution -system.membus.trans_dist::WriteReq 20515731 # Transaction distribution -system.membus.trans_dist::WriteResp 20515731 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 250692103 # Request fanout histogram -system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram -system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 250692103 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.membus.trans_dist::ReadReq 230176372 # Transaction distribution +system.membus.trans_dist::ReadResp 230176372 # Transaction distribution +system.membus.trans_dist::WriteReq 20515731 # Transaction distribution +system.membus.trans_dist::WriteResp 20515731 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 250692103 # Request fanout histogram +system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram +system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 250692103 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 0e62e6e73..af03b59c5 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957500 # Number of ticks simulated final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 722726 # Simulator instruction rate (inst/s) -host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1373280924 # Simulator tick rate (ticks/s) -host_mem_usage 338728 # Number of bytes of host memory used -host_seconds 182.74 # Real time elapsed on the host +host_inst_rate 582427 # Simulator instruction rate (inst/s) +host_op_rate 976201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1106694320 # Simulator tick rate (ticks/s) +host_mem_usage 282016 # Number of bytes of host memory used +host_seconds 226.76 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -446,17 +446,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6606 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |